diff --git a/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 0000000000..c8feab483c Binary files /dev/null and b/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ diff --git a/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM0.s b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM0.s new file mode 100644 index 0000000000..759490a736 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM0.s @@ -0,0 +1,240 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM3.s b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM3.s new file mode 100644 index 0000000000..c501ab60e5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM3.s @@ -0,0 +1,260 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V1.08 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM4.s b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM4.s new file mode 100644 index 0000000000..eb61098ffe --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM4.s @@ -0,0 +1,260 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V1.08 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/CMSIS/DSP_Lib/Examples/Common/G++/ARMCMx.ld b/CMSIS/DSP_Lib/Examples/Common/G++/ARMCMx.ld new file mode 100644 index 0000000000..778b055bb7 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/G++/ARMCMx.ld @@ -0,0 +1,198 @@ +/* Linker script to configure memory regions + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */ +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + .heap : + { + *(.heap) + } >ram + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM0.s b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM0.s new file mode 100644 index 0000000000..e0d749f599 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM0.s @@ -0,0 +1,220 @@ +/**************************************************************************//** + * @file startup_ARMCM0.s + * @brief CMSIS Core Device Startup File for + * ARMCM0 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000C00 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro def_irq_handler handler + .weak \handler + .set \handler, Default_Handler + .endm + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM3.s b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM3.s new file mode 100644 index 0000000000..d4b2b7b941 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM3.s @@ -0,0 +1,244 @@ +/**************************************************************************//** + * @file startup_ARMCM3.s + * @brief CMSIS Core Device Startup File for + * ARMCM3 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000C00 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro def_irq_handler handler + .weak \handler + .set \handler, Default_Handler + .endm + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM4.s b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM4.s new file mode 100644 index 0000000000..b7e7337c84 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM4.s @@ -0,0 +1,244 @@ +/**************************************************************************//** + * @file startup_ARMCM4.s + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000C00 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro def_irq_handler handler + .weak \handler + .set \handler, Default_Handler + .endm + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/GCC/ARMCMx.ld b/CMSIS/DSP_Lib/Examples/Common/GCC/ARMCMx.ld new file mode 100644 index 0000000000..fbc010c2dc --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/GCC/ARMCMx.ld @@ -0,0 +1,147 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM0.S b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM0.S new file mode 100644 index 0000000000..bdf720f5c4 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM0.S @@ -0,0 +1,208 @@ +/* File: startup_ARMCM0.S + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .flash_to_ram_loop_end + + movs r4, 0 +.flash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .flash_to_ram_loop +.flash_to_ram_loop_end: + +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM3.S b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM3.S new file mode 100644 index 0000000000..da2ef73342 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM3.S @@ -0,0 +1,221 @@ +/* File: startup_ARMCM3.S + * Purpose: startup file for Cortex-M3 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.flash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .flash_to_ram_loop +#else + subs r3, r2 + ble .flash_to_ram_loop_end +.flash_to_ram_loop: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .flash_to_ram_loop +.flash_to_ram_loop_end: +#endif + +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM4.S b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM4.S new file mode 100644 index 0000000000..3eef6802c1 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM4.S @@ -0,0 +1,221 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.flash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .flash_to_ram_loop +#else + subs r3, r2 + ble .flash_to_ram_loop_end +.flash_to_ram_loop: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .flash_to_ram_loop +.flash_to_ram_loop_end: +#endif + +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h b/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h new file mode 100644 index 0000000000..fcf4fa4cd1 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_clip_f32(float *pIn, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c b/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c new file mode 100644 index 0000000000..976ca2d3fa --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c @@ -0,0 +1,447 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param float* Pointer to the reference buffer + * @param float* Pointer to the test buffer + * @param uint32_t total number of samples + * @return float SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if(temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param q15_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q15_t* Pointer to Ref buffer + * @param q15_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if(diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param q31_t* Pointer to Ref buffer + * @param q31_t* Pointer to Test buffer + * @param uint32_t number of samples in the buffer + * @return none + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if(diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param q31_t* Pointer to input buffer + * @param uint32_t blockSize + * @param uint32_t guard_bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param uint32_t number of additions + * @return none + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Converts Q15 to floating-point + * @param uint32_t number of samples in the buffer + * @return none + */ + +void arm_apply_guard_bits (float32_t * pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param uint32_t number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param uint32_t number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t * pOut, + uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Clip the float values to +/- 1 + * @param pIn input buffer + * @param numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if(pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + + + diff --git a/CMSIS/DSP_Lib/Examples/Common/system_ARMCM0.c b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM0.c new file mode 100644 index 0000000000..b8d11eba8f --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM0.c @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL ( 5000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (5*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/CMSIS/DSP_Lib/Examples/Common/system_ARMCM3.c b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM3.c new file mode 100644 index 0000000000..1209dcbf4a --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM3.c @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL ( 5000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (5*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/CMSIS/DSP_Lib/Examples/Common/system_ARMCM4.c b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM4.c new file mode 100644 index 0000000000..2cad24fb40 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/Common/system_ARMCM4.c @@ -0,0 +1,70 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V1.07 + * @date 30. January 2012 + * + * @note + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "ARMCM4.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HSI ( 8000000UL) +#define __XTAL ( 5000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (5*__XTAL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini new file mode 100644 index 0000000000..51b32c0aec --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_class_marks_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt new file mode 100644 index 0000000000..70c295d5ef --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt @@ -0,0 +1,258 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
464
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj new file mode 100644 index 0000000000..d3f07797b5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_class_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt new file mode 100644 index 0000000000..718d720230 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt @@ -0,0 +1,258 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
456
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 3 + 1 + 0 + 0 + 37 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj new file mode 100644 index 0000000000..cac243e770 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_class_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt new file mode 100644 index 0000000000..211de4ef3c --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt @@ -0,0 +1,258 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
456
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lfclass_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ..\arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj new file mode 100644 index 0000000000..024578a797 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lfclass_marks_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ..\arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_class_marks_example.ini b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_class_marks_example.ini new file mode 100644 index 0000000000..51b32c0aec --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_class_marks_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_class_marks_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvopt new file mode 100644 index 0000000000..02005a12b7 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvopt @@ -0,0 +1,244 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
392
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/G++/startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvproj new file mode 100644 index 0000000000..7c3c89e241 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ../../Common/G++/startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvopt new file mode 100644 index 0000000000..f6f44bc025 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvopt @@ -0,0 +1,244 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
396
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/G++/startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvproj new file mode 100644 index 0000000000..2c27683161 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ../../Common/G++/startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvopt new file mode 100644 index 0000000000..6d72213cff --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvopt @@ -0,0 +1,244 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
396
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/G++/startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvproj new file mode 100644 index 0000000000..2af62767ee --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\G++ + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ../../Common/G++/startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini new file mode 100644 index 0000000000..51b32c0aec --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_class_marks_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt new file mode 100644 index 0000000000..9f87ad5035 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt @@ -0,0 +1,244 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
532
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM0.c + system_ARMCM0.c + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 138 + 138 + 0 + ../../Common/GCC/startup_ARMCM0.S + startup_ARMCM0.S + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj new file mode 100644 index 0000000000..6ebd3e54a1 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + startup_ARMCM0.S + 1 + ../../Common/GCC/startup_ARMCM0.S + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt new file mode 100644 index 0000000000..d8721bd81b --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt @@ -0,0 +1,244 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
640
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 180 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM3.c + system_ARMCM3.c + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 138 + 138 + 0 + ../../Common/GCC/startup_ARMCM3.S + startup_ARMCM3.S + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj new file mode 100644 index 0000000000..15742fec77 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + startup_ARMCM3.S + 1 + ../../Common/GCC/startup_ARMCM3.S + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt new file mode 100644 index 0000000000..6c6a48c7d6 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt @@ -0,0 +1,245 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_class_marks_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 193 + 1 +
640
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\CMSIS\CMSIS_Setup\CMSIS\DSP_Lib\Examples\arm_class_marks_example\GCC\..\arm_class_marks_example_f32.c + + \\arm_cortexM4lf_class_marks_example\../arm_class_marks_example_f32.c\193 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 135 + 193 + 0 + ../arm_class_marks_example_f32.c + arm_class_marks_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 122 + 138 + 0 + ../../Common/GCC/startup_ARMCM4.S + startup_ARMCM4.S + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj new file mode 100644 index 0000000000..b8264023db --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_class_marks_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_class_marks_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\GCC + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_class_marks_example_f32.c + 1 + ../arm_class_marks_example_f32.c + + + + + CMSIS Device + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + startup_ARMCM4.S + 1 + ../../Common/GCC/startup_ARMCM4.S + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 0000000000..6b7fdfcf5c --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + +uint32_t numStudents = 20; +uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; +uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + + while(1); /* main function does not return */ +} diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini new file mode 100644 index 0000000000..76ba07e0ab --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_convolution_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt new file mode 100644 index 0000000000..796c37736f --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 228 + 1 +
530
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228 + + + 1 + 0 + 225 + 1 +
526
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225 + + + + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj new file mode 100644 index 0000000000..165bd52f6e --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt new file mode 100644 index 0000000000..6f5d75fb94 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
516
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
520
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ..\arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 95 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj new file mode 100644 index 0000000000..0115d10036 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt new file mode 100644 index 0000000000..7d6c5e6e54 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
528
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
532
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ..\arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj new file mode 100644 index 0000000000..d10da979bd --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_convolution_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ..\arm_convolution_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_convolution_example.ini b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_convolution_example.ini new file mode 100644 index 0000000000..76ba07e0ab --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_convolution_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_convolution_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvopt new file mode 100644 index 0000000000..e33cb08a07 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 228 + 1 +
522
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228 + + + 1 + 0 + 225 + 1 +
520
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225 + + + + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvproj new file mode 100644 index 0000000000..b116e9e0b8 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ../../Common/GCC/startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvopt new file mode 100644 index 0000000000..87d5ea1e4d --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
496
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
498
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvproj new file mode 100644 index 0000000000..ce6d225223 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ../../Common/GCC/startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvopt new file mode 100644 index 0000000000..e27e5b1602 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
490
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
492
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvproj new file mode 100644 index 0000000000..740d17e79f --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\G++ + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ../../Common/GCC/startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini new file mode 100644 index 0000000000..76ba07e0ab --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_convolution_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt new file mode 100644 index 0000000000..8f80015cc4 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 228 + 1 +
564
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228 + + + 1 + 0 + 225 + 1 +
562
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225 + + + + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 136 + 136 + 0 + ../../Common/GCC/startup_ARMCM0.S + startup_ARMCM0.S + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj new file mode 100644 index 0000000000..7667ba9486 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.S + 1 + ../../Common/GCC/startup_ARMCM0.S + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt new file mode 100644 index 0000000000..7845ffd694 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
662
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
664
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 215 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 136 + 136 + 0 + ../../Common/GCC/startup_ARMCM3.S + startup_ARMCM3.S + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvproj new file mode 100644 index 0000000000..79851608ad --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.S + 1 + ../../Common/GCC/startup_ARMCM3.S + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt new file mode 100644 index 0000000000..efdbcfb8ae --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt @@ -0,0 +1,275 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_convolution_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 225 + 1 +
748
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\CMSIS\CMSIS_Setup\CMSIS\DSP_Lib\Examples\arm_convolution_example\GCC\..\arm_convolution_example_f32.c + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\225 + + + 1 + 0 + 228 + 1 +
750
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\CMSIS\CMSIS_Setup\CMSIS\DSP_Lib\Examples\arm_convolution_example\GCC\..\arm_convolution_example_f32.c + + \\arm_cortexM4lf_convolution_example\../arm_convolution_example_f32.c\228 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 173 + 228 + 0 + ../arm_convolution_example_f32.c + arm_convolution_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/Source/math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 122 + 138 + 0 + ../../Common/GCC/startup_ARMCM4.S + startup_ARMCM4.S + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvproj new file mode 100644 index 0000000000..170e2b8f13 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvproj @@ -0,0 +1,333 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_convolution_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_convolution_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\GCC + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_convolution_example_f32.c + 1 + ../arm_convolution_example_f32.c + + + math_helper.c + 1 + ../../Common/Source/math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.S + 1 + ../../Common/GCC/startup_ARMCM4.S + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 0000000000..8cf0522647 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ +-0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, +1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, +-0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, +-2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, +-0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, +-0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, +0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, +-0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, +-1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, +-1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, +-0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ +0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, +0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, +-0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, +-0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, +0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, +1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, +-1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, +0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, +0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, +-1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, +0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[126] = +{ +-0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, +5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, +-1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, +-7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, +-1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, +11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, +1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, +-0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, +-13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, +-0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, +8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, +7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, +-2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, +1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, +8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, +8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, +-6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, +-2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, +-3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, +-4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, +1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + if( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt new file mode 100644 index 0000000000..a7a05aa0c6 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_dotproduct_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ..\arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt new file mode 100644 index 0000000000..62e35bd8d7 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_dotProduct_example\../arm_dotproduct_example_f32.c\159 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 146 + 159 + 0 + ..\arm_dotproduct_example_f32.c + arm_dotproduct_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj new file mode 100644 index 0000000000..98e47d5776 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj @@ -0,0 +1,425 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_dotProduct_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ..\arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini new file mode 100644 index 0000000000..4fd5e984d5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini @@ -0,0 +1,13 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_dotproduct_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvopt new file mode 100644 index 0000000000..c128107418 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvopt @@ -0,0 +1,259 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
390
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_dotproduct_example\../arm_dotproduct_example_f32.c\156 + + + 1 + 0 + 159 + 1 +
392
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_dotproduct_example\../arm_dotproduct_example_f32.c\159 + + + + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 146 + 159 + 0 + ../arm_dotproduct_example_f32.c + arm_dotproduct_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvproj new file mode 100644 index 0000000000..e9d240d6c9 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_dotproduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ../../Common/GCC/startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvopt new file mode 100644 index 0000000000..a4a2d93d21 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvopt @@ -0,0 +1,259 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
398
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_dotProduct_example\../arm_dotproduct_example_f32.c\156 + + + 1 + 0 + 159 + 1 +
400
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_dotProduct_example\../arm_dotproduct_example_f32.c\159 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 130 + 159 + 0 + ../arm_dotproduct_example_f32.c + arm_dotproduct_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvproj new file mode 100644 index 0000000000..3ce20b11d4 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_dotProduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\G++ + -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ../../Common/GCC/startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvopt new file mode 100644 index 0000000000..b0279b9267 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvopt @@ -0,0 +1,259 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
394
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_dotProduct_example\../arm_dotproduct_example_f32.c\156 + + + 1 + 0 + 159 + 1 +
396
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_dotProduct_example\../arm_dotproduct_example_f32.c\159 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 146 + 159 + 0 + ../arm_dotproduct_example_f32.c + arm_dotproduct_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/GCC/startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvproj new file mode 100644 index 0000000000..62e97fb055 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_dotProduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\G++ + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections + ..\..\Common\G++\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ../../Common/GCC/startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_dotproduct_example.ini b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_dotproduct_example.ini new file mode 100644 index 0000000000..4fd5e984d5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_dotproduct_example.ini @@ -0,0 +1,13 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_dotproduct_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM0l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM0l_dotproduct_example.uvopt new file mode 100644 index 0000000000..0f1c324cd9 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM0l_dotproduct_example.uvopt @@ -0,0 +1,259 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
432
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_dotproduct_example\../arm_dotproduct_example_f32.c\156 + + + 1 + 0 + 159 + 1 +
434
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_dotproduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M0" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM0l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.S + 1 + ../../Common/GCC/startup_ARMCM0.S + + + system_ARMCM0.c + 1 + ../../Common/system_ARMCM0.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM3l_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM3l_dotproduct_example.uvopt new file mode 100644 index 0000000000..1a7cd41fa0 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM3l_dotproduct_example.uvopt @@ -0,0 +1,259 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
498
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_dotProduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotproduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM3l_math + ..\..\..\..\Lib\GCC + -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.S + 1 + ../../Common/GCC/startup_ARMCM3.S + + + system_ARMCM3.c + 1 + ../../Common/system_ARMCM3.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvopt new file mode 100644 index 0000000000..3ffe21f0cb --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvopt @@ -0,0 +1,261 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 156 + 1 +
578
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\CMSIS\CMSIS_Setup\CMSIS\DSP_Lib\Examples\arm_dotproduct_example\GCC\..\arm_dotproduct_example_f32.c + + \\arm_cortexM4lf_dotProduct_example\../arm_dotproduct_example_f32.c\156 + + + 1 + 0 + 159 + 1 +
580
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\CMSIS\CMSIS_Setup\CMSIS\DSP_Lib\Examples\arm_dotproduct_example\GCC\..\arm_dotproduct_example_f32.c + + \\arm_cortexM4lf_dotProduct_example\../arm_dotproduct_example_f32.c\159 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 104 + 159 + 0 + ../arm_dotproduct_example_f32.c + arm_dotproduct_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + 122 + 138 + 0 + ../../Common/GCC/startup_ARMCM4.S + startup_ARMCM4.S + + + 2 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../Common/system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 0 + 0 + 0 + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvproj new file mode 100644 index 0000000000..7a0ca84359 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvproj @@ -0,0 +1,328 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x3 + ARM-GNU + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_dotProduct_example + 1 + 0 + 0 + 1 + 0 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_dotProduct_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 1 + + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_cortexM4lf_math + ..\..\..\..\Lib\GCC + -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections + ..\..\Common\GCC\ARMCMx.ld + + + + + + Source Group 1 + + + arm_dotproduct_example_f32.c + 1 + ../arm_dotproduct_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.S + 1 + ../../Common/GCC/startup_ARMCM4.S + + + system_ARMCM4.c + 1 + ../../Common/system_ARMCM4.c + + + + + CMSIS DSP_Library + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_dotproduct_example.ini b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_dotproduct_example.ini new file mode 100644 index 0000000000..4fd5e984d5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_dotproduct_example.ini @@ -0,0 +1,13 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_dotproduct_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + diff --git a/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 0000000000..4e5ba4e9f5 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ +-0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, +-0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, +-0.0956484054836690, -0.8323494636500225, 0.2944108163926404, +-1.3361818579378040, 0.7143245518189522, 1.6235620644462707, +-0.6917757017022868, 0.8579966728282626, 1.2540014216025324, +-1.5937295764474768, -1.4409644319010200, 0.5711476236581780, +-0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, +-0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, +-0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, +-1.8561241921210170, 2.1343209047321410, 1.4358467535865909, +-0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, +-0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status == ARM_MATH_TEST_FAILURE) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt new file mode 100644 index 0000000000..668f821fb8 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
416
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_fft_bin_example\../arm_fft_bin_example_f32.c\146 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 133 + 146 + 0 + ..\arm_fft_bin_example_f32.c + arm_fft_bin_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_fft_bin_data.c + arm_fft_bin_data.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj new file mode 100644 index 0000000000..4615d84a69 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt new file mode 100644 index 0000000000..f8f68d62cb --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
498
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_fft_bin_example\../arm_fft_bin_example_f32.c\143 + + + 1 + 0 + 146 + 1 +
502
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_fft_bin_example\../arm_fft_bin_example_f32.c\146 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_fft_bin_data.c + arm_fft_bin_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 133 + 146 + 0 + ..\arm_fft_bin_example_f32.c + arm_fft_bin_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj new file mode 100644 index 0000000000..fef6889d81 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt new file mode 100644 index 0000000000..96130b63df --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 143 + 1 +
498
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fft_bin_example\../arm_fft_bin_example_f32.c\143 + + + 1 + 0 + 146 + 1 +
502
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fft_bin_example\../arm_fft_bin_example_f32.c\146 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_fft_bin_data.c + arm_fft_bin_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 133 + 146 + 0 + ..\arm_fft_bin_example_f32.c + arm_fft_bin_example_f32.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj new file mode 100644 index 0000000000..95c377490b --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj @@ -0,0 +1,430 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_fft_bin_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fft_bin_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fft_bin_data.c + 1 + ..\arm_fft_bin_data.c + + + arm_fft_bin_example_f32.c + 1 + ..\arm_fft_bin_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini new file mode 100644 index 0000000000..f25c9b37ab --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini @@ -0,0 +1,13 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_fft_bin_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + diff --git a/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 0000000000..24c0e15c51 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,268 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000, +-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000, +0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000, +-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000, +2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000, +1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000, +-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 0.000000000000000, +-3.488146646451150, 0.000000000000000, 1.323468578888120, 0.000000000000000, -0.099771155430726, 0.000000000000000, 1.561168082500454, 0.000000000000000, +1.025026795103179, 0.000000000000000, 0.928841900171200, 0.000000000000000, 2.930499509864950, 0.000000000000000, 2.013349089766430, 0.000000000000000, +2.381676148486737, 0.000000000000000, -3.081062307950236, 0.000000000000000, -0.389579115537544, 0.000000000000000, 0.181540149166620, 0.000000000000000, +-2.601953341353208, 0.000000000000000, 0.333435137783218, 0.000000000000000, -2.812945856162965, 0.000000000000000, 2.649109640172910, 0.000000000000000, +-1.003963025744654, 0.000000000000000, 1.552460768755035, 0.000000000000000, 0.088641345335247, 0.000000000000000, -2.519951327113426, 0.000000000000000, +-4.341348988610527, 0.000000000000000, 0.557772429359965, 0.000000000000000, -1.671267412948494, 0.000000000000000, 0.733951350960387, 0.000000000000000, +0.409263788034864, 0.000000000000000, 3.566033071952806, 0.000000000000000, 1.882565173848352, 0.000000000000000, -1.106017073793287, 0.000000000000000, +0.154456720778718, 0.000000000000000, -2.513205795512153, 0.000000000000000, 0.310978660939421, 0.000000000000000, 0.579706500111723, 0.000000000000000, +0.000086383683251, 0.000000000000000, -1.311866980897721, 0.000000000000000, 1.840007477574986, 0.000000000000000, -3.253005768451345, 0.000000000000000, +1.462584328739432, 0.000000000000000, 1.610103610851738, 0.000000000000000, 0.761914676858907, 0.000000000000000, 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All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + arm_cfft_radix4_instance_f32 S; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + /* Initialize the CFFT/CIFFT module */ + status = arm_cfft_radix4_init_f32(&S, fftSize, + ifftFlag, doBitReverse); + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_radix4_f32(&S, testInput_f32_10khz); + + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, + fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + if(testIndex != refIndex) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt new file mode 100644 index 0000000000..6458443b43 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fir_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 211 + 1 +
440
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_fir_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fir_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fir_data.c + 1 + ..\arm_fir_data.c + + + arm_fir_example_f32.c + 1 + ..\arm_fir_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt new file mode 100644 index 0000000000..ae2ec41716 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fir_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 211 + 1 +
530
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_fir_example\../arm_fir_example_f32.c\211 + + + 1 + 0 + 214 + 1 +
534
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_fir_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fir_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fir_data.c + 1 + ..\arm_fir_data.c + + + arm_fir_example_f32.c + 1 + ..\arm_fir_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt new file mode 100644 index 0000000000..22abd44400 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_fir_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 211 + 1 +
538
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fir_example\../arm_fir_example_f32.c\211 + + + 1 + 0 + 214 + 1 +
542
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_fir_example\../arm_fir_example_f32.c\214 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 77 + 0 + 0 + 0 + 0 + ..\arm_fir_data.c + arm_fir_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 201 + 214 + 0 + ..\arm_fir_example_f32.c + arm_fir_example_f32.c + + + 1 + 3 + 1 + 0 + 0 + 16 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj new file mode 100644 index 0000000000..91a378e138 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_fir_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_fir_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_fir_data.c + 1 + ..\arm_fir_data.c + + + arm_fir_example_f32.c + 1 + ..\arm_fir_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini new file mode 100644 index 0000000000..6de9e570a9 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini @@ -0,0 +1,13 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_fir_lpf_example.ini + +*/ + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c b/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c new file mode 100644 index 0000000000..e2e9ad658b --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c @@ -0,0 +1,94 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 0000000000..209671a811 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 29. November 2010 + * $Revision: V1.0.3 + * + * Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.1 2010/10/05 KK + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 KK + * Production release and review comments incorporated. + * ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + * 
+ *     h = fir1(28, 6/24);
+ *
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + * 
+ *     fliplr(h)
+ *
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +#define SNR_THRESHOLD_F32 140.0f +#define BLOCK_SIZE 32 +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ + +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ + +const float32_t firCoeffs32[NUM_TAPS] = { +-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, +-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, ++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, ++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt new file mode 100644 index 0000000000..6762df0d54 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 386 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_graphic_equalizer_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_graphic_equalizer_example_q31.c + 1 + ..\arm_graphic_equalizer_example_q31.c + + + arm_graphic_equalizer_data.c + 1 + ..\arm_graphic_equalizer_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvopt new file mode 100644 index 0000000000..702854b2d7 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 386 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_graphic_equalizer_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_graphic_equalizer_data.c + 1 + ..\arm_graphic_equalizer_data.c + + + arm_graphic_equalizer_example_q31.c + 1 + ..\arm_graphic_equalizer_example_q31.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvopt new file mode 100644 index 0000000000..1f3a0e668c --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 386 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_graphic_equalizer_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_graphic_equalizer_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_graphic_equalizer_data.c + 1 + ..\arm_graphic_equalizer_data.c + + + arm_graphic_equalizer_example_q31.c + 1 + ..\arm_graphic_equalizer_example_q31.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini new file mode 100644 index 0000000000..61b01a0a09 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_geq_5band_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 0000000000..52bc0b308a --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,94 @@ +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 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b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c new file mode 100644 index 0000000000..1ed0048e6f --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 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-745714425, -293206383, + 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, + 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, + 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, + 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, + 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 + +}; + +/* ---------------------------------------------------------------------- +** Desired gains, in dB, per band +** ------------------------------------------------------------------- */ + +int gainDB[5] = {0, -3, 6, 4, -6}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- + * Graphic equalizer Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + if (snr < SNR_THRESHOLD_F32) + { + status = ARM_MATH_TEST_FAILURE; + } + else + { + status = ARM_MATH_SUCCESS; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signal does not match the reference output. + ** ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + +/** \endlink */ + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt new file mode 100644 index 0000000000..3951d3a8b0 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 184 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_linear_interp_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_linear_interp_example_f32.c + 1 + ..\arm_linear_interp_example_f32.c + + + arm_linear_interp_data.c + 1 + ..\arm_linear_interp_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt new file mode 100644 index 0000000000..40486eead3 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 184 + 1 +
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_linear_interp_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_linear_interp_example_f32.c + 1 + ..\arm_linear_interp_example_f32.c + + + arm_linear_interp_data.c + 1 + ..\arm_linear_interp_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt new file mode 100644 index 0000000000..654fbd7571 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 184 + 1 +
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494
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_linear_interp_example\../arm_linear_interp_example_f32.c\181 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 171 + 181 + 0 + ..\arm_linear_interp_example_f32.c + arm_linear_interp_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_linear_interp_data.c + arm_linear_interp_data.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj new file mode 100644 index 0000000000..5f11754ead --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_linear_interp_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_linear_interp_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_linear_interp_example_f32.c + 1 + ..\arm_linear_interp_example_f32.c + + + arm_linear_interp_data.c + 1 + ..\arm_linear_interp_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini new file mode 100644 index 0000000000..b6d93ff8fe --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_linear_interp_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 0000000000..fb4626fa7b --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,23576 @@ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.00005 : (2*pi - 0.00005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +const float arm_linear_interep_table[188495] = { + + +-0.000000000000000122, -0.000049999999979173, -0.000099999999833667, -0.000149999999437717, -0.000199999998666767, -0.000249999997395817, -0.000299999995500311, -0.000349999992854362, +-0.000399999989333412, -0.000449999984812462, -0.000499999979166956, -0.000549999972271007, -0.000599999964000057, -0.000649999954229107, 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All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.00005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, + 0.188250329003310100, 0.432092748487532540, + -1.722010988459680800, 1.788766476323060600, + 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, + 0.187140422442966500, 0.418772124875992690, + -0.988588831792106880, 0.976338412038794010, + 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern const float arm_linear_interep_table[188495]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, (float32_t *)&arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if( snr2 > snr1) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt new file mode 100644 index 0000000000..af478541c3 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt @@ -0,0 +1,287 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_matrix_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_matrix_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_matrix_example_f32.c + 1 + ..\arm_matrix_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini b/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini new file mode 100644 index 0000000000..517a70f3f2 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_matrix_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 0000000000..5e074257f4 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * \image html matrixExample.gif + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + if( snr > SNR_THRESHOLD) + { + status = ARM_MATH_SUCCESS; + } + else + { + status = ARM_MATH_TEST_FAILURE; + } + + + /* ---------------------------------------------------------------------- + ** Loop here if the signals fail the PASS check. + ** This denotes a test failure + ** ------------------------------------------------------------------- */ + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt new file mode 100644 index 0000000000..80fbd56207 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 237 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_signal_converge_example\../arm_signal_converge_example_f32.c\237 + + + 1 + 0 + 240 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM0l_signal_converge_example\../arm_signal_converge_example_f32.c\240 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 227 + 240 + 0 + ..\arm_signal_converge_example_f32.c + arm_signal_converge_example_f32.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_signal_converge_data.c + arm_signal_converge_data.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM0.s + startup_ARMCM0.s + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM0.c + system_ARMCM0.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + arm_cortexM0l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj new file mode 100644 index 0000000000..9c2b779abd --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_signal_converge_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_signal_converge_example_f32.c + 1 + ..\arm_signal_converge_example_f32.c + + + arm_signal_converge_data.c + 1 + ..\arm_signal_converge_data.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt new file mode 100644 index 0000000000..2295372ca4 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 237 + 1 +
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+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM3l_signal_converge_example\../arm_signal_converge_example_f32.c\240 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_signal_converge_data.c + arm_signal_converge_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 227 + 240 + 0 + ..\arm_signal_converge_example_f32.c + arm_signal_converge_example_f32.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM3.s + startup_ARMCM3.s + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM3.c + system_ARMCM3.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + arm_cortexM3l_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvproj new file mode 100644 index 0000000000..f6079af45a --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_signal_converge_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_signal_converge_data.c + 1 + ..\arm_signal_converge_data.c + + + arm_signal_converge_example_f32.c + 1 + ..\arm_signal_converge_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvopt new file mode 100644 index 0000000000..e0b077b394 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvopt @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 237 + 1 +
562
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_signal_converge_example\../arm_signal_converge_example_f32.c\237 + + + 1 + 0 + 240 + 1 +
566
+ 0 + 0 + 0 + 0 + 1 + + + \\arm_cortexM4lf_signal_converge_example\../arm_signal_converge_example_f32.c\240 + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Source Group 1 + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\arm_signal_converge_data.c + arm_signal_converge_data.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 227 + 240 + 0 + ..\arm_signal_converge_example_f32.c + arm_signal_converge_example_f32.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\Source\math_helper.c + math_helper.c + + + + + CMSIS Device + 1 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + 126 + 126 + 0 + ..\..\Common\ARM\startup_ARMCM4.s + startup_ARMCM4.s + + + 2 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Common\system_ARMCM4.c + system_ARMCM4.c + + + + + CMSIS DSP_Library + 1 + 0 + 0 + + 3 + 6 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + arm_cortexM4lf_math.lib + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj new file mode 100644 index 0000000000..53b28e4dca --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_signal_converge_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_signal_converge_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_signal_converge_data.c + 1 + ..\arm_signal_converge_data.c + + + arm_signal_converge_example_f32.c + 1 + ..\arm_signal_converge_example_f32.c + + + math_helper.c + 1 + ..\..\Common\Source\math_helper.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini new file mode 100644 index 0000000000..3f091f4213 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_signal_converge_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 0000000000..195bbff1c2 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,229 @@ +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635, +0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903, +1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465, +0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 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0.903970, 0.541671, -0.465020 +}; + + + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 0000000000..6851d66e3f --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.000001f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + if (minValue > DELTA_COEFF) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Loop here if the signals did not pass the convergence check. + * This denotes a test failure + * ------------------------------------------------------------------- */ + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt new file mode 100644 index 0000000000..ece27c07e2 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_sin_cos_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_sin_cos_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_sin_cos_example_f32.c + 1 + ..\arm_sin_cos_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini new file mode 100644 index 0000000000..34b42cd172 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_sin_cos_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 0000000000..4ff50f1cab --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status == ARM_MATH_TEST_FAILURE) + { + while(1); + } + + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt new file mode 100644 index 0000000000..78cad0e47b --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
570
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM0l_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM0 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM0.s + 2 + ..\..\Common\ARM\startup_ARMCM0.s + + + system_ARMCM0.c + 1 + ..\..\Common\system_ARMCM0.c + + + + + CMSIS DSP_Library + + + arm_cortexM0l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt new file mode 100644 index 0000000000..cd82723f61 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
558
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM3l_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM3 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM3.s + 2 + ..\..\Common\ARM\startup_ARMCM3.s + + + system_ARMCM3.c + 1 + ..\..\Common\system_ARMCM3.c + + + + + CMSIS DSP_Library + + + arm_cortexM3l_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt new file mode 100644 index 0000000000..c433eeff47 --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt @@ -0,0 +1,273 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + -1 + + + + + .\arm_variance_example.ini + + + + + + + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + + + 0 + 0 + 182 + 1 +
624
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628
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### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\debug\ + arm_cortexM4lf_variance_example + 1 + 0 + 0 + 1 + 1 + .\debug\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + -1 + + + + + + .\arm_variance_example.ini + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + ARM_MATH_CM4, __FPU_PRESENT = 1 + + ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + Source Group 1 + + + arm_variance_example_f32.c + 1 + ..\arm_variance_example_f32.c + + + + + CMSIS Device + + + startup_ARMCM4.s + 2 + ..\..\Common\ARM\startup_ARMCM4.s + + + system_ARMCM4.c + 1 + ..\..\Common\system_ARMCM4.c + + + + + CMSIS DSP_Library + + + arm_cortexM4lf_math.lib + 4 + ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib + + + + + + + + diff --git a/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini new file mode 100644 index 0000000000..212b6079cf --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini @@ -0,0 +1,15 @@ + +/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions + + The file can be executed in the following way: + 1) manually from uVision command window (in debug mode) using command: + INCLUIDE arm_variance_example.ini + +*/ + + +// usual initialisation for target setup +MAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash +MAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM + + diff --git a/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c b/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 0000000000..d4a66c6daa --- /dev/null +++ b/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 29. November 2010 +* $Revision: V1.0.3 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.1 2010/10/05 KK +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 KK +* Production release and review comments incorporated. +* ------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ +-0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, +-1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, +0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, +-0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, +1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, +0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, +-0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, +-1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + if(diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + if( status != ARM_MATH_SUCCESS) + { + while(1); + } + + while(1); /* main function does not return */ +} + + /** \endlink */ + diff --git a/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt b/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt new file mode 100644 index 0000000000..5514cddd39 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt @@ -0,0 +1,4197 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\StatisticsFunctions\arm_min_q7.c + + + arm_min_q15.c + 1 + ..\StatisticsFunctions\arm_min_q15.c + + + arm_min_q31.c + 1 + ..\StatisticsFunctions\arm_min_q31.c + + + arm_power_f32.c + 1 + ..\StatisticsFunctions\arm_power_f32.c + + + arm_power_q7.c + 1 + ..\StatisticsFunctions\arm_power_q7.c + + + arm_power_q15.c + 1 + ..\StatisticsFunctions\arm_power_q15.c + + + arm_power_q31.c + 1 + ..\StatisticsFunctions\arm_power_q31.c + + + arm_rms_f32.c + 1 + ..\StatisticsFunctions\arm_rms_f32.c + + + arm_rms_q15.c + 1 + ..\StatisticsFunctions\arm_rms_q15.c + + + arm_rms_q31.c + 1 + ..\StatisticsFunctions\arm_rms_q31.c + + + arm_std_f32.c + 1 + ..\StatisticsFunctions\arm_std_f32.c + + + arm_std_q15.c + 1 + ..\StatisticsFunctions\arm_std_q15.c + + + arm_std_q31.c + 1 + ..\StatisticsFunctions\arm_std_q31.c + + + arm_var_f32.c + 1 + ..\StatisticsFunctions\arm_var_f32.c + + + arm_var_q15.c + 1 + ..\StatisticsFunctions\arm_var_q15.c + + + arm_var_q31.c + 1 + ..\StatisticsFunctions\arm_var_q31.c + + + + + SupportFunctions + + + arm_copy_f32.c + 1 + ..\SupportFunctions\arm_copy_f32.c + + + arm_copy_q7.c + 1 + ..\SupportFunctions\arm_copy_q7.c + + + arm_copy_q15.c + 1 + ..\SupportFunctions\arm_copy_q15.c + + + arm_copy_q31.c + 1 + ..\SupportFunctions\arm_copy_q31.c + + + arm_fill_f32.c + 1 + ..\SupportFunctions\arm_fill_f32.c + + + arm_fill_q7.c + 1 + ..\SupportFunctions\arm_fill_q7.c + + + arm_fill_q15.c + 1 + ..\SupportFunctions\arm_fill_q15.c + + + arm_fill_q31.c + 1 + ..\SupportFunctions\arm_fill_q31.c + + + arm_float_to_q7.c + 1 + ..\SupportFunctions\arm_float_to_q7.c + + + arm_float_to_q15.c + 1 + ..\SupportFunctions\arm_float_to_q15.c + + + arm_float_to_q31.c + 1 + ..\SupportFunctions\arm_float_to_q31.c + + + arm_q7_to_float.c + 1 + ..\SupportFunctions\arm_q7_to_float.c + + + arm_q7_to_q15.c + 1 + ..\SupportFunctions\arm_q7_to_q15.c + + + arm_q7_to_q31.c + 1 + ..\SupportFunctions\arm_q7_to_q31.c + + + arm_q15_to_float.c + 1 + ..\SupportFunctions\arm_q15_to_float.c + + + arm_q15_to_q7.c + 1 + ..\SupportFunctions\arm_q15_to_q7.c + + + arm_q15_to_q31.c + 1 + ..\SupportFunctions\arm_q15_to_q31.c + + + arm_q31_to_float.c + 1 + ..\SupportFunctions\arm_q31_to_float.c + + + arm_q31_to_q7.c + 1 + ..\SupportFunctions\arm_q31_to_q7.c + + + arm_q31_to_q15.c + 1 + ..\SupportFunctions\arm_q31_to_q15.c + + + + + CommonTables + + + arm_common_tables.c + 1 + ..\CommonTables\arm_common_tables.c + + + + + + + + diff --git a/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat b/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat new file mode 100644 index 0000000000..69cf1aa0e8 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat @@ -0,0 +1,29 @@ + +SET TMP=C:\Temp +SET TEMP=C:\Temp + +SET UVEXE=C:\Keil\UV4\UV4.EXE + +@echo Building DSP Library for Cortex-M0 Little Endian +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0 + +@echo Building DSP Library for Cortex-M0 Big Endian +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 BE" -o"DSP_Lib CM0 BE.txt" -j0 + +@echo Building DSP Library for Cortex-M3 Little Endian +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0 + +@echo Building DSP Library for Cortex-M3 Big Endian +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 BE" -o"DSP_Lib CM3 BE.txt" -j0 + +@echo Building DSP Library for Cortex-M4 Little Endian +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0 + +@echo Building DSP Library for Cortex-M4 Big Endian +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE" -o"DSP_Lib CM4 BE.txt" -j0 + +@echo Building DSP Library for Cortex-M4 with FPU Little Endian +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0 + +@echo Building DSP Library for Cortex-M4 with FPU Big Endian +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE FPU" -o"DSP_Lib CM4 BE FPU.txt" -j0 \ No newline at end of file diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000000..7070274da2 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_abs_f32.c +* +* Description: Vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" +#include + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAbs Vector Absolute Value + * + * Computes the absolute value of a vector on an element-by-element basis. + * + * 
        
+ *     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.        
+ *
+ * + * The operation can be done in-place by setting the input and output pointers to the same buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + /* read sample from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + + /* find absolute value */ + in1 = fabsf(in1); + + /* read sample from source */ + in4 = *(pSrc + 3); + + /* find absolute value */ + in2 = fabsf(in2); + + /* read sample from source */ + *pDst = in1; + + /* find absolute value */ + in3 = fabsf(in3); + + /* find absolute value */ + in4 = fabsf(in4); + + /* store result to destination */ + *(pDst + 1) = in2; + + /* store result to destination */ + *(pDst + 2) = in3; + + /* store result to destination */ + *(pDst + 3) = in4; + + + /* Update source pointer to process next sampels */ + pSrc += 4u; + + /* Update destination pointer to process next sampels */ + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAbs group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000000..6d6a4b6d80 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q15.c +* +* Description: Q15 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1; /* Input value1 */ + q15_t in2; /* Input value2 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + + /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), + ((in2 > 0) ? in2 : __QSUB16(0, in2)), 16); + +#else + + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), + ((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), + ((in2 > 0) ? in2 : __QSUB16(0, in2)), 16); + +#else + + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), + ((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in1 > 0) ? in1 : __QSUB16(0, in1); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q15_t in; /* Temporary input variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000000..d9e3e7aa3c --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q31.c +* +* Description: Q31 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q31_t in; /* Input value */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = (in1 > 0) ? in1 : __QSUB(0, in1); + *pDst++ = (in2 > 0) ? in2 : __QSUB(0, in2); + *pDst++ = (in3 > 0) ? in3 : __QSUB(0, in3); + *pDst++ = (in4 > 0) ? in4 : __QSUB(0, in4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000000..258ecef2c8 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q7.c +* +* Description: Q7 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q7_t in; /* Input value1 */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read inputs */ + in1 = (q31_t) * pSrc; + in2 = (q31_t) * (pSrc + 1); + in3 = (q31_t) * (pSrc + 2); + + /* find absolute value */ + out1 = (in1 > 0) ? in1 : __QSUB8(0, in1); + + /* read input */ + in4 = (q31_t) * (pSrc + 3); + + /* find absolute value */ + out2 = (in2 > 0) ? in2 : __QSUB8(0, in2); + + /* store result to destination */ + *pDst = (q7_t) out1; + + /* find absolute value */ + out3 = (in3 > 0) ? in3 : __QSUB8(0, in3); + + /* find absolute value */ + out4 = (in4 > 0) ? in4 : __QSUB8(0, in4); + + /* store result to destination */ + *(pDst + 1) = (q7_t) out2; + + /* store result to destination */ + *(pDst + 2) = (q7_t) out3; + + /* store result to destination */ + *(pDst + 3) = (q7_t) out4; + + /* update pointers to process next samples */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; +#else + + /* Run the below code for Cortex-M0 */ + blkCnt = blockSize; + +#endif // #define ARM_MATH_CM0 + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAbs group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000000..0961dd1db3 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_add_f32.c +* +* Description: Floating-point vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAdd Vector Addition + * + * Element-by-element addition of two vectors. + * + * 
        
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ + float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + + /* read four inputs from sourceA and four inputs from sourceB */ + inA1 = *pSrcA; + inB1 = *pSrcB; + inA2 = *(pSrcA + 1); + inB2 = *(pSrcB + 1); + inA3 = *(pSrcA + 2); + inB3 = *(pSrcB + 2); + inA4 = *(pSrcA + 3); + inB4 = *(pSrcB + 3); + + /* C = A + B */ + /* add and store result to destination */ + *pDst = inA1 + inB1; + *(pDst + 1) = inA2 + inB2; + *(pDst + 2) = inA3 + inB3; + *(pDst + 3) = inA4 + inB4; + + /* update pointers to process next samples */ + pSrcA += 4u; + pSrcB += 4u; + pDst += 4u; + + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAdd group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000000..788b2ebb2c --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_add_q15.c +* +* Description: Q15 vector addition +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + inA1 = *__SIMD32(pSrcA)++; + inA2 = *__SIMD32(pSrcA)++; + inB1 = *__SIMD32(pSrcB)++; + inB2 = *__SIMD32(pSrcB)++; + + *__SIMD32(pDst)++ = __QADD16(inA1, inB1); + *__SIMD32(pDst)++ = __QADD16(inA2, inB2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000000..c5b18711d4 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_add_q31.c +* +* Description: Q31 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + *pDst++ = __QADD(inA1, inB1); + *pDst++ = __QADD(inA2, inB2); + *pDst++ = __QADD(inA3, inB3); + *pDst++ = __QADD(inA4, inB4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAdd group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000000..5407c006fb --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_add_q7.c +* +* Description: Q7 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000000..6f7fbcebf2 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_f32.c +* +* Description: Floating-point dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup dot_prod Vector Dot Product + * + * Computes the dot product of two vectors. + * The vectors are multiplied element-by-element and then summed. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + +void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + /* Store the result back in the destination buffer */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000000..24611a05f5 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q15.c +* +* Description: Q15 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + * results are added to a 64-bit accumulator in 34.30 format. + * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + * there is no risk of overflow. + * The return result is in 34.30 format. + */ + +void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum = __SMLALD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + /* Store the result in the destination buffer in 34.30 format */ + *result = sum; + +} + +/** + * @} end of dot_prod group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000000..5e4031338c --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q31.c +* +* Description: Q31 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + * are truncated to 2.48 format by discarding the lower 14 bits. + * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + * There are 15 guard bits in the accumulator and there is no risk of overflow as long as + * the length of the vectors is less than 2^16 elements. + * The return result is in 16.48 format. + */ + +void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + sum += ((q63_t) inA1 * inB1) >> 14u; + sum += ((q63_t) inA2 * inB2) >> 14u; + sum += ((q63_t) inA3 * inB3) >> 14u; + sum += ((q63_t) inA4 * inB4) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result in the destination buffer in 16.48 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000000..ddf2d0c243 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q7.c +* +* Description: Q7 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + * results are added to an accumulator in 18.14 format. + * Nonsaturating additions are used and there is no danger of wrap around as long as + * the vectors are less than 2^18 elements long. + * The return result is in 18.14 format. + */ + +void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counter */ + + q31_t sum = 0; /* Temporary variables to store output */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t input1, input2; /* Temporary variables to store input */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */ + + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* read 4 samples at a time from sourceA */ + input1 = *__SIMD32(pSrcA)++; + /* read 4 samples at a time from sourceB */ + input2 = *__SIMD32(pSrcB)++; + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum = __SMLAD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + + /* Store the result in the destination buffer in 18.14 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000000..88a458b40a --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_mult_f32.c +* +* Description: Floating-point vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicMult Vector Multiplication + * + * Element-by-element multiplication of two vectors. + * + * 
        
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary input variables */ + float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ + float32_t out1, out2, out3, out4; /* temporary output variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + /* read sample from sourceA */ + inA1 = *pSrcA; + /* read sample from sourceB */ + inB1 = *pSrcB; + /* read sample from sourceA */ + inA2 = *(pSrcA + 1); + /* read sample from sourceB */ + inB2 = *(pSrcB + 1); + + /* out = sourceA * sourceB */ + out1 = inA1 * inB1; + + /* read sample from sourceA */ + inA3 = *(pSrcA + 2); + /* read sample from sourceB */ + inB3 = *(pSrcB + 2); + + /* out = sourceA * sourceB */ + out2 = inA2 * inB2; + + /* read sample from sourceA */ + inA4 = *(pSrcA + 3); + + /* store result to destination buffer */ + *pDst = out1; + + /* read sample from sourceB */ + inB4 = *(pSrcB + 3); + + /* out = sourceA * sourceB */ + out3 = inA3 * inB3; + + /* store result to destination buffer */ + *(pDst + 1) = out2; + + /* out = sourceA * sourceB */ + out4 = inA4 * inB4; + /* store result to destination buffer */ + *(pDst + 2) = out3; + /* store result to destination buffer */ + *(pDst + 3) = out4; + + + /* update pointers to process next samples */ + pSrcA += 4u; + pSrcB += 4u; + pDst += 4u; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000000..99d44a4ba3 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q15.c +* +* Description: Q15 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + + +/** + * @brief Q15 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* read two samples at a time from sourceA */ + inA1 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB1 = *__SIMD32(pSrcB)++; + /* read two samples at a time from sourceA */ + inA2 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB2 = *__SIMD32(pSrcB)++; + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store the result */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#endif // #ifndef ARM_MATH_BIG_ENDIAN + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000000..37ec8e25e1 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q31.c +* +* Description: Q31 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; /* temporary input variables */ + q31_t inB1, inB2, inB3, inB4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + out1 = ((q63_t) inA1 * inB1) >> 32; + out2 = ((q63_t) inA2 * inB2) >> 32; + out3 = ((q63_t) inA3 * inB3) >> 32; + out4 = ((q63_t) inA4 * inB4) >> 32; + + out1 = __SSAT(out1, 31); + out2 = __SSAT(out2, 31); + out3 = __SSAT(out3, 31); + out4 = __SSAT(out4, 31); + + *pDst++ = out1 << 1u; + *pDst++ = out2 << 1u; + *pDst++ = out3 << 1u; + *pDst++ = out4 << 1u; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000000..14ee23ea6a --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q7.c +* +* Description: Q7 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 DP +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q7 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000000..4f4d423ac9 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_negate_f32.c +* +* Description: Negates floating-point vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup negate Vector Negate + * + * Negates the elements of a vector. + * + * 
        
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.        
+ *
+ */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* read inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* negate the input */ + in1 = -in1; + in2 = -in2; + in3 = -in3; + in4 = -in4; + + /* store the result to destination */ + *pDst = in1; + *(pDst + 1) = in2; + *(pDst + 2) = in3; + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000000..21d58d1a4a --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q15.c +* +* Description: Negates Q15 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q15_t in; + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read two inputs at a time */ + in1 = _SIMD32_OFFSET(pSrc); + in2 = _SIMD32_OFFSET(pSrc + 2); + + /* negate two samples at a time */ + in1 = __QSUB16(0, in1); + + /* negate two samples at a time */ + in2 = __QSUB16(0, in2); + + /* store the result to destination 2 samples at a time */ + _SIMD32_OFFSET(pDst) = in1; + /* store the result to destination 2 samples at a time */ + _SIMD32_OFFSET(pDst + 2) = in2; + + + /* update pointers to process next samples */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000000..fc28c36218 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q31.c +* +* Description: Negates Q31 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t in; /* Temporary variable */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = __QSUB(0, in1); + *pDst++ = __QSUB(0, in2); + *pDst++ = __QSUB(0, in3); + *pDst++ = __QSUB(0, in4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000000..601fb73934 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q7.c +* +* Description: Negates Q7 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q7_t in; + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t input; /* Input values1-4 */ + q31_t zero = 0x00000000; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read four inputs */ + input = *__SIMD32(pSrc)++; + + /* Store the Negated results in the destination buffer in a single cycle by packing the results */ + *__SIMD32(pDst)++ = __QSUB8(zero, input); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ \ + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000000..4bdf06ee8d --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_offset_f32.c +* +* Description: Floating-point vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup offset Vector Offset + * + * Adds a constant offset to each element of a vector. + * + * 
        
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + /* read samples from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + + /* add offset to input */ + in1 = in1 + offset; + + /* read samples from source */ + in3 = *(pSrc + 2); + + /* add offset to input */ + in2 = in2 + offset; + + /* read samples from source */ + in4 = *(pSrc + 3); + + /* add offset to input */ + in3 = in3 + offset; + + /* store result to destination */ + *pDst = in1; + + /* add offset to input */ + in4 = in4 + offset; + + /* store result to destination */ + *(pDst + 1) = in2; + + /* store result to destination */ + *(pDst + 2) = in3; + + /* store result to destination */ + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of offset group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000000..f8158f066f --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q15.c +* +* Description: Q15 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000000..8b03ee3727 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q31.c +* +* Description: Q31 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t in1, in2, in3, in4; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + *pDst++ = __QADD(in1, offset); + *pDst++ = __QADD(in2, offset); + *pDst++ = __QADD(in3, offset); + *pDst++ = __QADD(in4, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000000..56643816f3 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q7.c +* +* Description: Q7 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000000..b77144a3ef --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_scale_f32.c +* +* Description: Multiplies a floating-point vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup scale Vector Scale + * + * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + * + * 
        
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        
+ *
+ * + * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + * a fractional multiplication scaleFract and an arithmetic shift shift. + * The shift allows the gain of the scaling operation to exceed 1.0. + * The algorithm used with fixed-point data is: + * + * 
        
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        
+ *
+ * + * The overall scale factor applied to the fixed-point data is + * 
        
+ *     scale = scaleFract * 2^shift.        
+ *
+ */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t in1, in2, in3, in4; /* temporary variabels */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + /* read input samples from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + + /* multiply with scaling factor */ + in1 = in1 * scale; + + /* read input sample from source */ + in3 = *(pSrc + 2); + + /* multiply with scaling factor */ + in2 = in2 * scale; + + /* read input sample from source */ + in4 = *(pSrc + 3); + + /* multiply with scaling factor */ + in3 = in3 * scale; + in4 = in4 * scale; + /* store the result to destination */ + *pDst = in1; + *(pDst + 1) = in2; + *(pDst + 2) = in3; + *(pDst + 3) = in4; + + /* update pointers to process next samples */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000000..9e79202fe3 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q15.c +* +* Description: Multiplies a Q15 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.15 format. + * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + + +void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 15 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q15_t in1, in2, in3, in4; + q31_t inA1, inA2; /* Temporary variables */ + q31_t out1, out2, out3, out4; + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 2 inputs from memory */ + inA1 = *__SIMD32(pSrc)++; + inA2 = *__SIMD32(pSrc)++; + + /* C = A * scale */ + /* Scale the inputs and then store the 2 results in the destination buffer + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) inA1 * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) inA2 * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store the result to destination */ + *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16); + *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000000..8e9b50e72f --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q31.c +* +* Description: Multiplies a Q31 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.31 format. + * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + uint32_t blkCnt; /* loop counter */ + q31_t in, out; + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t in1, in2, in3, in4; /* temporary input variables */ + q31_t out1, out2, out3, out4; /* temporary output variabels */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* read four inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* multiply input with scaler value */ + in1 = ((q63_t) in1 * scaleFract) >> 32; + in2 = ((q63_t) in2 * scaleFract) >> 32; + in3 = ((q63_t) in3 * scaleFract) >> 32; + in4 = ((q63_t) in4 * scaleFract) >> 32; + + /* apply shifting */ + out1 = in1 << kShift; + out2 = in2 << kShift; + + /* saturate the results. */ + if(in1 != (out1 >> kShift)) + out1 = 0x7FFFFFFF ^ (in1 >> 31); + + if(in2 != (out2 >> kShift)) + out2 = 0x7FFFFFFF ^ (in2 >> 31); + + out3 = in3 << kShift; + out4 = in4 << kShift; + + *pDst = out1; + *(pDst + 1) = out2; + + if(in3 != (out3 >> kShift)) + out3 = 0x7FFFFFFF ^ (in3 >> 31); + + if(in4 != (out4 >> kShift)) + out4 = 0x7FFFFFFF ^ (in4 >> 31); + + /* Store result destination */ + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update pointers to process next sampels */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + } + else + { + kShift = -kShift; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* read four inputs from source */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* multiply input with scaler value */ + in1 = ((q63_t) in1 * scaleFract) >> 32; + in2 = ((q63_t) in2 * scaleFract) >> 32; + in3 = ((q63_t) in3 * scaleFract) >> 32; + in4 = ((q63_t) in4 * scaleFract) >> 32; + + /* apply shifting */ + out1 = in1 >> kShift; + out2 = in2 >> kShift; + + out3 = in3 >> kShift; + out4 = in4 >> kShift; + + /* Store result destination */ + *pDst = out1; + *(pDst + 1) = out2; + + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update pointers to process next sampels */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + } + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + + if(sign == 0) + { + out = in << kShift; + if(in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + } + else + { + out = in >> kShift; + } + + *pDst++ = out; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000000..76c35e6561 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q7.c +* +* Description: Multiplies a Q7 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.7 format. + * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 7 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* C = A * scale */ + /* Scale the inputs and then store the results in the temporary variables. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Packing the individual outputs into 32bit and storing in + * destination buffer in single write */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000000..b8301e63d8 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,243 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q15.c +* +* Description: Shifts the elements of a Q15 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A << shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of shift group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000000..561225a899 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,195 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q31.c +* +* Description: Shifts the elements of a Q31 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ +/** + * @defgroup shift Vector Shift + * + * Shifts the elements of a fixed-point vector by a specified number of bits. + * There are separate functions for Q7, Q15, and Q31 data types. + * The underlying algorithm used is: + * + * 
        
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        
+ *
+ * + * If shift is positive then the elements of the vector are shifted to the left. + * If shift is negative then the elements of the vector are shifted to the right. + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + + q31_t in1, in2, in3, in4; /* Temporary input variables */ + q31_t out1, out2, out3, out4; /* Temporary output variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + in1 = *pSrc; + in2 = *(pSrc + 1); + out1 = in1 << shiftBits; + in3 = *(pSrc + 2); + out2 = in2 << shiftBits; + in4 = *(pSrc + 3); + if(in1 != (out1 >> shiftBits)) + out1 = 0x7FFFFFFF ^ (in1 >> 31); + + if(in2 != (out2 >> shiftBits)) + out2 = 0x7FFFFFFF ^ (in2 >> 31); + + *pDst = out1; + out3 = in3 << shiftBits; + *(pDst + 1) = out2; + out4 = in4 << shiftBits; + + if(in3 != (out3 >> shiftBits)) + out3 = 0x7FFFFFFF ^ (in3 >> 31); + + if(in4 != (out4 >> shiftBits)) + out4 = 0x7FFFFFFF ^ (in4 >> 31); + + *(pDst + 2) = out3; + *(pDst + 3) = out4; + + /* Update destination pointer to process next sampels */ + pSrc += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + *pDst = (in1 >> -shiftBits); + *(pDst + 1) = (in2 >> -shiftBits); + *(pDst + 2) = (in3 >> -shiftBits); + *(pDst + 3) = (in4 >> -shiftBits); + + + pSrc += 4u; + pDst += 4u; + + blkCnt--; + } + + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + + +} + +/** + * @} end of shift group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000000..6dfd25f650 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,215 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q7.c +* +* Description: Processing function for the Q7 Shifting +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * \par Conditions for optimum performance + * Input and output buffers should be aligned by 32-bit + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. + */ + +void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), + __SSAT((in2 << shiftBits), 8), + __SSAT((in3 << shiftBits), 8), + __SSAT((in4 << shiftBits), 8)); + /* Update source pointer to process next sampels */ + pSrc += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + shiftBits = -shiftBits; + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc; + in2 = *(pSrc + 1); + in3 = *(pSrc + 2); + in4 = *(pSrc + 3); + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits), + (in3 >> shiftBits), (in4 >> shiftBits)); + + + pSrc += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + in1 = *pSrc++; + *pDst++ = (in1 >> shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ +} + +/** + * @} end of shift group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000000..4a660db49b --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_sub_f32.c +* +* Description: Floating-point vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicSub Vector Subtraction + * + * Element-by-element subtraction of two vectors. + * + * 
        
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        
+ *
+ * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicSub + * @{ + */ + + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + float32_t inA1, inA2, inA3, inA4; /* temporary variables */ + float32_t inB1, inB2, inB3, inB4; /* temporary variables */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + /* Read 4 input samples from sourceA and sourceB */ + inA1 = *pSrcA; + inB1 = *pSrcB; + inA2 = *(pSrcA + 1); + inB2 = *(pSrcB + 1); + inA3 = *(pSrcA + 2); + inB3 = *(pSrcB + 2); + inA4 = *(pSrcA + 3); + inB4 = *(pSrcB + 3); + + /* dst = srcA - srcB */ + /* subtract and store the result */ + *pDst = inA1 - inB1; + *(pDst + 1) = inA2 - inB2; + *(pDst + 2) = inA3 - inB3; + *(pDst + 3) = inA4 - inB4; + + + /* Update pointers to process next sampels */ + pSrcA += 4u; + pSrcB += 4u; + pDst += 4u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicSub group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000000..d8cc12220a --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q15.c +* +* Description: Q15 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2; + q31_t inB1, inB2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer two samples at a time. */ + inA1 = *__SIMD32(pSrcA)++; + inA2 = *__SIMD32(pSrcA)++; + inB1 = *__SIMD32(pSrcB)++; + inB2 = *__SIMD32(pSrcB)++; + + *__SIMD32(pDst)++ = __QSUB16(inA1, inB1); + *__SIMD32(pDst)++ = __QSUB16(inA2, inB2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000000..34642f32e7 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q31.c +* +* Description: Q31 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inA3, inA4; + q31_t inB1, inB2, inB3, inB4; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + inA1 = *pSrcA++; + inA2 = *pSrcA++; + inB1 = *pSrcB++; + inB2 = *pSrcB++; + + inA3 = *pSrcA++; + inA4 = *pSrcA++; + inB3 = *pSrcB++; + inB4 = *pSrcB++; + + *pDst++ = __QSUB(inA1, inB1); + *pDst++ = __QSUB(inA2, inB2); + *pDst++ = __QSUB(inA3, inB3); + *pDst++ = __QSUB(inA4, inB4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicSub group + */ diff --git a/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000000..adbc7d0c08 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q7.c +* +* Description: Q7 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer 4 samples at a time. */ + *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000000..bf7ab3bed7 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,4689 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.c +* +* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" +#include "arm_common_tables.h" + +/** + * @ingroup groupTransforms + */ + +/** + * @addtogroup CFFT_CIFFT Complex FFT Tables + * @{ + */ + +/** +* \par +* Pseudo code for Generation of Bit reversal Table is +* \par +* 
for(l=1;l <= N/4;l++)    
+* {    
+*   for(i=0;i> 1;    
+*  }
+* \par +* where N = 4096 logN2 = 12 +* \par +* N is the maximum FFT Size supported +*/ + +/* +* @brief Table for bit reversal process +*/ +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, + 0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380, + 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540, + 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, + 0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620, + 0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0, + 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, + 0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, + 0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0, + 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, + 0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150, + 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0, + 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, + 0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0, + 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70, + 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, + 0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, + 0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508, + 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, + 0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8, + 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428, + 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, + 0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, + 0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368, + 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, + 0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, + 0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698, + 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, + 0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38, + 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738, + 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, + 0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578, + 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8, + 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, + 0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, + 0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444, + 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, + 0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324, + 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4, + 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, + 0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, + 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214, + 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, + 0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, + 0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754, + 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, + 0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4, + 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674, + 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, + 0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, + 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c, + 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, + 0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, + 0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc, + 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, + 0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c, + 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec, + 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, + 0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, + 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c, + 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, + 0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, + 0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c, + 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, + 0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc, + 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc, + 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, + 0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582, + 0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142, + 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, + 0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, + 0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2, + 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, + 0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2, + 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512, + 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, + 0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652, + 0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2, + 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, + 0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, + 0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2, + 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, + 0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a, + 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a, + 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, + 0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, + 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a, + 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, + 0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, + 0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a, + 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, + 0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a, + 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a, + 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, + 0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, + 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a, + 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, + 0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, + 0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa, + 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, + 0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46, + 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746, + 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, + 0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526, + 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6, 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+ 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, + 0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, + 0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e, + 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, + 0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e, + 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be, + 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, + 0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, + 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe, + 0x7fe, 0x1 +}; + + +/* +* @brief Floating-point Twiddle factors Table Generation +*/ + + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< 3N/4; i++)    
+* {    
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float32_t twiddleCoef[6144] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999998823451701880f, + 0.001533980186284766f, 0.999995293809576190f, 0.003067956762965976f, + 0.999989411081928400f, 0.004601926120448571f, 0.999981175282601110f, + 0.006135884649154475f, 0.999970586430974140f, 0.007669828739531097f, + 0.999957644551963900f, 0.009203754782059819f, 0.999942349676023910f, + 0.010737659167264491f, 0.999924701839144500f, 0.012271538285719925f, + 0.999904701082852900f, 0.013805388528060391f, 0.999882347454212560f, + 0.015339206284988100f, 0.999857641005823860f, 0.016872987947281710f, + 0.999830581795823400f, 0.018406729905804820f, 0.999801169887884260f, + 0.019940428551514441f, 0.999769405351215280f, 0.021474080275469508f, + 0.999735288260561680f, 0.023007681468839369f, 0.999698818696204250f, + 0.024541228522912288f, 0.999659996743959220f, 0.026074717829103901f, + 0.999618822495178640f, 0.027608145778965740f, 0.999575296046749220f, + 0.029141508764193722f, 0.999529417501093140f, 0.030674803176636626f, + 0.999481186966166950f, 0.032208025408304586f, 0.999430604555461730f, + 0.033741171851377580f, 0.999377670388002850f, 0.035274238898213947f, + 0.999322384588349540f, 0.036807222941358832f, 0.999264747286594420f, + 0.038340120373552694f, 0.999204758618363890f, 0.039872927587739811f, + 0.999142418724816910f, 0.041405640977076739f, 0.999077727752645360f, + 0.042938256934940820f, 0.999010685854073380f, 0.044470771854938668f, + 0.998941293186856870f, 0.046003182130914623f, 0.998869549914283560f, + 0.047535484156959303f, 0.998795456205172410f, 0.049067674327418015f, + 0.998719012233872940f, 0.050599749036899282f, 0.998640218180265270f, + 0.052131704680283324f, 0.998559074229759310f, 0.053663537652730520f, + 0.998475580573294770f, 0.055195244349689934f, 0.998389737407340160f, + 0.056726821166907748f, 0.998301544933892890f, 0.058258264500435752f, + 0.998211003360478190f, 0.059789570746639868f, 0.998118112900149180f, + 0.061320736302208578f, 0.998022873771486240f, 0.062851757564161406f, + 0.997925286198596000f, 0.064382630929857465f, 0.997825350411111640f, + 0.065913352797003805f, 0.997723066644191640f, 0.067443919563664051f, + 0.997618435138519550f, 0.068974327628266746f, 0.997511456140303450f, + 0.070504573389613856f, 0.997402129901275300f, 0.072034653246889332f, + 0.997290456678690210f, 0.073564563599667426f, 0.997176436735326190f, + 0.075094300847921305f, 0.997060070339482960f, 0.076623861392031492f, + 0.996941357764982160f, 0.078153241632794232f, 0.996820299291165670f, + 0.079682437971430126f, 0.996696895202896060f, 0.081211446809592441f, + 0.996571145790554840f, 0.082740264549375692f, 0.996443051350042630f, + 0.084268887593324071f, 0.996312612182778000f, 0.085797312344439894f, + 0.996179828595696980f, 0.087325535206192059f, 0.996044700901251970f, + 0.088853552582524600f, 0.995907229417411720f, 0.090381360877864983f, + 0.995767414467659820f, 0.091908956497132724f, 0.995625256380994310f, + 0.093436335845747787f, 0.995480755491926940f, 0.094963495329638992f, + 0.995333912140482280f, 0.096490431355252593f, 0.995184726672196930f, + 0.098017140329560604f, 0.995033199438118630f, 0.099543618660069319f, + 0.994879330794805620f, 0.101069862754827820f, 0.994723121104325700f, + 0.102595869022436280f, 0.994564570734255420f, 0.104121633872054590f, + 0.994403680057679100f, 0.105647153713410620f, 0.994240449453187900f, + 0.107172424956808840f, 0.994074879304879370f, 0.108697444013138720f, + 0.993906970002356060f, 0.110222207293883060f, 0.993736721940724600f, + 0.111746711211126590f, 0.993564135520595300f, 0.113270952177564350f, + 0.993389211148080650f, 0.114794926606510080f, 0.993211949234794500f, + 0.116318630911904750f, 0.993032350197851410f, 0.117842061508324980f, + 0.992850414459865100f, 0.119365214810991350f, 0.992666142448948020f, + 0.120888087235777080f, 0.992479534598709970f, 0.122410675199216200f, + 0.992290591348257370f, 0.123932975118512160f, 0.992099313142191800f, + 0.125454983411546230f, 0.991905700430609330f, 0.126976696496885870f, + 0.991709753669099530f, 0.128498110793793170f, 0.991511473318743900f, + 0.130019222722233350f, 0.991310859846115440f, 0.131540028702883120f, + 0.991107913723276890f, 0.133060525157139060f, 0.990902635427780010f, + 0.134580708507126170f, 0.990695025442664630f, 0.136100575175706200f, + 0.990485084256457090f, 0.137620121586486040f, 0.990272812363169110f, + 0.139139344163826200f, 0.990058210262297120f, 0.140658239332849210f, + 0.989841278458820530f, 0.142176803519448030f, 0.989622017463200890f, + 0.143695033150294470f, 0.989400427791380380f, 0.145212924652847460f, + 0.989176509964781010f, 0.146730474455361750f, 0.988950264510302990f, + 0.148247678986896030f, 0.988721691960323780f, 0.149764534677321510f, + 0.988490792852696590f, 0.151281037957330220f, 0.988257567730749460f, + 0.152797185258443440f, 0.988022017143283530f, 0.154312973013020100f, + 0.987784141644572180f, 0.155828397654265230f, 0.987543941794359230f, + 0.157343455616238250f, 0.987301418157858430f, 0.158858143333861450f, + 0.987056571305750970f, 0.160372457242928280f, 0.986809401814185530f, + 0.161886393780111830f, 0.986559910264775410f, 0.163399949382973230f, + 0.986308097244598670f, 0.164913120489969890f, 0.986053963346195440f, + 0.166425903540464100f, 0.985797509167567480f, 0.167938294974731170f, + 0.985538735312176060f, 0.169450291233967960f, 0.985277642388941220f, + 0.170961888760301220f, 0.985014231012239840f, 0.172473083996795950f, + 0.984748501801904210f, 0.173983873387463820f, 0.984480455383220930f, + 0.175494253377271430f, 0.984210092386929030f, 0.177004220412148750f, + 0.983937413449218920f, 0.178513770938997510f, 0.983662419211730250f, + 0.180022901405699510f, 0.983385110321551180f, 0.181531608261124970f, + 0.983105487431216290f, 0.183039887955140950f, 0.982823551198705240f, + 0.184547736938619620f, 0.982539302287441240f, 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-0.999995293809576190f, -0.001533980186285111f, -0.999998823451701880f, +}; + +/* +* @brief Q31 Twiddle factors Table +*/ + +/** +* \par +* Example code for Q31 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)    
+* {    
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q31(Fixed point 1.31): +* round(twiddleCoefQ31(i) * pow(2, 31)) +* +*/ + +const q31_t twiddleCoefQ31[6144] = { + 0x7fffffff, 0x0, 0x7ffff621, 0x3243f5, 0x7fffd886, 0x6487e3, 0x7fffa72c, + 0x96cbc1, + 0x7fff6216, 0xc90f88, 0x7fff0943, 0xfb5330, 0x7ffe9cb2, 0x12d96b1, + 0x7ffe1c65, 0x15fda03, + 0x7ffd885a, 0x1921d20, 0x7ffce093, 0x1c45ffe, 0x7ffc250f, 0x1f6a297, + 0x7ffb55ce, 0x228e4e2, + 0x7ffa72d1, 0x25b26d7, 0x7ff97c18, 0x28d6870, 0x7ff871a2, 0x2bfa9a4, + 0x7ff75370, 0x2f1ea6c, + 0x7ff62182, 0x3242abf, 0x7ff4dbd9, 0x3566a96, 0x7ff38274, 0x388a9ea, + 0x7ff21553, 0x3bae8b2, + 0x7ff09478, 0x3ed26e6, 0x7feeffe1, 0x41f6480, 0x7fed5791, 0x451a177, + 0x7feb9b85, 0x483ddc3, + 0x7fe9cbc0, 0x4b6195d, 0x7fe7e841, 0x4e8543e, 0x7fe5f108, 0x51a8e5c, + 0x7fe3e616, 0x54cc7b1, + 0x7fe1c76b, 0x57f0035, 0x7fdf9508, 0x5b137df, 0x7fdd4eec, 0x5e36ea9, + 0x7fdaf519, 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0x8816d327, + 0xd3670446, 0x88054677, 0xd396255a, 0x87f3cc48, 0xd3c54d47, 0x87e2649b, + 0xd3f47c06, 0x87d10f75, + 0xd423b191, 0x87bfccd7, 0xd452eddf, 0x87ae9cc5, 0xd48230e9, 0x879d7f41, + 0xd4b17aa8, 0x878c744d, + 0xd4e0cb15, 0x877b7bec, 0xd5102228, 0x876a9621, 0xd53f7fda, 0x8759c2ef, + 0xd56ee424, 0x87490258, + 0xd59e4eff, 0x8738545e, 0xd5cdc062, 0x8727b905, 0xd5fd3848, 0x8717304e, + 0xd62cb6a8, 0x8706ba3d, + 0xd65c3b7b, 0x86f656d3, 0xd68bc6ba, 0x86e60614, 0xd6bb585e, 0x86d5c802, + 0xd6eaf05f, 0x86c59c9f, + 0xd71a8eb5, 0x86b583ee, 0xd74a335b, 0x86a57df2, 0xd779de47, 0x86958aac, + 0xd7a98f73, 0x8685aa20, + 0xd7d946d8, 0x8675dc4f, 0xd809046e, 0x8666213c, 0xd838c82d, 0x865678eb, + 0xd868920f, 0x8646e35c, + 0xd898620c, 0x86376092, 0xd8c8381d, 0x8627f091, 0xd8f81439, 0x86189359, + 0xd927f65b, 0x860948ef, + 0xd957de7a, 0x85fa1153, 0xd987cc90, 0x85eaec88, 0xd9b7c094, 0x85dbda91, + 0xd9e7ba7f, 0x85ccdb70, + 0xda17ba4a, 0x85bdef28, 0xda47bfee, 0x85af15b9, 0xda77cb63, 0x85a04f28, + 0xdaa7dca1, 0x85919b76, + 0xdad7f3a2, 0x8582faa5, 0xdb08105e, 0x85746cb8, 0xdb3832cd, 0x8565f1b0, + 0xdb685ae9, 0x85578991, + 0xdb9888a8, 0x8549345c, 0xdbc8bc06, 0x853af214, 0xdbf8f4f8, 0x852cc2bb, + 0xdc293379, 0x851ea652, + 0xdc597781, 0x85109cdd, 0xdc89c109, 0x8502a65c, 0xdcba1008, 0x84f4c2d4, + 0xdcea6478, 0x84e6f244, + 0xdd1abe51, 0x84d934b1, 0xdd4b1d8c, 0x84cb8a1b, 0xdd7b8220, 0x84bdf286, + 0xddabec08, 0x84b06df2, + 0xdddc5b3b, 0x84a2fc62, 0xde0ccfb1, 0x84959dd9, 0xde3d4964, 0x84885258, + 0xde6dc84b, 0x847b19e1, + 0xde9e4c60, 0x846df477, 0xdeced59b, 0x8460e21a, 0xdeff63f4, 0x8453e2cf, + 0xdf2ff764, 0x8446f695, + 0xdf608fe4, 0x843a1d70, 0xdf912d6b, 0x842d5762, 0xdfc1cff3, 0x8420a46c, + 0xdff27773, 0x84140490, + 0xe02323e5, 0x840777d0, 0xe053d541, 0x83fafe2e, 0xe0848b7f, 0x83ee97ad, + 0xe0b54698, 0x83e2444d, + 0xe0e60685, 0x83d60412, 0xe116cb3d, 0x83c9d6fc, 0xe14794ba, 0x83bdbd0e, + 0xe17862f3, 0x83b1b649, + 0xe1a935e2, 0x83a5c2b0, 0xe1da0d7e, 0x8399e244, 0xe20ae9c1, 0x838e1507, + 0xe23bcaa2, 0x83825afb, + 0xe26cb01b, 0x8376b422, 0xe29d9a23, 0x836b207d, 0xe2ce88b3, 0x835fa00f, + 0xe2ff7bc3, 0x835432d8, + 0xe330734d, 0x8348d8dc, 0xe3616f48, 0x833d921b, 0xe3926fad, 0x83325e97, + 0xe3c37474, 0x83273e52, + 0xe3f47d96, 0x831c314e, 0xe4258b0a, 0x8311378d, 0xe4569ccb, 0x83065110, + 0xe487b2d0, 0x82fb7dd8, + 0xe4b8cd11, 0x82f0bde8, 0xe4e9eb87, 0x82e61141, 0xe51b0e2a, 0x82db77e5, + 0xe54c34f3, 0x82d0f1d5, + 0xe57d5fda, 0x82c67f14, 0xe5ae8ed8, 0x82bc1fa2, 0xe5dfc1e5, 0x82b1d381, + 0xe610f8f9, 0x82a79ab3, + 0xe642340d, 0x829d753a, 0xe6737319, 0x82936317, 0xe6a4b616, 0x8289644b, + 0xe6d5fcfc, 0x827f78d8, + 0xe70747c4, 0x8275a0c0, 0xe7389665, 0x826bdc04, 0xe769e8d8, 0x82622aa6, + 0xe79b3f16, 0x82588ca7, + 0xe7cc9917, 0x824f0208, 0xe7fdf6d4, 0x82458acc, 0xe82f5844, 0x823c26f3, + 0xe860bd61, 0x8232d67f, + 0xe8922622, 0x82299971, 0xe8c39280, 0x82206fcc, 0xe8f50273, 0x82175990, + 0xe92675f4, 0x820e56be, + 0xe957ecfb, 0x82056758, 0xe9896781, 0x81fc8b60, 0xe9bae57d, 0x81f3c2d7, + 0xe9ec66e8, 0x81eb0dbe, + 0xea1debbb, 0x81e26c16, 0xea4f73ee, 0x81d9dde1, 0xea80ff7a, 0x81d16321, + 0xeab28e56, 0x81c8fbd6, + 0xeae4207a, 0x81c0a801, 0xeb15b5e1, 0x81b867a5, 0xeb474e81, 0x81b03ac2, + 0xeb78ea52, 0x81a82159, + 0xebaa894f, 0x81a01b6d, 0xebdc2b6e, 0x819828fd, 0xec0dd0a8, 0x81904a0c, + 0xec3f78f6, 0x81887e9a, + 0xec71244f, 0x8180c6a9, 0xeca2d2ad, 0x8179223a, 0xecd48407, 0x8171914e, + 0xed063856, 0x816a13e6, + 0xed37ef91, 0x8162aa04, 0xed69a9b3, 0x815b53a8, 0xed9b66b2, 0x815410d4, + 0xedcd2687, 0x814ce188, + 0xedfee92b, 0x8145c5c7, 0xee30ae96, 0x813ebd90, 0xee6276bf, 0x8137c8e6, + 0xee9441a0, 0x8130e7c9, + 0xeec60f31, 0x812a1a3a, 0xeef7df6a, 0x8123603a, 0xef29b243, 0x811cb9ca, + 0xef5b87b5, 0x811626ec, + 0xef8d5fb8, 0x810fa7a0, 0xefbf3a45, 0x81093be8, 0xeff11753, 0x8102e3c4, + 0xf022f6da, 0x80fc9f35, + 0xf054d8d5, 0x80f66e3c, 0xf086bd39, 0x80f050db, 0xf0b8a401, 0x80ea4712, + 0xf0ea8d24, 0x80e450e2, + 0xf11c789a, 0x80de6e4c, 0xf14e665c, 0x80d89f51, 0xf1805662, 0x80d2e3f2, + 0xf1b248a5, 0x80cd3c2f, + 0xf1e43d1c, 0x80c7a80a, 0xf21633c0, 0x80c22784, 0xf2482c8a, 0x80bcba9d, + 0xf27a2771, 0x80b76156, + 0xf2ac246e, 0x80b21baf, 0xf2de2379, 0x80ace9ab, 0xf310248a, 0x80a7cb49, + 0xf342279b, 0x80a2c08b, + 0xf3742ca2, 0x809dc971, 0xf3a63398, 0x8098e5fb, 0xf3d83c77, 0x8094162c, + 0xf40a4735, 0x808f5a02, + 0xf43c53cb, 0x808ab180, 0xf46e6231, 0x80861ca6, 0xf4a07261, 0x80819b74, + 0xf4d28451, 0x807d2dec, + 0xf50497fb, 0x8078d40d, 0xf536ad56, 0x80748dd9, 0xf568c45b, 0x80705b50, + 0xf59add02, 0x806c3c74, + 0xf5ccf743, 0x80683143, 0xf5ff1318, 0x806439c0, 0xf6313077, 0x806055eb, + 0xf6634f59, 0x805c85c4, + 0xf6956fb7, 0x8058c94c, 0xf6c79188, 0x80552084, 0xf6f9b4c6, 0x80518b6b, + 0xf72bd967, 0x804e0a04, + 0xf75dff66, 0x804a9c4d, 0xf79026b9, 0x80474248, 0xf7c24f59, 0x8043fbf6, + 0xf7f4793e, 0x8040c956, + 0xf826a462, 0x803daa6a, 0xf858d0bb, 0x803a9f31, 0xf88afe42, 0x8037a7ac, + 0xf8bd2cef, 0x8034c3dd, + 0xf8ef5cbb, 0x8031f3c2, 0xf9218d9e, 0x802f375d, 0xf953bf91, 0x802c8ead, + 0xf985f28a, 0x8029f9b4, + 0xf9b82684, 0x80277872, 0xf9ea5b75, 0x80250ae7, 0xfa1c9157, 0x8022b114, + 0xfa4ec821, 0x80206af8, + 0xfa80ffcb, 0x801e3895, 0xfab3384f, 0x801c19ea, 0xfae571a4, 0x801a0ef8, + 0xfb17abc2, 0x801817bf, + 0xfb49e6a3, 0x80163440, 0xfb7c223d, 0x8014647b, 0xfbae5e89, 0x8012a86f, + 0xfbe09b80, 0x8011001f, + 0xfc12d91a, 0x800f6b88, 0xfc45174e, 0x800deaad, 0xfc775616, 0x800c7d8c, + 0xfca9956a, 0x800b2427, + 0xfcdbd541, 0x8009de7e, 0xfd0e1594, 0x8008ac90, 0xfd40565c, 0x80078e5e, + 0xfd729790, 0x800683e8, + 0xfda4d929, 0x80058d2f, 0xfdd71b1e, 0x8004aa32, 0xfe095d69, 0x8003daf1, + 0xfe3ba002, 0x80031f6d, + 0xfe6de2e0, 0x800277a6, 0xfea025fd, 0x8001e39b, 0xfed2694f, 0x8001634e, + 0xff04acd0, 0x8000f6bd, + 0xff36f078, 0x80009dea, 0xff69343f, 0x800058d4, 0xff9b781d, 0x8000277a, + 0xffcdbc0b, 0x800009df, + +}; + + +/* +* @brief Q15 Twiddle factors Table +*/ + +/** +* \par +* Example code for Q15 Twiddle factors Generation:: +* \par +* 
for(i = 0; i< 3N/4; i++)    
+* {    
+*	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);    
+*	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);    
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are interleaved fashion +* \par +* Convert Floating point to Q15(Fixed point 1.15): +* round(twiddleCoefQ15(i) * pow(2, 15)) +* +*/ + +const q15_t ALIGN4 twiddleCoefQ15[6144] = { + + 0x7fff, 0x0, 0x7fff, 0x32, 0x7fff, 0x65, 0x7fff, 0x97, + 0x7fff, 0xc9, 0x7fff, 0xfb, 0x7fff, 0x12e, 0x7ffe, 0x160, + 0x7ffe, 0x192, 0x7ffd, 0x1c4, 0x7ffc, 0x1f7, 0x7ffb, 0x229, + 0x7ffa, 0x25b, 0x7ff9, 0x28d, 0x7ff8, 0x2c0, 0x7ff7, 0x2f2, + 0x7ff6, 0x324, 0x7ff5, 0x356, 0x7ff4, 0x389, 0x7ff2, 0x3bb, + 0x7ff1, 0x3ed, 0x7fef, 0x41f, 0x7fed, 0x452, 0x7fec, 0x484, + 0x7fea, 0x4b6, 0x7fe8, 0x4e8, 0x7fe6, 0x51b, 0x7fe4, 0x54d, + 0x7fe2, 0x57f, 0x7fe0, 0x5b1, 0x7fdd, 0x5e3, 0x7fdb, 0x616, + 0x7fd9, 0x648, 0x7fd6, 0x67a, 0x7fd3, 0x6ac, 0x7fd1, 0x6de, + 0x7fce, 0x711, 0x7fcb, 0x743, 0x7fc8, 0x775, 0x7fc5, 0x7a7, + 0x7fc2, 0x7d9, 0x7fbf, 0x80c, 0x7fbc, 0x83e, 0x7fb9, 0x870, + 0x7fb5, 0x8a2, 0x7fb2, 0x8d4, 0x7fae, 0x906, 0x7fab, 0x938, + 0x7fa7, 0x96b, 0x7fa3, 0x99d, 0x7fa0, 0x9cf, 0x7f9c, 0xa01, + 0x7f98, 0xa33, 0x7f94, 0xa65, 0x7f90, 0xa97, 0x7f8b, 0xac9, + 0x7f87, 0xafb, 0x7f83, 0xb2d, 0x7f7e, 0xb60, 0x7f7a, 0xb92, + 0x7f75, 0xbc4, 0x7f71, 0xbf6, 0x7f6c, 0xc28, 0x7f67, 0xc5a, + 0x7f62, 0xc8c, 0x7f5d, 0xcbe, 0x7f58, 0xcf0, 0x7f53, 0xd22, + 0x7f4e, 0xd54, 0x7f49, 0xd86, 0x7f43, 0xdb8, 0x7f3e, 0xdea, + 0x7f38, 0xe1c, 0x7f33, 0xe4e, 0x7f2d, 0xe80, 0x7f27, 0xeb2, + 0x7f22, 0xee4, 0x7f1c, 0xf15, 0x7f16, 0xf47, 0x7f10, 0xf79, + 0x7f0a, 0xfab, 0x7f03, 0xfdd, 0x7efd, 0x100f, 0x7ef7, 0x1041, + 0x7ef0, 0x1073, 0x7eea, 0x10a4, 0x7ee3, 0x10d6, 0x7edd, 0x1108, + 0x7ed6, 0x113a, 0x7ecf, 0x116c, 0x7ec8, 0x119e, 0x7ec1, 0x11cf, + 0x7eba, 0x1201, 0x7eb3, 0x1233, 0x7eac, 0x1265, 0x7ea5, 0x1296, + 0x7e9d, 0x12c8, 0x7e96, 0x12fa, 0x7e8e, 0x132b, 0x7e87, 0x135d, + 0x7e7f, 0x138f, 0x7e78, 0x13c1, 0x7e70, 0x13f2, 0x7e68, 0x1424, + 0x7e60, 0x1455, 0x7e58, 0x1487, 0x7e50, 0x14b9, 0x7e48, 0x14ea, + 0x7e3f, 0x151c, 0x7e37, 0x154d, 0x7e2f, 0x157f, 0x7e26, 0x15b1, + 0x7e1e, 0x15e2, 0x7e15, 0x1614, 0x7e0c, 0x1645, 0x7e03, 0x1677, + 0x7dfb, 0x16a8, 0x7df2, 0x16da, 0x7de9, 0x170b, 0x7de0, 0x173c, + 0x7dd6, 0x176e, 0x7dcd, 0x179f, 0x7dc4, 0x17d1, 0x7dba, 0x1802, + 0x7db1, 0x1833, 0x7da7, 0x1865, 0x7d9e, 0x1896, 0x7d94, 0x18c7, + 0x7d8a, 0x18f9, 0x7d81, 0x192a, 0x7d77, 0x195b, 0x7d6d, 0x198d, + 0x7d63, 0x19be, 0x7d58, 0x19ef, 0x7d4e, 0x1a20, 0x7d44, 0x1a51, + 0x7d3a, 0x1a83, 0x7d2f, 0x1ab4, 0x7d25, 0x1ae5, 0x7d1a, 0x1b16, + 0x7d0f, 0x1b47, 0x7d05, 0x1b78, 0x7cfa, 0x1ba9, 0x7cef, 0x1bda, + 0x7ce4, 0x1c0c, 0x7cd9, 0x1c3d, 0x7cce, 0x1c6e, 0x7cc2, 0x1c9f, + 0x7cb7, 0x1cd0, 0x7cac, 0x1d01, 0x7ca0, 0x1d31, 0x7c95, 0x1d62, + 0x7c89, 0x1d93, 0x7c7e, 0x1dc4, 0x7c72, 0x1df5, 0x7c66, 0x1e26, + 0x7c5a, 0x1e57, 0x7c4e, 0x1e88, 0x7c42, 0x1eb8, 0x7c36, 0x1ee9, + 0x7c2a, 0x1f1a, 0x7c1e, 0x1f4b, 0x7c11, 0x1f7b, 0x7c05, 0x1fac, + 0x7bf9, 0x1fdd, 0x7bec, 0x200e, 0x7bdf, 0x203e, 0x7bd3, 0x206f, + 0x7bc6, 0x209f, 0x7bb9, 0x20d0, 0x7bac, 0x2101, 0x7b9f, 0x2131, + 0x7b92, 0x2162, 0x7b85, 0x2192, 0x7b78, 0x21c3, 0x7b6a, 0x21f3, + 0x7b5d, 0x2224, 0x7b50, 0x2254, 0x7b42, 0x2284, 0x7b34, 0x22b5, + 0x7b27, 0x22e5, 0x7b19, 0x2316, 0x7b0b, 0x2346, 0x7afd, 0x2376, + 0x7aef, 0x23a7, 0x7ae1, 0x23d7, 0x7ad3, 0x2407, 0x7ac5, 0x2437, + 0x7ab7, 0x2467, 0x7aa8, 0x2498, 0x7a9a, 0x24c8, 0x7a8c, 0x24f8, + 0x7a7d, 0x2528, 0x7a6e, 0x2558, 0x7a60, 0x2588, 0x7a51, 0x25b8, + 0x7a42, 0x25e8, 0x7a33, 0x2618, 0x7a24, 0x2648, 0x7a15, 0x2678, + 0x7a06, 0x26a8, 0x79f7, 0x26d8, 0x79e7, 0x2708, 0x79d8, 0x2738, + 0x79c9, 0x2768, 0x79b9, 0x2797, 0x79aa, 0x27c7, 0x799a, 0x27f7, + 0x798a, 0x2827, 0x797a, 0x2856, 0x796a, 0x2886, 0x795b, 0x28b6, + 0x794a, 0x28e5, 0x793a, 0x2915, 0x792a, 0x2945, 0x791a, 0x2974, + 0x790a, 0x29a4, 0x78f9, 0x29d3, 0x78e9, 0x2a03, 0x78d8, 0x2a32, + 0x78c8, 0x2a62, 0x78b7, 0x2a91, 0x78a6, 0x2ac1, 0x7895, 0x2af0, + 0x7885, 0x2b1f, 0x7874, 0x2b4f, 0x7863, 0x2b7e, 0x7851, 0x2bad, + 0x7840, 0x2bdc, 0x782f, 0x2c0c, 0x781e, 0x2c3b, 0x780c, 0x2c6a, + 0x77fb, 0x2c99, 0x77e9, 0x2cc8, 0x77d8, 0x2cf7, 0x77c6, 0x2d26, + 0x77b4, 0x2d55, 0x77a2, 0x2d84, 0x7790, 0x2db3, 0x777e, 0x2de2, + 0x776c, 0x2e11, 0x775a, 0x2e40, 0x7748, 0x2e6f, 0x7736, 0x2e9e, + 0x7723, 0x2ecc, 0x7711, 0x2efb, 0x76fe, 0x2f2a, 0x76ec, 0x2f59, + 0x76d9, 0x2f87, 0x76c7, 0x2fb6, 0x76b4, 0x2fe5, 0x76a1, 0x3013, + 0x768e, 0x3042, 0x767b, 0x3070, 0x7668, 0x309f, 0x7655, 0x30cd, + 0x7642, 0x30fc, 0x762e, 0x312a, 0x761b, 0x3159, 0x7608, 0x3187, + 0x75f4, 0x31b5, 0x75e1, 0x31e4, 0x75cd, 0x3212, 0x75b9, 0x3240, + 0x75a6, 0x326e, 0x7592, 0x329d, 0x757e, 0x32cb, 0x756a, 0x32f9, + 0x7556, 0x3327, 0x7542, 0x3355, 0x752d, 0x3383, 0x7519, 0x33b1, + 0x7505, 0x33df, 0x74f0, 0x340d, 0x74dc, 0x343b, 0x74c7, 0x3469, + 0x74b3, 0x3497, 0x749e, 0x34c4, 0x7489, 0x34f2, 0x7475, 0x3520, + 0x7460, 0x354e, 0x744b, 0x357b, 0x7436, 0x35a9, 0x7421, 0x35d7, + 0x740b, 0x3604, 0x73f6, 0x3632, 0x73e1, 0x365f, 0x73cb, 0x368d, + 0x73b6, 0x36ba, 0x73a0, 0x36e8, 0x738b, 0x3715, 0x7375, 0x3742, + 0x735f, 0x3770, 0x734a, 0x379d, 0x7334, 0x37ca, 0x731e, 0x37f7, + 0x7308, 0x3825, 0x72f2, 0x3852, 0x72dc, 0x387f, 0x72c5, 0x38ac, + 0x72af, 0x38d9, 0x7299, 0x3906, 0x7282, 0x3933, 0x726c, 0x3960, + 0x7255, 0x398d, 0x723f, 0x39ba, 0x7228, 0x39e7, 0x7211, 0x3a13, + 0x71fa, 0x3a40, 0x71e3, 0x3a6d, 0x71cc, 0x3a9a, 0x71b5, 0x3ac6, + 0x719e, 0x3af3, 0x7187, 0x3b20, 0x7170, 0x3b4c, 0x7158, 0x3b79, + 0x7141, 0x3ba5, 0x712a, 0x3bd2, 0x7112, 0x3bfe, 0x70fa, 0x3c2a, + 0x70e3, 0x3c57, 0x70cb, 0x3c83, 0x70b3, 0x3caf, 0x709b, 0x3cdc, + 0x7083, 0x3d08, 0x706b, 0x3d34, 0x7053, 0x3d60, 0x703b, 0x3d8c, + 0x7023, 0x3db8, 0x700b, 0x3de4, 0x6ff2, 0x3e10, 0x6fda, 0x3e3c, + 0x6fc2, 0x3e68, 0x6fa9, 0x3e94, 0x6f90, 0x3ec0, 0x6f78, 0x3eec, + 0x6f5f, 0x3f17, 0x6f46, 0x3f43, 0x6f2d, 0x3f6f, 0x6f14, 0x3f9a, + 0x6efb, 0x3fc6, 0x6ee2, 0x3ff1, 0x6ec9, 0x401d, 0x6eb0, 0x4048, + 0x6e97, 0x4074, 0x6e7d, 0x409f, 0x6e64, 0x40cb, 0x6e4a, 0x40f6, + 0x6e31, 0x4121, 0x6e17, 0x414d, 0x6dfe, 0x4178, 0x6de4, 0x41a3, + 0x6dca, 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0x987e, 0xb4dc, 0x9860, + 0xb505, 0x9843, 0xb52d, 0x9826, 0xb556, 0x9808, 0xb57f, 0x97eb, + 0xb5a8, 0x97ce, 0xb5d1, 0x97b0, 0xb5fa, 0x9793, 0xb623, 0x9776, + 0xb64c, 0x9759, 0xb675, 0x973c, 0xb69e, 0x9720, 0xb6c7, 0x9703, + 0xb6f1, 0x96e6, 0xb71a, 0x96c9, 0xb743, 0x96ad, 0xb76d, 0x9690, + 0xb796, 0x9674, 0xb7c0, 0x9657, 0xb7e9, 0x963b, 0xb813, 0x961f, + 0xb83c, 0x9603, 0xb866, 0x95e6, 0xb890, 0x95ca, 0xb8b9, 0x95ae, + 0xb8e3, 0x9592, 0xb90d, 0x9577, 0xb937, 0x955b, 0xb961, 0x953f, + 0xb98b, 0x9523, 0xb9b5, 0x9508, 0xb9df, 0x94ec, 0xba09, 0x94d0, + 0xba33, 0x94b5, 0xba5d, 0x949a, 0xba87, 0x947e, 0xbab1, 0x9463, + 0xbadc, 0x9448, 0xbb06, 0x942d, 0xbb30, 0x9412, 0xbb5b, 0x93f7, + 0xbb85, 0x93dc, 0xbbb0, 0x93c1, 0xbbda, 0x93a6, 0xbc05, 0x938b, + 0xbc2f, 0x9371, 0xbc5a, 0x9356, 0xbc85, 0x933c, 0xbcaf, 0x9321, + 0xbcda, 0x9307, 0xbd05, 0x92ec, 0xbd30, 0x92d2, 0xbd5b, 0x92b8, + 0xbd86, 0x929e, 0xbdb1, 0x9284, 0xbddc, 0x926a, 0xbe07, 0x9250, + 0xbe32, 0x9236, 0xbe5d, 0x921c, 0xbe88, 0x9202, 0xbeb3, 0x91e9, + 0xbedf, 0x91cf, 0xbf0a, 0x91b6, 0xbf35, 0x919c, 0xbf61, 0x9183, + 0xbf8c, 0x9169, 0xbfb8, 0x9150, 0xbfe3, 0x9137, 0xc00f, 0x911e, + 0xc03a, 0x9105, 0xc066, 0x90ec, 0xc091, 0x90d3, 0xc0bd, 0x90ba, + 0xc0e9, 0x90a1, 0xc114, 0x9088, 0xc140, 0x9070, 0xc16c, 0x9057, + 0xc198, 0x903e, 0xc1c4, 0x9026, 0xc1f0, 0x900e, 0xc21c, 0x8ff5, + 0xc248, 0x8fdd, 0xc274, 0x8fc5, 0xc2a0, 0x8fad, 0xc2cc, 0x8f95, + 0xc2f8, 0x8f7d, 0xc324, 0x8f65, 0xc351, 0x8f4d, 0xc37d, 0x8f35, + 0xc3a9, 0x8f1d, 0xc3d6, 0x8f06, 0xc402, 0x8eee, 0xc42e, 0x8ed6, + 0xc45b, 0x8ebf, 0xc487, 0x8ea8, 0xc4b4, 0x8e90, 0xc4e0, 0x8e79, + 0xc50d, 0x8e62, 0xc53a, 0x8e4b, 0xc566, 0x8e34, 0xc593, 0x8e1d, + 0xc5c0, 0x8e06, 0xc5ed, 0x8def, 0xc619, 0x8dd8, 0xc646, 0x8dc1, + 0xc673, 0x8dab, 0xc6a0, 0x8d94, 0xc6cd, 0x8d7e, 0xc6fa, 0x8d67, + 0xc727, 0x8d51, 0xc754, 0x8d3b, 0xc781, 0x8d24, 0xc7ae, 0x8d0e, + 0xc7db, 0x8cf8, 0xc809, 0x8ce2, 0xc836, 0x8ccc, 0xc863, 0x8cb6, + 0xc890, 0x8ca1, 0xc8be, 0x8c8b, 0xc8eb, 0x8c75, 0xc918, 0x8c60, + 0xc946, 0x8c4a, 0xc973, 0x8c35, 0xc9a1, 0x8c1f, 0xc9ce, 0x8c0a, + 0xc9fc, 0x8bf5, 0xca29, 0x8bdf, 0xca57, 0x8bca, 0xca85, 0x8bb5, + 0xcab2, 0x8ba0, 0xcae0, 0x8b8b, 0xcb0e, 0x8b77, 0xcb3c, 0x8b62, + 0xcb69, 0x8b4d, 0xcb97, 0x8b39, 0xcbc5, 0x8b24, 0xcbf3, 0x8b10, + 0xcc21, 0x8afb, 0xcc4f, 0x8ae7, 0xcc7d, 0x8ad3, 0xccab, 0x8abe, + 0xccd9, 0x8aaa, 0xcd07, 0x8a96, 0xcd35, 0x8a82, 0xcd63, 0x8a6e, + 0xcd92, 0x8a5a, 0xcdc0, 0x8a47, 0xcdee, 0x8a33, 0xce1c, 0x8a1f, + 0xce4b, 0x8a0c, 0xce79, 0x89f8, 0xcea7, 0x89e5, 0xced6, 0x89d2, + 0xcf04, 0x89be, 0xcf33, 0x89ab, 0xcf61, 0x8998, 0xcf90, 0x8985, + 0xcfbe, 0x8972, 0xcfed, 0x895f, 0xd01b, 0x894c, 0xd04a, 0x8939, + 0xd079, 0x8927, 0xd0a7, 0x8914, 0xd0d6, 0x8902, 0xd105, 0x88ef, + 0xd134, 0x88dd, 0xd162, 0x88ca, 0xd191, 0x88b8, 0xd1c0, 0x88a6, + 0xd1ef, 0x8894, 0xd21e, 0x8882, 0xd24d, 0x8870, 0xd27c, 0x885e, + 0xd2ab, 0x884c, 0xd2da, 0x883a, 0xd309, 0x8828, 0xd338, 0x8817, + 0xd367, 0x8805, 0xd396, 0x87f4, 0xd3c5, 0x87e2, 0xd3f4, 0x87d1, + 0xd424, 0x87c0, 0xd453, 0x87af, 0xd482, 0x879d, 0xd4b1, 0x878c, + 0xd4e1, 0x877b, 0xd510, 0x876b, 0xd53f, 0x875a, 0xd56f, 0x8749, + 0xd59e, 0x8738, 0xd5ce, 0x8728, 0xd5fd, 0x8717, 0xd62d, 0x8707, + 0xd65c, 0x86f6, 0xd68c, 0x86e6, 0xd6bb, 0x86d6, 0xd6eb, 0x86c6, + 0xd71b, 0x86b6, 0xd74a, 0x86a5, 0xd77a, 0x8696, 0xd7aa, 0x8686, + 0xd7d9, 0x8676, 0xd809, 0x8666, 0xd839, 0x8656, 0xd869, 0x8647, + 0xd898, 0x8637, 0xd8c8, 0x8628, 0xd8f8, 0x8619, 0xd928, 0x8609, + 0xd958, 0x85fa, 0xd988, 0x85eb, 0xd9b8, 0x85dc, 0xd9e8, 0x85cd, + 0xda18, 0x85be, 0xda48, 0x85af, 0xda78, 0x85a0, 0xdaa8, 0x8592, + 0xdad8, 0x8583, 0xdb08, 0x8574, 0xdb38, 0x8566, 0xdb68, 0x8558, + 0xdb99, 0x8549, 0xdbc9, 0x853b, 0xdbf9, 0x852d, 0xdc29, 0x851f, + 0xdc59, 0x8511, 0xdc8a, 0x8503, 0xdcba, 0x84f5, 0xdcea, 0x84e7, + 0xdd1b, 0x84d9, 0xdd4b, 0x84cc, 0xdd7c, 0x84be, 0xddac, 0x84b0, + 0xdddc, 0x84a3, 0xde0d, 0x8496, 0xde3d, 0x8488, 0xde6e, 0x847b, + 0xde9e, 0x846e, 0xdecf, 0x8461, 0xdeff, 0x8454, 0xdf30, 0x8447, + 0xdf61, 0x843a, 0xdf91, 0x842d, 0xdfc2, 0x8421, 0xdff2, 0x8414, + 0xe023, 0x8407, 0xe054, 0x83fb, 0xe085, 0x83ef, 0xe0b5, 0x83e2, + 0xe0e6, 0x83d6, 0xe117, 0x83ca, 0xe148, 0x83be, 0xe178, 0x83b2, + 0xe1a9, 0x83a6, 0xe1da, 0x839a, 0xe20b, 0x838e, 0xe23c, 0x8382, + 0xe26d, 0x8377, 0xe29e, 0x836b, 0xe2cf, 0x8360, 0xe2ff, 0x8354, + 0xe330, 0x8349, 0xe361, 0x833e, 0xe392, 0x8332, 0xe3c3, 0x8327, + 0xe3f4, 0x831c, 0xe426, 0x8311, 0xe457, 0x8306, 0xe488, 0x82fb, + 0xe4b9, 0x82f1, 0xe4ea, 0x82e6, 0xe51b, 0x82db, 0xe54c, 0x82d1, + 0xe57d, 0x82c6, 0xe5af, 0x82bc, 0xe5e0, 0x82b2, 0xe611, 0x82a8, + 0xe642, 0x829d, 0xe673, 0x8293, 0xe6a5, 0x8289, 0xe6d6, 0x827f, + 0xe707, 0x8276, 0xe739, 0x826c, 0xe76a, 0x8262, 0xe79b, 0x8259, + 0xe7cd, 0x824f, 0xe7fe, 0x8246, 0xe82f, 0x823c, 0xe861, 0x8233, + 0xe892, 0x822a, 0xe8c4, 0x8220, 0xe8f5, 0x8217, 0xe926, 0x820e, + 0xe958, 0x8205, 0xe989, 0x81fd, 0xe9bb, 0x81f4, 0xe9ec, 0x81eb, + 0xea1e, 0x81e2, 0xea4f, 0x81da, 0xea81, 0x81d1, 0xeab3, 0x81c9, + 0xeae4, 0x81c1, 0xeb16, 0x81b8, 0xeb47, 0x81b0, 0xeb79, 0x81a8, + 0xebab, 0x81a0, 0xebdc, 0x8198, 0xec0e, 0x8190, 0xec3f, 0x8188, + 0xec71, 0x8181, 0xeca3, 0x8179, 0xecd5, 0x8172, 0xed06, 0x816a, + 0xed38, 0x8163, 0xed6a, 0x815b, 0xed9b, 0x8154, 0xedcd, 0x814d, + 0xedff, 0x8146, 0xee31, 0x813f, 0xee62, 0x8138, 0xee94, 0x8131, + 0xeec6, 0x812a, 0xeef8, 0x8123, 0xef2a, 0x811d, 0xef5c, 0x8116, + 0xef8d, 0x8110, 0xefbf, 0x8109, 0xeff1, 0x8103, 0xf023, 0x80fd, + 0xf055, 0x80f6, 0xf087, 0x80f0, 0xf0b9, 0x80ea, 0xf0eb, 0x80e4, + 0xf11c, 0x80de, 0xf14e, 0x80d9, 0xf180, 0x80d3, 0xf1b2, 0x80cd, + 0xf1e4, 0x80c8, 0xf216, 0x80c2, 0xf248, 0x80bd, 0xf27a, 0x80b7, + 0xf2ac, 0x80b2, 0xf2de, 0x80ad, 0xf310, 0x80a8, 0xf342, 0x80a3, + 0xf374, 0x809e, 0xf3a6, 0x8099, 0xf3d8, 0x8094, 0xf40a, 0x808f, + 0xf43c, 0x808b, 0xf46e, 0x8086, 0xf4a0, 0x8082, 0xf4d3, 0x807d, + 0xf505, 0x8079, 0xf537, 0x8075, 0xf569, 0x8070, 0xf59b, 0x806c, + 0xf5cd, 0x8068, 0xf5ff, 0x8064, 0xf631, 0x8060, 0xf663, 0x805d, + 0xf695, 0x8059, 0xf6c8, 0x8055, 0xf6fa, 0x8052, 0xf72c, 0x804e, + 0xf75e, 0x804b, 0xf790, 0x8047, 0xf7c2, 0x8044, 0xf7f4, 0x8041, + 0xf827, 0x803e, 0xf859, 0x803b, 0xf88b, 0x8038, 0xf8bd, 0x8035, + 0xf8ef, 0x8032, 0xf922, 0x802f, 0xf954, 0x802d, 0xf986, 0x802a, + 0xf9b8, 0x8027, 0xf9ea, 0x8025, 0xfa1d, 0x8023, 0xfa4f, 0x8020, + 0xfa81, 0x801e, 0xfab3, 0x801c, 0xfae5, 0x801a, 0xfb18, 0x8018, + 0xfb4a, 0x8016, 0xfb7c, 0x8014, 0xfbae, 0x8013, 0xfbe1, 0x8011, + 0xfc13, 0x800f, 0xfc45, 0x800e, 0xfc77, 0x800c, 0xfcaa, 0x800b, + 0xfcdc, 0x800a, 0xfd0e, 0x8009, 0xfd40, 0x8008, 0xfd73, 0x8007, + 0xfda5, 0x8006, 0xfdd7, 0x8005, 0xfe09, 0x8004, 0xfe3c, 0x8003, + 0xfe6e, 0x8002, 0xfea0, 0x8002, 0xfed2, 0x8001, 0xff05, 0x8001, + 0xff37, 0x8001, 0xff69, 0x8000, 0xff9b, 0x8000, 0xffce, 0x8000, +}; + +/** + * @} end of CFFT_CIFFT group + */ + +/* +* @brief Q15 table for reciprocal +*/ +const q15_t ALIGN4 armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +/* +* @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000000..31bbaa7a80 --- /dev/null +++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. February 2012 +* $Revision: V1.1.0 +* +* Project: CMSIS DSP Library +* Title: arm_cmplx_conj_f32.c +* +* Description: Floating-point complex conjugate. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.1.0 2012/02/15 +* Updated with more optimizations, bug fixes and minor API changes. +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* ---------------------------------------------------------------------------- */ +#include "arm_math.h" + +/** + * @ingroup groupCmplxMath + */ + +/** + * @defgroup cmplx_conj Complex Conjugate + * + * Conjugates the elements of a complex data vector. + * + * The pSrc points to the source data and + * pDst points to the where the result should be written. + * numSamples specifies the number of complex samples + * and the data in each array is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * Each array has a total of 2*numSamples values. + * The underlying algorithm is used: + * + * 
        
+ * for(n=0; n        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup cmplx_conj        
+ * @{        
+ */
+
+/**        
+ * @brief  Floating-point complex conjugate.        
+ * @param  *pSrc points to the input vector        
+ * @param  *pDst points to the output vector        
+ * @param  numSamples number of complex samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inR1, inR2, inR3, inR4;
+  float32_t inI1, inI2, inI3, inI4;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* read real input samples */
+    inR1 = pSrc[0];
+    /* store real samples to destination */
+    pDst[0] = inR1;
+    inR2 = pSrc[2];
+    pDst[2] = inR2;
+    inR3 = pSrc[4];
+    pDst[4] = inR3;
+    inR4 = pSrc[6];
+    pDst[6] = inR4;
+
+    /* read imaginary input samples */
+    inI1 = pSrc[1];
+    inI2 = pSrc[3];
+
+    /* conjugate input */
+    inI1 = -inI1;
+
+    /* read imaginary input samples */
+    inI3 = pSrc[5];
+
+    /* conjugate input */
+    inI2 = -inI2;
+
+    /* read imaginary input samples */
+    inI4 = pSrc[7];
+
+    /* conjugate input */
+    inI3 = -inI3;
+
+    /* store imaginary samples to destination */
+    pDst[1] = inI1;
+    pDst[3] = inI2;
+
+    /* conjugate input */
+    inI4 = -inI4;
+
+    /* store imaginary samples to destination */
+    pDst[5] = inI3;
+
+    /* increment source pointer by 8 to process next sampels */
+    pSrc += 8u;
+
+    /* store imaginary sample to destination */
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to store next samples */
+    pDst += 8u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_conj group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 0000000000..c5a3703157
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_conj_q15.c    
+*    
+* Description:	Q15 complex conjugate.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_conj    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex conjugate.    
+ * @param  *pSrc points to the input vector    
+ * @param  *pDst points to the output vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t zero = 0;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    in1 = __QASX(zero, in1);
+    in2 = __QASX(zero, in2);
+    in3 = __QASX(zero, in3);
+    in4 = __QASX(zero, in4);
+
+#else
+
+    in1 = __QSAX(zero, in1);
+    in2 = __QSAX(zero, in2);
+    in3 = __QSAX(zero, in3);
+    in4 = __QSAX(zero, in4);
+
+#endif //       #ifndef ARM_MATH_BIG_ENDIAN
+
+    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+    *__SIMD32(pDst)++ = in1;
+    *__SIMD32(pDst)++ = in2;
+    *__SIMD32(pDst)++ = in3;
+    *__SIMD32(pDst)++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  q15_t in;
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of cmplx_conj group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 0000000000..7475962d53
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,172 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_conj_q31.c    
+*    
+* Description:	Q31 complex conjugate.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @addtogroup cmplx_conj        
+ * @{        
+ */
+
+/**        
+ * @brief  Q31 complex conjugate.        
+ * @param  *pSrc points to the input vector        
+ * @param  *pDst points to the output vector        
+ * @param  numSamples number of complex samples in each vector        
+ * @return none.        
+ *        
+ * Scaling and Overflow Behavior:        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.        
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */
+  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    /* read real input sample */
+    inR1 = pSrc[0];
+    /* store real input sample */
+    pDst[0] = inR1;
+
+    /* read imaginary input sample */
+    inI1 = pSrc[1];
+
+    /* read real input sample */
+    inR2 = pSrc[2];
+    /* store real input sample */
+    pDst[2] = inR2;
+
+    /* read imaginary input sample */
+    inI2 = pSrc[3];
+
+    /* negate imaginary input sample */
+    inI1 = __QSUB(0, inI1);
+
+    /* read real input sample */
+    inR3 = pSrc[4];
+    /* store real input sample */
+    pDst[4] = inR3;
+
+    /* read imaginary input sample */
+    inI3 = pSrc[5];
+
+    /* negate imaginary input sample */
+    inI2 = __QSUB(0, inI2);
+
+    /* read real input sample */
+    inR4 = pSrc[6];
+    /* store real input sample */
+    pDst[6] = inR4;
+
+    /* negate imaginary input sample */
+    inI3 = __QSUB(0, inI3);
+
+    /* store imaginary input sample */
+    inI4 = pSrc[7];
+
+    /* store imaginary input samples */
+    pDst[1] = inI1;
+
+    /* negate imaginary input sample */
+    inI4 = __QSUB(0, inI4);
+
+    /* store imaginary input samples */
+    pDst[3] = inI2;
+
+    /* increment source pointer by 8 to proecess next samples */
+    pSrc += 8u;
+
+    /* store imaginary input samples */
+    pDst[5] = inI3;
+    pDst[7] = inI4;
+
+    /* increment destination pointer by 8 to process next samples */
+    pDst += 8u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_conj group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 0000000000..4f265d6902
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_f32.c    
+*    
+* Description:	Floating-point complex dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @defgroup cmplx_dot_prod Complex Dot Product    
+ *    
+ * Computes the dot product of two complex vectors.    
+ * The vectors are multiplied element-by-element and then summed.    
+ *   
+ * The pSrcA points to the first complex input vector and    
+ * pSrcB points to the second complex input vector.    
+ * numSamples specifies the number of complex samples    
+ * and the data in each array is stored in an interleaved fashion    
+ * (real, imag, real, imag, ...).    
+ * Each array has a total of 2*numSamples values.    
+ *    
+ * The underlying algorithm is used:    
+ * 
    
+ * realResult=0;    
+ * imagResult=0;    
+ * for(n=0; n    
+ *    
+ * There are separate functions for floating-point, Q15, and Q31 data types.    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Floating-point complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 0000000000..33df820a5c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_q15.c    
+*    
+* Description:	Processing function for the Q15 Complex Dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.    
+ * As a final step, the accumulators are converted to 8.24 format.    
+ * The return results realResult and imagResult are in 8.24 format.    
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum) >> 6;
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 0000000000..d371dff8b2
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_dot_prod_q31.c    
+*    
+* Description:	Q31 complex dot product    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_dot_prod    
+ * @{    
+ */
+
+/**    
+ * @brief  Q31 complex dot product    
+ * @param  *pSrcA points to the first input vector    
+ * @param  *pSrcB points to the second input vector    
+ * @param  numSamples number of complex samples in each vector    
+ * @param  *realResult real part of the result returned here    
+ * @param  *imagResult imaginary part of the result returned here    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.    
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.    
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.    
+ * The return results realResult and imagResult are in 16.48 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**    
+ * @} end of cmplx_dot_prod group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 0000000000..59bbc27422
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_f32.c    
+*    
+* Description:	Floating-point complex magnitude.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @defgroup cmplx_mag Complex Magnitude    
+ *    
+ * Computes the magnitude of the elements of a complex data vector.    
+ *   
+ * The pSrc points to the source data and    
+ * pDst points to the where the result should be written.    
+ * numSamples specifies the number of complex samples    
+ * in the input array and the data is stored in an interleaved fashion    
+ * (real, imag, real, imag, ...).    
+ * The input array has a total of 2*numSamples values;    
+ * the output array has a total of numSamples values.    
+ * The underlying algorithm is used:    
+ *    
+ * 
    
+ * for(n=0; n    
+ *    
+ * There are separate functions for floating-point, Q15, and Q31 data types.    
+ */
+
+/**    
+ * @addtogroup cmplx_mag    
+ * @{    
+ */
+/**    
+ * @brief Floating-point complex magnitude.    
+ * @param[in]       *pSrc points to complex input buffer    
+ * @param[out]      *pDst points to real output buffer    
+ * @param[in]       numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of cmplx_mag group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 0000000000..122ca8bc1f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_q15.c    
+*    
+* Description:	Q15 complex magnitude.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q15 complex magnitude    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.    
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of cmplx_mag group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 0000000000..59384f5dc3
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_q31.c    
+*    
+* Description:	Q31 complex magnitude    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @addtogroup cmplx_mag        
+ * @{        
+ */
+
+/**        
+ * @brief  Q31 complex magnitude        
+ * @param  *pSrc points to the complex input vector        
+ * @param  *pDst points to the real output vector        
+ * @param  numSamples number of complex samples in the input vector        
+ * @return none.        
+ *        
+ * Scaling and Overflow Behavior:        
+ * \par        
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.        
+ * Input down scaling is not required.        
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */
+  q31_t out1, out2, out3, out4;                  /* Accumulators */
+  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* read complex input from source buffer */
+    real1 = pSrc[0];
+    imag1 = pSrc[1];
+    real2 = pSrc[2];
+    imag2 = pSrc[3];
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* read complex input from source buffer */
+    real1 = pSrc[4];
+    imag1 = pSrc[5];
+    real2 = pSrc[6];
+    imag2 = pSrc[7];
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[0]);
+
+    /* calculate power of input values */
+    mul1 = (q63_t) real1 *real1;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[1]);
+
+    /* calculate power of input values */
+    mul2 = (q63_t) imag1 *imag1;
+    mul3 = (q63_t) real2 *real2;
+    mul4 = (q63_t) imag2 *imag2;
+
+    /* get the result to 3.29 format */
+    out1 = (q31_t) (mul1 >> 33);
+    out2 = (q31_t) (mul2 >> 33);
+    out3 = (q31_t) (mul3 >> 33);
+    out4 = (q31_t) (mul4 >> 33);
+
+    /* add real and imaginary accumulators */
+    out1 = out1 + out2;
+    out3 = out3 + out4;
+
+    /* calculate square root */
+    arm_sqrt_q31(out1, &pDst[2]);
+
+    /* increment destination by 8 to process next samples */
+    pSrc += 8u;
+
+    /* calculate square root */
+    arm_sqrt_q31(out3, &pDst[3]);
+
+    /* increment destination by 4 to process next samples */
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_mag group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 0000000000..7350fd1c9a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_f32.c    
+*    
+* Description:	Floating-point complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared        
+ *        
+ * Computes the magnitude squared of the elements of a complex data vector.        
+ *       
+ * The pSrc points to the source data and        
+ * pDst points to the where the result should be written.        
+ * numSamples specifies the number of complex samples        
+ * in the input array and the data is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The input array has a total of 2*numSamples values;        
+ * the output array has a total of numSamples values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * 
        
+ * for(n=0; n        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup cmplx_mag_squared        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex magnitude squared        
+ * @param[in]  *pSrc points to the complex input vector        
+ * @param[out]  *pDst points to the real output vector        
+ * @param[in]  numSamples number of complex samples in the input vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */
+  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */
+  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */
+  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    /* read real input sample from source buffer */
+    real1 = pSrc[0];
+    /* read imaginary input sample from source buffer */
+    imag1 = pSrc[1];
+
+    /* calculate power of real value */
+    mul1 = real1 * real1;
+
+    /* read real input sample from source buffer */
+    real2 = pSrc[2];
+
+    /* calculate power of imaginary value */
+    mul2 = imag1 * imag1;
+
+    /* read imaginary input sample from source buffer */
+    imag2 = pSrc[3];
+
+    /* calculate power of real value */
+    mul3 = real2 * real2;
+
+    /* read real input sample from source buffer */
+    real3 = pSrc[4];
+
+    /* calculate power of imaginary value */
+    mul4 = imag2 * imag2;
+
+    /* read imaginary input sample from source buffer */
+    imag3 = pSrc[5];
+
+    /* calculate power of real value */
+    mul5 = real3 * real3;
+    /* calculate power of imaginary value */
+    mul6 = imag3 * imag3;
+
+    /* read real input sample from source buffer */
+    real4 = pSrc[6];
+
+    /* accumulate real and imaginary powers */
+    out1 = mul1 + mul2;
+
+    /* read imaginary input sample from source buffer */
+    imag4 = pSrc[7];
+
+    /* accumulate real and imaginary powers */
+    out2 = mul3 + mul4;
+
+    /* calculate power of real value */
+    mul7 = real4 * real4;
+    /* calculate power of imaginary value */
+    mul8 = imag4 * imag4;
+
+    /* store output to destination */
+    pDst[0] = out1;
+
+    /* accumulate real and imaginary powers */
+    out3 = mul5 + mul6;
+
+    /* store output to destination */
+    pDst[1] = out2;
+
+    /* accumulate real and imaginary powers */
+    out4 = mul7 + mul8;
+
+    /* store output to destination */
+    pDst[2] = out3;
+
+    /* increment destination pointer by 8 to process next samples */
+    pSrc += 8u;
+
+    /* store output to destination */
+    pDst[3] = out4;
+
+    /* increment destination pointer by 4 to process next samples */
+    pDst += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of cmplx_mag_squared group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 0000000000..623229b8f7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_q15.c    
+*    
+* Description:	Q15 complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag_squared    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex magnitude squared    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in1, in2, in3, in4;
+  q31_t acc2, acc3;
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    in2 = *__SIMD32(pSrc)++;
+    in3 = *__SIMD32(pSrc)++;
+    in4 = *__SIMD32(pSrc)++;
+
+    acc0 = __SMUAD(in1, in1);
+    acc1 = __SMUAD(in2, in2);
+    acc2 = __SMUAD(in3, in3);
+    acc3 = __SMUAD(in4, in4);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+    *pDst++ = (q15_t) (acc1 >> 17);
+    *pDst++ = (q15_t) (acc2 >> 17);
+    *pDst++ = (q15_t) (acc3 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    in1 = *__SIMD32(pSrc)++;
+    acc0 = __SMUAD(in1, in1);
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (acc0 >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of cmplx_mag_squared group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 0000000000..d45ccfab2f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cmplx_mag_squared_q31.c    
+*    
+* Description:	Q31 complex magnitude squared.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup cmplx_mag_squared    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex magnitude squared    
+ * @param  *pSrc points to the complex input vector    
+ * @param  *pDst points to the real output vector    
+ * @param  numSamples number of complex samples in the input vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of cmplx_mag_squared group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 0000000000..2ec9ee862b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_f32.c    
+*    
+* Description:	Floating-point complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication        
+ *        
+ * Multiplies a complex vector by another complex vector and generates a complex result.        
+ * The data in the complex arrays is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The parameter numSamples represents the number of complex        
+ * samples processed.  The complex arrays have a total of 2*numSamples        
+ * real values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * 
        
+ * for(n=0; n        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup CmplxByCmplxMult        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex-by-complex multiplication        
+ * @param[in]  *pSrcA points to the first input vector        
+ * @param[in]  *pSrcB points to the second input vector        
+ * @param[out]  *pDst  points to the output vector        
+ * @param[in]  numSamples number of complex samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */
+  float32_t acc1, acc2, acc3, acc4;
+
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA;                /* A[2 * i] */
+    c1 = *pSrcB;                /* B[2 * i] */
+
+    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */
+    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */
+
+    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */
+    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */
+    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */
+    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */
+    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */
+
+    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */
+    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */
+    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */
+
+    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */
+    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */
+    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */
+    acc1 = (a1 * c1);
+
+    d1 = *(pSrcB + 5);
+    acc2 = (b1 * c1);
+
+    *(pDst + 2) = acc3;
+    *(pDst + 3) = acc4;
+
+    a2 = *(pSrcA + 6);
+    acc1 -= (b1 * d1);
+
+    c2 = *(pSrcB + 6);
+    acc2 += (a1 * d1);
+
+    b2 = *(pSrcA + 7);
+    acc3 = (a2 * c2);
+
+    d2 = *(pSrcB + 7);
+    acc4 = (b2 * c2);
+
+    *(pDst + 4) = acc1;
+    pSrcA += 8u;
+
+    acc3 -= (b2 * d2);
+    acc4 += (a2 * d2);
+
+    *(pDst + 5) = acc2;
+    pSrcB += 8u;
+
+    *(pDst + 6) = acc3;
+    *(pDst + 7) = acc4;
+
+    pDst += 8u;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a1 = *pSrcA++;
+    b1 = *pSrcA++;
+    c1 = *pSrcB++;
+    d1 = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a1 * c1) - (b1 * d1);
+    *pDst++ = (a1 * d1) + (b1 * c1);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of CmplxByCmplxMult group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 0000000000..0219aea48a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_q15.c    
+*    
+* Description:	Q15 complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByCmplxMult    
+ * @{    
+ */
+
+/**    
+ * @brief  Q15 complex-by-complex multiplication    
+ * @param[in]  *pSrcA points to the first input vector    
+ * @param[in]  *pSrcB points to the second input vector    
+ * @param[out]  *pDst  points to the output vector    
+ * @param[in]  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of CmplxByCmplxMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 0000000000..13fc060a2e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,318 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_cmplx_q31.c    
+*    
+* Description:	Q31 complex-by-complex multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByCmplxMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex-by-complex multiplication    
+ * @param[in]  *pSrcA points to the first input vector    
+ * @param[in]  *pSrcB points to the second input vector    
+ * @param[out]  *pDst  points to the output vector    
+ * @param[in]  numSamples number of complex samples in each vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
+ * Input down scaling is not required.    
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t mul1, mul2, mul3, mul4;
+  q31_t out1, out2;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.     
+   ** a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.     
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    mul1 = (q31_t) (((q63_t) a * c) >> 32);
+    mul2 = (q31_t) (((q63_t) b * d) >> 32);
+    mul3 = (q31_t) (((q63_t) a * d) >> 32);
+    mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+    mul1 = (mul1 >> 1);
+    mul2 = (mul2 >> 1);
+    mul3 = (mul3 >> 1);
+    mul4 = (mul4 >> 1);
+
+    out1 = mul1 - mul2;
+    out2 = mul3 + mul4;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = out1;
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = out2;
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of CmplxByCmplxMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 0000000000..7a5bdf9cda
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_f32.c    
+*    
+* Description:	Floating-point complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupCmplxMath        
+ */
+
+/**        
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication        
+ *        
+ * Multiplies a complex vector by a real vector and generates a complex result.        
+ * The data in the complex arrays is stored in an interleaved fashion        
+ * (real, imag, real, imag, ...).        
+ * The parameter numSamples represents the number of complex        
+ * samples processed.  The complex arrays have a total of 2*numSamples        
+ * real values while the real array has a total of numSamples        
+ * real values.        
+ *        
+ * The underlying algorithm is used:        
+ *        
+ * 
        
+ * for(n=0; n        
+ *        
+ * There are separate functions for floating-point, Q15, and Q31 data types.        
+ */
+
+/**        
+ * @addtogroup CmplxByRealMult        
+ * @{        
+ */
+
+
+/**        
+ * @brief  Floating-point complex-by-real multiplication        
+ * @param[in]  *pSrcCmplx points to the complex input vector        
+ * @param[in]  *pSrcReal points to the real input vector        
+ * @param[out]  *pCmplxDst points to the complex output vector        
+ * @param[in]  numSamples number of samples in each vector        
+ * @return none.        
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */
+  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */
+  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */
+  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */
+  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read input from complex input buffer */
+    inA1 = pSrcCmplx[0];
+    inA2 = pSrcCmplx[1];
+    /* read input from real input buffer */
+    inB1 = pSrcReal[0];
+
+    /* read input from complex input buffer */
+    inA3 = pSrcCmplx[2];
+
+    /* multiply complex buffer real input with real buffer input */
+    out1 = inA1 * inB1;
+
+    /* read input from complex input buffer */
+    inA4 = pSrcCmplx[3];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out2 = inA2 * inB1;
+
+    /* read input from real input buffer */
+    inB2 = pSrcReal[1];
+    /* read input from complex input buffer */
+    inA5 = pSrcCmplx[4];
+
+    /* multiply complex buffer real input with real buffer input */
+    out3 = inA3 * inB2;
+
+    /* read input from complex input buffer */
+    inA6 = pSrcCmplx[5];
+    /* read input from real input buffer */
+    inB3 = pSrcReal[2];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out4 = inA4 * inB2;
+
+    /* read input from complex input buffer */
+    inA7 = pSrcCmplx[6];
+
+    /* multiply complex buffer real input with real buffer input */
+    out5 = inA5 * inB3;
+
+    /* read input from complex input buffer */
+    inA8 = pSrcCmplx[7];
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out6 = inA6 * inB3;
+
+    /* read input from real input buffer */
+    inB4 = pSrcReal[3];
+
+    /* store result to destination bufer */
+    pCmplxDst[0] = out1;
+
+    /* multiply complex buffer real input with real buffer input */
+    out7 = inA7 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[1] = out2;
+
+    /* multiply complex buffer imaginary input with real buffer input */
+    out8 = inA8 * inB4;
+
+    /* store result to destination bufer */
+    pCmplxDst[2] = out3;
+    pCmplxDst[3] = out4;
+    pCmplxDst[4] = out5;
+
+    /* incremnet complex input buffer by 8 to process next samples */
+    pSrcCmplx += 8u;
+
+    /* store result to destination bufer */
+    pCmplxDst[5] = out6;
+
+    /* increment real input buffer by 4 to process next samples */
+    pSrcReal += 4u;
+
+    /* store result to destination bufer */
+    pCmplxDst[6] = out7;
+    pCmplxDst[7] = out8;
+
+    /* increment destination buffer by 8 to process next sampels */
+    pCmplxDst += 8u;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+}
+
+/**        
+ * @} end of CmplxByRealMult group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 0000000000..a44158c4ff
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_q15.c    
+*    
+* Description:	Q15 complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByRealMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q15 complex-by-real multiplication    
+ * @param[in]  *pSrcCmplx points to the complex input vector    
+ * @param[in]  *pSrcReal points to the real input vector    
+ * @param[out]  *pCmplxDst points to the complex output vector    
+ * @param[in]  numSamples number of samples in each vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA1, inA2;                              /* Temporary variables to hold input data */
+  q31_t inB1;                                    /* Temporary variables to hold input data */
+  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read complex number both real and imaginary from complex input buffer */
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    /* read two real values at a time from real input buffer */
+    inB1 = *__SIMD32(pSrcReal)++;
+    /* read complex number both real and imaginary from complex input buffer */
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+    /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* saturate the result */
+    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+    /* pack real and imaginary outputs and store them to destination */
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    inA1 = *__SIMD32(pSrcCmplx)++;
+    inB1 = *__SIMD32(pSrcReal)++;
+    inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of CmplxByRealMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 0000000000..b286acdb6d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,215 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cmplx_mult_real_q31.c    
+*    
+* Description:	Q31 complex by real multiplication    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupCmplxMath    
+ */
+
+/**    
+ * @addtogroup CmplxByRealMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Q31 complex-by-real multiplication    
+ * @param[in]  *pSrcCmplx points to the complex input vector    
+ * @param[in]  *pSrcReal points to the real input vector    
+ * @param[out]  *pCmplxDst points to the complex output vector    
+ * @param[in]  numSamples number of samples in each vector    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t inA1;                                    /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */
+  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */
+  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+    inB2 = *pSrcReal++;
+    /* read imaginary input from complex input buffer */
+    inA3 = *pSrcCmplx++;
+    inA4 = *pSrcCmplx++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+    out3 = ((q63_t) inA3 * inB2) >> 32;
+    out4 = ((q63_t) inA4 * inB2) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+    out3 = __SSAT(out3, 31);
+    out4 = __SSAT(out4, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+    out3 = out3 << 1;
+    out4 = out4 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+    *pCmplxDst++ = out3;
+    *pCmplxDst++ = out4;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    /* read real input from complex input buffer */
+    inA1 = *pSrcCmplx++;
+    inA2 = *pSrcCmplx++;
+    /* read input from real input bufer */
+    inB1 = *pSrcReal++;
+
+    /* multiply complex input with real input */
+    out1 = ((q63_t) inA1 * inB1) >> 32;
+    out2 = ((q63_t) inA2 * inB1) >> 32;
+
+    /* sature the result */
+    out1 = __SSAT(out1, 31);
+    out2 = __SSAT(out2, 31);
+
+    /* get result in 1.31 format */
+    out1 = out1 << 1;
+    out2 = out2 << 1;
+
+    /* store the result to destination buffer */
+    *pCmplxDst++ = out1;
+    *pCmplxDst++ = out2;
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    inA1 = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of CmplxByRealMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 0000000000..37e48f609b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_f32.c    
+*    
+* Description:	Floating-point PID Control initialization function    
+*				   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point PID Control.   
+ * @param[in,out] *S points to an instance of the PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.   
+ * @return none.   
+ * \par Description:   
+ * \par    
+ * The resetStateFlag specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: A0, A1 A2    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(float32_t));
+  }
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 0000000000..1816bc9aa1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_q15.c    
+*    
+* Description:	Q15 PID Control initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @param[in,out] *S points to an instance of the Q15 PID structure.    
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.    
+ * @return none.    
+ * \par Description:   
+ * \par    
+ * The resetStateFlag specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: A0, A1 A2    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 0000000000..da40ce973d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_init_q31.c    
+*    
+* Description:	Q31 PID Control initialization function     
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q31 PID Control.   
+ * @param[in,out] *S points to an instance of the Q31 PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
+ * @return none.    
+ * \par Description:   
+ * \par    
+ * The resetStateFlag specifies whether to set state to zero or not. \n   
+ * The function computes the structure fields: A0, A1 A2    
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
+ * also sets the state variables to all zeros.    
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q31_t));
+  }
+
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 0000000000..491ad5268b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,57 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_f32.c    
+*    
+* Description:	Floating-point PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the floating-point PID Control.   
+* @param[in] *S	Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 0000000000..dc00787460
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_q15.c    
+*    
+* Description:	Q15 PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the Q15 PID Control.   
+* @param[in] *S		Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 0000000000..b1ff753af3
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,57 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_pid_reset_q31.c    
+*    
+* Description:	Q31 PID Control reset function   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**    
+ * @addtogroup PID    
+ * @{    
+ */
+
+/**    
+* @brief  Reset function for the Q31 PID Control.   
+* @param[in] *S	Instance pointer of PID control data structure.   
+* @return none.    
+* \par Description:   
+* The function resets the state buffer to zeros.    
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**    
+ * @} end of PID group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 0000000000..1679a780c7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,428 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_cos_f32.c    
+*    
+* Description:	Sine and Cosine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupController    
+ */
+
+/**    
+ * @defgroup SinCos Sine Cosine   
+ *    
+ * Computes the trigonometric sine and cosine values using a combination of table lookup   
+ * and linear interpolation.     
+ * There are separate functions for Q31 and floating-point data types.   
+ * The input to the floating-point version is in degrees while the   
+ * fixed-point Q31 have a scaled input with the range   
+ * [-1 0.9999] mapping to [-180 179] degrees.   
+ *   
+ * The implementation is based on table lookup using 360 values together with linear interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index.   
+ *  -# Compute the fractional portion (fract) of the input.   
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.      
+ *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).    
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.      
+ *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).    
+ */
+
+ /**    
+ * @addtogroup SinCos    
+ * @{    
+ */
+
+
+/**    
+* \par    
+* Cosine Table is generated from following loop    
+* 
for(i = 0; i < 360; i++)    
+* {    
+*    cosTable[i]= cos((i-180) * PI/180.0);    
+* } 
   
+*/
+
+static const float32_t cosTable[360] = {
+  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f,
+  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068200f, -0.961261695938318670f,
+  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+  -0.920504853452440150f, -0.913545457642600760f,
+  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+  -0.857167300702112220f, -0.848048096156425960f,
+  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+  -0.777145961456970680f, -0.766044443118977900f,
+  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+  -0.681998360062498370f, -0.669130606358858240f,
+  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+  -0.573576436351045830f, -0.559192903470746680f,
+  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+  -0.453990499739546750f, -0.438371146789077510f,
+  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156420f, -0.309016994374947340f,
+  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+  -0.190808995376544800f, -0.173648177666930300f,
+  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+  -0.052335956242943620f, -0.034899496702500733f,
+  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+  0.087155742747658138f, 0.104528463267653460f,
+  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+  0.224951054343864920f, 0.241921895599667900f,
+  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+  0.358367949545300380f, 0.374606593415911960f,
+  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+  0.484809620246337110f, 0.500000000000000110f,
+  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658290f,
+  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+  0.707106781186547570f, 0.719339800338651190f,
+  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f,
+  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+  0.874619707139395740f, 0.882947592858926990f,
+  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908430f,
+  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805690f,
+  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f,
+  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f,
+  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f,
+  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+  0.945518575599316850f, 0.939692620785908430f,
+  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+  0.891006524188367900f, 0.882947592858926990f,
+  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+  0.819152044288991800f, 0.809016994374947450f,
+  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651190f,
+  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+  0.629320391049837500f, 0.615661475325658290f,
+  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+  0.515038074910054380f, 0.500000000000000110f,
+  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+  0.390731128489273940f, 0.374606593415911960f,
+  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+  0.258819045102520740f, 0.241921895599667900f,
+  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+  0.121869343405147490f, 0.104528463267653460f,
+  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+  -0.017452406437283477f, -0.034899496702500733f,
+  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+  -0.156434465040231040f, -0.173648177666930300f,
+  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+  -0.292371704722736660f, -0.309016994374947340f,
+  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+  -0.422618261740699330f, -0.438371146789077510f,
+  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+  -0.544639035015027080f, -0.559192903470746680f,
+  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+  -0.656059028990507500f, -0.669130606358858240f,
+  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+  -0.754709580222772010f, -0.766044443118977900f,
+  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+  -0.838670567945424160f, -0.848048096156425960f,
+  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+  -0.906307787036649940f, -0.913545457642600760f,
+  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+  -0.956304755963035440f, -0.961261695938318670f,
+  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570250f,
+  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**    
+* \par    
+* Sine Table is generated from following loop    
+* 
for(i = 0; i < 360; i++)    
+* {    
+*    sinTable[i]= sin((i-180) * PI/180.0);    
+* } 
    
+*/
+
+
+static const float32_t sinTable[360] = {
+  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+  -0.121869343405147550f, -0.139173100960065740f,
+  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+  -0.258819045102521020f, -0.275637355816999660f,
+  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+  -0.390731128489274160f, -0.406736643075800430f,
+  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+  -0.515038074910054380f, -0.529919264233204900f,
+  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+  -0.629320391049837720f, -0.642787609686539470f,
+  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+  -0.731353701619170570f, -0.743144825477394240f,
+  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+  -0.819152044288992020f, -0.829037572555041740f,
+  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+  -0.891006524188367900f, -0.898794046299166930f,
+  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+  -0.945518575599316850f, -0.951056516295153640f,
+  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+  -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+  -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+  -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+  -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+  -0.933580426497201740f, -0.927183854566787420f,
+  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+  -0.874619707139395740f, -0.866025403784438600f,
+  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+  -0.798635510047292830f, -0.788010753606722010f,
+  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+  -0.707106781186547460f, -0.694658370458997250f,
+  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+  -0.601815023152048270f, -0.587785252292473140f,
+  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+  -0.484809620246337060f, -0.469471562785890810f,
+  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+  -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+  -0.224951054343865000f, -0.207911690817759310f,
+  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+  -0.087155742747658166f, -0.069756473744125302f,
+  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+  0.052335956242943828f, 0.069756473744125302f,
+  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+  0.190808995376544800f, 0.207911690817759310f,
+  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+  0.325568154457156640f, 0.342020143325668710f,
+  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+  0.453990499739546750f, 0.469471562785890810f,
+  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+  0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+  0.681998360062498480f, 0.694658370458997250f,
+  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+  0.777145961456970790f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+  0.857167300702112220f, 0.866025403784438600f,
+  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+  0.920504853452440260f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+  0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+  0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+  0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+  0.987688340595137660f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+  0.956304755963035550f, 0.951056516295153640f,
+  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+  0.906307787036650050f, 0.898794046299166930f,
+  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+  0.838670567945424050f, 0.829037572555041740f,
+  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+  0.754709580222771790f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+  0.656059028990507280f, 0.642787609686539470f,
+  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+  0.544639035015026860f, 0.529919264233204900f,
+  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+  0.422618261740699500f, 0.406736643075800430f,
+  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+  0.292371704722737050f, 0.275637355816999660f,
+  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+  0.156434465040230980f, 0.139173100960065740f,
+  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+  0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**    
+ * @brief  Floating-point sin_cos function.   
+ * @param[in]  theta    input value in degrees    
+ * @param[out] *pSinVal points to the processed sine output.    
+ * @param[out] *pCosVal points to the processed cos output.    
+ * @return none.   
+ */
+
+
+void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal)
+{
+  int32_t i;                                     /* Index for reading nearwst output values */
+  float32_t x1 = -179.0f;                        /* Initial input value */
+  float32_t y0, y1;                              /* nearest output values */
+  float32_t y2, y3;
+  float32_t fract;                               /* fractional part of input */
+
+  /* Calculation of fractional part */
+  if(theta > 0.0f)
+  {
+    fract = theta - (float32_t) ((int32_t) theta);
+  }
+  else
+  {
+    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+  }
+
+  /* index calculation for reading nearest output values */
+  i = (uint32_t) (theta - x1);
+
+  /* Checking min and max index of table */
+  if(i < 0)
+  {
+    i = 0;
+  }
+  else if(i >= 359)
+  {
+    i = 358;
+  }
+
+  /* reading nearest sine output values */
+  y0 = sinTable[i];
+  y1 = sinTable[i + 1u];
+
+  /* reading nearest cosine output values */
+  y2 = cosTable[i];
+  y3 = cosTable[i + 1u];
+
+  y1 = y1 - y0;
+  y3 = y3 - y2;
+
+  y1 = fract * y1;
+  y3 = fract * y3;
+
+  /* Calculation of sine value */
+  *pSinVal = y0 + y1;
+
+  /* Calculation of cosine value */
+  *pCosVal = y2 + y3;
+
+}
+
+/**    
+ * @} end of SinCos group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 0000000000..e22d25e539
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,324 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_cos_q31.c    
+*    
+* Description:	Cosine & Sine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupController    
+ */
+
+ /**    
+ * @addtogroup SinCos    
+ * @{    
+ */
+
+/**    
+* \par    
+* Sine Table is generated from following loop    
+* 
for(i = 0; i < 360; i++)    
+* {    
+*    sinTable[i]= sin((i-180) * PI/180.0);    
+* } 
   
+* Convert above coefficients to fixed point 1.31 format.    
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+  0xf06695da,
+  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+  0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+  0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+  0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+  0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+  0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+  0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+  0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+  0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+  0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+  0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+  0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+  0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+  0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+  0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+  0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+  0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+  0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+  0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+  0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+  0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+  0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+  0x6b2f1d2,
+  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+  0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+  0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+  0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+  0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+  0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+  0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+  0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+  0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+  0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+  0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+  0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+  0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+  0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+  0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+  0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+  0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+  0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+  0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+  0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+  0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+  0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+  0x4779632, 0x23be165,
+
+
+};
+
+/**    
+* \par    
+* Cosine Table is generated from following loop    
+* 
for(i = 0; i < 360; i++)    
+* {    
+*    cosTable[i]= cos((i-180) * PI/180.0);    
+* } 
   
+* \par    
+* Convert above coefficients to fixed point 1.31 format.    
+*/
+static const int32_t cosTableQ31[360] = {
+  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69,
+  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3,
+  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f,
+  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786,
+  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c,
+  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a,
+  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e,
+  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9,
+  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860,
+  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223,
+  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e,
+  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+  0xb27eb5c,
+  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237,
+  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040,
+  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc,
+  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651,
+  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a,
+  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b,
+  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df,
+  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c,
+  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885,
+  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0,
+  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4,
+  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5,
+  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0,
+  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075,
+  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964,
+  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83,
+  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211,
+  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484,
+  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45,
+  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83,
+  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26,
+  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+  0xfdc41e9b,
+  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+  0xee2f9369, 0xebf9f498,
+  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061,
+  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512,
+  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2,
+  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb,
+  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d,
+  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d,
+  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f,
+  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46,
+  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf,
+  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**    
+ * @brief  Q31 sin_cos function.   
+ * @param[in]  theta    scaled input value in degrees    
+ * @param[out] *pSinVal points to the processed sine output.    
+ * @param[out] *pCosVal points to the processed cosine output.    
+ * @return none.   
+ *    
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].   
+ *    
+ */
+
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t x0;                                      /* Nearest input value */
+  q31_t y0, y1;                                  /* Nearest output values */
+  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */
+  int32_t i;                                     /* Index */
+  q31_t oneByXSpacing;                           /* 1/ xSpacing value */
+  q31_t out;                                     /* temporary variable */
+  uint32_t sign_bits;                            /* No.of sign bits */
+  uint32_t firstX = 0x80000000;                  /* First X value */
+
+  /* Calculation of index */
+  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+  /* Checking min and max index of table */
+  if(i < 0)
+  {
+    i = 0;
+  }
+  else if(i >= 359)
+  {
+    i = 358;
+  }
+
+  /* Calculation of first nearest input value */
+  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+  /* Reading nearest sine output values from table */
+  y0 = sinTableQ31[i];
+  y1 = sinTableQ31[i + 1u];
+
+  /* Calculation of 1/(x1-x0) */
+  /* (x1-x0) is xSpacing which is fixed value */
+  sign_bits = 8u;
+  oneByXSpacing = 0x5A000000;
+
+  /* Calculation of (theta - x0)/(x1-x0) */
+  out =
+    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pSinVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+  /* Reading nearest cosine output values from table */
+  y0 = cosTableQ31[i];
+  y1 = cosTableQ31[i + 1u];
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pCosVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+}
+
+/**    
+ * @} end of SinCos group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 0000000000..bee758bff7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,280 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_f32.c    
+*    
+* Description:	Fast cosine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**    
+ * @ingroup groupFastMath    
+ */
+
+/**    
+ * @defgroup cos Cosine    
+ *    
+ * Computes the trigonometric cosine function using a combination of table lookup   
+ * and cubic interpolation.  There are separate functions for   
+ * Q15, Q31, and floating-point data types.   
+ * The input to the floating-point version is in radians while the   
+ * fixed-point Q15 and Q31 have a scaled input with the range   
+ * [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.   
+ *   
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index   
+ *  -# Fetch the four table values a, b, c, and d     
+ *  -# Compute the fractional portion (fract) of the table index.   
+ *  -# Calculation of wa, wb, wc, wd    
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
+ *   
+ * where   
+ * 
    
+ *    a=Table[index-1];    
+ *    b=Table[index+0];    
+ *    c=Table[index+1];    
+ *    d=Table[index+2];    
+ * 
   
+ * and   
+ * 
    
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ * 
    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+
+/**    
+* \par    
+* Example code for Generation of Cos Table:   
+* tableSize = 256;    
+* 
for(n = -1; n < (tableSize + 2); n++)    
+* {    
+*	cosTable[n+1]= cos(2*pi*n/tableSize);    
+* } 
    
+* where pi value is  3.14159265358979    
+*/
+
+static const float32_t cosTable[260] = {
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f
+};
+
+/**   
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.   
+ * @param[in] x input value in radians.   
+ * @return cos(x).   
+ */
+
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;
+  int32_t index;
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;
+  float32_t wa, wb, wc, wd;
+  float32_t a, b, c, d;
+  float32_t *tablePtr;
+  int32_t n;
+  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+  float32_t oneminusfractby2;
+  float32_t frby2xfrsq, frby6xfrsq;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & cosTable[index];
+
+  /* Read four nearest values of input value from the cos table */
+  a = tablePtr[0];
+  b = tablePtr[1];
+  c = tablePtr[2];
+  d = tablePtr[3];
+
+  /* Cubic interpolation process */
+  fractsq = fract * fract;
+  fractby2 = fract * 0.5f;
+  fractby6 = fract * 0.166666667f;
+  fractby3 = fract * 0.3333333333333f;
+  fractsqby2 = fractsq * 0.5f;
+  frby2xfrsq = (fractby2) * fractsq;
+  frby6xfrsq = (fractby6) * fractsq;
+  oneminusfractby2 = 1.0f - fractby2;
+  wb = fractsqby2 - fractby3;
+  wc = (fractsqby2 + fract);
+  wa = wb - frby6xfrsq;
+  wb = frby2xfrsq - fractsq;
+  cosVal = wa * a;
+  wc = wc - frby2xfrsq;
+  wd = (frby6xfrsq) - fractby6;
+  wb = wb + oneminusfractby2;
+
+  /* Calculate cos value */
+  cosVal = (cosVal + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (cosVal);
+
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 0000000000..0edf68b893
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_q15.c    
+*    
+* Description:	Fast cosine calculation for Q15 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+/**   
+* \par    
+* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps    
+* \par    
+* First Generate cos values in floating point:    
+* tableSize = 256;     
+* 
for(n = -1; n < (tableSize + 1); n++)    
+* {    
+*	cosTable[n+1]= cos(2*pi*n/tableSize);    
+* }
   
+* where pi value is  3.14159265358979    
+* \par    
+* Secondly Convert Floating point to Q15(Fixed point):    
+*	(cosTable[i] * pow(2, 15))    
+* \par    
+* Finally Rounding to nearest integer is done    
+* 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    
+*/
+
+static const q15_t cosTableQ15[259] = {
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**   
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  cos(x).   
+ *   
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q31_t cosVal;                                  /* Temporary variable for output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t in, in2;                                 /* Temporary variables for input */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & cosTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a * wa */
+  cosVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal += b * wb;
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the cos table */
+  c = *tablePtr++;
+
+  /* cosVal += c*wc */
+  cosVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal += d * wd;
+
+  /* Convert output value in 1.15(q15) format and saturate */
+  cosVal = __SSAT((cosVal >> 15), 16);
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) cosVal);
+
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 0000000000..1326215fe4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_cos_q31.c    
+*    
+* Description:	Fast cosine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup cos    
+ * @{    
+ */
+
+/**    
+ * \par    
+ * Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps    
+ * First Generate cos values in floating point:    
+ * tableSize = 256;      
+ * 
for(n = -1; n < (tableSize + 1); n++)    
+ * {    
+ *	cosTable[n+1]= cos(2*pi*n/tableSize);    
+ * } 
     
+ * where pi value is  3.14159265358979    
+ * \par    
+ * Secondly Convert Floating point to Q31(Fixed point):    
+ *	(cosTable[i] * pow(2, 31))    
+ * \par    
+ * Finally Rounding to nearest integer is done    
+ * 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**   
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  cos(x).   
+ *   
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = ((q31_t) index) * tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & cosTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a*wa */
+  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+  /* Read third nearest values of output value from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+
+  /* convert cosVal in 2.30 format to 1.31 format */
+  return (__QADD(cosVal, cosVal));
+
+}
+
+/**    
+ * @} end of cos group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 0000000000..bfe58d5c81
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,281 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_f32.c    
+*    
+* Description:	Fast sine calculation for floating-point values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+/**    
+ * @defgroup sin Sine    
+ *    
+ * Computes the trigonometric sine function using a combination of table lookup   
+ * and cubic interpolation.  There are separate functions for   
+ * Q15, Q31, and floating-point data types.   
+ * The input to the floating-point version is in radians while the   
+ * fixed-point Q15 and Q31 have a scaled input with the range   
+ * [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.   
+ *   
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.   
+ * The steps used are:   
+ *  -# Calculation of the nearest integer table index   
+ *  -# Fetch the four table values a, b, c, and d     
+ *  -# Compute the fractional portion (fract) of the table index.   
+ *  -# Calculation of wa, wb, wc, wd    
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
+ *   
+ * where   
+ * 
    
+ *    a=Table[index-1];    
+ *    b=Table[index+0];    
+ *    c=Table[index+1];    
+ *    d=Table[index+2];    
+ * 
   
+ * and   
+ * 
    
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ * 
    
+ */
+
+/**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+
+/**   
+ * \par    
+ * Example code for Generation of Floating-point Sin Table:   
+ * tableSize = 256;    
+ * 
for(n = -1; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);    
+ * }
    
+ * \par    
+ * where pi value is  3.14159265358979    
+ */
+
+static const float32_t sinTable[259] = {
+  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**   
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.   
+ * @param[in] x input value in radians.   
+ * @return  sin(x).   
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variable */
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */
+  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */
+  float32_t a, b, c, d;                          /* Four nearest output values */
+  float32_t *tablePtr;                           /* Pointer to table */
+  int32_t n;
+  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+  float32_t oneminusfractby2;
+  float32_t frby2xfrsq, frby6xfrsq;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & sinTable[index];
+
+  /* Read four nearest values of input value from the sin table */
+  a = tablePtr[0];
+  b = tablePtr[1];
+  c = tablePtr[2];
+  d = tablePtr[3];
+
+  /* Cubic interpolation process */
+  fractsq = fract * fract;
+  fractby2 = fract * 0.5f;
+  fractby6 = fract * 0.166666667f;
+  fractby3 = fract * 0.3333333333333f;
+  fractsqby2 = fractsq * 0.5f;
+  frby2xfrsq = (fractby2) * fractsq;
+  frby6xfrsq = (fractby6) * fractsq;
+  oneminusfractby2 = 1.0f - fractby2;
+  wb = fractsqby2 - fractby3;
+  wc = (fractsqby2 + fract);
+  wa = wb - frby6xfrsq;
+  wb = frby2xfrsq - fractsq;
+  sinVal = wa * a;
+  wc = wc - frby2xfrsq;
+  wd = (frby6xfrsq) - fractby6;
+  wb = wb + oneminusfractby2;
+
+  /* Calculate sin value */
+  sinVal = (sinVal + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (sinVal);
+
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 0000000000..b53ca3ecc4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_q15.c    
+*    
+* Description:	Fast sine calculation for Q15 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+
+/**    
+ * \par    
+ * Example code for Generation of Q15 Sin Table:   
+ * \par    
+ * 
tableSize = 256;    
+ * for(n = -1; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);    
+ * } 
    
+ * where pi value is  3.14159265358979    
+ * \par    
+ * Convert Floating point to Q15(Fixed point):    
+ *	(sinTable[i] * pow(2, 15))    
+ * \par    
+ * rounding to nearest integer is done    
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
+ */
+
+
+static const q15_t sinTableQ15[259] = {
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324
+};
+
+
+/**   
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  sin(x).   
+ *   
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t fract, in, in2;                          /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) ((index) * tableSpacing);
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & sinTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += ((q31_t) fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a * wa */
+  sinVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+    (((q31_t) fract >> 1u) - 0x7FFF);
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*      sinVal += b*wb */
+  sinVal += b * wb;
+
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /* sinVal += c*wc */
+  sinVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal += d * wd;
+
+  /* Convert output value in 1.15(q15) format and saturate */
+  sinVal = __SSAT((sinVal >> 15), 16);
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) sinVal);
+
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 0000000000..336796b5c1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,240 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_sin_q31.c    
+*    
+* Description:	Fast sine calculation for Q31 values.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFastMath    
+ */
+
+ /**    
+ * @addtogroup sin    
+ * @{    
+ */
+
+/**   
+ * \par    
+ * Tables generated are in Q31(1.31 Fixed point format)    
+ * Generation of sin values in floating point:    
+ * 
tableSize = 256;      
+ * for(n = -1; n < (tableSize + 1); n++)    
+ * {    
+ *	sinTable[n+1]= sin(2*pi*n/tableSize);    
+ * } 
    
+ * where pi value is  3.14159265358979    
+ * \par    
+ * Convert Floating point to Q31(Fixed point):    
+ *	(sinTable[i] * pow(2, 31))    
+ * \par    
+ * rounding to nearest integer is done    
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
+ */
+
+static const q31_t sinTableQ31[259] = {
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**   
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.   
+ * @param[in] x Scaled input value in radians.   
+ * @return  sin(x).   
+ *   
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
+ */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */
+  int32_t index;                                 /* Index variables */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (uint32_t) in / (uint32_t) tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q31_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Checking min and max index of table */
+  if(index < 0)
+  {
+    index = 0;
+  }
+  else if(index > 256)
+  {
+    index = 256;
+  }
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & sinTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a*wa */
+  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*  sinVal += b*wb */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+  /* convert sinVal in 2.30 format to 1.31 format */
+  return (__QADD(sinVal, sinVal));
+
+}
+
+/**    
+ * @} end of sin group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 0000000000..0a6d6a53a2
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------     
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
+*     
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*     
+* Project:      CMSIS DSP Library  
+* Title:		arm_sqrt_q15.c     
+*     
+* Description:	Q15 square root function.    
+*     
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.0 2011/03/08 
+*     Alpha release. 
+* 
+* Version 1.0.1 2011/09/30 
+*     Beta release.  
+*     
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**     
+ * @ingroup groupFastMath     
+ */
+
+/**     
+ * @addtogroup SQRT     
+ * @{     
+ */
+
+  /**    
+   * @brief  Q15 square root function.    
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.    
+   * @param[out]  *pOut  square root of input value.    
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if    
+   * in is negative value and returns zero output for negative values.    
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q15_t number, temp1, var1, signBits1, half;
+  q31_t bits_val1;
+  float32_t temp_float1;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if(number > 0)
+  {
+    signBits1 = __CLZ(number) - 17;
+
+    /* Shift by the number of signBits1 */
+    if((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /*Convert to float */
+    temp_float1 = number * 3.051757812500000e-005f;
+    /*Store as integer */
+    bits_val1 = *(int *) &temp_float1;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
+    /* Store as float */
+    temp_float1 = *(float *) &bits_val1;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 16384);
+
+    /* 1st iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 2nd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+    /* 3rd iteration */
+    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+                                     ((q15_t)
+                                      ((((q15_t)
+                                         (((q31_t) var1 * var1) >> 15)) *
+                                        (q31_t) half) >> 15))) >> 15)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+    /* Shift the output down accordingly */
+    if((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**     
+ * @} end of SQRT group     
+ */
diff --git a/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 0000000000..2a3b7ac18d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------     
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
+*     
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*     
+* Project:      CMSIS DSP Library  
+* Title:		arm_sqrt_q31.c     
+*     
+* Description:	Q31 square root function.    
+*     
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.0 2011/03/08 
+*     Alpha release. 
+* 
+* Version 1.0.1 2011/09/30 
+*     Beta release.  
+*     
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**     
+ * @ingroup groupFastMath     
+ */
+
+/**     
+ * @addtogroup SQRT     
+ * @{     
+ */
+
+/**    
+ * @brief Q31 square root function.    
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.    
+ * @param[out]  *pOut square root of input value.    
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if    
+ * in is negative value and returns zero output for negative values.    
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q31_t number, temp1, bits_val1, var1, signBits1, half;
+  float32_t temp_float1;
+
+  number = in;
+
+  /* If the input is a positive number then compute the signBits. */
+  if(number > 0)
+  {
+    signBits1 = __CLZ(number) - 1;
+
+    /* Shift by the number of signBits1 */
+    if((signBits1 % 2) == 0)
+    {
+      number = number << signBits1;
+    }
+    else
+    {
+      number = number << (signBits1 - 1);
+    }
+
+    /* Calculate half value of the number */
+    half = number >> 1;
+    /* Store the number for later use */
+    temp1 = number;
+
+    /*Convert to float */
+    temp_float1 = number * 4.6566128731e-010f;
+    /*Store as integer */
+    bits_val1 = *(int *) &temp_float1;
+    /* Subtract the shifted value from the magic number to give intial guess */
+    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
+    /* Store as float */
+    temp_float1 = *(float *) &bits_val1;
+    /* Convert to integer format */
+    var1 = (q31_t) (temp_float1 * 1073741824);
+
+    /* 1st iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 2nd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+    /* 3rd iteration */
+    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+                                     ((q31_t)
+                                      ((((q31_t)
+                                         (((q63_t) var1 * var1) >> 31)) *
+                                        (q63_t) half) >> 31))) >> 31)) << 2;
+
+    /* Multiply the inverse square root with the original value */
+    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+    /* Shift the output down accordingly */
+    if((signBits1 % 2) == 0)
+    {
+      var1 = var1 >> (signBits1 / 2);
+    }
+    else
+    {
+      var1 = var1 >> ((signBits1 - 1) / 2);
+    }
+    *pOut = var1;
+
+    return (ARM_MATH_SUCCESS);
+  }
+  /* If the number is a negative number then store zero as its square root value */
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**     
+ * @} end of SQRT group     
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 0000000000..a6745c0cd4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c    
+*    
+* Description:	High precision Q31 Biquad cascade filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1_32x64    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.    
+ * @param[in]     numStages     number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs      points to the filter coefficients.    
+ * @param[in]     *pState       points to the state buffer.    
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.    
+ * @return        none    
+ *    
+ * Coefficient and State Ordering:    
+ *    
+ * \par    
+ * The coefficients are stored in the array pCoeffs in the following order:    
+ * 
    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * 
    
+ * where b1x and a1x are the coefficients for the first stage,    
+ * b2x and a2x are the coefficients for the second stage,    
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.    
+ *    
+ * \par    
+ * The pState points to state variables array and size of each state variable is 1.63 format.    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
+ * The state variables are arranged in the state array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1_32x64 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 0000000000..82d6164ee1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,553 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_32x64_q31.c    
+*    
+* Description:	High precision Q31 Biquad cascade filter processing function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter    
+ *    
+ * This function implements a high precision Biquad cascade filter which operates on    
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables    
+ * are in 1.63 format.  The double precision state variables reduce quantization noise    
+ * in the filter and provide a cleaner output.    
+ * These filters are particularly useful when implementing filters in which the    
+ * singularities are close to the unit circle.  This is common for low pass or high    
+ * pass filters with very low cutoff frequencies.    
+ *    
+ * The function operates on blocks of input and output data    
+ * and each call to the function processes blockSize samples through    
+ * the filter. pSrc and pDst points to input and output arrays    
+ * containing blockSize Q31 values.    
+ *    
+ * \par Algorithm    
+ * Each Biquad stage implements a second order filter using the difference equation:    
+ * 
    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ * 
    
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
+ * \image html Biquad.gif "Single Biquad filter stage"    
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
+ * Pay careful attention to the sign of the feedback coefficients.    
+ * Some design tools use the difference equation    
+ * 
    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ * 
    
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
+ *    
+ * \par    
+ * Higher order filters are realized as a cascade of second order sections.    
+ * numStages refers to the number of second order stages used.    
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.    
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
+ *    
+ * \par    
+ * The pState points to state variables array .    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.    
+ * The state variables are arranged in the array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ *    
+ * \par    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values of data in 1.63 format.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ *    
+ * \par Init Function    
+ * There is also an associated initialization function which performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * For example, to statically initialize the filter instance structure use    
+ * 
    
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    
+ * 
    
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken while using Biquad Cascade 32x64 filter function.    
+ * Following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Filter gain    
+ * - Overflow and saturation    
+ *    
+ * \par    
+ * Filter coefficients are represented as fractional values and    
+ * restricted to lie in the range [-1 +1).    
+ * The processing function has an additional scaling parameter postShift    
+ * which allows the filter coefficients to exceed the range [+1 -1).    
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
+ * This essentially scales the filter coefficients by 2^postShift.    
+ * For example, to realize the coefficients    
+ * 
    
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ * 
    
+ * set the Coefficient array to:    
+ * 
    
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ * 
    
+ * and set postShift=1    
+ *    
+ * \par    
+ * The second thing to keep in mind is the gain through the filter.    
+ * The frequency response of a Biquad filter is a function of its coefficients.    
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
+ *    
+ * \par    
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.    
+ * This is described in the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1_32x64    
+ * @{    
+ */
+
+/**    
+ * @details    
+    
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
+ * 1.31 format by discarding the low 32 bits.    
+ *    
+ * \par    
+ * Two related functions are provided in the CMSIS DSP library.    
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.    
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.    
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */
+  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+  q31_t acc_l, acc_h;                            /*  temporary output               */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = (q31_t) (pState[0]);
+    Xn2 = (q31_t) (pState[1]);
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and    
+     * stored in the destination buffer    
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut = acc_h;
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc +=  b1 * x[n-1] */
+      acc = (q63_t) Xn *b1;
+
+      /* acc =  b0 * x[n] */
+      acc += (q63_t) Xn2 *b0;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn1 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *(pOut + 1u) = acc_h;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn1 *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn2 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 2u) = acc_h;
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *(pOut + 3u) = acc_h;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* update output pointer */
+      pOut += 4u;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+      //Yn1 = acc << shift; 
+
+      /* Store the output in the destination buffer in 1.31 format. */
+//      *pOut++ = (q31_t) (acc >> (32 - shift)); 
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and        
+     * stored in the destination buffer            
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]            
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) Xn *b0;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) Xn1 *b1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) Xn2 *b2;
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = acc_h;
+
+      //Yn1 = acc << shift; 
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      //*pOut++ = (q31_t) (acc >> (32 - shift)); 
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = (q63_t) Xn1;
+    *pState++ = (q63_t) Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*    #ifndef ARM_MATH_CM0     */
+}
+
+  /**    
+   * @} end of BiquadCascadeDF1_32x64 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 0000000000..ee20dfeec2
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,421 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_f32.c    
+*    
+* Description:	Processing function for the    
+*               floating-point Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure    
+ *    
+ * This set of functions implements arbitrary order recursive (IIR) filters.    
+ * The filters are implemented as a cascade of second order Biquad sections.    
+ * The functions support Q15, Q31 and floating-point data types.  
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.    
+ *    
+ * The functions operate on blocks of input and output data and each call to the function    
+ * processes blockSize samples through the filter.    
+ * pSrc points to the array of input data and    
+ * pDst points to the array of output data.    
+ * Both arrays contain blockSize values.    
+ *    
+ * \par Algorithm    
+ * Each Biquad stage implements a second order filter using the difference equation:    
+ * 
    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ * 
    
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
+ * \image html Biquad.gif "Single Biquad filter stage"    
+ * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
+ * Pay careful attention to the sign of the feedback coefficients.    
+ * Some design tools use the difference equation    
+ * 
    
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ * 
    
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
+ *    
+ * \par    
+ * Higher order filters are realized as a cascade of second order sections.    
+ * numStages refers to the number of second order stages used.    
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.    
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
+ *    
+ * \par    
+ * The pState points to state variables array.    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
+ * The state variables are arranged in the pState array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ *    
+ * \par    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values.    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Init Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * 
    
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    
+ * 
    
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.    
+ * Following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Filter gain    
+ * - Overflow and saturation    
+ *    
+ * \par    
+ * Scaling of coefficients:     
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range [-1 +1).    
+ * The fixed-point functions have an additional scaling parameter postShift    
+ * which allow the filter coefficients to exceed the range [+1 -1).    
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
+ * This essentially scales the filter coefficients by 2^postShift.    
+ * For example, to realize the coefficients    
+ * 
    
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ * 
    
+ * set the pCoeffs array to:    
+ * 
    
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ * 
    
+ * and set postShift=1    
+ *    
+ * \par    
+ * Filter gain:     
+ * The frequency response of a Biquad filter is a function of its coefficients.    
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
+ *    
+ * \par    
+ * Overflow and saturation:     
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.    
+ * @param[in]  *pSrc      points to the block of input data.    
+ * @param[out] *pDst      points to the block of output data.    
+ * @param[in]  blockSize  number of samples to process per call.    
+ * @return     none.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*   #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**    
+   * @} end of BiquadCascadeDF1 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 0000000000..29afffa03c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_fast_q15.c    
+*    
+* Description:	Fast processing function for the    
+*				Q15 Biquad cascade filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.9  2010/08/16     
+*    Initial version    
+*    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).    
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.    
+ *    
+ * \par    
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:       
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */
+      acc = __SMLAD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
+      acc = __SMLAD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+}
+
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 0000000000..0a479fe6b8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,275 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_fast_q31.c    
+*    
+* Description:	Processing function for the    
+*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.9  2010/08/27     
+*    Initial version    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return 	   none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function    
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.    
+ *    
+ * \par    
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.    
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:       
+     *       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Read the second input */
+      Xn2 = *(pIn + 1u);
+
+      /* Store the output in the destination buffer. */
+      *pOut = Yn2;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Read the third input  */
+      Xn1 = *(pIn + 2u);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 1u) = Yn1;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Read the forth input */
+      Xn = *(pIn + 3u);
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 2u) = Yn2;
+      pIn += 4u;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      Xn2 = Xn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Xn1 = Xn     */
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *(pOut + 3u) = Yn1;
+      pOut += 4u;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+}
+
+/**    
+  * @} end of BiquadCascadeDF1 group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 0000000000..d50b69f3c1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,107 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df1_init_f32.c    
+*    
+* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @brief  Initialization function for the floating-point Biquad cascade filter.    
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients array.    
+ * @param[in]     *pState      points to the state array.    
+ * @return        none    
+ *    
+ *    
+ * Coefficient and State Ordering:    
+ *    
+ * \par    
+ * The coefficients are stored in the array pCoeffs in the following order:    
+ * 
    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * 
    
+ *    
+ * \par    
+ * where b1x and a1x are the coefficients for the first stage,    
+ * b2x and a2x are the coefficients for the second stage,    
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.    
+ *    
+ * \par    
+ * The pState is a pointer to state array.    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
+ * The state variables are arranged in the pState array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ *    
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 0000000000..d5fda28ac5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df1_init_q15.c    
+*    
+* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients.    
+ * @param[in]     *pState      points to the state buffer.    
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format    
+ * @return        none    
+ *    
+ * Coefficient and State Ordering:    
+ *    
+ * \par    
+ * The coefficients are stored in the array pCoeffs in the following order:    
+ * 
    
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    
+ * 
    
+ * where b1x and a1x are the coefficients for the first stage,    
+ * b2x and a2x are the coefficients for the second stage,    
+ * and so on.  The pCoeffs array contains a total of 6*numStages values.    
+ * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.    
+ *    
+ * \par    
+ * The state variables are stored in the array pState.    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
+ * The state variables are arranged in the pState array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 0000000000..dbbb8aa2b5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_init_q31.c    
+*    
+* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]     numStages    number of 2nd order stages in the filter.    
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.    
+ * @param[in]     *pState      points to the state buffer.    
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    
+ * @return        none    
+ *    
+ * Coefficient and State Ordering:    
+ *    
+ * \par    
+ * The coefficients are stored in the array pCoeffs in the following order:    
+ * 
    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * 
    
+ * where b1x and a1x are the coefficients for the first stage,    
+ * b2x and a2x are the coefficients for the second stage,    
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.    
+ *    
+ * \par    
+ * The pState points to state variables array.    
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
+ * The state variables are arranged in the pState array as:    
+ * 
    
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ * 
    
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
+ * The state array has a total length of 4*numStages values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 0000000000..484cd85e89
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_q15.c    
+*    
+* Description:	Processing function for the    
+*				Q15 Biquad cascade DirectFormI(DF1) filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 Biquad cascade filter.    
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the location where the output result is written.    
+ * @param[in]  blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.    
+ * Finally, the result is saturated to 1.15 format.    
+ *    
+ * \par    
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc_l, acc_h;
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+  int32_t uShift = (32 - lShift);
+
+  do
+  {
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = *__SIMD32(pState)++;
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = *__SIMD32(pState)--;
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      out = __SSAT(out, 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:         
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**    
+ * @} end of BiquadCascadeDF1 group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 0000000000..5626bdd1ca
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,400 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df1_q31.c    
+*    
+* Description:	Processing function for the    
+*				Q31 Biquad cascade filter    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF1    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 Biquad cascade filter.    
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.    
+ * @param[in]  *pSrc      points to the block of input data.    
+ * @param[out] *pDst      points to the block of output data.    
+ * @param[in]  blockSize  number of samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
+ * 1.31 format by discarding the low 32 bits.    
+ *    
+ * \par    
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q63_t acc;                                     /*  accumulator                   */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  q31_t acc_l, acc_h;                            /*  temporary output variables    */
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:    
+     *    
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      /* Calc lower part of acc */
+      acc_l = acc & 0xffffffff;
+
+      /* Calc upper part of acc */
+      acc_h = (acc >> 32) & 0xffffffff;
+
+      /* Apply shift for lower part of acc and upper part of acc */
+      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:         
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> lShift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+}
+
+/**    
+  * @} end of BiquadCascadeDF1 group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 0000000000..a8cb0c98c1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,377 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_biquad_cascade_df2T_f32.c    
+*    
+* Description:  Processing function for the floating-point transposed    
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+ * @ingroup groupFilters       
+ */
+
+/**       
+ * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
+ *       
+ * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
+ * The filters are implemented as a cascade of second order Biquad sections.       
+ * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
+ * Only floating-point data is supported.       
+ *       
+ * This function operate on blocks of input and output data and each call to the function       
+ * processes blockSize samples through the filter.       
+ * pSrc points to the array of input data and       
+ * pDst points to the array of output data.       
+ * Both arrays contain blockSize values.       
+ *       
+ * \par Algorithm       
+ * Each Biquad stage implements a second order filter using the difference equation:       
+ * 
       
+ *    y[n] = b0 * x[n] + d1       
+ *    d1 = b1 * x[n] + a1 * y[n] + d2       
+ *    d2 = b2 * x[n] + a2 * y[n]       
+ * 
       
+ * where d1 and d2 represent the two state values.       
+ *       
+ * \par       
+ * A Biquad filter using a transposed Direct Form II structure is shown below.       
+ * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       
+ * Pay careful attention to the sign of the feedback coefficients.       
+ * Some design tools flip the sign of the feedback coefficients:       
+ * 
       
+ *    y[n] = b0 * x[n] + d1;       
+ *    d1 = b1 * x[n] - a1 * y[n] + d2;       
+ *    d2 = b2 * x[n] - a2 * y[n];       
+ * 
       
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       
+ *       
+ * \par       
+ * Higher order filters are realized as a cascade of second order sections.       
+ * numStages refers to the number of second order stages used.       
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.       
+ * A 9th order filter would be realized with numStages=5 second order stages with the       
+ * coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       
+ *       
+ * \par       
+ * pState points to the state variable array.       
+ * Each Biquad stage has 2 state variables d1 and d2.       
+ * The state variables are arranged in the pState array as:       
+ * 
       
+ *     {d11, d12, d21, d22, ...}       
+ * 
       
+ * where d1x refers to the state variables for the first Biquad and       
+ * d2x refers to the state variables for the second Biquad.       
+ * The state array has a total length of 2*numStages values.       
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.       
+ *       
+ * \par       
+ * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
+ * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
+ * That is why the Direct Form I structure supports Q15 and Q31 data types.    
+ * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    
+ * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
+ * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
+ *       
+ * \par Instance Structure       
+ * The coefficients and state variables for a filter are stored together in an instance data structure.       
+ * A separate instance structure must be defined for each filter.       
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
+ *       
+ * \par Init Functions       
+ * There is also an associated initialization function.      
+ * The initialization function performs following operations:       
+ * - Sets the values of the internal structure fields.       
+ * - Zeros out the values in the state buffer.       
+ *       
+ * \par       
+ * Use of the initialization function is optional.       
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.       
+ * Set the values in the state buffer to zeros before static initialization.       
+ * For example, to statically initialize the instance structure use       
+ * 
       
+ *     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
+ * 
       
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       
+ * pCoeffs is the address of the coefficient buffer;        
+ *       
+ */
+
+/**       
+ * @addtogroup BiquadCascadeDF2T       
+ * @{       
+ */
+
+/**      
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
+ * @param[in]  *S        points to an instance of the filter data structure.      
+ * @param[in]  *pSrc     points to the block of input data.      
+ * @param[out] *pDst     points to the block of output data      
+ * @param[in]  blockSize number of samples to process.      
+ * @return none.      
+ */
+
+void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  State pointer             */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc0;                                /*  accumulator               */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn;                                  /*  temporary input           */
+  float32_t d1, d2;                              /*  state variables           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+#ifndef ARM_MATH_CM0
+
+  float32_t Xn1, Xn2;                            /*  Input State variables     */
+  float32_t acc1;                                /*  accumulator               */
+
+
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+
+      /* y[n] = b0 * x[n] + d1 */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      /* d2 = b2 * x[n] + a2 * y[n] */
+
+      /* Read the first input */
+      Xn1 = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn1) + d1;
+
+      /* d1 = b1 * x[n] + d2 */
+      d1 = (b1 * Xn1) + d2;
+
+      /* d2 = b2 * x[n] */
+      d2 = (b2 * Xn1);
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* d1 = b1 * x[n] + a1 * y[n] */
+      d1 = (a1 * acc0) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      d2 = (a2 * acc0) + d2;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc1 = (b0 * Xn2) + d1;
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      d1 = (b1 * Xn2) + d2;
+
+      d2 = (b2 * Xn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc1;
+
+      d1 = (a1 * acc1) + d1;
+
+      d2 = (a2 * acc1) + d2;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn1) + d1;
+
+      d1 = (b1 * Xn1) + d2;
+
+      d2 = (b2 * Xn1);
+
+      /* Read the fourth input */
+      Xn2 = *pIn++;
+
+      d1 = (a1 * acc0) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      d2 = (a2 * acc0) + d2;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc1 = (b0 * Xn2) + d1;
+
+      d1 = (b1 * Xn2) + d2;
+
+      d2 = (b2 * Xn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc1;
+
+      d1 = (a1 * acc1) + d1;
+
+      d2 = (a2 * acc1) + d2;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*  #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**       
+   * @} end of BiquadCascadeDF2T group       
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 0000000000..e4225d008f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_biquad_cascade_df2T_init_f32.c    
+*    
+* Description:  Initialization function for the floating-point transposed   
+*               direct form II Biquad cascade filter.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup BiquadCascadeDF2T    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the filter data structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @return        none   
+ *    
+ * Coefficient and State Ordering:    
+ * \par    
+ * The coefficients are stored in the array pCoeffs in the following order:    
+ * 
    
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ * 
    
+ *    
+ * \par    
+ * where b1x and a1x are the coefficients for the first stage,    
+ * b2x and a2x are the coefficients for the second stage,    
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.    
+ *    
+ * \par    
+ * The pState is a pointer to state array.    
+ * Each Biquad stage has 2 state variables d1, and d2.    
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
+ * The state array has a total length of 2*numStages values.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**    
+ * @} end of BiquadCascadeDF2T group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 0000000000..48dd45f2bd
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,646 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_f32.c    
+*    
+* Description:	Convolution of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup Conv Convolution    
+ *    
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.    
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.    
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.    
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.    
+ *    
+ * \par Algorithm    
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
+ * Then the convolution    
+ *    
+ * 
    
+ *                   c[n] = a[n] * b[n]    
+ * 
    
+ *    
+ * \par    
+ * is defined as    
+ * \image html ConvolutionEquation.gif    
+ * \par    
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.    
+ * pSrcA points to the first input vector of length srcALen and    
+ * pSrcB points to the second input vector of length srcBLen.    
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.    
+ *    
+ * \par    
+ * Conceptually, when two signals a[n] and b[n] are convolved,    
+ * the signal b[n] slides over a[n].    
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.    
+ *    
+ * \par    
+ * Note that convolution is a commutative operation:    
+ *    
+ * 
    
+ *                   a[n] * b[n] = b[n] * a[n].    
+ * 
    
+ *    
+ * \par    
+ * This means that switching the A and B arguments to the convolution functions has no effect.    
+ *    
+ * Fixed-Point Behavior    
+ *    
+ * \par    
+ * Convolution requires summing up a large number of intermediate products.    
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
+ * Refer to the function specific documentation below for further details of the particular algorithm used.    
+ *
+ *
+ * Fast Versions
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * Opt Versions
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of floating-point sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px + 3u);
+        px += 4u;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 0000000000..3e85a25ba7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,538 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *     
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results    
+ * but provides only a single guard bit. There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
+ *    
+ * \par    
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
+ */
+
+void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifdef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* Pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.       
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x2, y2, acc0);
+      acc2 = __SMLAD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* update scratch pointers */
+      pIn2 += 4u;
+      pScr1 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 0000000000..e21be35235
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1405 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q15.c   
+*   
+* Description:	Fast Q15 Convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+* 
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results   
+ * but provides only a single guard bit. There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q15_t a, b;
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;	  
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {	
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 0000000000..e675c11ced
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,572 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_fast_q31.c    
+*    
+* Description:	Q31 Convolution (fast version).    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ *    
+ * \par    
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 0000000000..70b4125d9d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,544 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_opt_q15.c    
+*    
+* Description:	Convolution of Q15 sequences.      
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q15 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).    
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *    
+ *       
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * This approach provides 33 guard bits and there is no risk of overflow.    
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
+ *  
+ *   
+ * \par    
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.     
+ * 
+ *  
+ */
+
+void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  uint32_t tapCnt;                               /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2 + srcBLen - 1;
+
+  /* points to smaller length sequence */
+  px = pIn2;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  /* Copy smaller length input sequence in reverse order into second scratch buffer */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr2-- = *px++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Assuming scratch1 buffer is aligned by 32-bit */
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr1, srcALen);
+
+  /* Update pointers */
+  pScr1 += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = py;
+
+  /* First part of the processing with loop unrolling process 4 data points at a time.       
+   ** a second loop below process for the remaining 1 to 3 samples. */
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x1, y1, acc0);
+      acc2 = __SMLALD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = _SIMD32_OFFSET(pScr1);
+
+      /* multiply and accumlate */
+      acc0 = __SMLALD(x2, y2, acc0);
+      acc2 = __SMLALD(x1, y2, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr1;
+	  b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr1 + 2);
+	  b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+      pScr1 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2);
+      acc1 += (*pScr1++ * *pIn2);
+      acc2 += (*pScr1++ * *pIn2);
+      acc3 += (*pScr1++ * *pIn2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pOut)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read next two samples from scratch1 buffer */
+      acc0 += (*pScr1++ * *pIn2++);
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 0000000000..7fe9f55cf7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,434 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_opt_q7.c    
+*    
+* Description:	Convolution of Q7 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q7 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
+ *       
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.    
+ *
+ */
+
+void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* pointer to take end of scratch2 buffer */
+  pScr2 = pScratch2;
+
+  /* points to smaller length sequence */
+  px = pIn2 + srcBLen - 1;
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * px--;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Initialze temporary scratch pointer */
+  pScr1 = pScratch1;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif
+
+  /* Temporary pointer for scratch2 */
+  py = pScratch2;
+
+  /* Initialization of pIn2 pointer */
+  pIn2 = (q7_t *) py;
+
+  pScr2 = py;
+
+  /* Actual convolution process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+    out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+    out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+    out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate convolution for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 0000000000..58f5727353
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,661 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_f32.c    
+*    
+* Description:	Partial convolution of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup PartialConv Partial Convolution    
+ *    
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.    
+ * Each function has two additional arguments.    
+ * firstIndex specifies the starting index of the subset of output samples.    
+ * numPoints is the number of output samples to compute.    
+ * The function computes the output in the range    
+ * [firstIndex, ..., firstIndex+numPoints-1].    
+ * The output array pDst contains numPoints values.    
+ *    
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].    
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.    
+ * Otherwise the functions return ARM_MATH_SUCCESS.    
+ * \note Refer arm_conv_f32() for details on fixed point behavior.   
+ *
+ * 
+ * Fast Versions
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * Opt Versions
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of floating-point sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0u, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = (int32_t) check - (int32_t) srcALen;
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0u; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 0000000000..25b3ba8c30
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,763 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Partial convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
+ *     
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;
+
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+
+    /* Copy smaller length input sequence in reverse order into second scratch buffer */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Assuming scratch1 buffer is aligned by 32-bit */
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* First part of the processing with loop unrolling process 4 data points at a time.       
+     ** a second loop below process for the remaining 1 to 3 samples. */
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x2, y2, acc0);
+
+        acc2 = __SMLAD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+        acc1 = __SMLADX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+       ** Then store the output in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2u);
+        y11 = *(pIn2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 0000000000..98216bb6ab
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1473 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q15.c   
+*   
+* Description:	Fast Q15 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+      py = py - 1u;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+        /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+          /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+          /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+          /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+          /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q15_t a, b;
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >=srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+  while(blockSize1 > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+      sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+      py = py - 1u;
+
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+      /* read x[0], x[1] samples */
+	  a = *px++;
+	  b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *px;
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *px;
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x2 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  x2 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+		a = *py;
+		b = *(py+1);
+		py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  a = *(px + 2);
+	  b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 4);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px+1);
+		px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+		a = *py;
+		b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		c0 = __PKHBT(a, b, 16);
+
+#else
+
+ 		c0 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+	  x3 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  x3 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+		c0 = *(py-1);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		a = *(px+2);
+		b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+		x3 = __PKHBT(a, b, 16);
+
+#else
+
+ 		x3 = __PKHBT(b, a, 16);;
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+	  *pOut++ = (q15_t)(acc0 >> 15);
+	  *pOut++ = (q15_t)(acc1 >> 15);
+	  *pOut++ = (q15_t)(acc2 >> 15);
+	  *pOut++ = (q15_t)(acc3 >> 15);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+	py++;
+
+    while(k > 0u)
+    {	
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+  while(blockSize3 > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 0000000000..17902f593f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,599 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_fast_q31.c    
+*    
+* Description:	Fast Q31 Partial convolution.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par    
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------    
+     * Stage3 process    
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 0000000000..fe14f9fd3b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,764 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_opt_q15.c    
+*    
+* Description:	Partial convolution of Q15 sequences.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q15 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, state buffers should be aligned by 32-bit    
+ *    
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *  
+ * 
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
+  q31_t y1, y2;                                  /* State variables */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+    /* Copy (srcALen) samples in scratch buffer */
+    arm_copy_q15(pIn1, pScr1, srcALen);
+
+    /* Update pointers */
+    pScr1 += srcALen;
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pIn2);
+        y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x1, y1, acc0);
+        acc2 = __SMLALD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLALDX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = _SIMD32_OFFSET(pScr1);
+
+        /* multiply and accumlate */
+        acc0 = __SMLALD(x2, y2, acc0);
+        acc2 = __SMLALD(x1, y2, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y1, acc3);
+        acc1 = __SMLALDX(x3, y2, acc1);
+
+        x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLALDX(x3, y2, acc3);
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pIn2)++;
+
+        acc0 = __SMLALD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pOut = pDst;                            /* output pointer */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  uint32_t j, k, blkCnt;                         /* loop counter */
+  arm_status status;                             /* Status variable */
+  uint32_t tapCnt;                               /* loop count */
+  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
+  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2 + srcBLen - 1;
+
+    /* points to smaller length sequence */
+    px = pIn2;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr2-- = *px++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = *pIn1++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = py;
+
+    pScratch1 += firstIndex;
+
+    pOut = pDst + firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2;
+        y11 = *(pIn2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+        acc2 += (q63_t) x20 *y10;
+        acc2 += (q63_t) x21 *y11;
+
+        /* multiply and accumlate */
+        acc1 += (q63_t) x11 *y10;
+        acc1 += (q63_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x21 *y10;
+        acc3 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pIn2 + 2u);
+        y11 = *(pIn2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x20 *y10;
+        acc0 += (q63_t) x21 *y11;
+        acc2 += (q63_t) x10 *y10;
+        acc2 += (q63_t) x11 *y11;
+        acc1 += (q63_t) x21 *y10;
+        acc1 += (q63_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q63_t) x11 *y10;
+        acc3 += (q63_t) x20 *y11;
+
+        /* update scratch pointers */
+        pIn2 += 4u;
+        pScr1 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2);
+        acc1 += (*pScr1++ * *pIn2);
+        acc2 += (*pScr1++ * *pIn2);
+        acc3 += (*pScr1++ * *pIn2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = __SSAT((acc0 >> 15), 16);
+      *pOut++ = __SSAT((acc1 >> 15), 16);
+      *pOut++ = __SSAT((acc2 >> 15), 16);
+      *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+
+    blkCnt = numPoints & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pIn2++;
+        y11 = *pIn2++;
+
+        /* multiply and accumlate */
+        acc0 += (q63_t) x10 *y10;
+        acc0 += (q63_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pIn2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+      /* Initialization of inputB pointer */
+      pIn2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 0000000000..513d89d877
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,806 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_opt_q7.c    
+*    
+* Description:	Partial convolution of Q7 sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q7 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit   
+ * 
+ *
+ * 
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update pointer */
+    pScr1 += (srcBLen - 1u);
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* Read next two samples from scratch1 buffer */
+      x2 = *__SIMD32(pScr1)++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2);
+
+        /* multiply and accumlate */
+        acc0 = __SMLAD(x1, y1, acc0);
+        acc2 = __SMLAD(x2, y1, acc2);
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        /* multiply and accumlate */
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x1, x2, 0);
+#else
+        x3 = __PKHBT(x2, x1, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        /* Read four samples from smaller buffer */
+        y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+        acc0 = __SMLAD(x2, y1, acc0);
+
+        acc2 = __SMLAD(x1, y1, acc2);
+
+        acc1 = __SMLADX(x3, y1, acc1);
+
+        x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+        x3 = __PKHBT(x2, x1, 0);
+#else
+        x3 = __PKHBT(x1, x2, 0);
+#endif
+
+        acc3 = __SMLADX(x3, y1, acc3);
+
+        pScr2 += 4u;
+
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x1 = *__SIMD32(pScr1)++;
+
+        /* Read two samples from smaller buffer */
+        y1 = *__SIMD32(pScr2)++;
+
+        acc0 = __SMLAD(x1, y1, acc0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+
+  }
+
+  return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+
+  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
+  q15_t x4;                                      /* Temporary input variable */
+  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
+  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
+  q7_t *px;                                      /* Temporary input1 pointer */
+  q15_t *py;                                     /* Temporary input2 pointer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  arm_status status;
+  q7_t *pOut = pDst;                             /* output pointer */
+  q15_t x10, x11, x20, x21;                      /* Temporary input variables */
+  q15_t y10, y11;                                /* Temporary input variables */
+  q7_t out0, out1, out2, out3;                   /* temporary variables */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* pointer to take end of scratch2 buffer */
+    pScr2 = pScratch2;
+
+    /* points to smaller length sequence */
+    px = pIn2 + srcBLen - 1;
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcBLen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcBLen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * px--;
+      *pScr2++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Initialze temporary scratch pointer */
+    pScr1 = pScratch1;
+
+    /* Fill (srcBLen - 1u) zeros in scratch buffer */
+    arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+    /* Update temporary scratch pointer */
+    pScr1 += (srcBLen - 1u);
+
+    /* Copy (srcALen) samples in scratch buffer */
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = srcALen >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = srcALen % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      x4 = (q15_t) * pIn1++;
+      *pScr1++ = x4;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Apply loop unrolling and do 4 Copies simultaneously. */
+    k = (srcBLen - 1u) >> 2u;
+
+    /* First part of the processing with loop unrolling copies 4 data points at a time.       
+     ** a second loop below copies for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner */
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, copy remaining samples here.       
+     ** No loop unrolling is used. */
+    k = (srcBLen - 1u) % 0x4u;
+
+    while(k > 0u)
+    {
+      /* copy second buffer in reversal manner for remaining samples */
+      *pScr1++ = 0;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+
+    /* Temporary pointer for scratch2 */
+    py = pScratch2;
+
+    /* Initialization of pIn2 pointer */
+    pIn2 = (q7_t *) py;
+
+    pScr2 = py;
+
+    pOut = pDst + firstIndex;
+
+    pScratch1 += firstIndex;
+
+    /* Actual convolution process starts here */
+    blkCnt = (numPoints) >> 2;
+
+
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* Read two samples from scratch1 buffer */
+      x10 = *pScr1++;
+      x11 = *pScr1++;
+
+      /* Read next two samples from scratch1 buffer */
+      x20 = *pScr1++;
+      x21 = *pScr1++;
+
+      tapCnt = (srcBLen) >> 2u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read four samples from smaller buffer */
+        y10 = *pScr2;
+        y11 = *(pScr2 + 1u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+        acc2 += (q31_t) x20 *y10;
+        acc2 += (q31_t) x21 *y11;
+
+
+        acc1 += (q31_t) x11 *y10;
+        acc1 += (q31_t) x20 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1;
+        x11 = *(pScr1 + 1u);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x21 *y10;
+        acc3 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch2 buffer */
+        y10 = *(pScr2 + 2u);
+        y11 = *(pScr2 + 3u);
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x20 *y10;
+        acc0 += (q31_t) x21 *y11;
+        acc2 += (q31_t) x10 *y10;
+        acc2 += (q31_t) x11 *y11;
+        acc1 += (q31_t) x21 *y10;
+        acc1 += (q31_t) x10 *y11;
+
+        /* Read next two samples from scratch1 buffer */
+        x20 = *(pScr1 + 2);
+        x21 = *(pScr1 + 3);
+
+        /* multiply and accumlate */
+        acc3 += (q31_t) x11 *y10;
+        acc3 += (q31_t) x20 *y11;
+
+        /* update scratch pointers */
+
+        pScr1 += 4u;
+        pScr2 += 4u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+
+
+      /* Update scratch pointer for remaining samples of smaller length sequence */
+      pScr1 -= 4u;
+
+
+      /* apply same above for remaining samples of smaller length sequence */
+      tapCnt = (srcBLen) & 3u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2);
+        acc1 += (*pScr1++ * *pScr2);
+        acc2 += (*pScr1++ * *pScr2);
+        acc3 += (*pScr1++ * *pScr2++);
+
+        pScr1 -= 3u;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+
+      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 4u;
+
+    }
+
+    blkCnt = (numPoints) & 0x3;
+
+    /* Calculate convolution for remaining samples of Bigger length sequence */
+    while(blkCnt > 0)
+    {
+      /* Initialze temporary scratch pointer as scratch1 */
+      pScr1 = pScratch1;
+
+      /* Clear Accumlators */
+      acc0 = 0;
+
+      tapCnt = (srcBLen) >> 1u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read next two samples from scratch1 buffer */
+        x10 = *pScr1++;
+        x11 = *pScr1++;
+
+        /* Read two samples from smaller buffer */
+        y10 = *pScr2++;
+        y11 = *pScr2++;
+
+        /* multiply and accumlate */
+        acc0 += (q31_t) x10 *y10;
+        acc0 += (q31_t) x11 *y11;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      tapCnt = (srcBLen) & 1u;
+
+      /* apply same above for remaining samples of smaller length sequence */
+      while(tapCnt > 0u)
+      {
+
+        /* accumlate the results */
+        acc0 += (*pScr1++ * *pScr2++);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      blkCnt--;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+      /* Initialization of inputB pointer */
+      pScr2 = py;
+
+      pScratch1 += 1u;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  return (status);
+
+}
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 0000000000..8c7ed5f861
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,778 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q15.c   
+*   
+* Description:	Partial convolution of Q15 sequences.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+* 
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.  
+ * 
+ * \par    
+ * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
+ * 
+ */
+
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+		c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+  	  
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+  
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)  */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 0000000000..16a0606488
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,599 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_partial_q31.c    
+*    
+* Description:	Partial convolution of Q31 sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup PartialConv    
+ * @{    
+ */
+
+/**    
+ * @brief Partial convolution of Q31 sequences.    
+ * @param[in]       *pSrcA points to the first input sequence.    
+ * @param[in]       srcALen length of the first input sequence.    
+ * @param[in]       *pSrcB points to the second input sequence.    
+ * @param[in]       srcBLen length of the second input sequence.    
+ * @param[out]      *pDst points to the location where the output result is written.    
+ * @param[in]       firstIndex is the first output sample to start with.    
+ * @param[in]       numPoints is the number of output points to be computed.    
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
+ *    
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */
+  q31_t x0, x1, x2, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds    
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally    
+     * divided into three stages according to the number of multiplications that has to be    
+     * taken place between inputA samples and inputB samples. In the first stage of the    
+     * algorithm, the multiplications increase by one for every iteration.    
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+     * In the third stage of the algorithm, the multiplications decrease by one    
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex    
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------    
+     * Initializations of stage1    
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]    
+     * sum = x[0] * y[1] + x[1] * y[0]    
+     * ....    
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.    
+       The count variable holds the number of MAC operations performed.    
+       Since the partial convolution starts from firstIndex    
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------    
+     * Stage1 process    
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------    
+     * Initializations of stage2    
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+     * ....    
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------    
+     * Stage2 process    
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+     * So, to loop unroll over blockSize2,    
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blkCnt */
+
+      blkCnt = blockSize2 / 3;
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+
+        /* read x[0], x[1] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+
+        /* Apply loop unrolling and compute 3 MACs simultaneously. */
+        k = srcBLen / 3;
+
+        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+         ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py);
+
+          /* Read x[2] sample */
+          x2 = *(px);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py - 1u);
+
+          /* Read x[3] sample */
+          x0 = *(px + 1u);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py - 2u);
+
+          /* Read x[4] sample */
+          x1 = *(px + 2u);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x1 *c0;
+
+
+          px += 3u;
+
+          py -= 3u;
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+         ** No loop unrolling is used. */
+        k = srcBLen - (3 * (srcBLen / 3));
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+
+        /* Increment the pointer pIn1 index, count by 3 */
+        count += 3u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,    
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------    
+     * Initializations of stage3    
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+     * ....    
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+     * sum +=  x[srcALen-1] * y[srcBLen-1]    
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.    
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------    
+     * Stage3 process    
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #ifndef ARM_MATH_CM0      */
+
+}
+
+/**    
+ * @} end of PartialConv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 0000000000..ed205838ed
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,733 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q7.c   
+*   
+* Description:	Partial convolution of Q7 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q7 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *  
+ * \par    
+ * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
+ *  
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 0u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 4 */
+        count += 4u;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the pointer pIn1 index, count by 1 */
+ 	    count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+      	px = pIn1 + count;
+        py = pSrc2;	
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 0000000000..1907719e74
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,733 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q15.c   
+*   
+* Description:	Convolution of Q15 sequences.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
+ *
+ * \par    
+ * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
+ *  
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      py = py - 1u;
+
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px+1);
+	  px+= 2u;
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px+1);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *__SIMD32(py)--;
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px+2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px+3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py+1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = _SIMD32_OFFSET(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px+1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+		c0 = *(py-1);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 =  _SIMD32_OFFSET(px+2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+       /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*  #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 0000000000..769b95abb0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,564 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_conv_q31.c    
+*    
+* Description:	Convolution of Q31 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Conv    
+ * @{    
+ */
+
+/**    
+ * @brief Convolution of Q31 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2;                        /* Accumulator */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally    
+   * divided into three stages according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first stage of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
+   * In the third stage of the algorithm, the multiplications decrease by one    
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.    
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]    
+   * sum = x[0] * y[1] + x[1] * y[0]    
+   * ....    
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py);
+
+        /* Read x[3] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py - 1u);
+
+        /* Read x[4] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py - 2u);
+
+        /* Read x[5] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3u;
+        py -= 3u;
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
+   * sum +=  x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31u);
+  }
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of Conv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 0000000000..eb78fd5333
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,689 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q7.c   
+*   
+* Description:	Convolution of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*  
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
+ *
+ * \par    
+ * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
+ * 
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = (srcALen - srcBLen) + 1u;
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 0000000000..6a99eafc15
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,738 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_f32.c    
+*    
+* Description:	 Correlation of floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup Corr Correlation    
+ *    
+ * Correlation is a mathematical operation that is similar to convolution.    
+ * As with convolution, correlation uses two signals to produce a third signal.    
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.    
+ * Correlation is commonly used to measure the similarity between two signals.    
+ * It has applications in pattern recognition, cryptanalysis, and searching.    
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.    
+ * Fast versions of the Q15 and Q31 functions are also provided.    
+ *    
+ * \par Algorithm    
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
+ * The convolution of the two signals is denoted by    
+ * 
    
+ *                   c[n] = a[n] * b[n]    
+ * 
    
+ * In correlation, one of the signals is flipped in time    
+ * 
    
+ *                   c[n] = a[n] * b[-n]    
+ * 
    
+ *    
+ * \par    
+ * and this is mathematically defined as    
+ * \image html CorrelateEquation.gif    
+ * \par    
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.    
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).    
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.    
+ *    
+ * Note   
+ * \par  
+ * The pDst should be initialized to all zeros before being used.  
+ *  
+ * Fixed-Point Behavior    
+ * \par    
+ * Correlation requires summing up a large number of intermediate products.    
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
+ * Refer to the function specific documentation below for further details of the particular algorithm used.    
+ *
+ *
+ * Fast Versions
+ *
+ * \par 
+ * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.   
+ *
+ *
+ * Opt Versions
+ *
+ * \par 
+ * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+/**    
+ * @brief Correlation of floating-point sequences.    
+ * @param[in]  *pSrcA points to the first input sequence.    
+ * @param[in]  srcALen length of the first input sequence.    
+ * @param[in]  *pSrcB points to the second input sequence.    
+ * @param[in]  srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,    
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while(j > 0u)   
+    //{   
+    //  /* Zero is stored in the destination buffer */   
+    //  *pOut++ = 0.0f;   
+
+    //  /* Decrement the loop counter */   
+    //  j--;   
+    //}   
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two    
+   * inputs of same length. But to improve the performance, we include zeroes    
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted   
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 0000000000..a99225a2f5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,507 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_fast_opt_q15.c    
+*    
+* Description:	Fast Q15 Correlation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+ * @return none.    
+ *    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch buffers should be aligned by 32-bit    
+ *    
+ *     
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
+ *    
+ * \par    
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
+ */
+
+void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1u) % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLAD(x1, y1, acc0);
+
+      acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+	  a = *pScr;
+	  b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLAD(x2, y2, acc0);
+
+      acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      acc1 = __SMLADX(x3, y2, acc1);
+
+	  a = *(pScr + 2);
+	  b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+
+      pScr += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15u, 16));
+    pOut += inc;
+
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1u;
+
+  }
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 0000000000..0c79bc8968
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1314 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q15.c   
+*   
+* Description:	Fast Q15 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q15_t a, b;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+	  a = *px;
+	  b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  x0 = __PKHBT(a, b, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  x0 = __PKHBT(b, a, 16);
+	  a = *(px + 2);
+	  x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3], x[4] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x2 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x2 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x3 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+		  a = *(py + 2);
+		  b = *(py + 3);
+
+		  py += 4u;
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5], x[6] */
+	  	a = *(px + 2);
+	  	b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x0 = __PKHBT(a, b, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x0 = __PKHBT(b, a, 16);
+	  	a = *(px + 4);
+	  	x1 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+		a = *px;
+		b = *(px + 1);
+
+		px++;;
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		x3 = __PKHBT(a, b, 16);
+	
+#else
+	
+		x3 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+		  a = *py;
+		  b = *(py + 1);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		  c0 = __PKHBT(a, b, 16);
+	
+#else
+	
+		  c0 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		py += 2u;
+
+        /* Read x[7], x[8], x[9] */
+	  	a = *px;
+	  	b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  	x3 = __PKHBT(a, b, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(b, a, 16);
+
+#else
+
+	  	x3 = __PKHBT(b, a, 16);
+	  	a = *(px + 2);
+	  	x2 = __PKHBT(a, b, 16);
+
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        c0 = (*py);
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+		b = *(px + 3);
+	
+#ifndef ARM_MATH_BIG_ENDIAN
+	
+		x3 = __PKHBT(a, b, 16);
+	
+#else
+	
+		x3 = __PKHBT(b, a, 16);
+	
+#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
+
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 0000000000..628fd3ea55
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,607 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_fast_q31.c    
+*    
+* Description:	Fast Q31 Correlation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ *    
+ * \par    
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 4 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
index 0000000000..cc33b54f5a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_opt_q15.c    
+*    
+* Description:	Correlation of Q15 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @return none.    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch buffers should be aligned by 32-bit    
+ *     
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * This approach provides 33 guard bits and there is no risk of overflow.    
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
+ *    
+ * \par    
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *  
+ * 
+ */
+
+
+void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */
+  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
+  int32_t inc = 1;                               /* output pointer increment     */
+  uint32_t tapCnt;
+  q31_t y1, y2;
+  q15_t *pScr;                                   /* Intermediate pointers        */
+  q15_t *pOut = pDst;                            /* output pointer               */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+  q15_t a, b;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  pScr = pScratch;
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Copy (srcALen) samples in scratch buffer */
+  arm_copy_q15(pIn1, pScr, srcALen);
+
+  /* Update pointers */
+  //pIn1 += srcALen;    
+  pScr += srcALen;
+
+#else
+
+  /* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = srcALen % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = *pIn1++;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  j = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  j = (srcBLen - 1u) % 0x4u;
+
+  while(j > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr++ = 0;
+
+    /* Decrement the loop counter */
+    j--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for scratch2 */
+  py = pIn2;
+
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read four samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr)++;
+
+    /* Read next four samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pIn2);
+      y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+      x1 = _SIMD32_OFFSET(pScr);
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+      x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#else	 
+
+      /* Read four samples from smaller buffer */
+	  a = *pIn2;
+	  b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      y1 = __PKHBT(a, b, 16);
+#else
+      y1 = __PKHBT(b, a, 16);
+#endif
+	  
+	  a = *(pIn2 + 2);
+	  b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+      y2 = __PKHBT(a, b, 16);
+#else
+      y2 = __PKHBT(b, a, 16);
+#endif				
+
+      acc0 = __SMLALD(x1, y1, acc0);
+
+      acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc1 = __SMLALDX(x3, y1, acc1);
+
+	  a = *pScr;
+	  b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(a, b, 16);
+#else
+      x1 = __PKHBT(b, a, 16);
+#endif
+
+      acc0 = __SMLALD(x2, y2, acc0);
+
+      acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y1, acc3);
+
+      acc1 = __SMLALDX(x3, y2, acc1);
+
+	  a = *(pScr + 2);
+	  b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x2 = __PKHBT(a, b, 16);
+#else
+      x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      pIn2 += 4u;
+
+      pScr += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2);
+      acc1 += (*pScr++ * *pIn2);
+      acc2 += (*pScr++ * *pIn2);
+      acc3 += (*pScr++ * *pIn2++);
+
+      pScr -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+
+    /* Store the results in the accumulators in the destination buffer. */
+    *pOut = (__SSAT(acc0 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc1 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc2 >> 15u, 16));
+    pOut += inc;
+    *pOut = (__SSAT(acc3 >> 15u, 16));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr = pScratch;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+
+      acc0 += (*pScr++ * *pIn2++);
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr++ * *pIn2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pIn2 = py;
+
+    pScratch += 1u;
+
+  }
+
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
index 0000000000..6749b01b38
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,463 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_opt_q7.c    
+*    
+* Description:	Correlation of Q7 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+* 
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q7 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
+ * @return none.    
+ *    
+ *    
+ * \par Restrictions    
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
+ *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
+ *        
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.  
+ *  
+ * 
+ */
+
+
+
+void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2)
+{
+  q7_t *pOut = pDst;                             /* output pointer                */
+  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */
+  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */
+  q7_t *pIn1;                                    /* inputA pointer                */
+  q7_t *pIn2;                                    /* inputB pointer                */
+  q15_t *py;                                     /* Intermediate inputB pointer   */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
+  uint32_t j, k = 0u, blkCnt;                    /* loop counter                  */
+  int32_t inc = 1;                               /* output pointer increment          */
+  uint32_t outBlockSize;                         /* loop counter                  */
+  q15_t x4;                                      /* Temporary input variable      */
+  uint32_t tapCnt;                               /* loop counter                  */
+  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,        
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,        
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB        
+     * to make their lengths equal.        
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+
+  /* Copy (srcBLen) samples in scratch buffer */
+  k = srcBLen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcBLen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn2++;
+    *pScr2++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* Fill (srcBLen - 1u) zeros in scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update temporary scratch pointer */
+  pScr1 += (srcBLen - 1u);
+
+  /* Copy (srcALen) samples in scratch buffer */
+  k = srcALen >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = srcALen % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    x4 = (q15_t) * pIn1++;
+    *pScr1++ = x4;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+  arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+  /* Update pointer */
+  pScr1 += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+  k = (srcBLen - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling copies 4 data points at a time.       
+   ** a second loop below copies for the remaining 1 to 3 samples. */
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner */
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+  /* If the count is not a multiple of 4, copy remaining samples here.       
+   ** No loop unrolling is used. */
+  k = (srcBLen - 1u) % 0x4u;
+
+  while(k > 0u)
+  {
+    /* copy second buffer in reversal manner for remaining samples */
+    *pScr1++ = 0;
+
+    /* Decrement the loop counter */
+    k--;
+  }
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /* Temporary pointer for second sequence */
+  py = pScratch2;
+
+  /* Initialization of pScr2 pointer */
+  pScr2 = pScratch2;
+
+  /* Actual correlation process starts here */
+  blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Read two samples from scratch1 buffer */
+    x1 = *__SIMD32(pScr1)++;
+
+    /* Read next two samples from scratch1 buffer */
+    x2 = *__SIMD32(pScr1)++;
+
+    tapCnt = (srcBLen) >> 2u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2);
+
+      /* multiply and accumlate */
+      acc0 = __SMLAD(x1, y1, acc0);
+      acc2 = __SMLAD(x2, y1, acc2);
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      /* multiply and accumlate */
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      /* Read next two samples from scratch1 buffer */
+      x1 = *__SIMD32(pScr1)++;
+
+      /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x1, x2, 0);
+#else
+      x3 = __PKHBT(x2, x1, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      /* Read four samples from smaller buffer */
+      y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+      acc0 = __SMLAD(x2, y1, acc0);
+
+      acc2 = __SMLAD(x1, y1, acc2);
+
+      acc1 = __SMLADX(x3, y1, acc1);
+
+      x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+      x3 = __PKHBT(x2, x1, 0);
+#else
+      x3 = __PKHBT(x1, x2, 0);
+#endif
+
+      acc3 = __SMLADX(x3, y1, acc3);
+
+      pScr2 += 4u;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+
+
+    /* Update scratch pointer for remaining samples of smaller length sequence */
+    pScr1 -= 4u;
+
+
+    /* apply same above for remaining samples of smaller length sequence */
+    tapCnt = (srcBLen) & 3u;
+
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2);
+      acc1 += (*pScr1++ * *pScr2);
+      acc2 += (*pScr1++ * *pScr2);
+      acc3 += (*pScr1++ * *pScr2++);
+
+      pScr1 -= 3u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
+    pOut += inc;
+    *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 4u;
+
+  }
+
+
+  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+  /* Calculate correlation for remaining samples of Bigger length sequence */
+  while(blkCnt > 0)
+  {
+    /* Initialze temporary scratch pointer as scratch1 */
+    pScr1 = pScratch1;
+
+    /* Clear Accumlators */
+    acc0 = 0;
+
+    tapCnt = (srcBLen) >> 1u;
+
+    while(tapCnt > 0u)
+    {
+      acc0 += (*pScr1++ * *pScr2++);
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    tapCnt = (srcBLen) & 1u;
+
+    /* apply same above for remaining samples of smaller length sequence */
+    while(tapCnt > 0u)
+    {
+
+      /* accumlate the results */
+      acc0 += (*pScr1++ * *pScr2++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    blkCnt--;
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+    pOut += inc;
+
+    /* Initialization of inputB pointer */
+    pScr2 = py;
+
+    pScratch1 += 1u;
+
+  }
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 0000000000..fc4134b7b8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,718 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q15.c   
+*   
+* Description:	Correlation of Q15 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences. 
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
+ *
+ * \par    
+ * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
+ * 
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *__SIMD32(px);
+      /* read x[1], x[2] samples */
+      x1 = _SIMD32_OFFSET(px + 1);
+	  px += 2u;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *__SIMD32(px);
+
+        /* Read x[3], x[4] */
+        x3 = _SIMD32_OFFSET(px + 1);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *__SIMD32(py)++;
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = _SIMD32_OFFSET(px + 2);
+
+        /* Read x[5], x[6] */
+        x1 = _SIMD32_OFFSET(px + 3);
+
+		px += 4u;
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *__SIMD32(px);
+		px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py);
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+		px += 2u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *__SIMD32(py)++;
+
+        /* Read x[7], x[8] */
+        x3 = *__SIMD32(px);
+
+        /* Read x[9] */
+        x2 = _SIMD32_OFFSET(px + 1);
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        c0 = (*py);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+#else
+
+        c0 = c0 & 0x0000FFFF;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = _SIMD32_OFFSET(px + 2);
+		px += 3u;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 0000000000..c81f8600dc
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,664 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_correlate_q31.c    
+*    
+* Description:	Correlation of Q31 sequences.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.11 2011/10/18  
+*    Bug Fix in conv, correlation, partial convolution.  
+* 
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup Corr    
+ * @{    
+ */
+
+/**    
+ * @brief Correlation of Q31 sequences.    
+ * @param[in] *pSrcA points to the first input sequence.    
+ * @param[in] srcALen length of the first input sequence.    
+ * @param[in] *pSrcB points to the second input sequence.    
+ * @param[in] srcBLen length of the second input sequence.    
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * Thus, if the accumulator overflows it wraps around and distorts the result.    
+ * The input signals should be scaled down to avoid intermediate overflows.    
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */
+  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,    
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,    
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB    
+     * to make their lengths equal.    
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally    
+   * divided into three parts according to the number of multiplications that has to be    
+   * taken place between inputA samples and inputB samples. In the first part of the    
+   * algorithm, the multiplications increase by one for every iteration.    
+   * In the second part of the algorithm, srcBLen number of multiplications are done.    
+   * In the third part of the algorithm, the multiplications decrease by one    
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.    
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------    
+   * Initializations of stage1    
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]    
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
+   * ....    
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------    
+   * Stage1 process    
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------    
+   * Initializations of stage2    
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
+   * ....    
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------    
+   * Stage2 process    
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
+   * So, to loop unroll over blockSize2,    
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll by 3 */
+    blkCnt = blockSize2 / 3;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+
+      /* Apply loop unrolling and compute 3 MACs simultaneously. */
+      k = srcBLen / 3;
+
+      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
+       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py);
+
+        /* Read x[2] sample */
+        x2 = *(px);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py + 1u);
+
+        /* Read x[3] sample */
+        x0 = *(px + 1u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x0 * c0);
+
+        /* Read y[2] sample */
+        c0 = *(py + 2u);
+
+        /* Read x[4] sample */
+        x1 = *(px + 2u);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x1 * c0);
+
+        /* update scratch pointers */
+        px += 3u;
+        py += 3u;
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
+       ** No loop unrolling is used. */
+      k = srcBLen - (3 * (srcBLen / 3));
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 3 */
+      count += 3u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,    
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------    
+   * Initializations of stage3    
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
+   * ....    
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
+   * sum +=  x[srcALen-1] * y[0]    
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.    
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------    
+   * Stage3 process    
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.    
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two    
+   * inputs of same length. But to improve the performance, we include zeroes    
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted   
+   * using correlation but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate correlation for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to correlation equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q31_t) (sum >> 31u);
+    else
+      *pDst++ = (q31_t) (sum >> 31u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of Corr group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 0000000000..e03e4997b6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,789 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q7.c   
+*   
+* Description:	Correlation of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*
+* Version 1.0.11 2011/10/18 
+*    Bug Fix in conv, correlation, partial convolution. 
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
+ *
+ * \par    
+ * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
+ * 
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+	  count += 4u;
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+	  count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 0000000000..1546f407dd
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,518 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_f32.c    
+*    
+* Description:	FIR decimation for floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator    
+ *    
+ * These functions combine an FIR filter together with a decimator.    
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.    
+ * Conceptually, the functions are equivalent to the block diagram below:    
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"    
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized    
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.    
+ * The user of the function is responsible for providing the filter coefficients.    
+ *    
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.    
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the    
+ * samples output by the decimator are computed.    
+ * The functions operate on blocks of input and output data.    
+ * pSrc points to an array of blockSize input values and    
+ * pDst points to an array of blockSize/M output values.    
+ * In order to have an integer number of output samples blockSize    
+ * must always be a multiple of the decimation factor M.    
+ *    
+ * The library provides separate functions for Q15, Q31 and floating-point data types.    
+ *    
+ * \par Algorithm:    
+ * The FIR portion of the algorithm uses the standard form filter:    
+ * 
    
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * 
    
+ * where, b[n] are the filter coefficients.    
+ * \par   
+ * The pCoeffs points to a coefficient array of size numTaps.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to a state array of size numTaps + blockSize - 1.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * 
    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * 
    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * 
    
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    
+ * 
    
+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;    
+ * pCoeffs is the address of the coefficient buffer;    
+ * pState is the address of the state buffer.    
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+  /**    
+   * @brief Processing function for the floating-point FIR decimator.    
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.    
+   * @param[in] *pSrc     points to the block of input data.    
+   * @param[out] *pDst    points to the block of output data.    
+   * @param[in] blockSize number of input samples to process per call.    
+   * @return none.    
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  uint32_t blkCntN4;
+  float32_t *px0, *px1, *px2, *px3;
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 4;
+  blkCntN4 = outBlockSize - (4 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy 4 * decimation factor number of new input samples into the state buffer */
+    i = 4 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer for all the samples */
+    px0 = pState;
+    px1 = pState + S->M;
+    px2 = pState + 2 * S->M;
+    px3 = pState + 3 * S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample for acc0 */
+      x0 = *(px0++);
+      /* Read x[n-numTaps-1] sample for acc1 */
+      x1 = *(px1++);
+      /* Read x[n-numTaps-1] sample for acc2 */
+      x2 = *(px2++);
+      /* Read x[n-numTaps-1] sample for acc3 */
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch  state variables for acc0, acc1, acc2, acc3 */
+      x0 = *(px0++);
+      x1 = *(px1++);
+      x2 = *(px2++);
+      x3 = *(px3++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + 4 * S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN4 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 0000000000..96f50e6f2b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,590 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_fast_q15.c    
+*    
+* Description:	Fast Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * \par Restrictions   
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
+ *	In this case input, output, state buffers should be aligned by 32-bit   
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).    
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
+ *    
+ * \par    
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
+ * Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.    
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  q31_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 0000000000..a43fd0b4c9
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,343 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_fast_q31.c    
+*    
+* Description:	Fast Q31 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
+ *    
+ * \par    
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
+ * Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.    
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q31_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+  uint32_t blkCntN2;
+  q31_t x1;
+  q31_t acc0, acc1;
+  q31_t *px0, *px1;
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+
+  blkCnt = outBlockSize / 2;
+  blkCntN2 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+    px1 = pState + S->M;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb);
+
+      /* Read x[n-numTaps-1] for sample 0 sample 1 */
+      x0 = *(px0);
+      x1 = *(px1);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb + 1u);
+
+      /* Read x[n-numTaps-2]  for sample 0 sample 1  */
+      x0 = *(px0 + 1u);
+      x1 = *(px1 + 1u);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb + 2u);
+
+      /* Read x[n-numTaps-3]  for sample 0 sample 1 */
+      x0 = *(px0 + 2u);
+      x1 = *(px1 + 2u);
+      pb += 4u;
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb - 1u);
+
+      /* Read x[n-numTaps-4] for sample 0 sample 1 */
+      x0 = *(px0 + 3u);
+      x1 = *(px1 + 3u);
+
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* update state pointers */
+      px0 += 4u;
+      px1 += 4u;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px0++);
+      x1 = *(px1++);
+
+      /* Perform the multiply-accumulate */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN2 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCntN2--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 0000000000..b655a6be6d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_f32.c    
+*    
+* Description:  Floating-point FIR Decimator initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point FIR decimator.    
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * blockSize is not a multiple of M.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().    
+ * M is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 0000000000..1a1fee8a2e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_q15.c    
+*    
+* Description:  Initialization function for the Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q15 FIR decimator.    
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * blockSize is not a multiple of M.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples    
+ * to the call arm_fir_decimate_q15().    
+ * M is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 0000000000..e2ac8165e6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_decimate_init_q31.c    
+*    
+* Description:  Initialization function for Q31 FIR Decimation filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q31 FIR decimator.    
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] numTaps  number of coefficients in the filter.    
+ * @param[in] M  decimation factor.    
+ * @param[in] *pCoeffs points to the filter coefficients.    
+ * @param[in] *pState points to the state buffer.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * blockSize is not a multiple of M.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().    
+ * M is the decimation factor.    
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 0000000000..28b5f13dd6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_q15.c    
+*    
+* Description:	Q15 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR decimator.    
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the location where the output result is written.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ *    
+ * \par    
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+#ifndef ARM_MATH_CM0
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px0)++;
+
+      x1 = *__SIMD32(px1)++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c1 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c1, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  q63_t acc0, acc1;
+  q15_t *px0, *px1;
+  uint32_t blkCntN3;
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize / 2;
+  blkCntN3 = outBlockSize - (2 * blkCnt);
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = 2 * S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    acc0 = 0;
+    acc1 = 0;
+
+    /* Initialize state pointer */
+    px0 = pState;
+
+    px1 = pState + S->M;
+
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px0++;
+      x1 = *px1++;
+
+      /* Perform the multiply-accumulate */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M * 2;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  while(blkCntN3 > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-1] and sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-2] and  sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3]  coefficients */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *pb++;
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor       
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCntN3--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#else
+
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+}
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 0000000000..59c0fed7f8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,306 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_decimate_q31.c    
+*    
+* Description:	Q31 FIR Decimator.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_decimate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR decimator.    
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
+ *    
+ * \par    
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor    
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor           
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_decimate group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 0000000000..7f951f86bc
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,554 @@
+/* ----------------------------------------------------------------------  
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_fir_f32.c  
+*  
+* Description:	Floating-point FIR filter processing function.  
+*  
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated.  
+*  
+* Version 0.0.5  2010/04/26   
+* 	 incorporated review comments and updated with latest CMSIS layer  
+*  
+* Version 0.0.3  2010/03/10   
+*    Initial version  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**  
+ * @ingroup groupFilters  
+ */
+
+/**  
+ * @defgroup FIR Finite Impulse Response (FIR) Filters  
+ *  
+ * This set of functions implements Finite Impulse Response (FIR) filters  
+ * for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.  
+ * The functions operate on blocks of input and output data and each call to the function processes  
+ * blockSize samples through the filter.  pSrc and  
+ * pDst points to input and output arrays containing blockSize values.  
+ *  
+ * \par Algorithm:  
+ * The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.  
+ * Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].  
+ * 
  
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  
+ * 
  
+ * \par  
+ * \image html FIR.gif "Finite Impulse Response filter"  
+ * \par  
+ * pCoeffs points to a coefficient array of size numTaps.  
+ * Coefficients are stored in time reversed order.  
+ * \par  
+ * 
  
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  
+ * 
  
+ * \par  
+ * pState points to a state array of size numTaps + blockSize - 1.  
+ * Samples in the state buffer are stored in the following order.  
+ * \par  
+ * 
  
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  
+ * 
  
+ * \par  
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.  
+ * The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,  
+ * to be avoided and yields a significant speed improvement.  
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.  
+ * \par Instance Structure  
+ * The coefficients and state variables for a filter are stored together in an instance data structure.  
+ * A separate instance structure must be defined for each filter.  
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.  
+ * There are separate instance structure declarations for each of the 4 supported data types.  
+ *  
+ * \par Initialization Functions  
+ * There is also an associated initialization function for each data type.  
+ * The initialization function performs the following operations:  
+ * - Sets the values of the internal structure fields.  
+ * - Zeros out the values in the state buffer.  
+ *  
+ * \par  
+ * Use of the initialization function is optional.  
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.  
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.  
+ * Set the values in the state buffer to zeros before static initialization.  
+ * The code below statically initializes each of the 4 different data type filter instance structures  
+ * 
  
+ *arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  
+ *arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  
+ *arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  
+ *arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  
+ * 
  
+ *  
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;  
+ * pCoeffs is the address of the coefficient buffer.  
+ *  
+ * \par Fixed-Point Behavior  
+ * Care must be taken when using the fixed-point versions of the FIR filter functions.  
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.  
+ * Refer to the function specific documentation below for usage guidelines.  
+ */
+
+/**  
+ * @addtogroup FIR  
+ * @{  
+ */
+
+/**  
+ *  
+ * @param[in]  *S points to an instance of the floating-point FIR filter structure.  
+ * @param[in]  *pSrc points to the block of input data.  
+ * @param[out] *pDst points to the block of output data.  
+ * @param[in]  blockSize number of samples to process per call.  
+ * @return     none.  
+ *  
+ */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
+  float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.  
+   * The variables acc0 ... acc3 hold output values that are being computed:  
+   *  
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
+   */
+  blkCnt = blockSize >> 3;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+    acc4 = 0.0f;
+    acc5 = 0.0f;
+    acc6 = 0.0f;
+    acc7 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the first three samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *px++;
+    x1 = *px++;
+    x2 = *px++;
+    x3 = *px++;
+    x4 = *px++;
+    x5 = *px++;
+    x6 = *px++;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 3u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.  
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x7 = *(px++);
+
+      /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+      acc0 += x0 * c0;
+
+      /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+      acc1 += x1 * c0;
+
+      /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+      acc2 += x2 * c0;
+
+      /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+      acc3 += x3 * c0;
+
+      /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
+      acc4 += x4 * c0;
+
+      /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
+      acc5 += x5 * c0;
+
+      /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
+      acc6 += x6 * c0;
+
+      /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
+      acc7 += x7 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x1 * c0;
+      acc1 += x2 * c0;
+      acc2 += x3 * c0;
+      acc3 += x4 * c0;
+      acc4 += x5 * c0;
+      acc5 += x6 * c0;
+      acc6 += x7 * c0;
+      acc7 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x2 * c0;
+      acc1 += x3 * c0;
+      acc2 += x4 * c0;
+      acc3 += x5 * c0;
+      acc4 += x6 * c0;
+      acc5 += x7 * c0;
+      acc6 += x0 * c0;
+      acc7 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x3 * c0;
+      acc1 += x4 * c0;
+      acc2 += x5 * c0;
+      acc3 += x6 * c0;
+      acc4 += x7 * c0;
+      acc5 += x0 * c0;
+      acc6 += x1 * c0;
+      acc7 += x2 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x4 * c0;
+      acc1 += x5 * c0;
+      acc2 += x6 * c0;
+      acc3 += x7 * c0;
+      acc4 += x0 * c0;
+      acc5 += x1 * c0;
+      acc6 += x2 * c0;
+      acc7 += x3 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x4 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x5 * c0;
+      acc1 += x6 * c0;
+      acc2 += x7 * c0;
+      acc3 += x0 * c0;
+      acc4 += x1 * c0;
+      acc5 += x2 * c0;
+      acc6 += x3 * c0;
+      acc7 += x4 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x5 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x6 * c0;
+      acc1 += x7 * c0;
+      acc2 += x0 * c0;
+      acc3 += x1 * c0;
+      acc4 += x2 * c0;
+      acc5 += x3 * c0;
+      acc6 += x4 * c0;
+      acc7 += x5 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x6 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x7 * c0;
+      acc1 += x0 * c0;
+      acc2 += x1 * c0;
+      acc3 += x2 * c0;
+      acc4 += x3 * c0;
+      acc5 += x4 * c0;
+      acc6 += x5 * c0;
+      acc7 += x6 * c0;
+
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x8u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x7 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+      acc4 += x4 * c0;
+      acc5 += x5 * c0;
+      acc6 += x6 * c0;
+      acc7 += x7 * c0;
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+      x3 = x4;
+      x4 = x5;
+      x5 = x6;
+      x6 = x7;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 8;
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+    *pDst++ = acc4;
+    *pDst++ = acc5;
+    *pDst++ = acc6;
+    *pDst++ = acc7;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x8u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc0;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.  
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.  
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t acc;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+/**  
+ * @} end of FIR group  
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 0000000000..59abff2f55
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_fast_q15.c    
+*    
+* Description:  Q15 Fast FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.9  2010/08/16     
+*    Initial version    
+*    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * This fast version uses a 32-bit accumulator with 2.30 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
+ *    
+ * \par    
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_fir_init_q15() to initialize the filter structure.    
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.      
+   * The variables acc0 ... acc3 hold output values that are being computed:      
+   *      
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.      
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.      
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLADX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4u;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLADX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLADX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1u;
+
+    do
+    {
+
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.      
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 0000000000..e384ff9732
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,309 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_fast_q31.c    
+*    
+* Description:	Processing function for the Q31 Fast FIR filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.9  2010/08/27     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q31 structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
+ * These intermediate results are added to a 2.30 accumulator.    
+ * Finally, the accumulator is saturated and converted to a 1.31 result.    
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ *    
+ * \par    
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
+ * Use the function arm_fir_init_q31() to initialize the filter structure.    
+ */
+
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31    
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 =
+        (q31_t) ((((q63_t) acc0 << 32) +
+                  ((q63_t) (*px++) * (*(pb++)))) >> 32);
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.31    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 0000000000..aaeddf5f6b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_f32.c    
+*    
+* Description:  Floating-point FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]     *pState points to the state buffer.    
+ * @param[in] 	  blockSize number of samples that are processed per call.    
+ * @return 		  none.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().    
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 0000000000..02bb336235
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_q15.c    
+*    
+* Description:  Q15 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.    
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.    
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]      *pState points to the state buffer.    
+ * @param[in]      blockSize is number of samples processed per call.    
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if    
+ * numTaps is not greater than or equal to 4 and even.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * Note that numTaps must be even and greater than or equal to 4.    
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.    
+ * For example, to implement a filter with numTaps=3 and coefficients    
+ * 
    
+ *     {0.3, -0.8, 0.3}    
+ * 
    
+ * set numTaps=4 and use the coefficients:    
+ * 
    
+ *     {0.3, -0.8, 0.3, 0}.    
+ * 
    
+ * Similarly, to implement a two point filter    
+ * 
    
+ *     {0.3, -0.3}    
+ * 
    
+ * set numTaps=4 and use the coefficients:    
+ * 
    
+ *     {0.3, -0.3, 0, 0}.    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3  and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().    
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if(numTaps & 0x1u)
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */
+    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 0000000000..997a78427f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_init_q31.c    
+*    
+* Description:	Q31 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @details    
+ *    
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
+ * @param[in] 	  *pState points to the state buffer.    
+ * @param[in] 	  blockSize number of samples that are processed per call.    
+ * @return        none.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().    
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 0000000000..65a49a823e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_init_q7.c    
+*    
+* Description:  Q7 FIR filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+/**    
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.    
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
+ * @param[in]     *pState points to the state buffer.    
+ * @param[in]     blockSize number of samples that are processed per call.    
+ * @return     	  none    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().    
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 0000000000..c966a0ced7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,574 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_interpolate_f32.c    
+*    
+* Description:	FIR interpolation for floating-point sequences.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator    
+ *    
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.    
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.    
+ * Conceptually, the functions are equivalent to the block diagram below:    
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"    
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized    
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.    
+ * The user of the function is responsible for providing the filter coefficients.    
+ *    
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.    
+ * The upsampler inserts L-1 zeros between each sample.    
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.    
+ * This leads to an efficient implementation without any wasted effort.    
+ * The functions operate on blocks of input and output data.    
+ * pSrc points to an array of blockSize input values and    
+ * pDst points to an array of blockSize*L output values.    
+ *    
+ * The library provides separate functions for Q15, Q31, and floating-point data types.    
+ *    
+ * \par Algorithm:    
+ * The functions use a polyphase filter structure:    
+ * 
    
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    
+ *    ...    
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    
+ * 
    
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.    
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.    
+ * \par    
+ * pCoeffs points to a coefficient array of size numTaps.    
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the    
+ * initialization functions.    
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length    
+ * phaseLength=numTaps/L.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to a state array of size blockSize + phaseLength - 1.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * 
    
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * 
    
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.    
+ *    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * 
    
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    
+ * 
    
+ * where L is the interpolation factor; phaseLength=numTaps/L is the    
+ * length of each of the shorter FIR filters used internally,    
+ * pCoeffs is the address of the coefficient buffer;    
+ * pState is the address of the state buffer.    
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point FIR interpolator.    
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ */
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+  float32_t acc0, acc1, acc2, acc3;
+  float32_t x1, x2, x3;
+  uint32_t blkCntN4;
+  float32_t c1, c2, c3;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 4;
+  blkCntN4 = blockSize - (4 * blkCnt);
+
+  /* Samples loop unrolled by 4 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+      x1 = *(ptr1++);
+      x2 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Read the coefficient */
+        c1 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x1 * c1;
+        acc1 += x2 * c1;
+        acc2 += x3 * c1;
+        acc3 += x0 * c1;
+
+        /* Read the coefficient */
+        c2 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x2 * c2;
+        acc1 += x3 * c2;
+        acc2 += x0 * c2;
+        acc3 += x1 * c2;
+
+        /* Read the coefficient */
+        c3 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x2 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x3 * c3;
+        acc1 += x0 * c3;
+        acc2 += x1 * c3;
+        acc3 += x2 * c3;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x3 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += x0 * c0;
+        acc1 += x1 * c0;
+        acc2 += x2 * c0;
+        acc3 += x3 * c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = acc0;
+      *(pDst + S->L) = acc1;
+      *(pDst + 2 * S->L) = acc2;
+      *(pDst + 3 * S->L) = acc3;
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 4;
+
+    pDst += S->L * 3;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+
+  while(blkCntN4 > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCntN4--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 0000000000..b193472647
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,116 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_f32.c    
+*    
+* Description:  Floating-point FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the floating-point FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length numTaps is not a multiple of the interpolation factor L.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * 
    
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length (numTaps/L)+blockSize-1 words    
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().    
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 0000000000..b344fc785a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,115 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_q15.c    
+*    
+* Description:  Q15 FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief  Initialization function for the Q15 FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length numTaps is not a multiple of the interpolation factor L.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * 
    
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length (numTaps/L)+blockSize-1 words    
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().    
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 0000000000..f0383b8e9b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,116 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_interpolate_init_q31.c    
+*    
+* Description:  Q31 FIR interpolator initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+
+/**    
+ * @brief  Initialization function for the Q31 FIR interpolator.    
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.    
+ * @param[in]     L         upsample factor.    
+ * @param[in]     numTaps   number of filter coefficients in the filter.    
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
+ * @param[in]     *pState   points to the state buffer.    
+ * @param[in]     blockSize number of input samples to process per call.    
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
+ * the filter length numTaps is not a multiple of the interpolation factor L.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ * 
    
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.    
+ * \par    
+ * pState points to the array of state variables.    
+ * pState is of length (numTaps/L)+blockSize-1 words    
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().    
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 0000000000..d17d8d8037
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,503 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fir_interpolate_q15.c    
+*    
+* Description:	Q15 FIR interpolation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 FIR interpolator.    
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q15_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete.    
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	*pStateCurnt++ = *pState++;
+	
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+	
+	/* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 0000000000..689b4d3372
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,499 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fir_interpolate_q31.c    
+*    
+* Description:	Q31 FIR interpolation.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Interpolate    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 FIR interpolator.    
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.    
+ * @param[in] *pSrc     points to the block of input data.    
+ * @param[out] *pDst    points to the block of output data.    
+ * @param[in] blockSize number of input samples to process per call.    
+ * @return none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).    
+ * since numTaps/L additions occur per output sample.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
+ */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+  uint32_t blkCntN2;
+  q63_t acc0, acc1;
+  q31_t x1;
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Initialise  blkCnt */
+  blkCnt = blockSize / 2;
+  blkCntN2 = blockSize - (2 * blkCnt);
+
+  /* Samples loop unrolled by 2 */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = (S->L);
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      acc0 = 0;
+      acc1 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+
+      x0 = *(ptr1++);
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 2);
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2 + S->L * 3);
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x1 *c0;
+        acc1 += (q63_t) x0 *c0;
+
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += 4 * S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+
+        /* Read the input sample */
+        x1 = *(ptr1++);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Perform the multiply-accumulate */
+        acc0 += (q63_t) x0 *c0;
+        acc1 += (q63_t) x1 *c0;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* update states for next sample processing */
+        x0 = x1;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst = (q31_t) (acc0 >> 31);
+      *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+      pDst++;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 2;
+
+    pDst += S->L;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blkCntN2;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.        
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.        
+         * So instead of multiplying zeros with coefficients,        
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1        
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1           
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+ /**    
+  * @} end of FIR_Interpolate group    
+  */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 0000000000..3745ffb6a2
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,499 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_f32.c    
+*    
+* Description:	Processing function for the floating-point FIR Lattice filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters    
+ *    
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters    
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
+ * variety of adaptive filter applications.  The filter structure is feedforward and    
+ * the net impulse response is finite length.    
+ * The functions operate on blocks    
+ * of input and output data and each call to the function processes    
+ * blockSize samples through the filter.  pSrc and    
+ * pDst point to input and output arrays containing blockSize values.    
+ *    
+ * \par Algorithm:    
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"    
+ * The following difference equation is implemented:    
+ * 
    
+ *    f0[n] = g0[n] = x[n]    
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    
+ *    y[n] = fM[n]    
+ * 
    
+ * \par    
+ * pCoeffs points to tha array of reflection coefficients of size numStages.    
+ * Reflection Coefficients are stored in the following order.    
+ * \par    
+ * 
    
+ *    {k1, k2, ..., kM}    
+ * 
    
+ * where M is number of stages    
+ * \par    
+ * pState points to a state array of size numStages.    
+ * The state variables (g values) hold previous inputs and are stored in the following order.    
+ * 
    
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}    
+ * 
    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
+ * 
    
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    
+ * 
    
+ * \par    
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;    
+ * pCoeffs is the address of the coefficient buffer.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+  /**    
+   * @brief Processing function for the floating-point FIR lattice filter.    
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.    
+   * @param[in]  *pSrc     points to the block of input data.    
+   * @param[out] *pDst     points to the block of output data    
+   * @param[in]  blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer    
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1    
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1    
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr            
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1            
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 0000000000..a53ae92e2f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,78 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_f32.c    
+*    
+* Description:  Floating-point FIR Lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Initialization function for the floating-point FIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.    
+ * @param[in] numStages  number of filter stages.    
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.    
+ * @return none.    
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 0000000000..8db4985090
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,78 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_q15.c    
+*    
+* Description:  Q15 FIR Lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q15 FIR lattice filter.    
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.    
+   * @param[in] numStages  number of filter stages.    
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.     
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.     
+   * @return none.    
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 0000000000..035c5e056a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,78 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_lattice_init_q31.c    
+*    
+* Description:  Q31 FIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q31 FIR lattice filter.    
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.    
+   * @param[in] numStages  number of filter stages.    
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.    
+   * @return none.    
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 0000000000..abfb33cf24
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,531 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_q15.c    
+*    
+* Description:	Q15 FIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+/**    
+ * @brief Processing function for the Q15 FIR lattice filter.    
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer    
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.    
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1    
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1    
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt            
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt            
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 0000000000..9fb46459dc
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,348 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_lattice_q31.c    
+*    
+* Description:	Q31 FIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Lattice    
+ * @{    
+ */
+
+
+/**    
+ * @brief Processing function for the Q31 FIR lattice filter.    
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.    
+ * @param[in]  *pSrc     points to the block of input data.    
+ * @param[out] *pDst     points to the block of output data    
+ * @param[in]  blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.    
+ */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+  q31_t k;
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.        
+     a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1u);
+    gnext1 = gcurr1 + (gnext1 << 1u);
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+    fnext2 = fcurr2 + (fnext2 << 1u);
+    gnext2 = fcurr1 + (gnext2 << 1u);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr2;
+
+    /* f1(n) is saved in fcurr1        
+       for next stage processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext2;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+      fnext1 = fcurr1 + (fnext1 << 1u);
+      fnext2 = fcurr2 + (fnext2 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+      gnext2 = gnext1 + (gnext2 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1u);
+
+      /* f1(n) is saved in fcurr1        
+         for next stage processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n - 1) from state buffer */
+    gcurr1 = *px;
+
+    /* Read the reflection coefficient */
+    k = *pk++;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+    fnext1 = fcurr1 + (fnext1 << 1u);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+    gnext1 = gcurr1 + (gnext1 << 1u);
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1        
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* Read the reflection coefficient */
+      k = *pk++;
+
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+      fnext1 = fcurr1 + (fnext1 << 1u);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+      gnext1 = gcurr1 + (gnext1 << 1u);
+
+      /* f1(n) is saved in fcurr1        
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1            
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1            
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+
+/**    
+ * @} end of FIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 0000000000..368014f435
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,689 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_q15.c    
+*    
+* Description:  Q15 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**       
+ * @ingroup groupFilters       
+ */
+
+/**       
+ * @addtogroup FIR       
+ * @{       
+ */
+
+/**       
+ * @brief Processing function for the Q15 FIR filter.       
+ * @param[in] *S points to an instance of the Q15 FIR structure.       
+ * @param[in] *pSrc points to the block of input data.       
+ * @param[out] *pDst points to the block of output data.       
+ * @param[in]  blockSize number of samples to process per call.       
+ * @return none.       
+ *   
+ *   
+ * \par Restrictions   
+ *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
+ *	In this case input, output, state buffers should be aligned by 32-bit   
+ *   
+ * Scaling and Overflow Behavior:       
+ * \par       
+ * The function is implemented using a 64-bit internal accumulator.       
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.       
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.       
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.       
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.       
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.       
+ *       
+ * \par       
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.       
+ */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.       
+   * The variables acc0 ... acc3 hold output values that are being computed:       
+   *       
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]       
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]       
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]       
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]       
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.       
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = _SIMD32_OFFSET(px1);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = _SIMD32_OFFSET(px1 + 1u);
+
+    px1 += 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.       
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = _SIMD32_OFFSET(px1);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = _SIMD32_OFFSET(px1 + 1u);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px1 + 2u);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = _SIMD32_OFFSET(px1 + 3u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+
+      px1 += 4u;
+
+      tapCnt--;
+
+    }
+
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Fetch 4 state variables */
+      x2 = _SIMD32_OFFSET(px1);
+
+      x3 = _SIMD32_OFFSET(px1 + 1u);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      px1 += 2u;
+
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+
+      c0 = *__SIMD32(pb)++;
+      x0 = *__SIMD32(px1)++;
+
+      acc0 = __SMLALD(x0, c0, acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.       
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Copy state values to start of state buffer */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.      
+   * The variables acc0 ... acc3 hold output values that are being computed:      
+   *      
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
+   */
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.      
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+    px = pState;
+
+    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *__SIMD32(px)++;
+
+    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+    x2 = *__SIMD32(px)++;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.      
+     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0)
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack  x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = _SIMD32_OFFSET(px);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *__SIMD32(pb)++;
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* Read state x[n-N-6], x[n-N-7] with offset */
+      x2 = _SIMD32_OFFSET(px + 2u);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack  x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALDX(x1, c0, acc3);
+
+      /* Update state pointer for next state reading */
+      px += 4u;
+
+      /* Decrement tap count */
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+
+      /* Read last two coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x2, x0, 0);
+#else
+      x1 = __PKHBT(x0, x2, 0);
+#endif
+
+      /* Read last state variables */
+      x0 = *__SIMD32(px);
+
+      /* Perform the multiply-accumulates */
+      acc1 = __SMLALDX(x1, c0, acc1);
+
+      /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+      x1 = __PKHBT(x0, x2, 0);
+#else
+      x1 = __PKHBT(x2, x0, 0);
+#endif
+
+      /* Perform the multiply-accumulates */
+      acc3 = __SMLALDX(x1, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px = pState;
+    pb = pCoeffs;
+
+    tapCnt = numTaps >> 1u;
+
+    do
+    {
+      acc0 += (q31_t) * px++ * *pb++;
+	  acc0 += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.      
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0 */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15         
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+
+
+/**       
+ * @} end of FIR group       
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 0000000000..b3b84ec51f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,363 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_q31.c    
+*    
+* Description:	Q31 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process per call.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.  
+ *    
+ * \par    
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2;                              /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2;                        /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize / 3;
+  blockSize = blockSize - (3 * blkCnt);
+
+  tapCnt = numTaps / 3;
+  tapCntN3 = numTaps - (3 * tapCnt);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy three new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first two samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1] */
+    x0 = *(px++);
+    x1 = *(px++);
+
+    /* Loop unrolling.  Process 3 taps at a time. */
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *pb;
+
+      /* Read x[n-numTaps-2] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 1u);
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x0 * c0);
+
+      /* Read the coefficient and state */
+      c0 = *(pb + 2u);
+      x1 = *(px++);
+
+      /* update coefficient pointer */
+      pb += 3u;
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+    i = tapCntN3;
+
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 3 to process the next group of 3 samples */
+    pState = pState + 3;
+
+    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31    
+     ** Then store the 3 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+    *pDst++ = (q31_t) (acc1 >> 31u);
+    *pDst++ = (q31_t) (acc2 >> 31u);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+
+  while(blockSize > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blockSize--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31         
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 0000000000..624afa130a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,388 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_q7.c    
+*    
+* Description:  Q7 FIR filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR    
+ * @{    
+ */
+
+/**    
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.    
+ * @param[in]   *pSrc points to the block of input data.    
+ * @param[out]  *pDst points to the block of output data.    
+ * @param[in]   blockSize number of samples to process per call.    
+ * @return 	none.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.    
+ * Finally, the result is truncated to 1.7 format.    
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.    
+   * The variables acc0 ... acc3 hold output values that are being computed:    
+   *    
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:    
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31    
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7u), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7u), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7u), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7u), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.14 format.  Convert to 1.7    
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.    
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while(i > 0u)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.         
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* Copy q7_t data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 0000000000..e969d5c842
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,365 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_f32.c    
+*    
+* Description:	Floating-point sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters    
+ *    
+ * This group of functions implements sparse FIR filters.     
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.   
+ * Sparse filters are used for simulating reflections in communications and audio applications.   
+ *   
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.    
+ * The functions operate on blocks  of input and output data and each call to the function processes    
+ * blockSize samples through the filter.  pSrc and    
+ * pDst points to input and output arrays respectively containing blockSize values.    
+ *    
+ * \par Algorithm:    
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.   
+ * This is in addition to the coefficient array b.   
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.   
+ * 
   
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    
+ * 
    
+ * \par    
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"   
+ * \par    
+ * pCoeffs points to a coefficient array of size numTaps;    
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;   
+ * pState points to a state array of size maxDelay + blockSize, where   
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.   
+ * Some of the processing functions also require temporary working buffers.   
+ *   
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 4 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 4 different data type filter instance structures    
+ * 
    
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ * 
    
+ * \par    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the floating-point sparse FIR filter.   
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.   
+ * @param[in]  *pSrc       points to the block of input data.   
+ * @param[out] *pDst       points to the block of output data   
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize   number of input samples to process per call.   
+ * @return none.   
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 0000000000..2934352d05
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_f32.c    
+*    
+* Description:	Floating-point sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs holds the filter coefficients and has length numTaps.    
+ * pState holds the filter's state variables and must be of length    
+ * maxDelay + blockSize, where maxDelay    
+ * is the maximum number of delay line values.    
+ * blockSize is the    
+ * number of samples processed by the arm_fir_sparse_f32() function.    
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 0000000000..47a116e952
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q15.c    
+*    
+* Description:	Q15 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs holds the filter coefficients and has length numTaps.    
+ * pState holds the filter's state variables and must be of length    
+ * maxDelay + blockSize, where maxDelay    
+ * is the maximum number of delay line values.    
+ * blockSize is the    
+ * number of words processed by arm_fir_sparse_q15() function.    
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 0000000000..360a219b20
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,101 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q31.c    
+*    
+* Description:	Q31 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs holds the filter coefficients and has length numTaps.    
+ * pState holds the filter's state variables and must be of length    
+ * maxDelay + blockSize, where maxDelay    
+ * is the maximum number of delay line values.    
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.    
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 0000000000..b400297ca6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_fir_sparse_init_q7.c    
+*    
+* Description:	Q7 sparse FIR filter initialization function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief  Initialization function for the Q7 sparse FIR filter.   
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.   
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.   
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.   
+ * @param[in]     *pState    points to the state buffer.   
+ * @param[in]     *pTapDelay points to the array of offset times.   
+ * @param[in]     maxDelay   maximum offset time supported.   
+ * @param[in]     blockSize  number of samples that will be processed per block.   
+ * @return none   
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs holds the filter coefficients and has length numTaps.    
+ * pState holds the filter's state variables and must be of length    
+ * maxDelay + blockSize, where maxDelay    
+ * is the maximum number of delay line values.    
+ * blockSize is the    
+ * number of samples processed by the arm_fir_sparse_q7() function.    
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 0000000000..016f833456
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,406 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q15.c    
+*    
+* Description:	Q15 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the Q15 sparse FIR filter.   
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.   
+ * @param[in]  *pSrc        points to the block of input data.   
+ * @param[out] *pDst        points to the block of output data   
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize    number of input samples to process per call.   
+ * @return none.   
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 32-bit accumulator.   
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.   
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.   
+ * If the accumulator result overflows it will wrap around rather than saturate.   
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.    
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.    
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.       
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 0000000000..3d2f6d4028
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,370 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q31.c    
+*    
+* Description:	Q31 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+/**   
+ * @brief Processing function for the Q31 sparse FIR filter.   
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.   
+ * @param[in]  *pSrc       points to the block of input data.   
+ * @param[out] *pDst       points to the block of output data   
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize   number of input samples to process per call.   
+ * @return none.   
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 32-bit accumulator.   
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.   
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.    
+ * If the accumulator result overflows, it wraps around rather than saturate.   
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 0000000000..ace5d07037
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,398 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_fir_sparse_q7.c    
+*    
+* Description:	Q7 sparse FIR filter processing function.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup FIR_Sparse    
+ * @{    
+ */
+
+
+/**   
+ * @brief Processing function for the Q7 sparse FIR filter.   
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.   
+ * @param[in]  *pSrc        points to the block of input data.   
+ * @param[out] *pDst        points to the block of output data   
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
+ * @param[in]  blockSize    number of input samples to process per call.   
+ * @return none.   
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.   
+ * Finally, the result is truncated to 1.7 format.   
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.    
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and    
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.    
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,    
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and    
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.    
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,    
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and           
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and           
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.       
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of FIR_Sparse group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 0000000000..074605553d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_f32.c    
+*    
+* Description:	Floating-point IIR Lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters    
+ *    
+ * This set of functions implements lattice filters    
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
+ * variety of adaptive filter applications.  The filter structure has feedforward and    
+ * feedback components and the net impulse response is infinite length.    
+ * The functions operate on blocks    
+ * of input and output data and each call to the function processes    
+ * blockSize samples through the filter.  pSrc and    
+ * pDst point to input and output arrays containing blockSize values.    
+    
+ * \par Algorithm:    
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"    
+ * 
    
+ *    fN(n)   =  x(n)    
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    
+ * 
    
+ * \par    
+ * pkCoeffs points to array of reflection coefficients of size numStages.     
+ * Reflection coefficients are stored in time-reversed order.    
+ * \par    
+ * 
    
+ *    {kN, kN-1, ....k1}    
+ * 
    
+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).     
+ * Ladder coefficients are stored in time-reversed order.    
+ * \par    
+ * 
    
+ *    {vN, vN-1, ...v0}    
+ * 
    
+ * pState points to a state array of size numStages + blockSize.    
+ * The state variables shown in the figure above (the g values) are stored in the pState array.    
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter.    
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+  *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ *    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
+ * 
    
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ * 
    
+ * \par    
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;    
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point IIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+  float32_t k1, k2;
+  float32_t v1, v2, v3, v4;
+  float32_t gcurr2;
+  float32_t fnext2;
+
+  /* initialise loop count */
+  blkCnt = blockSize;
+
+  /* initialise state pointer */
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fnext2 = *pSrc++;
+
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+
+    /* Set accumulator to zero */
+    acc = 0.0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages) >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Read gN-1(n-1) from state buffer */
+      gcurr1 = *px1;
+
+      /* read reflection coefficient kN */
+      k1 = *pk;
+
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* read ladder coefficient vN */
+      v1 = *pv;
+
+      /* read next reflection coefficient kN-1 */
+      k2 = *(pk + 1u);
+
+      /* Read gN-2(n-1) from state buffer */
+      gcurr2 = *(px1 + 1u);
+
+      /* read next ladder coefficient vN-1 */
+      v2 = *(pv + 1u);
+
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read reflection coefficient kN-2 */
+      k1 = *(pk + 2u);
+
+      /* write gN(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Read gN-3(n-1) from state buffer */
+      gcurr1 = *(px1 + 2u);
+
+      /* y(n) += gN(n) * vN  */
+      acc += (gnext * v1);
+
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fnext1 = fnext2 - (k1 * gcurr1);
+
+      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = gcurr2 + (k2 * fnext2);
+
+      /* Read gN-4(n-1) from state buffer */
+      gcurr2 = *(px1 + 3u);
+
+      /* y(n) += gN-1(n) * vN-1  */
+      acc += (gnext * v2);
+
+      /* read reflection coefficient kN-3 */
+      k2 = *(pk + 3u);
+
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext2 = fnext1 - (k2 * gcurr2);
+
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = gcurr1 + (k1 * fnext1);
+
+      /* read ladder coefficient vN-2 */
+      v3 = *(pv + 2u);
+
+      /* y(n) += gN-2(n) * vN-2  */
+      acc += (gnext * v3);
+
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointer */
+      pk += 4u;
+
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext2 * k2) + gcurr2;
+
+      /* read next ladder coefficient vN-3 */
+      v4 = *(pv + 3u);
+
+      /* y(n) += gN-4(n) * vN-4  */
+      acc += (gnext * v4);
+
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* update pointers */
+      px1 += 4u;
+      pv += 4u;
+
+      tapCnt--;
+
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr1 = *px1++;
+      /* Process sample for last taps */
+      fnext1 = fnext2 - ((*pk) * gcurr1);
+      gnext = (fnext1 * (*pk++)) + gcurr1;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fnext2 = fnext1;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext2 * (*pv));
+
+    *px2++ = fnext2;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer        
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 0000000000..89c00c24df
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,86 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_f32.c    
+*    
+* Description:  Floating-point IIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Initialization function for the floating-point IIR lattice filter.    
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
+ * @param[in] numStages number of stages in the filter.    
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**    
+   * @} end of IIR_Lattice group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 0000000000..7dac99fcab
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,86 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_q15.c    
+*    
+* Description:  Q15 IIR lattice filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q15 IIR lattice filter.    
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
+   * @param[in] numStages  number of stages in the filter.    
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.    
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.    
+   * @param[in] blockSize number of samples to process per call.    
+   * @return none.    
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 0000000000..73b18a5977
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,86 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_iir_lattice_init_q31.c    
+*    
+* Description:  Initialization function for the Q31 IIR lattice filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for the Q31 IIR lattice filter.    
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
+   * @param[in] numStages number of stages in the filter.    
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 0000000000..5f0f891d18
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,457 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_q15.c    
+*    
+* Description:	Q15 IIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 IIR lattice filter.    
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q15_t v1, v2;
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* 	#ifndef ARM_MATH_BIG_ENDIAN		*/
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      v = *__SIMD32(pv)++;
+
+#else
+
+	  v1 = *pv++;
+	  v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+	  v = __PKHBT(v1, v2, 16);
+
+#else
+
+	  v = __PKHBT(v2, v1, 16);
+
+#endif	/* #ifndef ARM_MATH_BIG_ENDIAN	 */
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2u);
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif /*	#ifndef UNALIGNED_SUPPORT_DISABLE */
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4u;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 0000000000..adfd4dfb5d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_iir_lattice_q31.c    
+*    
+* Description:	Q31 IIR lattice filter processing function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup IIR_Lattice    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 IIR lattice filter.    
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[out] *pDst points to the block of output data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clip.    
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.    
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**    
+ * @} end of IIR_Lattice group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 0000000000..90fa8ae1e9
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,434 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_f32.c    
+*    
+* Description:	Processing function for the floating-point LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup LMS Least Mean Square (LMS) Filters    
+ *    
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.    
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.    
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.    
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.    
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.    
+ *    
+ * An LMS filter consists of two components as shown below.    
+ * The first component is a standard transversal or FIR filter.    
+ * The second component is a coefficient update mechanism.    
+ * The LMS filter has two input signals.    
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
+ * This "error signal" tends towards zero as the filter adapts.    
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"    
+ *    
+ * The functions operate on blocks of data and each call to the function processes    
+ * blockSize samples through the filter.    
+ * pSrc points to input signal, pRef points to reference signal,    
+ * pOut points to output signal and pErr points to error signal.    
+ * All arrays contain blockSize values.    
+ *    
+ * The functions operate on a block-by-block basis.    
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
+ *    
+ * \par Algorithm:    
+ * The output signal y[n] is computed by a standard FIR filter:    
+ * 
    
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * 
    
+ *    
+ * \par    
+ * The error signal equals the difference between the reference signal d[n] and the filter output:    
+ * 
    
+ *     e[n] = d[n] - y[n].    
+ * 
    
+ *    
+ * \par    
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:    
+ * 
    
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    
+ * 
    
+ * where mu is the step size and controls the rate of coefficient convergence.    
+ *\par    
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to a state array of size numTaps + blockSize - 1.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * 
    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * 
    
+ * \par    
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
+ * to be avoided and yields a significant speed improvement.    
+ * The state variables are updated after each block of data is processed.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter and    
+ * coefficient and state arrays cannot be shared among instances.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Set the values in the state buffer to zeros before static initialization.    
+ * The code below statically initializes each of the 3 different data type filter instance structures    
+ * 
    
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    
+ * 
    
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;    
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.    
+ *    
+ * \par Fixed-Point Behavior:    
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.    
+ * The following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Overflow and saturation    
+ *    
+ * \par Scaling of Coefficients:    
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range [-1 +1).    
+ * The fixed-point functions have an additional scaling parameter postShift.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
+ * This essentially scales the filter coefficients by 2^postShift and    
+ * allows the filter coefficients to exceed the range [+1 -1).    
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.    
+ *    
+ * \par Overflow and Saturation:    
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
+ * described separately as part of the function specific documentation below.    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+/**           
+ * @details           
+ * This function operates on floating-point data types.       
+ *    
+ * @brief Processing function for floating-point LMS filter.    
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[in]  *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return     none.    
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+   * start of the state buffer. This prepares the state buffer for the        
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 0000000000..a2f51240a5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,90 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_f32.c    
+*    
+* Description:  Floating-point LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for floating-point LMS filter.    
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to the coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+/**    
+ * \par Description:    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().    
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 0000000000..8f42949a61
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,100 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_q15.c    
+*    
+* Description:  Q15 LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+/**    
+* @brief Initialization function for the Q15 LMS filter.    
+* @param[in] *S points to an instance of the Q15 LMS filter structure.    
+* @param[in] numTaps  number of filter coefficients.    
+* @param[in] *pCoeffs points to the coefficient buffer.    
+* @param[in] *pState points to the state buffer.    
+* @param[in] mu step size that controls filter coefficient updates.    
+* @param[in] blockSize number of samples to process.    
+* @param[in] postShift bit shift applied to coefficients.    
+* @return    none.    
+*    
+* \par Description:    
+* pCoeffs points to the array of filter coefficients stored in time reversed order:    
+* 
    
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+* 
    
+* The initial filter coefficients serve as a starting point for the adaptive filter.    
+* pState points to the array of state variables and size of array is    
+* numTaps+blockSize-1 samples, where blockSize is the number of    
+* input samples processed by each call to arm_lms_q15().    
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 0000000000..58edb659ba
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,100 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_init_q31.c    
+*    
+* Description:  Q31 LMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q31 LMS filter.    
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * \par Description:    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * pState points to an array of length numTaps+blockSize-1 samples,    
+ * where blockSize is the number of input samples processed by each call to    
+ * arm_lms_q31().    
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**    
+ * @} end of LMS group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 0000000000..b2ac452069
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,456 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_f32.c    
+*    
+* Description:	Processing function for the floating-point Normalised LMS.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @defgroup LMS_NORM Normalized LMS Filters    
+ *    
+ * This set of functions implements a commonly used adaptive filter.    
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization    
+ * factor which increases the adaptation rate of the filter.    
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.    
+ *    
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.    
+ * The first component is a standard transversal or FIR filter.    
+ * The second component is a coefficient update mechanism.    
+ * The NLMS filter has two input signals.    
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
+ * This "error signal" tends towards zero as the filter adapts.    
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"    
+ *    
+ * The functions operate on blocks of data and each call to the function processes    
+ * blockSize samples through the filter.    
+ * pSrc points to input signal, pRef points to reference signal,    
+ * pOut points to output signal and pErr points to error signal.    
+ * All arrays contain blockSize values.    
+ *    
+ * The functions operate on a block-by-block basis.    
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
+ *    
+ * \par Algorithm:    
+ * The output signal y[n] is computed by a standard FIR filter:    
+ * 
    
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ * 
    
+ *    
+ * \par    
+ * The error signal equals the difference between the reference signal d[n] and the filter output:    
+ * 
    
+ *     e[n] = d[n] - y[n].    
+ * 
    
+ *    
+ * \par    
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:    
+ * 
    
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    
+ * 
    
+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:    
+ * 
    
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    
+ * 
    
+ * where mu is the step size and controls the rate of coefficient convergence.    
+ *\par    
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
+ * Coefficients are stored in time reversed order.    
+ * \par    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * \par    
+ * pState points to a state array of size numTaps + blockSize - 1.    
+ * Samples in the state buffer are stored in the order:    
+ * \par    
+ * 
    
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ * 
    
+ * \par    
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
+ * to be avoided and yields a significant speed improvement.    
+ * The state variables are updated after each block of data is processed.    
+ * \par Instance Structure    
+ * The coefficients and state variables for a filter are stored together in an instance data structure.    
+ * A separate instance structure must be defined for each filter and    
+ * coefficient and state arrays cannot be shared among instances.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Zeros out the values in the state buffer.    
+ * \par    
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.    
+ * \par Fixed-Point Behavior:    
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.    
+ * The following issues must be considered:    
+ * - Scaling of coefficients    
+ * - Overflow and saturation    
+ *    
+ * \par Scaling of Coefficients:    
+ * Filter coefficients are represented as fractional values and    
+ * coefficients are restricted to lie in the range [-1 +1).    
+ * The fixed-point functions have an additional scaling parameter postShift.    
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
+ * This essentially scales the filter coefficients by 2^postShift and    
+ * allows the filter coefficients to exceed the range [+1 -1).    
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.    
+ *    
+ * \par Overflow and Saturation:    
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
+ * described separately as part of the function specific documentation below.    
+ */
+
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+
+  /**    
+   * @brief Processing function for floating-point normalized LMS filter.    
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.    
+   * @param[in] *pSrc points to the block of input data.    
+   * @param[in] *pRef points to the block of reference data.    
+   * @param[out] *pOut points to the block of output data.    
+   * @param[out] *pErr points to the block of error data.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     satrt of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of LMS_NORM group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 0000000000..3d31cfb257
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,100 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_f32.c    
+*    
+* Description:  Floating-point NLMS filter initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for floating-point normalized LMS filter.    
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @return none.    
+   *    
+ * \par Description:    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * pState points to an array of length numTaps+blockSize-1 samples,    
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().    
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 0000000000..a1cf1b001d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,107 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_q15.c    
+*    
+* Description:  Q15 NLMS initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q15 normalized LMS filter.    
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * pState points to the array of state variables and size of array is    
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed    
+ * by each call to arm_lms_norm_q15().    
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q15_t *) armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 0000000000..a2fae7b381
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,106 @@
+/*-----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_lms_norm_init_q31.c    
+*    
+* Description:  Q31 NLMS initialization function.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+  /**    
+   * @brief Initialization function for Q31 normalized LMS filter.    
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
+   * @param[in] numTaps  number of filter coefficients.    
+   * @param[in] *pCoeffs points to coefficient buffer.    
+   * @param[in] *pState points to state buffer.    
+   * @param[in] mu step size that controls filter coefficient updates.    
+   * @param[in] blockSize number of samples to process.    
+   * @param[in] postShift bit shift applied to coefficients.    
+   * @return none.    
+ *    
+ * Description:    
+ * \par    
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:    
+ * 
    
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ * 
    
+ * The initial filter coefficients serve as a starting point for the adaptive filter.    
+ * pState points to an array of length numTaps+blockSize-1 samples,    
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().    
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = (q31_t *) armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 0000000000..a1229a2036
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_q15.c    
+*    
+* Description:	Q15 NLMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+/**    
+* @brief Processing function for Q15 normalized LMS filter.    
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
+* @param[in] *pSrc points to the block of input data.    
+* @param[in] *pRef points to the block of reference data.    
+* @param[out] *pOut points to the block of output data.    
+* @param[out] *pErr points to the block of error data.    
+* @param[in] blockSize number of samples to process.    
+* @return none.    
+*    
+* Scaling and Overflow Behavior:     
+* \par     
+* The function is implemented using a 64-bit internal accumulator.     
+* Both coefficients and state variables are represented in 1.15 format and    
+* multiplications yield a 2.30 result. The 2.30 intermediate results are    
+* accumulated in a 64-bit accumulator in 34.30 format.     
+* There is no risk of internal overflow with this approach and the full    
+* precision of intermediate multiplications is preserved. After all additions    
+* have been performed, the accumulator is truncated to 34.15 format by    
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a    
+* result in 1.15 format.    
+*    
+* \par   
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
+*    
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */ 
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+      acc += (((q31_t) * px++ * (*pb++)));
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16u);
+
+    /* Converting the result to 1.15 format */
+    //acc = __SSAT((acc >> (16u - shift)), 16u); 
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     satrt of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1u) data */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**    
+   * @} end of LMS_NORM group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 0000000000..791a8637cc
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,426 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_norm_q31.c    
+*    
+* Description:	Processing function for the Q31 NLMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS_NORM    
+ * @{    
+ */
+
+/**    
+* @brief Processing function for Q31 normalized LMS filter.    
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
+* @param[in] *pSrc points to the block of input data.    
+* @param[in] *pRef points to the block of reference data.    
+* @param[out] *pOut points to the block of output data.    
+* @param[out] *pErr points to the block of error data.    
+* @param[in] blockSize number of samples to process.    
+* @return none.    
+*    
+* Scaling and Overflow Behavior:     
+* \par     
+* The function is implemented using an internal 64-bit accumulator.     
+* The accumulator has a 2.62 format and maintains full precision of the intermediate   
+* multiplication results but provides only a single guard bit.     
+* Thus, if the accumulator result overflows it wraps around rather than clip.     
+* In order to avoid overflows completely the input signal must be scaled down by    
+* log2(numTaps) bits. The reference signal should not be scaled down.     
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
+* and saturated to 1.31 format to yield the final result.     
+* The output signal and error signal are in 1.31 format.     
+*    
+* \par    
+* 	In this filter, filter coefficients are updated for each sample and the    
+* updation of filter cofficients are saturted.    
+*     
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+//  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */      
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+    //acc = (q31_t) (acc >> shift); 
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
+     start of the state buffer. This prepares the state buffer for the        
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of LMS_NORM group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 0000000000..91237c12d8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,374 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_q15.c    
+*    
+* Description:	Processing function for the Q15 LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+ /**    
+ * @brief Processing function for Q15 LMS filter.    
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.    
+ * @param[in] *pSrc points to the block of input data.    
+ * @param[in] *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in] blockSize number of samples to process.    
+ * @return none.    
+ *    
+ * \par Scaling and Overflow Behavior:    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
+ *   
+ * \par   
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+ *    
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t acc_l, acc_h;
+  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
+  int32_t uShift = (32 - lShift);
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    while(tapCnt > 0u)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+#endif
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    /* Apply shift for lower part of acc and upper part of acc */
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT(acc, 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
+     start of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 0000000000..c43d55d1df
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,364 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_lms_q31.c    
+*    
+* Description:	Processing function for the Q31 LMS filter.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**    
+ * @ingroup groupFilters    
+ */
+
+/**    
+ * @addtogroup LMS    
+ * @{    
+ */
+
+ /**    
+ * @brief Processing function for Q31 LMS filter.    
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.    
+ * @param[in]  *pSrc points to the block of input data.    
+ * @param[in]  *pRef points to the block of reference data.    
+ * @param[out] *pOut points to the block of output data.    
+ * @param[out] *pErr points to the block of error data.    
+ * @param[in]  blockSize number of samples to process.    
+ * @return     none.    
+ *    
+ * \par Scaling and Overflow Behavior:     
+ * The function is implemented using an internal 64-bit accumulator.     
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate    
+ * multiplication results but provides only a single guard bit.     
+ * Thus, if the accumulator result overflows it wraps around rather than clips.     
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(numTaps) bits.     
+ * The reference signal should not be scaled down.     
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
+ * and saturated to 1.31 format to yield the final result.     
+ * The output signal and error signal are in 1.31 format.     
+ *    
+ * \par    
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  q31_t coef;                                    /* Temporary variable for coef */
+  q31_t acc_l, acc_h;                            /*  temporary input */
+  uint32_t uShift = ((uint32_t) S->postShift + 1u);
+  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     satrt of the state buffer. This prepares the state buffer for the    
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    /* Calc lower part of acc */
+    acc_l = acc & 0xffffffff;
+
+    /* Calc upper part of acc */
+    acc_h = (acc >> 32) & 0xffffffff;
+
+    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb += (coef << 1u);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
+     start of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of LMS group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt b/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt
new file mode 100644
index 0000000000..0740c1eb79
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt
@@ -0,0 +1,3937 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
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+    *.s*; *.src; *.a*
+    *.obj
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+    *.plm
+    *.cpp
+  
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diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj b/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj
new file mode 100644
index 0000000000..6c370a47d6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj
@@ -0,0 +1,3253 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+      ARM-GNU
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+            
+            
+            
+            
+            
+            -Wl,--gc-sections
+            
+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
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+            
+            
+              arm_abs_q7.c
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+            
+            
+              arm_abs_q15.c
+              1
+              ../BasicMathFunctions/arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
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+              ../BasicMathFunctions/arm_add_q7.c
+            
+            
+              arm_add_q15.c
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+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
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+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ../BasicMathFunctions/arm_mult_q31.c
+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
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+            
+            
+              arm_sub_f32.c
+              1
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+            
+            
+              arm_sub_q7.c
+              1
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+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
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+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
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+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
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diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt b/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt
new file mode 100644
index 0000000000..b56521505e
--- /dev/null
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diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj b/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj
new file mode 100644
index 0000000000..6ace95fc32
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj
@@ -0,0 +1,3253 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM3 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M3
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
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+          4349
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+          
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+            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\G++\"
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+            
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+              -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE
+              
+              ..\..\..\Include
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+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
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+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt b/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt
new file mode 100644
index 0000000000..84e27482e5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt
@@ -0,0 +1,4197 @@
+
+
+
+  1.0
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+      arm_q31_to_q15.c
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+  
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+  
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+      ../CommonTables/arm_common_tables.c
+      arm_common_tables.c
+    
+  
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+
diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj b/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj
new file mode 100644
index 0000000000..3c2a5e6adb
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj
@@ -0,0 +1,6495 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM4 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M4
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE
+          
+          
+          
+          5125
+          
+          
+          
+          
+          
+          
+          
+          
+          
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+          0
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+          
+          
+          
+          
+          
+            0
+            0
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+          
+          .\intermediateFiles\
+          arm_cortexM4l_math
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+          .\intermediateFiles\
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+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            1
+            0
+            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\G++\"
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
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+          
+            1
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+          -1
+          
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+            
+            
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+            
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+            
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+            
+            
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+        
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+            0
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+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            "Cortex-M4"
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
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+              
+                0
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+                0x0
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+              
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+              
+                0
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+              
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+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            0
+            0
+            5
+            2
+            1
+            
+              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE
+              
+              ..\..\..\Include
+            
+          
+          
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            1
+            0
+            1
+            
+            
+            
+            
+            
+            -mcpu=cortex-m4 -Wl,--gc-sections
+            
+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
+              ../BasicMathFunctions/arm_abs_f32.c
+            
+            
+              arm_abs_q7.c
+              1
+              ../BasicMathFunctions/arm_abs_q7.c
+            
+            
+              arm_abs_q15.c
+              1
+              ../BasicMathFunctions/arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
+              1
+              ../BasicMathFunctions/arm_add_q7.c
+            
+            
+              arm_add_q15.c
+              1
+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
+              ../BasicMathFunctions/arm_mult_f32.c
+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ../BasicMathFunctions/arm_mult_q31.c
+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
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+            
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+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
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+            
+            
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+              1
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+            
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+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
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+            
+              arm_correlate_q7.c
+              1
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+            
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+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
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+              1
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+            
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+              1
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+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
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+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
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+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
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+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
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+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
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+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
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+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
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+              1
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+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
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+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
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+            
+            
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+              1
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+            
+            
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+            
+            
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+            
+            
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+            
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+            
+            
+              arm_std_q31.c
+              1
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+            
+            
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+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
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+              1
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+          
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+              1
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
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+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
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+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
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+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
+              ../BasicMathFunctions/arm_abs_f32.c
+            
+            
+              arm_abs_q7.c
+              1
+              ../BasicMathFunctions/arm_abs_q7.c
+            
+            
+              arm_abs_q15.c
+              1
+              ../BasicMathFunctions/arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
+              1
+              ../BasicMathFunctions/arm_add_q7.c
+            
+            
+              arm_add_q15.c
+              1
+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
+              ../BasicMathFunctions/arm_mult_f32.c
+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ../BasicMathFunctions/arm_mult_q31.c
+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
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+              1
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+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
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+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
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+            
+            
+              arm_dct4_q15.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
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+              1
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+            
+          
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+          
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+              1
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+            
+            
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+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
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+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
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+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
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+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
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+            
+            
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+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
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+            
+            
+              arm_q7_to_q15.c
+              1
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+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
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+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
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+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
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+          
+        
+      
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+    
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+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
+              ../BasicMathFunctions/arm_abs_f32.c
+            
+            
+              arm_abs_q7.c
+              1
+              ../BasicMathFunctions/arm_abs_q7.c
+            
+            
+              arm_abs_q15.c
+              1
+              ../BasicMathFunctions/arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
+              1
+              ../BasicMathFunctions/arm_add_q7.c
+            
+            
+              arm_add_q15.c
+              1
+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
+              ../BasicMathFunctions/arm_mult_f32.c
+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ../BasicMathFunctions/arm_mult_q31.c
+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
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+              1
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+              1
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+            
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+              1
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+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
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+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
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+            
+            
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+              1
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+            
+              arm_sqrt_q15.c
+              1
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+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
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+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
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+            
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+            
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+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+              1
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+            
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+            
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+            
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+            
+              arm_scale_q31.c
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+            
+            
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+            
+            
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+              1
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+            
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+              1
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+            
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+            
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+            
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+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_cmplx_mag_f32.c
+              1
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+            
+            
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+              1
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+            
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+              1
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+            
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+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
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+              1
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+            
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+            
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+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat b/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat
new file mode 100644
index 0000000000..007812c2d0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat
@@ -0,0 +1,17 @@
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+@echo   Building DSP Library for Cortex-M0 Little Endian
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M3 Little Endian
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M4 Little Endian
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M4 with FPU Little Endian
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0
diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
new file mode 100644
index 0000000000..6ecf373652
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
@@ -0,0 +1,3937 @@
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+
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diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
new file mode 100644
index 0000000000..dfdbbd51b6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
@@ -0,0 +1,3253 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
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+      DSP_Lib CM0 LE
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+      ARM-GNU
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+              -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE
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+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
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+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
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+        
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_max_q31.c
+              1
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+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
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+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+            
+            
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+            
+            
+              arm_std_f32.c
+              1
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+            
+            
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+              1
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+            
+            
+              arm_std_q31.c
+              1
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+            
+            
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+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
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+            
+          
+        
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+            
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+              1
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+            
+            
+              arm_copy_q7.c
+              1
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+            
+            
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+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
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+            
+            
+              arm_float_to_q7.c
+              1
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+            
+            
+              arm_float_to_q15.c
+              1
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+            
+            
+              arm_float_to_q31.c
+              1
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+            
+            
+              arm_q7_to_float.c
+              1
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+            
+            
+              arm_q7_to_q15.c
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+            
+            
+              arm_q7_to_q31.c
+              1
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+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
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+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
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+          
+        
+        
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+            
+              arm_common_tables.c
+              1
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+              ..\..\..\Include
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+            -Wl,--gc-sections
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+          BasicMathFunctions
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+            
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+            
+              arm_abs_q15.c
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+            
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+              arm_add_f32.c
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+              arm_add_q7.c
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+            
+              arm_dot_prod_f32.c
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+            
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+            
+            
+              arm_dot_prod_q15.c
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+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
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+          FastMathFunctions
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+            
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+            
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+            
+              arm_sqrt_q31.c
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+          
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+        
+          ComplexMathFunctions
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+            
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+              arm_cmplx_conj_q31.c
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+              arm_cmplx_dot_prod_f32.c
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+              arm_cmplx_mult_real_f32.c
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+            
+            
+              arm_cmplx_mult_real_q15.c
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+            
+              arm_cmplx_mult_real_q31.c
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+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
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+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
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+            
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+            
+            
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+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
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+              arm_biquad_cascade_df1_fast_q31.c
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+              arm_biquad_cascade_df1_init_f32.c
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+            
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+              arm_biquad_cascade_df2T_f32.c
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+            
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+              arm_conv_q7.c
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+            
+            
+              arm_correlate_f32.c
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+              arm_correlate_fast_q15.c
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+            
+              arm_correlate_fast_q31.c
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+            
+            
+              arm_correlate_q7.c
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+            
+            
+              arm_correlate_opt_q7.c
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+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
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+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
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+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
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+            
+            
+              arm_fir_decimate_fast_q31.c
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+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
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+            
+            
+              arm_fir_decimate_init_q31.c
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+            
+            
+              arm_fir_decimate_q15.c
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+              ../FilteringFunctions/arm_fir_decimate_q15.c
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+            
+              arm_fir_decimate_q31.c
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+            
+            
+              arm_fir_f32.c
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+            
+            
+              arm_fir_fast_q15.c
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+            
+            
+              arm_fir_fast_q31.c
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+            
+              arm_fir_init_f32.c
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+            
+            
+              arm_fir_init_q7.c
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+            
+              arm_fir_init_q15.c
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+            
+              arm_fir_init_q31.c
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+            
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+            
+            
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+            
+            
+              arm_fir_interpolate_init_q15.c
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+            
+              arm_fir_interpolate_init_q31.c
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+            
+            
+              arm_fir_interpolate_q15.c
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+            
+              arm_fir_interpolate_q31.c
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+            
+              arm_fir_lattice_f32.c
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+            
+              arm_fir_lattice_init_f32.c
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+            
+              arm_fir_lattice_init_q15.c
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+            
+              arm_fir_lattice_init_q31.c
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+            
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+            
+              arm_fir_lattice_q31.c
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+            
+              arm_fir_q7.c
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+            
+            
+              arm_fir_q15.c
+              1
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+            
+            
+              arm_fir_q31.c
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+            
+            
+              arm_fir_sparse_f32.c
+              1
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+            
+            
+              arm_fir_sparse_init_f32.c
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+            
+            
+              arm_fir_sparse_init_q7.c
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+            
+            
+              arm_fir_sparse_init_q15.c
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+            
+            
+              arm_fir_sparse_init_q31.c
+              1
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+            
+            
+              arm_fir_sparse_q7.c
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+            
+              arm_fir_sparse_q15.c
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+            
+              arm_fir_sparse_q31.c
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+            
+              arm_iir_lattice_f32.c
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+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
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+            
+              arm_iir_lattice_init_q15.c
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+            
+              arm_iir_lattice_init_q31.c
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+            
+              arm_iir_lattice_q15.c
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+            
+              arm_iir_lattice_q31.c
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+            
+              arm_lms_f32.c
+              1
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+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
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+              ../FilteringFunctions/arm_lms_init_q15.c
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+            
+              arm_lms_init_q31.c
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+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
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+            
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+            
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+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
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+              1
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+            
+            
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+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
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+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
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+            
+            
+              arm_mat_trans_f32.c
+              1
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+            
+            
+              arm_mat_trans_q15.c
+              1
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+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
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+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
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+              1
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+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
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+            
+            
+              arm_dct4_init_q15.c
+              1
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+            
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+            
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+            
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+        
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+            
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+            
+            
+              arm_pid_init_q15.c
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+            
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+              arm_q15_to_q7.c
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+            
+              arm_q15_to_q31.c
+              1
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+            
+            
+              arm_q31_to_float.c
+              1
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+            
+            
+              arm_q31_to_q7.c
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+            
+            
+              arm_q31_to_q15.c
+              1
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+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
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+
diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
new file mode 100644
index 0000000000..8e5a82fd8e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
@@ -0,0 +1,3937 @@
+
+
+
+  1.0
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diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
new file mode 100644
index 0000000000..a32c386769
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
@@ -0,0 +1,3253 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
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+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
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diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
new file mode 100644
index 0000000000..9201baab89
--- /dev/null
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diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
new file mode 100644
index 0000000000..ad55fd5688
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
@@ -0,0 +1,6495 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM4 LE
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M4
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE
+          
+          
+          
+          5125
+          
+          
+          
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+            
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+          
+          
+            1
+            0
+            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\GCC\"
+            
+            0
+            0
+          
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+          
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+          0
+          0
+          3
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+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
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+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM4
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+            "Cortex-M4"
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+            
+          
+          
+            0
+            0
+            0
+            0
+            0
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+            
+              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE
+              
+              ..\..\..\Include
+            
+          
+          
+            0
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+              arm_scale_f32.c
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+            
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+            
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+          
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+            
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+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
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+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
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+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
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+          
+            
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+              1
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+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
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+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
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+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
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+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
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+            
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+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
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+              arm_common_tables.c
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+              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, UNALIGNED_SUPPORT_DISABLE
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+              ..\..\..\Include
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+      
+      
+        
+          BasicMathFunctions
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+            
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+            
+              arm_abs_q7.c
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+            
+              arm_abs_q15.c
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+              ../BasicMathFunctions/arm_abs_q15.c
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+            
+              arm_abs_q31.c
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+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
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+            
+              arm_add_q7.c
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+            
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+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
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+              ../BasicMathFunctions/arm_dot_prod_q15.c
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+            
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+              1
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+            
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+            
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+            
+            
+              arm_sub_q31.c
+              1
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+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
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+            
+            
+              arm_cos_q31.c
+              1
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+            
+            
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+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
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+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
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+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
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+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
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+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
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+              1
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+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
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+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
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+              1
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+            
+            
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+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
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+            
+            
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+              1
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+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
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+              1
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+            
+            
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+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
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+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
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+            
+            
+              arm_conv_opt_q7.c
+              1
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+            
+            
+              arm_conv_q15.c
+              1
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+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
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+            
+            
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+              1
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+            
+            
+              arm_mat_scale_q31.c
+              1
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+            
+            
+              arm_mat_sub_f32.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_mat_trans_q15.c
+              1
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+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
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+          
+            
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+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+            
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+            
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
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+            
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+              1
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+            
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+            
+            
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+            
+            
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+            
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+            
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+            
+            
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+            
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+            
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+            
+            
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+              1
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+            
+            
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+            
+            
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+            
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+              1
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+              1
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+            
+              arm_float_to_q7.c
+              1
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+            
+            
+              arm_float_to_q15.c
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+            
+            
+              arm_float_to_q31.c
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+              1
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+            
+              arm_q15_to_float.c
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+              ../SupportFunctions/arm_q15_to_q31.c
+            
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+              arm_q31_to_float.c
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+              ../SupportFunctions/arm_q31_to_float.c
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+              1
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+          
+            
+              arm_abs_f32.c
+              1
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+            
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+              1
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+            
+            
+              arm_abs_q15.c
+              1
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+            
+            
+              arm_abs_q31.c
+              1
+              ../BasicMathFunctions/arm_abs_q31.c
+            
+            
+              arm_add_f32.c
+              1
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+            
+            
+              arm_add_q7.c
+              1
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+            
+            
+              arm_add_q15.c
+              1
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+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
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+            
+            
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+              1
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+            
+            
+              arm_mult_q7.c
+              1
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+            
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+              1
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+            
+            
+              arm_mult_q31.c
+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+              1
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+            
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+            
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+            
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+              1
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+            
+              arm_scale_q31.c
+              1
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+            
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+            
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+              1
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+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_opt_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_opt_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_opt_q7.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_opt_q15.c
+              1
+              ../FilteringFunctions/arm_conv_opt_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_opt_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_opt_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_opt_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_opt_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_bitreversal.c
+              1
+              ../TransformFunctions/arm_bitreversal.c
+            
+            
+              arm_cfft_radix2_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_f32.c
+            
+            
+              arm_cfft_radix2_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_f32.c
+            
+            
+              arm_cfft_radix2_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q15.c
+            
+            
+              arm_cfft_radix2_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_init_q31.c
+            
+            
+              arm_cfft_radix2_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q15.c
+            
+            
+              arm_cfft_radix2_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix2_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat b/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
new file mode 100644
index 0000000000..007812c2d0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
@@ -0,0 +1,17 @@
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+@echo   Building DSP Library for Cortex-M0 Little Endian
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M3 Little Endian
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M4 Little Endian
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0
+
+@echo   Building DSP Library for Cortex-M4 with FPU Little Endian
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 0000000000..09099ccb81
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_add_f32.c    
+*    
+* Description:	Floating-point matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixAdd Matrix Addition        
+ *        
+ * Adds two matrices.        
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"        
+ *        
+ * The functions check to make sure that        
+ * pSrcA, pSrcB, and pDst have the same        
+ * number of rows and columns.        
+ */
+
+/**        
+ * @addtogroup MatrixAdd        
+ * @{        
+ */
+
+
+/**        
+ * @brief Floating-point matrix addition.        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+
+#ifndef ARM_MATH_CM0
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA + sourceB */
+      out1 = inA1 + inB1;
+
+      /* out = sourceA + sourceB */
+      out2 = inA2 + inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixAdd group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 0000000000..4bfc878622
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_add_q15.c    
+*    
+* Description:	Q15 matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixAdd    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix addition.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4u;
+
+    /* q15 pointers of input and output are initialized */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixAdd group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 0000000000..1f7be21c55
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_add_q31.c    
+*    
+* Description:	Q31 matrix addition    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**      
+ * @ingroup groupMatrix      
+ */
+
+/**      
+ * @addtogroup MatrixAdd      
+ * @{      
+ */
+
+/**      
+ * @brief Q31 matrix addition.      
+ * @param[in]       *pSrcA points to the first input matrix structure      
+ * @param[in]       *pSrcB points to the second input matrix structure      
+ * @param[out]      *pDst points to output matrix structure      
+ * @return     		The function returns either      
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      
+ *      
+ * Scaling and Overflow Behavior:      
+ * \par      
+ * The function uses saturating arithmetic.      
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.      
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#ifndef ARM_MATH_CM0
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Add and saturate */
+      out2 = __QADD(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Add and saturate */
+      out1 = __QADD(inA1, inB1);
+      out2 = __QADD(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.      
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QADD(inA1, inB1);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+
+      *pOut++ = inA1;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**      
+ * @} end of MatrixAdd group      
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 0000000000..9ffc96ee3e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_f32.c    
+*    
+* Description:	Floating-point matrix initialization.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInit Matrix Initialization    
+ *    
+ * Initializes the underlying matrix data structure.    
+ * The functions set the numRows,    
+ * numCols, and pData fields    
+ * of the matrix data structure.    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+/**    
+   * @brief  Floating-point matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 0000000000..2bada7feda
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_q15.c    
+*    
+* Description:	Q15 matrix initialization.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+  /**    
+   * @brief  Q15 matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 0000000000..8828c2d2ea
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_init_q31.c    
+*    
+* Description:	Q31 matrix initialization.    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInit Matrix Initialization    
+ *    
+ */
+
+/**    
+ * @addtogroup MatrixInit    
+ * @{    
+ */
+
+  /**    
+   * @brief  Q31 matrix initialization.    
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
+   * @param[in]     nRows          number of rows in the matrix.    
+   * @param[in]     nColumns       number of columns in the matrix.    
+   * @param[in]     *pData	   points to the matrix data array.    
+   * @return        none    
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**    
+ * @} end of MatrixInit group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 0000000000..f346916e0c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,668 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_inverse_f32.c    
+*    
+* Description:	Floating-point matrix inverse.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixInv Matrix Inverse    
+ *    
+ * Computes the inverse of a matrix.    
+ *    
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant    
+ * is non-zero). The function checks that the input and output matrices are square and of the    
+ * same size.    
+ *    
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
+ * inversion of floating-point matrices.    
+ *    
+ * \par Algorithm    
+ * The Gauss-Jordan method is used to find the inverse.    
+ * The algorithm performs a sequence of elementary row-operations till it    
+ * reduces the input matrix to an identity matrix. Applying the same sequence    
+ * of elementary row-operations to an identity matrix yields the inverse matrix.    
+ * If the input matrix is singular, then the algorithm terminates and returns error status    
+ * ARM_MATH_SINGULAR.    
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
+ */
+
+/**    
+ * @addtogroup MatrixInv    
+ * @{    
+ */
+
+/**    
+ * @brief Floating-point matrix inverse.    
+ * @param[in]       *pSrc points to input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns    
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size    
+ * of the output matrix does not match the size of the input matrix.    
+ * If the input matrix is found to be singular (non-invertible), then the function returns    
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.    
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------    
+	 * Matrix Inverse can be solved using elementary row operations.    
+	 *    
+	 *	Gauss-Jordan Method:    
+	 *    
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
+	 *        augmented matrix as follows:    
+	 *				        _ 	      	       _         _	       _    
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
+	 *					   |           |        |   =   |           |    
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
+	 *    
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *    
+	 *		3. Begin with the first row. Let i = 1.    
+	 *    
+	 *	    4. Check to see if the pivot for row i is zero.    
+	 *		   The pivot is the element of the main diagonal that is on the current row.    
+	 *		   For instance, if working with row i, then the pivot element is aii.    
+	 *		   If the pivot is zero, exchange that row with a row below it that does not    
+	 *		   contain a zero in column i. If this is not possible, then an inverse    
+	 *		   to that matrix does not exist.    
+	 *    
+	 *	    5. Divide every element of row i by the pivot.    
+	 *    
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
+	 *		   a multiple of row i so that each new element in column i below row i is zero.    
+	 *    
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
+	 *		   for every element below and above the main diagonal.    
+	 *    
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.    
+       * If there is no non zero element to replace in the rows below,    
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to    
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------       
+	 * Matrix Inverse can be solved using elementary row operations.        
+	 *        
+	 *	Gauss-Jordan Method:       
+	 *	 	       
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
+	 *        augmented matrix as follows:        
+	 *				        _  _	      _	    _	   _   _         _	       _       
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
+	 *					   |  |            | | |        |   |   =   |           |        
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
+	 *					          
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
+	 *       
+	 *		3. Begin with the first row. Let i = 1.       
+	 *       
+	 *	    4. Check to see if the pivot for row i is zero.       
+	 *		   The pivot is the element of the main diagonal that is on the current row.       
+	 *		   For instance, if working with row i, then the pivot element is aii.       
+	 *		   If the pivot is zero, exchange that row with a row below it that does not        
+	 *		   contain a zero in column i. If this is not possible, then an inverse        
+	 *		   to that matrix does not exist.       
+	 *	       
+	 *	    5. Divide every element of row i by the pivot.       
+	 *	       
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
+	 *		   a multiple of row i so that each new element in column i below row i is zero.       
+	 *	       
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
+	 *		   for every element below and above the main diagonal.        
+	 *		   		          
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.     
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..    
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points     
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points     
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to     
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns     
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns     
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix     
+         * by the pivot element */
+        *pInT1++ = *pInT1 / in;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix     
+         * by the pivot element */
+        *pInT2++ = *pInT2 / in;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i     
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,     
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,     
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pInT1++ = *pInT1 - (in * *pPRT_in++);
+          }
+          /* Loop over the number of columns to     
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row     
+               and a multiple of the reference row  */
+            *pInT2++ = *pInT2 - (in * *pPRT_pDst++);
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixInv group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 0000000000..a2f513628e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_f32.c    
+*    
+* Description:  Floating-point matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @defgroup MatrixMult Matrix Multiplication    
+ *    
+ * Multiplies two matrices.    
+ *    
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"    
+    
+ * Matrix multiplication is only defined if the number of columns of the    
+ * first matrix equals the number of rows of the second matrix.    
+ * Multiplying an M x N matrix with an N x P matrix results    
+ * in an M x P matrix.    
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of    
+ * pSrcA and pSrcB are equal; and (2) that the size of the output    
+ * matrix equals the outer dimensions of pSrcA and pSrcB.    
+ */
+
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Floating-point matrix multiplication.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t in1, in2, in3, in4;
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2u;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[0];
+          in2 = pIn1[1];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+
+          in3 = *pIn2;
+          pIn2 += numColsB;
+          in1 = pIn1[2];
+          in2 = pIn1[3];
+          sum += in1 * in3;
+          in4 = *pIn2;
+          pIn2 += numColsB;
+          sum += in2 * in4;
+          pIn1 += 4u;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set     
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 0000000000..a88e3cdd1a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_fast_q15.c    
+*    
+* Description:	 Q15 matrix multiplication (fast variant)    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @param[in]		*pState points to the array for storing intermediate results    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that    
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.    
+ * The result of each 1.15 x 1.15 multiplication is truncated to        
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30        
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.        
+ *        
+ * \par        
+ * The fast version has the same overflow behavior as the standard version but provides        
+ * less precision since it discards the low 16 bits of each multiplication result.        
+ * In order to avoid overflows completely the input signals must be scaled down.        
+ * Scale down one of the input matrices by log2(numColsA) bits to        
+ * avoid overflows, as a total of numColsA additions are computed internally for each        
+ * output element.        
+ *        
+ * \par    
+ * See arm_mat_mult_q15() for a slower implementation of this function    
+ * which uses 64-bit accumulation to provide higher precision.    
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t inA1, inA2, inB1, inB2;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inA2, inB1, inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+        
+		/* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set        
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          inA1 = *__SIMD32(pInA)++;
+          inB1 = *__SIMD32(pInB)++;
+          inA2 = *__SIMD32(pInA)++;
+          inB2 = *__SIMD32(pInB)++;
+
+          sum = __SMLAD(inA1, inB1, sum);
+          sum = __SMLAD(inA2, inB2, sum);
+
+#else
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA++;
+          sum += inA1 * inB1;
+          inB2 = *pInB++;
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          sum += inA2 * inB2;
+          inA2 = *pInA++;
+          inB2 = *pInB++;
+
+          sum += inA1 * inB1;
+          sum += inA2 * inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += (q31_t) (*pInA++) * (*pInB++);
+
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (sum >> 15);
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixMult group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 0000000000..7fdbb1cb89
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,218 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_fast_q31.c    
+*    
+* Description:	 Q31 matrix multiplication (fast variant).    
+*    
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that    
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.    
+ * The result of each 1.31 x 1.31 multiplication is truncated to    
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30    
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.    
+ *    
+ * \par    
+ * The fast version has the same overflow behavior as the standard version but provides    
+ * less precision since it discards the low 32 bits of each multiplication result.    
+ * In order to avoid overflows completely the input signals must be scaled down.    
+ * Scale down one of the input matrices by log2(numColsA) bits to    
+ * avoid overflows, as a total of numColsA additions are computed internally for each    
+ * output element.    
+ *    
+ * \par    
+ * See arm_mat_mult_q31() for a slower implementation of this function    
+ * which uses 64-bit accumulation to provide higher precision.    
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */    
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          inB1 = *pIn2;
+          pIn2 += numColsB;
+
+          inA1 = pIn1[0];
+          inA2 = pIn1[1];
+
+          inB2 = *pIn2;
+          pIn2 += numColsB;
+
+          inB3 = *pIn2;
+          pIn2 += numColsB;
+
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
+
+          inA3 = pIn1[2];
+          inA4 = pIn1[3];
+
+          inB4 = *pIn2;
+          pIn2 += numColsB;
+
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
+
+          pIn1 += 4u;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++ = sum << 1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 0000000000..b48d204ed5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,467 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_q15.c    
+*    
+* Description:	 Q15 matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+
+/**    
+ * @brief Q15 matrix multiplication    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @param[in]		*pState points to the array for storing intermediate results   
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the    
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.    
+ * The 2.30 intermediate    
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach    
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then    
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to    
+ * 1.15 format.    
+ *    
+ * \par    
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.    
+ *    
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q63_t sum;                                     /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+  q15_t in;                                      /* Temporary variable to hold the input value */
+  q15_t inA1, inB1, inA2, inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#else
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read one element from the row */
+        in = *pInB++;
+
+        /* Store one element in the destination */
+        *px = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+       /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set        
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          pSourceA1 = *__SIMD32(pInA)++;
+          pSourceB1 = *__SIMD32(pInB)++;
+
+          pSourceA2 = *__SIMD32(pInA)++;
+          pSourceB2 = *__SIMD32(pInB)++;
+
+          /* Multiply and Accumlates */
+          sum = __SMLALD(pSourceA1, pSourceB1, sum);
+          sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+          /* read real and imag values from pSrcA and pSrcB buffer */
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          inA2 = *pInA++;
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          inB2 = *pInB++;
+
+          inA1 = *pInA++;
+          inB1 = *pInB++;
+          /* Multiply and Accumlates */
+          sum += inA2 * inB2;
+          inA2 = *pInA++;
+          inB2 = *pInB++;
+
+          /* Multiply and Accumlates */
+          sum += inA1 * inB1;
+          sum += inA2 * inB2;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process remaining column samples */
+        colCnt = numColsA & 3u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pInA++ * *pInB++;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set          
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixMult group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 0000000000..eb76522042
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_mult_q31.c    
+*    
+* Description:	 Q31 matrix multiplication.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixMult    
+ * @{    
+ */
+
+/**    
+ * @brief Q31 matrix multiplication    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate    
+ * multiplication results but provides only a single guard bit. There is no saturation    
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and    
+ * distorts the result. The input signals should be scaled down to avoid intermediate    
+ * overflows. The input is thus scaled down by log2(numColsA) bits    
+ * to avoid overflows, as a total of numColsA additions are performed internally.    
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
+ *    
+ * \par    
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
+ *    
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+  q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          b0 = *pIn2;
+          pIn2 += numColsB;
+
+          a0 = *pIn1++;
+          a1 = *pIn1++;
+
+          b1 = *pIn2;
+          pIn2 += numColsB;
+          b2 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a0 *b0;
+          sum += (q63_t) a1 *b1;
+
+          a2 = *pIn1++;
+          a3 = *pIn1++;
+
+          b3 = *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) a2 *b2;
+          sum += (q63_t) a3 *b3;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set          
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixMult group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 0000000000..e64cfd1d12
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:        arm_mat_scale_f32.c    
+*    
+* Description:	Multiplies a floating-point matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixScale Matrix Scale        
+ *        
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the        
+ * matrix by the scalar.  For example:        
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"        
+ *        
+ * The function checks to make sure that the input and output matrices are of the same size.        
+ *        
+ * In the fixed-point Q15 and Q31 functions, scale is represented by        
+ * a fractional multiplication scaleFract and an arithmetic shift shift.        
+ * The shift allows the gain of the scaling operation to exceed 1.0.        
+ * The overall scale factor applied to the fixed-point data is        
+ * 
        
+ *     scale = scaleFract * 2^shift.        
+ * 
        
+ */
+
+/**        
+ * @addtogroup MatrixScale        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point matrix scaling.        
+ * @param[in]       *pSrc points to input matrix structure        
+ * @param[in]       scale scale factor to be applied         
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either ARM_MATH_SIZE_MISMATCH         
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.        
+ *        
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifndef ARM_MATH_CM0
+
+  float32_t in1, in2, in3, in4;                  /* temporary variables */
+  float32_t out1, out2, out3, out4;              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      in1 = pIn[0];
+      in2 = pIn[1];
+      in3 = pIn[2];
+      in4 = pIn[3];
+
+      out1 = in1 * scale;
+      out2 = in2 * scale;
+      out3 = in3 * scale;
+      out4 = in4 * scale;
+
+
+      pOut[0] = out1;
+      pOut[1] = out2;
+      pOut[2] = out3;
+      pOut[3] = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 0000000000..58011254c8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_scale_q15.c    
+*    
+* Description:	Multiplies a Q15 matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixScale    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix scaling.    
+ * @param[in]       *pSrc points to input matrix    
+ * @param[in]       scaleFract fractional portion of the scale factor    
+ * @param[in]       shift number of bits to shift the result by    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The input data *pSrc and scaleFract are in 1.15 format.    
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifndef ARM_MATH_CM0
+
+  q15_t in1, in2, in3, in4;
+  q31_t out1, out2, out3, out4;
+  q31_t inA1, inA2;
+
+#endif //     #ifndef ARM_MATH_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      /* Reading 2 inputs from memory */
+      inA1 = _SIMD32_OFFSET(pIn);
+      inA2 = _SIMD32_OFFSET(pIn + 2);
+
+      /* C = A * scale */
+      /* Scale the inputs and then store the 2 results in the destination buffer        
+       * in single cycle by packing the outputs */
+      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+      out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+      out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+      out1 = out1 >> totShift;
+      inA1 = _SIMD32_OFFSET(pIn + 4);
+      out2 = out2 >> totShift;
+      inA2 = _SIMD32_OFFSET(pIn + 6);
+      out3 = out3 >> totShift;
+      out4 = out4 >> totShift;
+
+      in1 = (q15_t) (__SSAT(out1, 16));
+      in2 = (q15_t) (__SSAT(out2, 16));
+      in3 = (q15_t) (__SSAT(out3, 16));
+      in4 = (q15_t) (__SSAT(out4, 16));
+
+      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 0000000000..e5e1241254
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,201 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_scale_q31.c    
+*    
+* Description:	Multiplies a Q31 matrix by a scalar.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @addtogroup MatrixScale        
+ * @{        
+ */
+
+/**        
+ * @brief Q31 matrix scaling.        
+ * @param[in]       *pSrc points to input matrix        
+ * @param[in]       scaleFract fractional portion of the scale factor        
+ * @param[in]       shift number of bits to shift the result by        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
+ *        
+ * @details        
+ * Scaling and Overflow Behavior:        
+ * \par        
+ * The input data *pSrc and scaleFract are in 1.31 format.        
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.        
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = shift + 1;                  /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+  q31_t in1, in2, out1;                          /* temporary variabels */
+
+#ifndef ARM_MATH_CM0
+
+  q31_t in3, in4, out2, out3, out4;              /* temporary variables */
+
+#endif //      #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch  */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif //    #ifdef ARM_MATH_MATRIX_CHECK
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Read values from input */
+      in1 = *pIn;
+      in2 = *(pIn + 1);
+      in3 = *(pIn + 2);
+      in4 = *(pIn + 3);
+
+      /* multiply input with scaler value */
+      in1 = ((q63_t) in1 * scaleFract) >> 32;
+      in2 = ((q63_t) in2 * scaleFract) >> 32;
+      in3 = ((q63_t) in3 * scaleFract) >> 32;
+      in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+      /* apply shifting */
+      out1 = in1 << totShift;
+      out2 = in2 << totShift;
+
+      /* saturate the results. */
+      if(in1 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+      if(in2 != (out2 >> totShift))
+        out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      out3 = in3 << totShift;
+      out4 = in4 << totShift;
+
+      *pOut = out1;
+      *(pOut + 1) = out2;
+
+      if(in3 != (out3 >> totShift))
+        out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+      if(in4 != (out4 >> totShift))
+        out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+      *(pOut + 2) = out3;
+      *(pOut + 3) = out4;
+
+      /* update pointers to process next sampels */
+      pIn += 4u;
+      pOut += 4u;
+
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      in1 = *pIn++;
+
+      in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+      out1 = in2 << totShift;
+
+      if(in2 != (out1 >> totShift))
+        out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+      *pOut++ = out1;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixScale group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 0000000000..3544d8e825
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_f32.c    
+*    
+* Description:	Floating-point matrix subtraction.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @defgroup MatrixSub Matrix Subtraction        
+ *        
+ * Subtract two matrices.        
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"        
+ *        
+ * The functions check to make sure that        
+ * pSrcA, pSrcB, and pDst have the same        
+ * number of rows and columns.        
+ */
+
+/**        
+ * @addtogroup MatrixSub        
+ * @{        
+ */
+
+/**        
+ * @brief Floating-point matrix subtraction        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+
+#ifndef ARM_MATH_CM0
+
+  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* out = sourceA - sourceB */
+      out1 = inA1 - inB1;
+
+
+      /* out = sourceA - sourceB */
+      out2 = inA2 - inB2;
+
+      /* Store result in destination */
+      pOut[2] = out1;
+
+      /* Store result in destination */
+      pOut[3] = out2;
+
+
+      /* update pointers to process next sampels */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixSub group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 0000000000..1857fd837c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_q15.c    
+*    
+* Description:	Q15 Matrix subtraction    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixSub    
+ * @{    
+ */
+
+/**    
+ * @brief Q15 matrix subtraction.    
+ * @param[in]       *pSrcA points to the first input matrix structure    
+ * @param[in]       *pSrcB points to the second input matrix structure    
+ * @param[out]      *pDst points to output matrix structure    
+ * @return     		The function returns either    
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ *    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixSub group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 0000000000..279fd7f7c1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_sub_q31.c    
+*    
+* Description:	Q31 matrix subtraction    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupMatrix        
+ */
+
+/**        
+ * @addtogroup MatrixSub        
+ * @{        
+ */
+
+/**        
+ * @brief Q31 matrix subtraction.        
+ * @param[in]       *pSrcA points to the first input matrix structure        
+ * @param[in]       *pSrcB points to the second input matrix structure        
+ * @param[out]      *pDst points to output matrix structure        
+ * @return     		The function returns either        
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
+ *        
+ * Scaling and Overflow Behavior:        
+ * \par        
+ * The function uses saturating arithmetic.        
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t inA1, inB1;                              /* temporary variables */
+
+#ifndef ARM_MATH_CM0
+
+  q31_t inA2, inB2;                              /* temporary variables */
+  q31_t out1, out2;                              /* temporary variables */
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+  /* Check for matrix mismatch condition  */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      /* Read values from source A */
+      inA1 = pIn1[0];
+
+      /* Read values from source B */
+      inB1 = pIn2[0];
+
+      /* Read values from source A */
+      inA2 = pIn1[1];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Read values from source B */
+      inB2 = pIn2[1];
+
+      /* Read values from source A */
+      inA1 = pIn1[2];
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Read values from source B */
+      inB1 = pIn2[2];
+
+      /* Store result in destination */
+      pOut[0] = out1;
+      pOut[1] = out2;
+
+      /* Read values from source A */
+      inA2 = pIn1[3];
+
+      /* Read values from source B */
+      inB2 = pIn2[3];
+
+      /* Subtract and saturate */
+      out1 = __QSUB(inA1, inB1);
+
+      /* Subtract and saturate */
+      out2 = __QSUB(inA2, inB2);
+
+      /* Store result in destination */
+      pOut[2] = out1;
+      pOut[3] = out2;
+
+      /* update pointers to process next samples */
+      pIn1 += 4u;
+      pIn2 += 4u;
+      pOut += 4u;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      inA1 = *pIn1++;
+      inB1 = *pIn2++;
+
+      inA1 = __QSUB(inA1, inB1);
+
+      *pOut++ = inA1;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**        
+ * @} end of MatrixSub group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 0000000000..235028f5ab
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_f32.c    
+*    
+* Description:	Floating-point matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+/**    
+ * @defgroup MatrixTrans Matrix Transpose    
+ *    
+ * Tranposes a matrix.    
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.    
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"    
+ */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/**    
+  * @brief Floating-point matrix transpose.    
+  * @param[in]  *pSrc points to the input matrix    
+  * @param[out] *pDst points to the output matrix    
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 0000000000..be9c78e003
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,282 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_q15.c    
+*    
+* Description:	Q15 matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/*    
+ * @brief Q15 matrix transpose.    
+ * @param[in]  *pSrc points to the input matrix    
+ * @param[out] *pDst points to the output matrix    
+ * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+#else
+
+  q15_t in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2u;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+#else	 
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+ 
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read one element from the row */
+        in = *pSrcA++;
+
+        /* Store one element in the destination */
+        *pOut = in;
+
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 0000000000..253a923d1c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_mat_trans_q31.c    
+*    
+* Description:	Q31 matrix transpose.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+*    incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupMatrix    
+ */
+
+/**    
+ * @addtogroup MatrixTrans    
+ * @{    
+ */
+
+/*    
+  * @brief Q31 matrix transpose.    
+  * @param[in]  *pSrc points to the input matrix    
+  * @param[out] *pDst points to the output matrix    
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2u;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while(row > 0u);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**    
+ * @} end of MatrixTrans group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 0000000000..afd9648852
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_f32.c    
+*    
+* Description:	Maximum value of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup Max Maximum    
+ *    
+ * Computes the maximum value of an array of data.     
+ * The function returns both the maximum value and its position within the array.     
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 0000000000..939b5236f6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q15.c    
+*    
+* Description:	Maximum value of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 0000000000..18e7572975
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q31.c    
+*    
+* Description:	Maximum value of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+ * @return none.    
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 0000000000..110a8fe5f7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_max_q7.c    
+*    
+* Description:	Maximum value of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Max    
+ * @{    
+ */
+
+
+/**    
+ * @brief Maximum value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult maximum value returned here    
+ * @param[out]      *pIndex index of maximum value returned here    
+  * @return none.    
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 1u;
+    }
+
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 2u;
+    }
+
+    maxVal2 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the maximum value */
+    if(out < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal1 = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal1)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal1;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+}
+
+/**    
+ * @} end of Max group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 0000000000..7823d746ca
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_f32.c    
+*    
+* Description:	Mean value of a floating-point vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup mean Mean    
+ *    
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.    
+ * The underlying algorithm is used:    
+ *    
+ * 
    
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    
+ * 
    
+ *    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+
+/**    
+ * @brief Mean value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ */
+
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 0000000000..49ec1e62e7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q15.c    
+*    
+* Description:	Mean value of a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.15 format and is accumulated in a 32-bit     
+ * accumulator in 17.15 format.     
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.    
+ *    
+ */
+
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 0000000000..88a5de2995
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q31.c    
+*    
+* Description:	Mean value of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *\par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.31 format and is accumulated in a 64-bit    
+ * accumulator in 33.31 format.    
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.    
+ *    
+ */
+
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    sum += in1;
+    sum += in2;
+    sum += in3;
+    sum += in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 0000000000..a34c011bc1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_mean_q7.c    
+*    
+* Description:	Mean value of a Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup mean    
+ * @{    
+ */
+
+/**    
+ * @brief Mean value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult mean value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.     
+ * The input is represented in 1.7 format and is accumulated in a 32-bit    
+ * accumulator in 25.7 format.    
+ * There is no risk of internal overflow with this approach, and the     
+ * full precision of intermediate result is preserved.     
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.    
+ *    
+ */
+
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    in = *__SIMD32(pSrc)++;
+
+    sum += ((in << 24) >> 24);
+    sum += ((in << 16) >> 24);
+    sum += ((in << 8) >> 24);
+    sum += (in >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**    
+ * @} end of mean group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 0000000000..dc2fdf624f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_f32.c    
+*    
+* Description:	Minimum value of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup Min Minimum    
+ *    
+ * Computes the minimum value of an array of data.     
+ * The function returns both the minimum value and its position within the array.     
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
+ */
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+  * @return none.    
+ *    
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t minVal1, out;                        /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 0000000000..35b67bb1e9
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q15.c    
+*    
+* Description:	Minimum value of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 0000000000..4a9befc75c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q31.c    
+*    
+* Description:	Minimum value of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q31_t minVal1, out;                            /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  blkCnt = (blockSize - 1u);
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 0000000000..aaf8ad9ff8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,170 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_min_q7.c    
+*    
+* Description:	Minimum value of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup Min    
+ * @{    
+ */
+
+
+/**    
+ * @brief Minimum value of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult minimum value returned here    
+ * @param[out]      *pIndex index of minimum value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex, count;              /* loop counter */
+
+  /* Initialise the count value. */
+  count = 0u;
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 1u;
+    }
+
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 2u;
+    }
+
+    minVal2 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and its index */
+      out = minVal1;
+      outIndex = count + 3u;
+    }
+
+    /* compare for the minimum value */
+    if(out > minVal2)
+    {
+      /* Update the minimum value and its index */
+      out = minVal2;
+      outIndex = count + 4u;
+    }
+
+    count += 4u;
+
+    blkCnt--;
+  }
+
+  /* if (blockSize - 1u ) is not multiple of 4 */
+  blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal1, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  blkCnt = (blockSize - 1u);
+
+#endif //      #ifndef ARM_MATH_CM0
+
+  while(blkCnt > 0)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal1 = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal1)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal1;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+
+}
+
+/**    
+ * @} end of Min group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 0000000000..5ee0060d8f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_f32.c    
+*    
+* Description:	Sum of the squares of the elements of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup power Power    
+ *    
+ * Calculates the sum of the squares of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * 
    
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    
+ * 
    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+
+/**    
+ * @brief Sum of the squares of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 0000000000..aed06a17ac
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q15.c    
+*    
+* Description:	Sum of the squares of the elements of a Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.     
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 34.30 format.     
+ *    
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 0000000000..43f03f757f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q31.c    
+*    
+* Description:	Sum of the squares of the elements of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.31 format.    
+ * Intermediate multiplication yields a 2.62 format, and this    
+ * result is truncated to 2.48 format by discarding the lower 14 bits.    
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 16.48 format.     
+ *    
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 0000000000..5cb99b4c2f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_power_q7.c    
+*    
+* Description:	Sum of the squares of the elements of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup power    
+ * @{    
+ */
+
+/**    
+ * @brief Sum of the squares of the elements of a Q7 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult sum of the squares value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 32-bit internal accumulator.     
+ * The input is represented in 1.7 format.   
+ * Intermediate multiplication yields a 2.14 format, and this    
+ * result is added without saturation to an accumulator in 18.14 format.    
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the return result is in 18.14 format.     
+ *    
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q31_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    input1 = *__SIMD32(pSrc)++;
+
+    in1 = __SXTB16(__ROR(input1, 8));
+    in2 = __SXTB16(input1);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* calculate power and accumulate to accumulator */
+    sum = __SMLAD(in1, in1, sum);
+    sum = __SMLAD(in2, in2, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**    
+ * @} end of power group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 0000000000..573896ed4d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_f32.c    
+*    
+* Description:	Root mean square value of an array of F32 type    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup RMS Root mean square (RMS)    
+ *    
+ *     
+ * Calculates the Root Mean Sqaure of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * 
    
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    
+ * 
    
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.     
+ */
+
+/**    
+ * @addtogroup RMS    
+ * @{    
+ */
+
+
+/**    
+ * @brief Root Mean Square of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult rms value returned here    
+ * @return none.    
+ *    
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**    
+ * @} end of RMS group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 0000000000..491c652e7a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_q15.c    
+*    
+* Description:	Root Mean Square of the elements of a Q15 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup RMS    
+ * @{    
+ */
+
+/**    
+ * @brief Root Mean Square of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult rms value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.    
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ *    
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in1 = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of RMS group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 0000000000..54038eb12e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_rms_q31.c    
+*    
+* Description:	Root Mean Square of the elements of a Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @addtogroup RMS        
+ * @{        
+ */
+
+
+/**        
+ * @brief Root Mean Square of the elements of a Q31 vector.        
+ * @param[in]       *pSrc points to the input vector        
+ * @param[in]       blockSize length of the input vector        
+ * @param[out]      *pResult rms value returned here        
+ * @return none.        
+ *        
+ * @details        
+ * Scaling and Overflow Behavior:        
+ *        
+ *\par        
+ * The function is implemented using an internal 64-bit accumulator.        
+ * The input is represented in 1.31 format, and intermediate multiplication        
+ * yields a 2.62 format.        
+ * The accumulator maintains full precision of the intermediate multiplication results,         
+ * but provides only a single guard bit.        
+ * There is no saturation on intermediate additions.        
+ * If the accumulator overflows, it wraps around and distorts the result.         
+ * In order to avoid overflows completely, the input signal must be scaled down by         
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
+ *        
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.        
+   ** a second loop below computes the remaining 1 to 7 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    /* read two samples from source buffer */
+    in1 = pSrc[0];
+    in2 = pSrc[1];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in1 *in1;
+    sum += (q63_t) in2 *in2;
+
+    /* read two samples from source buffer */
+    in3 = pSrc[2];
+    in4 = pSrc[3];
+
+    /* calculate power and accumulate to accumulator */
+    sum += (q63_t) in3 *in3;
+    sum += (q63_t) in4 *in4;
+
+
+    /* update source buffer to process next samples */
+    pSrc += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.        
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+
+  sum = __SSAT(sum >> 31, 31);
+
+
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);
+}
+
+/**        
+ * @} end of RMS group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 0000000000..6442d5c295
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_f32.c    
+*    
+* Description:	Standard deviation of the elements of a floating-point vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup STD Standard deviation    
+ *    
+ * Calculates the standard deviation of the elements in the input vector.     
+ * The underlying algorithm is used:    
+ *   
+ * 
    
+ * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))   
+ *   
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
+ *   
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ * 
   
+ *    
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+
+/**    
+ * @brief Standard deviation of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, squareOfMean;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t var;                                 /* Temporary varaince storage */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples     
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 0000000000..2d1a49a505
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,197 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_q15.c    
+*    
+* Description:	Standard deviation of an array of Q15 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+/**    
+ * @brief Standard deviation of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+    sum += in1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  q15_t in;                                      /* input value */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+  /* Compute mean of all input values */
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean of the input samples   
+   * and then store the result in a temporary variable, squareOfMean.*/
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 0000000000..45bec01a1f
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,184 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_std_q31.c    
+*    
+* Description:	Standard deviation of an array of Q31 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup STD    
+ * @{    
+ */
+
+
+/**    
+ * @brief Standard deviation of the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult standard deviation value returned here    
+ * @return none.    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ *\par    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The input is represented in 1.31 format, and intermediate multiplication    
+ * yields a 2.62 format.    
+ * The accumulator maintains full precision of the intermediate multiplication results,     
+ * but provides only a single guard bit.    
+ * There is no saturation on intermediate additions.    
+ * If the accumulator overflows it wraps around and distorts the result.    
+ * In order to avoid overflows completely the input signal must be scaled down by     
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.     
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.    
+ *    
+ */
+
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t mean;                                    /* mean */
+  q31_t in;                                      /* input value */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**    
+ * @} end of STD group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 0000000000..2adcfb443b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,184 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_f32.c    
+*    
+* Description:	Variance of the elements of a floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @defgroup variance  Variance    
+ *    
+ * Calculates the variance of the elements in the input vector.    
+ * The underlying algorithm is used:    
+ *    
+ * 
    
+ * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)   
+ *   
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
+ *   
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ * 
   
+ *    
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**    
+ * @addtogroup variance    
+ * @{    
+ */
+
+
+/**    
+ * @brief Variance of the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult variance value returned here    
+ * @return none.    
+ *    
+ */
+
+
+void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in;
+    sumOfSquares += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  float32_t squareOfSum;                         /* Square of Sum */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples     
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of variance group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 0000000000..08dbc6587c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_q15.c    
+*    
+* Description:	Variance of an array of Q15 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupStats    
+ */
+
+/**    
+ * @addtogroup variance    
+ * @{    
+ */
+
+/**    
+ * @brief Variance of the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to the input vector    
+ * @param[in]       blockSize length of the input vector    
+ * @param[out]      *pResult variance value returned here    
+ * @return none.    
+ *    
+ * @details    
+ * Scaling and Overflow Behavior:    
+ *    
+ * \par    
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this    
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.    
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
+ * full precision of the intermediate multiplication is preserved.    
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
+ * 15 bits, and then saturated to yield a result in 1.15 format.    
+ *    
+ */
+
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Input variable */
+  q15_t in1;                                     /* Temporary variable */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+    in = *__SIMD32(pSrc)++;
+    sum += ((in << 16) >> 16);
+    sum += (in >> 16);
+    sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum += in1;
+    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples     
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples     
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+  mean = __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**    
+ * @} end of variance group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 0000000000..13d6c15cb5
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,170 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_var_q31.c    
+*    
+* Description:	Variance of an array of Q31 type.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**        
+ * @ingroup groupStats        
+ */
+
+/**        
+ * @addtogroup variance        
+ * @{        
+ */
+
+/**        
+ * @brief Variance of the elements of a Q31 vector.        
+ * @param[in]       *pSrc points to the input vector        
+ * @param[in]       blockSize length of the input vector        
+ * @param[out]      *pResult variance value returned here        
+ * @return none.        
+ *        
+ * @details        
+ * Scaling and Overflow Behavior:        
+ *        
+ *\par        
+ * The function is implemented using an internal 64-bit accumulator.        
+ * The input is represented in 1.31 format, and intermediate multiplication        
+ * yields a 2.62 format.        
+ * The accumulator maintains full precision of the intermediate multiplication results,         
+ * but provides only a single guard bit.        
+ * There is no saturation on intermediate additions.        
+ * If the accumulator overflows it wraps around and distorts the result.        
+ * In order to avoid overflows completely the input signal must be scaled down by         
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
+ *        
+ */
+
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0, sumSquare = 0;                  /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t mean;                                    /* mean */
+  q31_t in;                                      /* input value */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q63_t sumSquare1 = 0;                          /* Accumulator */
+  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples        
+     * and then store the result in a temporary variable, sum. */
+    /* read input samples from source buffer */
+    in1 = pSrc[0];
+    in2 = pSrc[1];
+
+    /* calculate sum of inputs */
+    sum += in1;
+    /* calculate sum of squares */
+    sumSquare += ((q63_t) (in1) * (in1));
+    in3 = pSrc[2];
+    sum += in2;
+    sumSquare1 += ((q63_t) (in2) * (in2));
+    in4 = pSrc[3];
+    sum += in3;
+    sumSquare += ((q63_t) (in3) * (in3));
+    sum += in4;
+    sumSquare1 += ((q63_t) (in4) * (in4));
+
+    /* update input pointer to process next samples */
+    pSrc += 4u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* add two accumulators */
+  sumSquare = sumSquare + sumSquare1;
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples        
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sumSquare += ((q63_t) (in) * (in));
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+  /* Compute Mean of squares of the input samples        
+   * and then store the result in a temporary variable, meanOfSquares. */
+  sumSquare = (sumSquare >> 31);
+  meanOfSquares = (q31_t) ((sumSquare * t) >> 30);
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**        
+ * @} end of variance group        
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 0000000000..619c1577a6
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_f32.c    
+*    
+* Description:	Copies the elements of a floating-point vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup copy Vector Copy    
+ *    
+ * Copies sample by sample from source vector to destination vector.    
+ *    
+ * 
    
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.    
+ * 
    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a floating-point vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 0000000000..00be9dc0b2
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q15.c    
+*    
+* Description:	Copies the elements of a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+/**    
+ * @brief Copies the elements of a Q15 vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Read two inputs */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 0000000000..7ab0849f6e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q31.c    
+*    
+* Description:	Copies the elements of a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a Q31 vector.     
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 0000000000..425885753e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_copy_q7.c    
+*    
+* Description:	Copies the elements of a Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup copy    
+ * @{    
+ */
+
+/**    
+ * @brief Copies the elements of a Q7 vector.    
+ * @param[in]       *pSrc points to input vector    
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the input vector   
+ * @return none.    
+ *    
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of BasicCopy group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 0000000000..439e60db0c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_f32.c    
+*    
+* Description:	Fills a constant value into a floating-point vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup Fill Vector Fill    
+ *    
+ * Fills the destination vector with a constant value.    
+ *    
+ * 
    
+ * 	pDst[n] = value;   0 <= n < blockSize.    
+ * 
    
+ *   
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a floating-point vector.     
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  float32_t in1 = value;
+  float32_t in2 = value;
+  float32_t in3 = value;
+  float32_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 0000000000..8f60d3b4ef
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q15.c    
+*    
+* Description:	Fills a constant value into a Q15 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q15 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16u);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 0000000000..35565c3cf7
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q31.c    
+*    
+* Description:	Fills a constant value into a Q31 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q31 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1 = value;
+  q31_t in2 = value;
+  q31_t in3 = value;
+  q31_t in4 = value;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = in1;
+    *pDst++ = in2;
+    *pDst++ = in3;
+    *pDst++ = in4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 0000000000..481d4c8f7b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_fill_q7.c    
+*    
+* Description:	Fills a constant value into a Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup Fill    
+ * @{    
+ */
+
+/**    
+ * @brief Fills a constant value into a Q7 vector.    
+ * @param[in]       value input value to be filled   
+ * @param[out]      *pDst points to output vector    
+ * @param[in]       blockSize length of the output vector   
+ * @return none.    
+ *    
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of Fill group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 0000000000..1537b93ab9
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q15.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q15 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ * 
    
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    
+ * 
    
+ * \par Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
+ * \note   
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ *    
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 0000000000..3ab52b9ff0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q31.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q31 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup float_to_x  Convert 32-bit floating point value    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q31 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ *\par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    
+ * 
    
+ * Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
+ *   
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 0000000000..dea14c6a14
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_float_to_q7.c    
+*    
+* Description:	Converts the elements of the floating-point vector to Q7 vector.   
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup float_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the floating-point vector to Q7 vector.    
+ * @param[in]       *pSrc points to the floating-point input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ *\par Description:    
+ * \par   
+ * The equation used for the conversion process is:    
+ * 
    
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    
+ * 
    
+ * \par Scaling and Overflow Behavior:    
+ * \par    
+ * The function uses saturating arithmetic.    
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
+ * \note   
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
+ * defined in the preprocessor section of project options.     
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+ * @} end of float_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 0000000000..ce51e9a395
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_float.c    
+*    
+* Description:	Converts the elements of the Q15 vector to floating-point vector.     
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q15_to_x  Convert 16-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+
+
+
+/**    
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 0000000000..a0f66c29e8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_q31.c    
+*    
+* Description:	Converts the elements of the Q15 vector to Q31 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q15 vector to Q31 vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:   
+ *   
+ * 
    
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* extract lower 16 bits to 32 bit result */
+    out1 = in1 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out2 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out3 = in2 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out4 = in2 & 0xFFFF0000;
+
+#else
+
+    /* extract upper 16 bits to 32 bit result */
+    out1 = in1 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out2 = in1 << 16u;
+    /* extract upper 16 bits to 32 bit result */
+    out3 = in2 & 0xFFFF0000;
+    /* extract lower 16 bits to 32 bit result */
+    out4 = in2 << 16u;
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = out1;
+    *pDst++ = out2;
+    *pDst++ = out3;
+    *pDst++ = out4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 0000000000..87fe63d9eb
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q15_to_q7.c    
+*    
+* Description:	Converts the elements of the Q15 vector to Q7 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q15_to_x    
+ * @{    
+ */
+
+
+/**    
+ * @brief Converts the elements of the Q15 vector to Q7 vector.     
+ * @param[in]       *pSrc points to the Q15 input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    
+ * 
   
+ *   
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    in1 = *__SIMD32(pIn)++;
+    in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in1, in2, 16);
+
+#endif //      #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* rotate packed value by 24 */
+    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+    /* anding with 0xff00ff00 to get two 8 bit values */
+    out1 = out1 & 0xFF00FF00;
+    /* anding with 0x00ff00ff to get two 8 bit values */
+    out2 = out2 & 0x00FF00FF;
+
+    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+    out1 = out1 | out2;
+
+    /* store 4 samples at a time to destiantion buffer */
+    *__SIMD32(pDst)++ = out1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q15_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 0000000000..94deec9a1b
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_float.c    
+*    
+* Description:	Converts the elements of the Q31 vector to floating-point vector.      
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q31_to_x  Convert 32-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 0000000000..ba79f85a13
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_q15.c    
+*    
+* Description:	Converts the elements of the Q31 vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to Q15 vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *     
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q31_t out1, out2;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __PKHTB(in2, in1, 16);
+    out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHTB(in3, in4, 16);
+
+#endif //      #ifdef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 0000000000..afc8fdbed4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q31_to_q7.c    
+*    
+* Description:	Converts the elements of the Q31 vector to Q7 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q31_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q31 vector to Q7 vector.    
+ * @param[in]       *pSrc points to the Q31 input vector    
+ * @param[out]      *pDst points to the Q7 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     
+ * 
    
+ *   
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t in1, in2, in3, in4;
+  q7_t out1, out2, out3, out4;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    in1 = *pIn++;
+    in2 = *pIn++;
+    in3 = *pIn++;
+    in4 = *pIn++;
+
+    out1 = (q7_t) (in1 >> 24);
+    out2 = (q7_t) (in2 >> 24);
+    out3 = (q7_t) (in3 >> 24);
+    out4 = (q7_t) (in4 >> 24);
+
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q31_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 0000000000..be4ac5fe30
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_float.c    
+*    
+* Description:	Converts the elements of the Q7 vector to floating-point vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @defgroup q7_to_x  Convert 8-bit Integer value    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the floating-point output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *		     
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 0000000000..019ca48159
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_q15.c    
+*    
+* Description:	Converts the elements of the Q7 vector to Q15 vector.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+
+
+
+/**    
+ * @brief Converts the elements of the Q7 vector to Q15 vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q15 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    
+ * 
    
+ *   
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+  q31_t in;
+  q31_t in1, in2;
+  q31_t out1, out2;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+    /* rotatate in by 8 and extend two q7_t values to q15_t values */
+    in1 = __SXTB16(__ROR(in, 8));
+
+    /* extend remainig two q7_t values to q15_t values */
+    in2 = __SXTB16(in);
+
+    in1 = in1 << 8u;
+    in2 = in2 << 8u;
+
+    in1 = in1 & 0xFF00FF00;
+    in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out2 = __PKHTB(in1, in2, 16);
+    out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+    out1 = __PKHTB(in1, in2, 16);
+    out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+    *__SIMD32(pDst)++ = out1;
+    *__SIMD32(pDst)++ = out2;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 0000000000..bbbcc6f4a3
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:		arm_q7_to_q31.c    
+*    
+* Description:	Converts the elements of the Q7 vector to Q31 vector.  
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupSupport    
+ */
+
+/**    
+ * @addtogroup q7_to_x    
+ * @{    
+ */
+
+/**    
+ * @brief Converts the elements of the Q7 vector to Q31 vector.    
+ * @param[in]       *pSrc points to the Q7 input vector    
+ * @param[out]      *pDst points to the Q31 output vector   
+ * @param[in]       blockSize length of the input vector    
+ * @return none.    
+ *    
+ * \par Description:    
+ *    
+ * The equation used for the conversion process is:    
+ *   
+ * 
    
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   
+ * 
     
+ *   
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  q31_t in;
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (in & 0xFF000000);
+
+#else
+
+    *pDst++ = (in & 0xFF000000);
+    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif //              #ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**    
+ * @} end of q7_to_x group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
new file mode 100644
index 0000000000..3da790ebb1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,222 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_bitreversal.c    
+*    
+* Description:	This file has common tables like Bitreverse, reciprocal etc which are used across different functions    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Initial Version  
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*    
+ * @brief  In-place bit reversal function.   
+ * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.   
+ * @param[in]      fftSize      length of the FFT.   
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.   
+ * @param[in]      *pBitRevTab  points to the bit reversal table.   
+ * @return none.   
+ */
+
+void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  uint16_t fftLenBy2, fftLenBy2p1;
+  uint16_t i, j;
+  float32_t in;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftSize >> 1u;
+  fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
+
+
+
+/*    
+ * @brief  In-place bit reversal function.   
+ * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.   
+ * @param[in]      fftLen       length of the FFT.   
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
+ * @param[in]      *pBitRevTab  points to bit reversal table.   
+ * @return none.   
+ */
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTable)
+{
+  uint32_t fftLenBy2, fftLenBy2p1, i, j;
+  q31_t in;
+
+  /*  Initializations      */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTable;
+
+    /*  Updating the bit reversal index depending on the fft length */
+    pBitRevTable += bitRevFactor;
+  }
+}
+
+
+
+/*    
+   * @brief  In-place bit reversal function.   
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.   
+   * @param[in]      fftLen       length of the FFT.   
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
+   * @param[in]      *pBitRevTab  points to bit reversal table.   
+   * @return none.   
+ */
+
+void arm_bitreversal_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  q31_t *pSrc = (q31_t *) pSrc16;
+  q31_t in;
+  uint32_t fftLenBy2, fftLenBy2p1;
+  uint32_t i, j;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[i];
+      pSrc[i] = pSrc[j];
+      pSrc[j] = in;
+
+      /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+      /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+      in = pSrc[i + fftLenBy2p1];
+      pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+      pSrc[j + fftLenBy2p1] = in;
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
+    /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
+    in = pSrc[i + 1u];
+    pSrc[i + 1u] = pSrc[j + fftLenBy2];
+    pSrc[j + fftLenBy2] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
index 0000000000..274b699281
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,511 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_f32.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.   
+ * \par   
+ * This set of functions implements CFFT/CIFFT   
+ * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.   
+ * Complex input is stored in input buffer in an interleaved fashion.   
+ *   
+ * \par   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.   
+ * \par  
+ * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.   
+ * 
 {real[0], imag[0], real[1], imag[1],..} 
   
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Internally, the function utilize a radix-2 decimation in frequency(DIF) algorithm   
+ * and the size of the FFT supported are of the lengths [16, 32, 64, 128, 256, 512, 1024, 2048, 4096].  
+ *    
+ *   
+ * \par Algorithm:   
+ *   
+ * Complex Fast Fourier Transform:   
+ * \par    
+ * Input real and imaginary data:   
+ * 
   
+ * x(n) = xa + j * ya   
+ * x(n+N/2 ) = xb + j * yb   
+ * 
   
+ * where N is length of FFT   
+ * \par   
+ * Output real and imaginary data:   
+ * 
   
+ * X(2r) = xa'+ j * ya'   
+ * X(2r+1) = xb'+ j * yb'   
+ * 
   
+ * \par   
+ * Twiddle factors for radix-2 FFT:   
+ * 
   
+ * Wn = cosVal + j * (- sinVal)   
+ * 
   
+ *   
+ * \par   
+ * \image html CFFT_Radix2.gif "Radix-2 Decimation-in Frequency Complex Fast Fourier Transform"   
+ *   
+ * \par   
+ * Output from Radix-2 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.   
+ * \par   
+ *  Butterfly CFFT equations:   
+ * 
   
+ * xa' = xa + xb  
+ * ya' = ya + yb  
+ * xb' = (xa-xb)* cosVal + (ya-yb) * sinVal   
+ * yb' = (ya-yb)* cosVal - (xa-xb) * sinVal   
+ * 
   
+ *   
+ *   
+ * Complex Inverse Fast Fourier Transform:   
+ * \par   
+ * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.   
+ *   
+ * \par   
+ *  Modified Butterfly CIFFT equations:   
+ * 
   
+ * xa' = xa + xb  
+ * ya' = ya + yb  
+ * xb' = (xa-xb)* cosVal - (ya-yb) * sinVal   
+ * yb' = (ya-yb)* cosVal + (xa-xb) * sinVal   
+ * 
   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor table and bit reversal table pointers   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_cfft_radix2_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+ *arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ *arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ * 
   
+ * \par   
+ * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);   
+ * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    
+ * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.   
+ * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    
+ * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   
+ * onebyfftLen value of 1/fftLen to calculate CIFFT;   
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+
+/**   
+ * @addtogroup Radix2_CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the floating-point Radix-2 CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-2  */
+    arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier, S->onebyfftLen);
+  }
+  else
+  {
+    /*  Complex FFT radix-2  */
+    arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+
+/**    
+ * @} end of Radix2_CFFT_CIFFT group    
+ */
+
+
+
+/* ----------------------------------------------------------------------    
+** Internal helper function used by the FFTs    
+** ------------------------------------------------------------------- */
+
+/*    
+ * @brief  Core function for the floating-point CFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to the twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix2_butterfly_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  float32_t xt, yt, cosVal, sinVal;
+
+#ifndef ARM_MATH_CM0
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+
+    /*  Twiddle coefficients index modifier */
+    ia = ia + twidCoefModifier;
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i + 0], pSrc[i + fftLen/1] */
+    l = i + n2;
+
+    /*  Butterfly implementation */
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+    pSrc[2u * l] = xt * cosVal + yt * sinVal;
+
+    pSrc[2u * l + 1u] = yt * cosVal - xt * sinVal;
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+        pSrc[2u * l] = xt * cosVal + yt * sinVal;
+
+        pSrc[2u * l + 1u] = yt * cosVal - xt * sinVal;
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+  }                             // groups loop end 
+
+#else
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  // loop for stage 
+  for (k = fftLen; k > 1; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+        pSrc[2 * l] = (cosVal * xt + sinVal * yt);      // >> 15; 
+        pSrc[2 * l + 1] = (cosVal * yt - sinVal * xt);  // >> 15; 
+
+      }
+    }
+    twidCoefModifier = twidCoefModifier << 1u;
+  }
+
+#endif //    #ifndef ARM_MATH_CM0
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen)
+{
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  float32_t xt, yt, cosVal, sinVal;
+
+#ifndef ARM_MATH_CM0
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+    pSrc[2u * l] = xt * cosVal - yt * sinVal;
+
+    pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+        pSrc[2u * l] = xt * cosVal - yt * sinVal;
+
+        pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) * onebyfftLen;
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) * onebyfftLen;
+
+    pSrc[2u * l] = xt * onebyfftLen;
+
+    pSrc[2u * l + 1u] = yt * onebyfftLen;
+
+  }                             // butterfly loop end 
+
+#else
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  // loop for stage 
+  for (k = fftLen; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+        pSrc[2u * l] = xt * cosVal - yt * sinVal;
+
+        pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) * onebyfftLen;
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) * onebyfftLen;
+
+    pSrc[2u * l] = xt * onebyfftLen;
+
+    pSrc[2u * l + 1u] = yt * onebyfftLen;
+
+  }                             // butterfly loop end 
+
+#endif //      #ifndef ARM_MATH_CM0
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
index 0000000000..a41ed25d2c
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,198 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup Radix2_CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+* @brief  Initialization function for the floating-point CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 2048u:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.00048828125;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+  case 512u:
+    /*  Initializations of structure parameters for 512 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.001953125;
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    S->onebyfftLen = 0.0078125;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    S->onebyfftLen = 0.03125;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of Radix2_CFFT_CIFFT group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100644
index 0000000000..86aa149b2d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix2_init_q15.c    
+*    
+* Description:	Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+
+/**    
+ * @addtogroup Radix2_CFFT_CIFFT    
+ * @{    
+ */
+
+/**   
+* @brief Initialization function for the Q15 CFFT/CIFFT.   
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoefQ15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 2048u:
+    /*  Initializations of structure parameters for 2048 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 512u:
+    /*  Initializations of structure parameters for 512 point FFT */
+    S->twidCoefModifier = 8u;
+    S->bitRevFactor = 8u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of Radix2_CFFT_CIFFT group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100644
index 0000000000..29aa9a74bd
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,164 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_init_q31.c   
+*   
+* Description:	Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup Radix2_CFFT_CIFFT   
+ * @{   
+ */
+
+
+/**    
+*    
+* @brief  Initialization function for the Q31 CFFT/CIFFT.   
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoefQ31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 2048 point FFT */
+  case 2048u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 2u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 2u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+    /*  Initializations of structure parameters for 512 point FFT */
+  case 512u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 8u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 8u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 128u:
+    /*  Initializations of structure parameters for 128 point FFT */
+    S->twidCoefModifier = 32u;
+    S->bitRevFactor = 32u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 32u:
+    /*  Initializations of structure parameters for 32 point FFT */
+    S->twidCoefModifier = 128u;
+    S->bitRevFactor = 128u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of Radix2_CFFT_CIFFT group   
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100644
index 0000000000..00c7420cf4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,712 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_q15.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.    
+ */
+
+
+/**   
+ * @addtogroup Radix2_CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the fixed-point CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+                                     S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    arm_radix2_butterfly_q15(pSrc, S->fftLen,
+                             S->pTwiddle, S->twidCoefModifier);
+  }
+
+  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**   
+ * @} end of Radix2_CFFT_CIFFT group   
+ */
+
+void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16u;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUAD(coeff, R) >> 16;
+    out2 = __SMUSDX(coeff, R);
+
+#else
+
+    out1 = __SMUSDX(R, coeff) >> 16u;
+    out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16u;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(coeff, R) >> 16;
+        out2 = __SMUSDX(coeff, R);
+
+#else
+
+        out1 = __SMUSDX(R, coeff) >> 16u;
+        out2 = __SMUAD(coeff, R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+    i += n1;
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+  }                             // groups loop end 
+
+
+#else
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = pSrc[2 * i] - pSrc[2 * l];
+      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+      pSrc[2u * l] = xt;
+
+      pSrc[2u * l + 1u] = yt;
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+#endif //             #ifndef ARM_MATH_CM0
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q15_t in;
+  q31_t T, S, R;
+  q31_t coeff, out1, out2;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16u;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    i++;
+    l++;
+
+    T = _SIMD32_OFFSET(pSrc + (2 * i));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    S = _SIMD32_OFFSET(pSrc + (2 * l));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    R = __QSUB16(T, S);
+
+    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    out1 = __SMUSD(coeff, R) >> 16;
+    out2 = __SMUADX(coeff, R);
+#else
+
+    out1 = __SMUADX(R, coeff) >> 16u;
+    out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+    _SIMD32_OFFSET(pSrc + (2u * l)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16u;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        i += n1;
+
+        l = i + n2;
+
+        T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+        S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+        R = __QSUB16(T, S);
+
+        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(coeff, R) >> 16;
+        out2 = __SMUADX(coeff, R);
+#else
+
+        out1 = __SMUADX(R, coeff) >> 16u;
+        out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif //     #ifndef ARM_MATH_BIG_ENDIAN
+
+        _SIMD32_OFFSET(pSrc + (2u * l)) =
+          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+
+      T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+      S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+      R = __QSUB16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+      _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+#else
+
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q15_t xt, yt, cosVal, sinVal;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (j = 0; j < n2; j++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    // loop for butterfly 
+    for (i = j; i < fftLen; i += n1)
+    {
+      l = i + n2;
+      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+      pSrc[2 * i + 1] =
+        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+    }                           // butterfly loop end 
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+  }                             // groups loop end 
+
+
+#endif //             #ifndef ARM_MATH_CM0
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100644
index 0000000000..dd4b9e6b24
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,310 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix2_q31.c   
+*   
+* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.    
+ */
+
+
+/**   
+ * @addtogroup Radix2_CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the fixed-point CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+                                     S->pTwiddle, S->twidCoefModifier);
+  }
+  else
+  {
+    arm_radix2_butterfly_q31(pSrc, S->fftLen,
+                             S->pTwiddle, S->twidCoefModifier);
+  }
+
+  arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**   
+ * @} end of Radix2_CFFT_CIFFT group   
+ */
+
+void arm_radix2_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q31_t xt, yt, cosVal, sinVal;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+    xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+    pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+    yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+    pSrc[2 * i + 1] =
+      ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+    pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) +
+                    ((int32_t) (((q63_t) yt * sinVal) >> 32)));
+
+    pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) -
+                         ((int32_t) (((q63_t) xt * sinVal) >> 32)));
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) +
+                        ((int32_t) (((q63_t) yt * sinVal) >> 32)));
+
+        pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) -
+                             ((int32_t) (((q63_t) xt * sinVal) >> 32)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+    i += n1;
+    l = i + n2;
+
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+  }                             // butterfly loop end 
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  int i, j, k, l;
+  int n1, n2, ia;
+  q31_t xt, yt, cosVal, sinVal;
+
+  //N = fftLen; 
+  n2 = fftLen;
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  // loop for groups 
+  for (i = 0; i < n2; i++)
+  {
+    cosVal = pCoef[ia * 2];
+    sinVal = pCoef[(ia * 2) + 1];
+    ia = ia + twidCoefModifier;
+
+    l = i + n2;
+    xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+    pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+    yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+    pSrc[2 * i + 1] =
+      ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+    pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) -
+                    ((int32_t) (((q63_t) yt * sinVal) >> 32)));
+
+    pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) +
+                         ((int32_t) (((q63_t) xt * sinVal) >> 32)));
+
+  }                             // groups loop end 
+
+  twidCoefModifier = twidCoefModifier << 1u;
+
+  // loop for stage 
+  for (k = fftLen / 2; k > 2; k = k >> 1)
+  {
+    n1 = n2;
+    n2 = n2 >> 1;
+    ia = 0;
+
+    // loop for groups 
+    for (j = 0; j < n2; j++)
+    {
+      cosVal = pCoef[ia * 2];
+      sinVal = pCoef[(ia * 2) + 1];
+      ia = ia + twidCoefModifier;
+
+      // loop for butterfly 
+      for (i = j; i < fftLen; i += n1)
+      {
+        l = i + n2;
+        xt = pSrc[2 * i] - pSrc[2 * l];
+        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+        pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) -
+                        ((int32_t) (((q63_t) yt * sinVal) >> 32)));
+
+        pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) +
+                             ((int32_t) (((q63_t) xt * sinVal) >> 32)));
+
+      }                         // butterfly loop end 
+
+    }                           // groups loop end 
+
+    twidCoefModifier = twidCoefModifier << 1u;
+  }                             // stages loop end 
+
+  n1 = n2;
+  n2 = n2 >> 1;
+  ia = 0;
+
+  cosVal = pCoef[ia * 2];
+  sinVal = pCoef[(ia * 2) + 1];
+  ia = ia + twidCoefModifier;
+
+  // loop for butterfly 
+  for (i = 0; i < fftLen; i += n1)
+  {
+    l = i + n2;
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+    i += n1;
+    l = i + n2;
+
+    xt = pSrc[2 * i] - pSrc[2 * l];
+    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+    pSrc[2u * l] = xt;
+
+    pSrc[2u * l + 1u] = yt;
+
+  }                             // butterfly loop end 
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 0000000000..d51e9830bc
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1236 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_f32.c    
+*    
+* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @defgroup Radix4_CFFT_CIFFT Radix-4 Complex FFT Functions    
+ *    
+ * \par    
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).    
+ * Computational complexity of CFFT reduces drastically when compared to DFT.    
+ * \par    
+ * This set of functions implements CFFT/CIFFT    
+ * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.    
+ * Complex input is stored in input buffer in an interleaved fashion.    
+ *    
+ * \par    
+ * The functions operate on blocks of input and output data and each call to the function processes    
+ * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.    
+ * \par   
+ * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.    
+ * 
 {real[0], imag[0], real[1], imag[1],..} 
    
+ *    
+ * \par Lengths supported by the transform:   
+ * \par    
+ * Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm    
+ * and the size of the FFT supported are of the lengths [16, 64, 256, 1024].   
+ *     
+ *    
+ * \par Algorithm:    
+ *    
+ * Complex Fast Fourier Transform:    
+ * \par     
+ * Input real and imaginary data:    
+ * 
    
+ * x(n) = xa + j * ya    
+ * x(n+N/4 ) = xb + j * yb    
+ * x(n+N/2 ) = xc + j * yc    
+ * x(n+3N 4) = xd + j * yd    
+ * 
    
+ * where N is length of FFT    
+ * \par    
+ * Output real and imaginary data:    
+ * 
    
+ * X(4r) = xa'+ j * ya'    
+ * X(4r+1) = xb'+ j * yb'    
+ * X(4r+2) = xc'+ j * yc'    
+ * X(4r+3) = xd'+ j * yd'    
+ * 
    
+ * \par    
+ * Twiddle factors for radix-4 FFT:    
+ * 
    
+ * Wn = co1 + j * (- si1)    
+ * W2n = co2 + j * (- si2)    
+ * W3n = co3 + j * (- si3)    
+ * 
    
+ *    
+ * \par    
+ * \image html CFFT.gif "Radix-4 Decimation-in Frequency Complex Fast Fourier Transform"    
+ *    
+ * \par    
+ * Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.    
+ * \par    
+ *  Butterfly CFFT equations:    
+ * 
    
+ * xa' = xa + xb + xc + xd    
+ * ya' = ya + yb + yc + yd    
+ * xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+ * yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+ * xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+ * yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+ * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+ * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+ * 
    
+ *    
+ *    
+ * Complex Inverse Fast Fourier Transform:    
+ * \par    
+ * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.    
+ *    
+ * \par    
+ *  Modified Butterfly CIFFT equations:    
+ * 
    
+ * xa' = xa + xb + xc + xd    
+ * ya' = ya + yb + yc + yd    
+ * xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+ * yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+ * xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+ * yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+ * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+ * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+ * 
    
+ *    
+ * \par Instance Structure    
+ * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Initializes twiddle factor table and bit reversal table pointers    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Manually initialize the instance structure as follows:    
+ * 
    
+ *arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};    
+ *arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
+ *arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
+ * 
    
+ * \par    
+ * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);    
+ * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);     
+ * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.    
+ * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;     
+ * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.    
+ * onebyfftLen value of 1/fftLen to calculate CIFFT;    
+ *   
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.   
+ * @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.   
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
+ * @return none.   
+ */
+
+void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier, S->onebyfftLen);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
+
+
+/* ----------------------------------------------------------------------    
+** Internal helper function used by the FFTs    
+** ------------------------------------------------------------------- */
+
+/*    
+ * @brief  Core function for the floating-point CFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to the twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  float32_t co1, co2, co3, si1, si2, si3;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+  float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+    Ybminusd;
+  float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+  float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+  float32_t *ptr1;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    xaIn = pSrc[(2u * i0)];
+    yaIn = pSrc[(2u * i0) + 1u];
+
+    xcIn = pSrc[(2u * i2)];
+    ycIn = pSrc[(2u * i2) + 1u];
+
+    xbIn = pSrc[(2u * i1)];
+    ybIn = pSrc[(2u * i1) + 1u];
+
+    xdIn = pSrc[(2u * i3)];
+    ydIn = pSrc[(2u * i3) + 1u];
+
+    /* xa + xc */
+    Xaplusc = xaIn + xcIn;
+    /* xb + xd */
+    Xbplusd = xbIn + xdIn;
+    /* ya + yc */
+    Yaplusc = yaIn + ycIn;
+    /* yb + yd */
+    Ybplusd = ybIn + ydIn;
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xa - xc */
+    Xaminusc = xaIn - xcIn;
+    /* xb - xd */
+    Xbminusd = xbIn - xdIn;
+    /* ya - yc */
+    Yaminusc = yaIn - ycIn;
+    /* yb + yd */
+    Ybminusd = ybIn - ydIn;
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+    /* (xa - xc) + (yb - yd) */
+    Xb12C_out = (Xaminusc + Ybminusd);
+    /* (ya - yc) + (xb - xd) */
+    Yb12C_out = (Yaminusc - Xbminusd);
+    /* (xa + xc) - (xb + xd) */
+    Xc12C_out = (Xaplusc - Xbplusd);
+    /* (ya + yc) - (yb + yd) */
+    Yc12C_out = (Yaplusc - Ybplusd);
+    /* (xa - xc) - (yb - yd) */
+    Xd12C_out = (Xaminusc - Ybminusd);
+    /* (ya - yc) + (xb - xd) */
+    Yd12C_out = (Xbminusd + Yaminusc);
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    Xb12_out = Xb12C_out * co1;
+    Yb12_out = Yb12C_out * co1;
+    Xc12_out = Xc12C_out * co2;
+    Yc12_out = Yc12C_out * co2;
+    Xd12_out = Xd12C_out * co3;
+    Yd12_out = Yd12C_out * co3;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    Xb12_out += Yb12C_out * si1;
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    Yb12_out -= Xb12C_out * si1;
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    Xc12_out += Yc12C_out * si2;
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    Yc12_out -= Xc12C_out * si2;
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    Xd12_out += Yd12C_out * si3;
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    Yd12_out -= Xd12C_out * si3;
+
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = Xc12_out;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = Yc12_out;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = Xb12_out;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = Yb12_out;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = Xd12_out;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = Yd12_out;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        xaIn = pSrc[(2u * i0)];
+        yaIn = pSrc[(2u * i0) + 1u];
+
+        xbIn = pSrc[(2u * i1)];
+        ybIn = pSrc[(2u * i1) + 1u];
+
+        xcIn = pSrc[(2u * i2)];
+        ycIn = pSrc[(2u * i2) + 1u];
+
+        xdIn = pSrc[(2u * i3)];
+        ydIn = pSrc[(2u * i3) + 1u];
+
+        /* xa - xc */
+        Xaminusc = xaIn - xcIn;
+        /* (xb - xd) */
+        Xbminusd = xbIn - xdIn;
+        /* ya - yc */
+        Yaminusc = yaIn - ycIn;
+        /* (yb - yd) */
+        Ybminusd = ybIn - ydIn;
+
+        /* xa + xc */
+        Xaplusc = xaIn + xcIn;
+        /* xb + xd */
+        Xbplusd = xbIn + xdIn;
+        /* ya + yc */
+        Yaplusc = yaIn + ycIn;
+        /* yb + yd */
+        Ybplusd = ybIn + ydIn;
+
+        /* (xa - xc) + (yb - yd) */
+        Xb12C_out = (Xaminusc + Ybminusd);
+        /* (ya - yc) -  (xb - xd) */
+        Yb12C_out = (Yaminusc - Xbminusd);
+        /* xa + xc -(xb + xd) */
+        Xc12C_out = (Xaplusc - Xbplusd);
+        /* (ya + yc) - (yb + yd) */
+        Yc12C_out = (Yaplusc - Ybplusd);
+        /* (xa - xc) - (yb - yd) */
+        Xd12C_out = (Xaminusc - Ybminusd);
+        /* (ya - yc) +  (xb - xd) */
+        Yd12C_out = (Xbminusd + Yaminusc);
+
+        pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+        pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+        Xb12_out = Xb12C_out * co1;
+        Yb12_out = Yb12C_out * co1;
+        Xc12_out = Xc12C_out * co2;
+        Yc12_out = Yc12C_out * co2;
+        Xd12_out = Xd12C_out * co3;
+        Yd12_out = Yd12C_out * co3;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        Xb12_out += Yb12C_out * si1;
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        Yb12_out -= Xb12C_out * si1;
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        Xc12_out += Yc12C_out * si2;
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        Yc12_out -= Xc12C_out * si2;
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        Xd12_out += Yd12C_out * si3;
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        Yd12_out -= Xd12C_out * si3;
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = Xc12_out;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = Yc12_out;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = Xb12_out;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = Yb12_out;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = Xd12_out;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = Yd12_out;
+
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+
+    xaIn = ptr1[0];
+    xcIn = ptr1[4];
+    yaIn = ptr1[1];
+    ycIn = ptr1[5];
+
+    /* xa + xc */
+    Xaplusc = xaIn + xcIn;
+
+    xbIn = ptr1[2];
+
+    /* xa - xc */
+    Xaminusc = xaIn - xcIn;
+
+    xdIn = ptr1[6];
+
+    /* ya + yc */
+    Yaplusc = yaIn + ycIn;
+
+    ybIn = ptr1[3];
+
+    /* ya - yc */
+    Yaminusc = yaIn - ycIn;
+
+    ydIn = ptr1[7];
+
+    /* xb + xd */
+    Xbplusd = xbIn + xdIn;
+
+    /* yb + yd */
+    Ybplusd = ybIn + ydIn;
+
+    /* xa' = xa + xb + xc + xd */
+    ptr1[0] = (Xaplusc + Xbplusd);
+
+    /* (xb-xd) */
+    Xbminusd = xbIn - xdIn;
+
+    /* ya' = ya + yb + yc + yd */
+    ptr1[1] = (Yaplusc + Ybplusd);
+
+    /* (yb-yd) */
+    Ybminusd = ybIn - ydIn;
+
+    /* xc' = (xa-xb+xc-xd) */
+    ptr1[2] = (Xaplusc - Xbplusd);
+    /* yc' = (ya-yb+yc-yd) */
+    ptr1[3] = (Yaplusc - Ybplusd);
+    /* xb' = (xa+yb-xc-yd) */
+    ptr1[4] = (Xaminusc + Ybminusd);
+    /* yb' = (ya-xb-yc+xd) */
+    ptr1[5] = (Yaminusc - Xbminusd);
+    /* xd' = (xa-yb-xc+yd)) */
+    ptr1[6] = (Xaminusc - Ybminusd);
+    /* yd' = (ya+xb-yc-xd) */
+    ptr1[7] = (Xbminusd + Yaminusc);
+
+    /* increment pointer by 8 */
+    ptr1 = ptr1 + 8u;
+
+  } while(--j);
+
+#else
+
+  float32_t t1, t2, r1, r2, s1, s2;
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the fft calculation */
+  n2 = fftLen;
+  n1 = n2;
+  for (k = fftLen; k > 1u; k >>= 2u)
+  {
+    /*  Initializations for the fft calculation */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  FFT Calculation */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*    
+ * @brief  Core function for the floating-point CIFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @param[in]      onebyfftLen      value of 1/fftLen.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen)
+{
+  float32_t co1, co2, co3, si1, si2, si3;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+  float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+    Ybminusd;
+  float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+  float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+  float32_t *ptr1;
+
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    xaIn = pSrc[(2u * i0)];
+    yaIn = pSrc[(2u * i0) + 1u];
+
+    xcIn = pSrc[(2u * i2)];
+    ycIn = pSrc[(2u * i2) + 1u];
+
+    xbIn = pSrc[(2u * i1)];
+    ybIn = pSrc[(2u * i1) + 1u];
+
+    xdIn = pSrc[(2u * i3)];
+    ydIn = pSrc[(2u * i3) + 1u];
+
+    /* xa + xc */
+    Xaplusc = xaIn + xcIn;
+    /* xb + xd */
+    Xbplusd = xbIn + xdIn;
+    /* ya + yc */
+    Yaplusc = yaIn + ycIn;
+    /* yb + yd */
+    Ybplusd = ybIn + ydIn;
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xa - xc */
+    Xaminusc = xaIn - xcIn;
+    /* xb - xd */
+    Xbminusd = xbIn - xdIn;
+    /* ya - yc */
+    Yaminusc = yaIn - ycIn;
+    /* yb - yd */
+    Ybminusd = ybIn - ydIn;
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+    /* (xa - xc) - (yb - yd) */
+    Xb12C_out = (Xaminusc - Ybminusd);
+    /* (ya - yc) + (xb - xd) */
+    Yb12C_out = (Yaminusc + Xbminusd);
+    /* (xa + xc) - (xb + xd) */
+    Xc12C_out = (Xaplusc - Xbplusd);
+    /* (ya + yc) - (yb + yd) */
+    Yc12C_out = (Yaplusc - Ybplusd);
+    /* (xa - xc) + (yb - yd) */
+    Xd12C_out = (Xaminusc + Ybminusd);
+    /* (ya - yc) - (xb - xd) */
+    Yd12C_out = (Yaminusc - Xbminusd);
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    Xb12_out = Xb12C_out * co1;
+    Yb12_out = Yb12C_out * co1;
+    Xc12_out = Xc12C_out * co2;
+    Yc12_out = Yc12C_out * co2;
+    Xd12_out = Xd12C_out * co3;
+    Yd12_out = Yd12C_out * co3;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    Xb12_out -= Yb12C_out * si1;
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    Yb12_out += Xb12C_out * si1;
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    Xc12_out -= Yc12C_out * si2;
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    Yc12_out += Xc12C_out * si2;
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    Xd12_out -= Yd12C_out * si3;
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    Yd12_out += Xd12C_out * si3;
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = Xc12_out;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = Yc12_out;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = Xb12_out;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = Yb12_out;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = Xd12_out;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = Yd12_out;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        xaIn = pSrc[(2u * i0)];
+        yaIn = pSrc[(2u * i0) + 1u];
+
+        xbIn = pSrc[(2u * i1)];
+        ybIn = pSrc[(2u * i1) + 1u];
+
+        xcIn = pSrc[(2u * i2)];
+        ycIn = pSrc[(2u * i2) + 1u];
+
+        xdIn = pSrc[(2u * i3)];
+        ydIn = pSrc[(2u * i3) + 1u];
+
+        /* xa - xc */
+        Xaminusc = xaIn - xcIn;
+        /* (xb - xd) */
+        Xbminusd = xbIn - xdIn;
+        /* ya - yc */
+        Yaminusc = yaIn - ycIn;
+        /* (yb - yd) */
+        Ybminusd = ybIn - ydIn;
+
+        /* xa + xc */
+        Xaplusc = xaIn + xcIn;
+        /* xb + xd */
+        Xbplusd = xbIn + xdIn;
+        /* ya + yc */
+        Yaplusc = yaIn + ycIn;
+        /* yb + yd */
+        Ybplusd = ybIn + ydIn;
+
+        /* (xa - xc) - (yb - yd) */
+        Xb12C_out = (Xaminusc - Ybminusd);
+        /* (ya - yc) +  (xb - xd) */
+        Yb12C_out = (Yaminusc + Xbminusd);
+        /* xa + xc -(xb + xd) */
+        Xc12C_out = (Xaplusc - Xbplusd);
+        /* (ya + yc) - (yb + yd) */
+        Yc12C_out = (Yaplusc - Ybplusd);
+        /* (xa - xc) + (yb - yd) */
+        Xd12C_out = (Xaminusc + Ybminusd);
+        /* (ya - yc) -  (xb - xd) */
+        Yd12C_out = (Yaminusc - Xbminusd);
+
+        pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+        pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+        Xb12_out = Xb12C_out * co1;
+        Yb12_out = Yb12C_out * co1;
+        Xc12_out = Xc12C_out * co2;
+        Yc12_out = Yc12C_out * co2;
+        Xd12_out = Xd12C_out * co3;
+        Yd12_out = Yd12C_out * co3;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        Xb12_out -= Yb12C_out * si1;
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        Yb12_out += Xb12C_out * si1;
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        Xc12_out -= Yc12C_out * si2;
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        Yc12_out += Xc12C_out * si2;
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        Xd12_out -= Yd12C_out * si3;
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        Yd12_out += Xd12C_out * si3;
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = Xc12_out;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = Yc12_out;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = Xb12_out;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = Yb12_out;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = Xd12_out;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = Yd12_out;
+
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+  /*  Initializations of last stage */
+
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+
+    xaIn = ptr1[0];
+    xcIn = ptr1[4];
+    yaIn = ptr1[1];
+    ycIn = ptr1[5];
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    Xaplusc = xaIn + xcIn;
+
+    xbIn = ptr1[2];
+
+    /* xa - xc */
+    Xaminusc = xaIn - xcIn;
+
+    xdIn = ptr1[6];
+
+    /* ya + yc */
+    Yaplusc = yaIn + ycIn;
+
+    ybIn = ptr1[3];
+
+    /* ya - yc */
+    Yaminusc = yaIn - ycIn;
+
+    ydIn = ptr1[7];
+
+    /* xc + xd */
+    Xbplusd = xbIn + xdIn;
+
+    /* yb + yd */
+    Ybplusd = ybIn + ydIn;
+
+    /* xa' = xa + xb + xc + xd */
+    ptr1[0] = (Xaplusc + Xbplusd) * onebyfftLen;
+
+    /* (xb-xd) */
+    Xbminusd = xbIn - xdIn;
+
+    /* ya' = ya + yb + yc + yd */
+    ptr1[1] = (Yaplusc + Ybplusd) * onebyfftLen;
+
+    /* (yb-yd) */
+    Ybminusd = ybIn - ydIn;
+
+    /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+    ptr1[2] = (Xaplusc - Xbplusd) * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
+    ptr1[3] = (Yaplusc - Ybplusd) * onebyfftLen;
+
+    /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+    ptr1[4] = (Xaminusc - Ybminusd) * onebyfftLen;
+
+    /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+    ptr1[5] = (Yaminusc + Xbminusd) * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+    ptr1[6] = (Xaminusc + Ybminusd) * onebyfftLen;
+
+    /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+    ptr1[7] = (Yaminusc - Xbminusd) * onebyfftLen;
+
+    /* increment source pointer by 8 for next calculations */
+    ptr1 = ptr1 + 8u;
+
+  } while(--j);
+
+#else
+
+  float32_t t1, t2, r1, r2, s1, s2;
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /*  Calculation of first stage */
+  for (k = fftLen; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 0000000000..f354e1dde1
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_f32.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+/**    
+* @brief  Initialization function for the floating-point CFFT/CIFFT.   
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 0000000000..5ace3483d8
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_q15.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+
+/**    
+* @brief Initialization function for the Q15 CFFT/CIFFT.   
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoefQ15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 0000000000..6614994f74
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_init_q31.c    
+*    
+* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+/**    
+*    
+* @brief  Initialization function for the Q31 CFFT/CIFFT.   
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
+* @param[in]     fftLen         length of the FFT.   
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
+*    
+* \par Description:   
+* \par    
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
+* \par    
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
+* \par    
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoefQ31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 0000000000..01d476e6c4
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1896 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_q15.c    
+*    
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
+*				In-place bit reversal using bit reversal table    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+
+/**    
+ * @details    
+ * @brief Processing function for the Q15 CFFT/CIFFT.   
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.   
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.   
+ * @return none.   
+ *     
+ * \par Input and output formats:    
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different FFT sizes.    
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
+ * \par   
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"    
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"    
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
+
+/*    
+* Radix-4 FFT algorithm used is :    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 FFT:    
+* Wn = co1 + j * (- si1)    
+* W2n = co2 + j * (- si2)    
+* W3n = co3 + j * (- si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+*    
+*/
+
+/**    
+ * @brief  Core function for the Q15 CFFT butterfly process.   
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  q15_t *ptr1;
+
+
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16u;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16u;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16u;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16u;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while(--j);
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2u] >> 2;
+    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2u] >> 2;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * (ic * 2u)];
+    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * (ic * 2u)];
+      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+      Co3 = pCoef16[3u * (ic * 2u)];
+      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        pSrc16[i0 * 2u] = out1;
+        pSrc16[(2u * i0) + 1u] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1u) - (T1 >> 1u);
+        R1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1u) + (T1 >> 1u);
+        S1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**    
+ * @brief  Core function for the Q15 CIFFT butterfly process.   
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+/*    
+* Radix-4 IFFT algorithm used is :    
+*    
+* CIFFT uses same twiddle coefficients as CFFT function    
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
+*    
+*    
+* IFFT is implemented with following changes in equations from FFT    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 IFFT:    
+* Wn = co1 + j * (si1)    
+* W2n = co2 + j * (si2)    
+* W3n = co3 + j * (si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+*    
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  q15_t *ptr1;
+
+
+
+  q31_t xaya, xbyb, xcyc, xdyd;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yc (real), xc(imag) input */
+    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* Read yd (real), xd(imag) input */
+    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+        /* Read yc (real), xc(imag) input */
+        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16u;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16u;
+        out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16u;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16u;
+        out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+
+  ptr1 = &pSrc16[0];
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  do
+  {
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD32(ptr1)++;
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD32(ptr1)++;
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD32(ptr1)++;
+
+    /* Read xd (real), yd(imag) input */
+    xdyd = *__SIMD32(ptr1)++;
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(xaya, xcyc);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(xbyb, xdyd);
+
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(xaya, xcyc);
+
+    /* Read yd (real), xd(imag) input */
+    /* T = packed( (yb - yd), (xb - xd))  */
+    U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  } while(--j);
+
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1u];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1u] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1u];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1u] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * ic * 2u];
+    Si3 = pCoef16[(3u * ic * 2u) + 1u];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1u] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * ic * 2u];
+      Si2 = pCoef16[2u * ic * 2u + 1u];
+      Co3 = pCoef16[3u * ic * 2u];
+      Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16u);
+        R1 = __SSAT(T1 + S1, 16u);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16u);
+        S1 = __SSAT(T1 - S1, 16u);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16u);
+        T1 = __SSAT(T1 + U1, 16u);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16u);
+        T1 = __SSAT(T1 - U1, 16u);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1u) + (T1 >> 1u);
+        R1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1u) - (T1 >> 1u);
+        S1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 0000000000..3a5c523dff
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,891 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_cfft_radix4_q31.c    
+*    
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
+*				In-place bit reversal using bit reversal table    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.5  2010/04/26     
+* 	 incorporated review comments and updated with latest CMSIS layer    
+*    
+* Version 0.0.3  2010/03/10     
+*    Initial version    
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup Radix4_CFFT_CIFFT    
+ * @{    
+ */
+
+/**    
+ * @details    
+ * @brief Processing function for the Q31 CFFT/CIFFT.    
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.   
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
+ * @return none.    
+ *     
+ * \par Input and output formats:    
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different FFT sizes.    
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
+ * \par   
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"    
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"    
+ *    
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**    
+ * @} end of Radix4_CFFT_CIFFT group    
+ */
+
+/*    
+* Radix-4 FFT algorithm used is :    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 FFT:    
+* Wn = co1 + j * (- si1)    
+* W2n = co2 + j * (- si2)    
+* W3n = co3 + j * (- si3)    
+*    
+*  Butterfly implementation:    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+*    
+*/
+
+/**    
+ * @brief  Core function for the Q31 CFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa + yb - xc - yd);
+    yb_out = (ya - xb - yc + xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa - yb - xc + yd);
+    yd_out = (ya + xb - yc - xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+
+  } while(--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**    
+ * @brief  Core function for the Q31 CIFFT butterfly process.   
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
+ * @param[in]      fftLen           length of the FFT.   
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.   
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+
+/*    
+* Radix-4 IFFT algorithm used is :    
+*    
+* CIFFT uses same twiddle coefficients as CFFT Function    
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
+*    
+*    
+* IFFT is implemented with following changes in equations from FFT    
+*    
+* Input real and imaginary data:    
+* x(n) = xa + j * ya    
+* x(n+N/4 ) = xb + j * yb    
+* x(n+N/2 ) = xc + j * yc    
+* x(n+3N 4) = xd + j * yd    
+*    
+*    
+* Output real and imaginary data:    
+* x(4r) = xa'+ j * ya'    
+* x(4r+1) = xb'+ j * yb'    
+* x(4r+2) = xc'+ j * yc'    
+* x(4r+3) = xd'+ j * yd'    
+*    
+*    
+* Twiddle factors for radix-4 IFFT:    
+* Wn = co1 + j * (si1)    
+* W2n = co2 + j * (si2)    
+* W3n = co3 + j * (si3)    
+    
+* The real and imaginary output values for the radix-4 butterfly are    
+* xa' = xa + xb + xc + xd    
+* ya' = ya + yb + yc + yd    
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+*    
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+  q31_t xa, xb, xc, xd;
+  q31_t ya, yb, yc, yd;
+  q31_t xa_out, xb_out, xc_out, xd_out;
+  q31_t ya_out, yb_out, yc_out, yd_out;
+
+  q31_t *ptr1;
+  q63_t xaya, xbyb, xcyc, xdyd;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  j = fftLen >> 2;
+  ptr1 = &pSrc[0];
+
+  /*  Calculations of last stage */
+  do
+  {
+#ifndef ARM_MATH_BIG_ENDIAN
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    xa = (q31_t) xaya;
+    ya = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    xb = (q31_t) xbyb;
+    yb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    xc = (q31_t) xcyc;
+    yc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    xd = (q31_t) xdyd;
+    yd = (q31_t) (xdyd >> 32);
+
+#else
+
+    /* Read xa (real), ya(imag) input */
+    xaya = *__SIMD64(ptr1)++;
+    ya = (q31_t) xaya;
+    xa = (q31_t) (xaya >> 32);
+
+    /* Read xb (real), yb(imag) input */
+    xbyb = *__SIMD64(ptr1)++;
+    yb = (q31_t) xbyb;
+    xb = (q31_t) (xbyb >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xcyc = *__SIMD64(ptr1)++;
+    yc = (q31_t) xcyc;
+    xc = (q31_t) (xcyc >> 32);
+
+    /* Read xc (real), yc(imag) input */
+    xdyd = *__SIMD64(ptr1)++;
+    yd = (q31_t) xdyd;
+    xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+    /* xa' = xa + xb + xc + xd */
+    xa_out = xa + xb + xc + xd;
+
+    /* ya' = ya + yb + yc + yd */
+    ya_out = ya + yb + yc + yd;
+
+    /* pointer updation for writing */
+    ptr1 = ptr1 - 8u;
+
+    /* writing xa' and ya' */
+    *ptr1++ = xa_out;
+    *ptr1++ = ya_out;
+
+    xc_out = (xa - xb + xc - xd);
+    yc_out = (ya - yb + yc - yd);
+
+    /* writing xc' and yc' */
+    *ptr1++ = xc_out;
+    *ptr1++ = yc_out;
+
+    xb_out = (xa - yb - xc + yd);
+    yb_out = (ya + xb - yc - xd);
+
+    /* writing xb' and yb' */
+    *ptr1++ = xb_out;
+    *ptr1++ = yb_out;
+
+    xd_out = (xa + yb - xc - yd);
+    yd_out = (ya - xb - yc + xd);
+
+    /* writing xd' and yd' */
+    *ptr1++ = xd_out;
+    *ptr1++ = yd_out;
+
+
+  } while(--j);
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 0000000000..fb79e31726
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_f32.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 F32.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions    
+ * Representation of signals by minimum number of values is important for storage and transmission.    
+ * The possibility of large discontinuity between the beginning and end of a period of a signal    
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.    
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the    
+ * spectrum and is very widely used in signal and image coding applications.    
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.    
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.    
+ *    
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.    
+ * Reordering of the input data makes the computation of DCT just a problem of    
+ * computing the DFT of a real signal with a few additional operations.    
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.    
+ *     
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.    
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.    
+ * DCT2 implementation can be described in the following steps:    
+ * - Re-ordering input    
+ * - Calculating Real FFT    
+ * - Multiplication of weights and Real FFT output and getting real part from the product.    
+ *    
+ * This process is explained by the block diagram below:    
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"    
+ *    
+ * \par Algorithm:    
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:    
+ * \image html DCT4Equation.gif    
+ * where k = 0,1,2,.....N-1    
+ *\par    
+ * Its inverse is defined as follows:    
+ * \image html IDCT4Equation.gif    
+ * where n = 0,1,2,.....N-1    
+ *\par    
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).    
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward    
+ * and inverse transform computation are identical.    
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.    
+ *    
+ * \par Lengths supported by the transform:    
+ *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().    
+ * The library provides separate functions for Q15, Q31, and floating-point data types.    
+ * \par Instance Structure    
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.    
+ * A separate instance structure must be defined for each transform.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().    
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Manually initialize the instance structure as follows:    
+ * 
    
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ * 
   
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;   
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);    
+ * \c pTwiddle points to the twiddle factor table;   
+ * \c pCosFactor points to the cosFactor table;   
+ * \c pRfft points to the real FFT instance;   
+ * \c pCfft points to the complex FFT instance;   
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()   
+ * and arm_rfft_f32() respectively for details regarding static initialization.   
+ *   
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.    
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+ /**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as,    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------    
+	 *  Step3: Multiply the FFT output with the weights.    
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------    
+	 *  Step3: Multiply the FFT output with the weights.    
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 0000000000..b5f91ea325
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16511 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_f32.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 F32    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
+* \par    
+* C command to generate the table    
+* 
    
+* for(i = 0; i< N; i++)    
+* {    
+*    weights[2*i]= cos(i*c);    
+*    weights[(2*i)+1]= -sin(i * c);    
+* } 
    
+* \par    
+* Where N is the Number of weights to be calculated and c is pi/(2*N)    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is 2*N.    
+*/
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
+  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+  -0.082740264549375692f,
+  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+  -0.088853552582524600f,
+  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
+  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+  -0.113270952177564350f,
+  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+  -0.119365214810991350f,
+  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+  -0.125454983411546230f,
+  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+  -0.131540028702883120f,
+  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+  -0.137620121586486040f,
+  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+  -0.143695033150294470f,
+  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+  -0.149764534677321510f,
+  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+  -0.155828397654265230f,
+  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+  -0.161886393780111830f,
+  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+  -0.167938294974731170f,
+  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+  -0.173983873387463820f,
+  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+  -0.180022901405699510f,
+  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+  -0.186055151663446630f,
+  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+  -0.192080397049892440f,
+  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+  -0.198098410717953560f,
+  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+  -0.204108966092816870f,
+  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+  -0.210111836880469610f,
+  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+  -0.216106797076219520f,
+  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+  -0.222093620973203510f,
+  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+  -0.228072083170885730f,
+  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+  -0.234041958583543430f,
+  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+  -0.240003022448741500f,
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+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
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+  -0.003834942569706228f,
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+  -0.005368906963996343f,
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+  -0.006902858724729756f,
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+  -0.008436794242369799f,
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+  -0.009970709907418031f,
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+  -0.011504602110422714f,
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+  -0.013038467241987334f,
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+  -0.014572301692779064f,
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+  -0.999999705862882230f
+};
+
+static const float32_t Weights_8192[16384] = {
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+    -0.014380574187649006,
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+    -0.014764028662127246,
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+    -0.015147480965280987,
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+    -0.015530931040716447,
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+  0.029524838936943035, -0.999564046915327740, 0.029333174389816984,
+    -0.999569689856698580,
+  0.029141508764193740, -0.999575296046749220, 0.028949842067120746,
+    -0.999580865485273700,
+  0.028758174305644590, -0.999586398172067070, 0.028566505486812797,
+    -0.999591894106925950,
+  0.028374835617672258, -0.999597353289648380, 0.028183164705269902,
+    -0.999602775720033530,
+  0.027991492756653365, -0.999608161397882110, 0.027799819778869434,
+    -0.999613510322995950,
+  0.027608145778965820, -0.999618822495178640, 0.027416470763989606,
+    -0.999624097914234570,
+  0.027224794740987910, -0.999629336579970110, 0.027033117717008563,
+    -0.999634538492192300,
+  0.026841439699098527, -0.999639703650710200, 0.026649760694305708,
+    -0.999644832055333610,
+  0.026458080709677145, -0.999649923705874240, 0.026266399752260809,
+    -0.999654978602144690,
+  0.026074717829104040, -0.999659996743959220, 0.025883034947254208,
+    -0.999664978131133310,
+  0.025691351113759395, -0.999669922763483760, 0.025499666335666818,
+    -0.999674830640828740,
+  0.025307980620024630, -0.999679701762987930, 0.025116293973880335,
+    -0.999684536129782140,
+  0.024924606404281485, -0.999689333741033640, 0.024732917918276334,
+    -0.999694094596566000,
+  0.024541228522912264, -0.999698818696204250, 0.024349538225237600,
+    -0.999703506039774650,
+  0.024157847032300020, -0.999708156627104880, 0.023966154951147241,
+    -0.999712770458023870,
+  0.023774461988827676, -0.999717347532362190, 0.023582768152388880,
+    -0.999721887849951310,
+  0.023391073448879338, -0.999726391410624470, 0.023199377885346890,
+    -0.999730858214216030,
+  0.023007681468839410, -0.999735288260561680, 0.022815984206405477,
+    -0.999739681549498660,
+  0.022624286105092803, -0.999744038080865430, 0.022432587171950024,
+    -0.999748357854501780,
+  0.022240887414024919, -0.999752640870248840, 0.022049186838366180,
+    -0.999756887127949080,
+  0.021857485452021874, -0.999761096627446610, 0.021665783262040089,
+    -0.999765269368586450,
+  0.021474080275469605, -0.999769405351215280, 0.021282376499358355,
+    -0.999773504575180990,
+  0.021090671940755180, -0.999777567040332940, 0.020898966606708289,
+    -0.999781592746521670,
+  0.020707260504265912, -0.999785581693599210, 0.020515553640476986,
+    -0.999789533881418780,
+  0.020323846022389572, -0.999793449309835270, 0.020132137657052664,
+    -0.999797327978704690,
+  0.019940428551514598, -0.999801169887884260, 0.019748718712823757,
+    -0.999804975037232870,
+  0.019557008148029204, -0.999808743426610520, 0.019365296864179146,
+    -0.999812475055878780,
+  0.019173584868322699, -0.999816169924900410, 0.018981872167508348,
+    -0.999819828033539420,
+  0.018790158768784596, -0.999823449381661570, 0.018598444679200642,
+    -0.999827033969133420,
+  0.018406729905804820, -0.999830581795823400, 0.018215014455646376,
+    -0.999834092861600960,
+  0.018023298335773701, -0.999837567166337090, 0.017831581553236088,
+    -0.999841004709904000,
+  0.017639864115082195, -0.999844405492175240, 0.017448146028360704,
+    -0.999847769513025900,
+  0.017256427300120978, -0.999851096772332190, 0.017064707937411529,
+    -0.999854387269971890,
+  0.016872987947281773, -0.999857641005823860, 0.016681267336780482,
+    -0.999860857979768540,
+  0.016489546112956454, -0.999864038191687680, 0.016297824282859176,
+    -0.999867181641464380,
+  0.016106101853537263, -0.999870288328982950, 0.015914378832040249,
+    -0.999873358254129260,
+  0.015722655225417017, -0.999876391416790410, 0.015530931040716478,
+    -0.999879387816854930,
+  0.015339206284988220, -0.999882347454212560, 0.015147480965280975,
+    -0.999885270328754520,
+  0.014955755088644378, -0.999888156440373320, 0.014764028662127416,
+    -0.999891005788962950,
+  0.014572301692779104, -0.999893818374418490, 0.014380574187649138,
+    -0.999896594196636680,
+  0.014188846153786343, -0.999899333255515390, 0.013997117598240459,
+    -0.999902035550953920,
+  0.013805388528060349, -0.999904701082852900, 0.013613658950295789,
+    -0.999907329851114300,
+  0.013421928871995907, -0.999909921855641540, 0.013230198300209845,
+    -0.999912477096339240,
+  0.013038467241987433, -0.999914995573113470, 0.012846735704377631,
+    -0.999917477285871770,
+  0.012655003694430301, -0.999919922234522750, 0.012463271219194662,
+    -0.999922330418976490,
+  0.012271538285719944, -0.999924701839144500, 0.012079804901056066,
+    -0.999927036494939640,
+  0.011888071072252072, -0.999929334386276070, 0.011696336806357907,
+    -0.999931595513069200,
+  0.011504602110422875, -0.999933819875236000, 0.011312866991496287,
+    -0.999936007472694620,
+  0.011121131456628141, -0.999938158305364590, 0.010929395512867561,
+    -0.999940272373166960,
+  0.010737659167264572, -0.999942349676023910, 0.010545922426868548,
+    -0.999944390213859060,
+  0.010354185298728884, -0.999946393986597460, 0.010162447789895645,
+    -0.999948360994165400,
+  0.009970709907418029, -0.999950291236490480, 0.009778971658346134,
+    -0.999952184713501780,
+  0.009587233049729183, -0.999954041425129780, 0.009395494088617302,
+    -0.999955861371306100,
+  0.009203754782059960, -0.999957644551963900, 0.009012015137106642,
+    -0.999959390967037450,
+  0.008820275160807512, -0.999961100616462820, 0.008628534860211857,
+    -0.999962773500176930,
+  0.008436794242369860, -0.999964409618118280, 0.008245053314331058,
+    -0.999966008970226920,
+  0.008053312083144991, -0.999967571556443780, 0.007861570555861883,
+    -0.999969097376711580,
+  0.007669828739531077, -0.999970586430974140, 0.007478086641202815,
+    -0.999972038719176730,
+  0.007286344267926684, -0.999973454241265940, 0.007094601626752279,
+    -0.999974832997189810,
+  0.006902858724729877, -0.999976174986897610, 0.006711115568908869,
+    -0.999977480210339940,
+  0.006519372166339549, -0.999978748667468830, 0.006327628524071549,
+    -0.999979980358237650,
+  0.006135884649154515, -0.999981175282601110, 0.005944140548638765,
+    -0.999982333440515350,
+  0.005752396229573737, -0.999983454831937730, 0.005560651699009764,
+    -0.999984539456826970,
+  0.005368906963996303, -0.999985587315143200, 0.005177162031583702,
+    -0.999986598406848000,
+  0.004985416908821652, -0.999987572731904080, 0.004793671602759852,
+    -0.999988510290275690,
+  0.004601926120448672, -0.999989411081928400, 0.004410180468937601,
+    -0.999990275106828920,
+  0.004218434655277024, -0.999991102364945590, 0.004026688686516664,
+    -0.999991892856248010,
+  0.003834942569706248, -0.999992646580707190, 0.003643196311896179,
+    -0.999993363538295150,
+  0.003451449920135975, -0.999994043728985820, 0.003259703401476044,
+    -0.999994687152754080,
+  0.003067956762966138, -0.999995293809576190, 0.002876210011656010,
+    -0.999995863699429940,
+  0.002684463154596083, -0.999996396822294350, 0.002492716198835898,
+    -0.999996893178149880,
+  0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
+    -0.999997775588762350,
+  0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
+    -0.999998510931137790,
+  0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
+    -0.999999099205167830,
+  0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
+    -0.999999540410766110,
+  0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
+    -0.999999834547867670,
+  0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
+    -0.999999981616429330,
+
+};
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
+* \par    
+* C command to generate the table    
+* \par    
+* 
 for(i = 0; i< N; i++)    
+* {    
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } 
    
+* \par    
+* where N is the number of factors to generate and c is pi/(2*N)    
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
+  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
+  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
+  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+  0.996850783822196610f,
+  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+  0.996602803001684130f,
+  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+  0.996345441776035900f,
+  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+  0.996078702567633980f,
+  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+  0.995802587887129160f,
+  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+  0.995517100333418110f,
+  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+  0.995222242593618360f,
+  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+  0.994918017443043200f,
+  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+  0.994604427745175660f,
+  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+  0.994281476451641550f,
+  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+  0.993949166602181130f,
+  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+  0.993607501324621610f,
+  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+  0.993256483834846440f,
+  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+  0.992896117436765980f,
+  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+  0.992526405522286100f,
+  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+  0.992147351571276090f,
+  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+  0.991758959151536110f,
+  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+  0.991361231918763460f,
+  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+  0.990954173616518500f,
+  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+  0.990537788076188750f,
+  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+  0.990112079216953770f,
+  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+  0.989677051045747210f,
+  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+  0.989232707657220050f,
+  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+  0.988779053233701520f,
+  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+  0.988316092045159690f,
+  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+  0.987843828449161740f,
+  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+  0.987362266890832400f,
+  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+  0.986871411902812470f,
+  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+  0.986371268105216030f,
+  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+  0.985861840205586980f,
+  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+  0.985343132998854790f,
+  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+  0.984815151367289140f,
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+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+  1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
+    1.999999549602533100,
+  1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
+    1.999997931848645600,
+  1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
+    1.999995137547503600,
+  1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
+    1.999991166700750800,
+  1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
+    1.999986019310723500,
+  1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
+    1.999979695380449400,
+  1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
+    1.999972194913648900,
+  1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
+    1.999963517914734100,
+  1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
+    1.999953664388809800,
+  1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
+    1.999942634341672600,
+  1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
+    1.999930427779810900,
+  1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
+    1.999917044710405500,
+  1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
+    1.999902485141329400,
+  1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
+    1.999886749081147800,
+  1.999882631240436700, 1.999878439869758200, 1.999874174969266300,
+    1.999869836539117700,
+  1.999865424579472000, 1.999860939090491600, 1.999856380072341000,
+    1.999851747525188200,
+  1.999847041449203300, 1.999842261844559700, 1.999837408711432600,
+    1.999832482050000900,
+  1.999827481860445300, 1.999822408142949900, 1.999817260897701400,
+    1.999812040124888700,
+  1.999806745824704000, 1.999801377997341800, 1.999795936642999600,
+    1.999790421761877400,
+  1.999784833354177900, 1.999779171420106700, 1.999773435959872000,
+    1.999767626973684400,
+  1.999761744461757700, 1.999755788424308200, 1.999749758861554900,
+    1.999743655773719400,
+  1.999737479161026100, 1.999731229023702200, 1.999724905361977200,
+    1.999718508176084000,
+  1.999712037466257600, 1.999705493232735800, 1.999698875475759600,
+    1.999692184195571900,
+  1.999685419392419000, 1.999678581066549400, 1.999671669218214600,
+    1.999664683847668800,
+  1.999657624955168700, 1.999650492540973900, 1.999643286605346800,
+    1.999636007148552400,
+  1.999628654170857900, 1.999621227672533800, 1.999613727653853500,
+    1.999606154115092500,
+  1.999598507056529000, 1.999590786478444600, 1.999582992381123000,
+    1.999575124764850800,
+  1.999567183629917100, 1.999559168976613900, 1.999551080805236100,
+    1.999542919116081000,
+  1.999534683909448600, 1.999526375185641800, 1.999517992944965800,
+    1.999509537187729200,
+  1.999501007914242600, 1.999492405124819700, 1.999483728819776900,
+    1.999474978999432800,
+  1.999466155664109600, 1.999457258814131500, 1.999448288449825500,
+    1.999439244571521700,
+  1.999430127179552500, 1.999420936274252800, 1.999411671855960900,
+    1.999402333925017300,
+  1.999392922481765500, 1.999383437526551300, 1.999373879059723500,
+    1.999364247081633500,
+  1.999354541592635500, 1.999344762593086500, 1.999334910083345700,
+    1.999324984063775700,
+  1.999314984534741100, 1.999304911496609700, 1.999294764949752100,
+    1.999284544894541100,
+  1.999274251331352400, 1.999263884260564600, 1.999253443682558900,
+    1.999242929597719200,
+  1.999232342006432000, 1.999221680909086400, 1.999210946306074500,
+    1.999200138197791100,
+  1.999189256584633600, 1.999178301467001900, 1.999167272845298900,
+    1.999156170719930100,
+  1.999144995091303600, 1.999133745959830600, 1.999122423325924200,
+    1.999111027190001000,
+  1.999099557552479900, 1.999088014413782800, 1.999076397774334000,
+    1.999064707634560700,
+  1.999052943994892300, 1.999041106855761900, 1.999029196217604100,
+    1.999017212080857400,
+  1.999005154445962200, 1.998993023313361700, 1.998980818683502100,
+    1.998968540556831800,
+  1.998956188933802800, 1.998943763814868800, 1.998931265200486900,
+    1.998918693091116200,
+  1.998906047487219600, 1.998893328389261400, 1.998880535797709700,
+    1.998867669713034500,
+  1.998854730135709400, 1.998841717066209400, 1.998828630505013400,
+    1.998815470452602400,
+  1.998802236909460500, 1.998788929876074100, 1.998775549352932400,
+    1.998762095340527400,
+  1.998748567839354000, 1.998734966849909000, 1.998721292372693100,
+    1.998707544408208700,
+  1.998693722956961500, 1.998679828019459300, 1.998665859596213500,
+    1.998651817687737300,
+  1.998637702294547000, 1.998623513417161700, 1.998609251056103100,
+    1.998594915211895600,
+  1.998580505885066100, 1.998566023076144600, 1.998551466785663400,
+    1.998536837014157900,
+  1.998522133762165900, 1.998507357030227900, 1.998492506818887200,
+    1.998477583128690100,
+  1.998462585960185000, 1.998447515313923400, 1.998432371190459500,
+    1.998417153590349900,
+  1.998401862514154200, 1.998386497962434800, 1.998371059935756300,
+    1.998355548434686400,
+  1.998339963459795400, 1.998324305011656600, 1.998308573090845200,
+    1.998292767697940100,
+  1.998276888833522300, 1.998260936498175400, 1.998244910692486000,
+    1.998228811417043700,
+  1.998212638672439900, 1.998196392459269400, 1.998180072778129600,
+    1.998163679629620500,
+  1.998147213014344900, 1.998130672932908000, 1.998114059385918400,
+    1.998097372373986300,
+  1.998080611897725700, 1.998063777957752600, 1.998046870554686100,
+    1.998029889689147700,
+  1.998012835361761900, 1.997995707573155600, 1.997978506323958600,
+    1.997961231614803200,
+  1.997943883446324800, 1.997926461819161000, 1.997908966733952500,
+    1.997891398191342400,
+  1.997873756191977000, 1.997856040736504500, 1.997838251825576400,
+    1.997820389459846700,
+  1.997802453639972300, 1.997784444366612600, 1.997766361640429800,
+    1.997748205462088500,
+  1.997729975832256600, 1.997711672751604200, 1.997693296220804000,
+    1.997674846240532000,
+  1.997656322811466500, 1.997637725934288300, 1.997619055609681600,
+    1.997600311838332500,
+  1.997581494620930300, 1.997562603958166600, 1.997543639850736200,
+    1.997524602299336500,
+  1.997505491304667000, 1.997486306867430900, 1.997467048988333000,
+    1.997447717668082000,
+  1.997428312907388200, 1.997408834706965000, 1.997389283067528800,
+    1.997369657989798400,
+  1.997349959474495200, 1.997330187522343700, 1.997310342134070800,
+    1.997290423310406100,
+  1.997270431052081900, 1.997250365359833200, 1.997230226234397900,
+    1.997210013676516700,
+  1.997189727686932400, 1.997169368266390900, 1.997148935415640600,
+    1.997128429135433400,
+  1.997107849426522600, 1.997087196289665000, 1.997066469725620200,
+    1.997045669735150000,
+  1.997024796319019300, 1.997003849477995600, 1.996982829212848900,
+    1.996961735524351900,
+  1.996940568413280600, 1.996919327880412900, 1.996898013926530000,
+    1.996876626552415400,
+  1.996855165758855600, 1.996833631546639300, 1.996812023916558800,
+    1.996790342869408000,
+  1.996768588405984300, 1.996746760527087700, 1.996724859233520500,
+    1.996702884526087900,
+  1.996680836405598100, 1.996658714872861800, 1.996636519928692000,
+    1.996614251573904900,
+  1.996591909809319400, 1.996569494635756600, 1.996547006054041100,
+    1.996524444064999400,
+  1.996501808669461000, 1.996479099868258400, 1.996456317662226300,
+    1.996433462052202600,
+  1.996410533039027400, 1.996387530623543900, 1.996364454806597500,
+    1.996341305589037100,
+  1.996318082971713500, 1.996294786955480800, 1.996271417541195300,
+    1.996247974729716200,
+  1.996224458521905600, 1.996200868918628100, 1.996177205920750800,
+    1.996153469529144100,
+  1.996129659744680300, 1.996105776568235100, 1.996081820000686500,
+    1.996057790042915500,
+  1.996033686695805300, 1.996009509960242400, 1.995985259837115500,
+    1.995960936327316300,
+  1.995936539431739000, 1.995912069151280800, 1.995887525486841300,
+    1.995862908439323100,
+  1.995838218009630800, 1.995813454198672700, 1.995788617007359100,
+    1.995763706436603200,
+  1.995738722487320600, 1.995713665160430600, 1.995688534456853800,
+    1.995663330377514400,
+  1.995638052923339300, 1.995612702095257400, 1.995587277894201400,
+    1.995561780321105600,
+  1.995536209376907600, 1.995510565062547800, 1.995484847378968600,
+    1.995459056327116000,
+  1.995433191907938000, 1.995407254122385700, 1.995381242971412600,
+    1.995355158455975200,
+  1.995329000577032800, 1.995302769335546500, 1.995276464732481200,
+    1.995250086768804100,
+  1.995223635445484900, 1.995197110763496000, 1.995170512723813100,
+    1.995143841327413400,
+  1.995117096575278200, 1.995090278468390600, 1.995063387007736600,
+    1.995036422194304700,
+  1.995009384029086800, 1.994982272513076600, 1.994955087647271000,
+    1.994927829432669800,
+  1.994900497870274900, 1.994873092961091200, 1.994845614706126400,
+    1.994818063106391000,
+  1.994790438162897600, 1.994762739876662100, 1.994734968248702800,
+    1.994707123280041100,
+  1.994679204971700100, 1.994651213324707000, 1.994623148340090700,
+    1.994595010018883000,
+  1.994566798362118300, 1.994538513370834200, 1.994510155046070700,
+    1.994481723388870100,
+  1.994453218400277900, 1.994424640081342100, 1.994395988433113700,
+    1.994367263456646100,
+  1.994338465152995000, 1.994309593523219600, 1.994280648568381500,
+    1.994251630289544600,
+  1.994222538687776100, 1.994193373764145500, 1.994164135519725000,
+    1.994134823955589800,
+  1.994105439072817700, 1.994075980872488800, 1.994046449355686200,
+    1.994016844523496000,
+  1.993987166377006600, 1.993957414917308700, 1.993927590145496900,
+    1.993897692062667200,
+  1.993867720669919400, 1.993837675968354700, 1.993807557959078600,
+    1.993777366643197900,
+  1.993747102021822900, 1.993716764096066200, 1.993686352867043200,
+    1.993655868335872300,
+  1.993625310503674100, 1.993594679371572200, 1.993563974940692800,
+    1.993533197212164800,
+  1.993502346187119700, 1.993471421866692200, 1.993440424252018900,
+    1.993409353344239600,
+  1.993378209144496700, 1.993346991653935300, 1.993315700873703200,
+    1.993284336804950900,
+  1.993252899448831400, 1.993221388806500900, 1.993189804879117500,
+    1.993158147667842800,
+  1.993126417173840500, 1.993094613398277400, 1.993062736342323000,
+    1.993030786007148800,
+  1.992998762393930000, 1.992966665503844000, 1.992934495338070800,
+    1.992902251897793000,
+  1.992869935184196300, 1.992837545198469000, 1.992805081941801700,
+    1.992772545415388200,
+  1.992739935620424700, 1.992707252558110200, 1.992674496229646500,
+    1.992641666636237700,
+  1.992608763779091000, 1.992575787659416100, 1.992542738278425300,
+    1.992509615637334100,
+  1.992476419737359900, 1.992443150579723500, 1.992409808165648100,
+    1.992376392496359300,
+  1.992342903573086000, 1.992309341397059600, 1.992275705969513800,
+    1.992241997291685400,
+  1.992208215364813700, 1.992174360190140900, 1.992140431768911500,
+    1.992106430102373400,
+  1.992072355191776300, 1.992038207038373300, 1.992003985643419700,
+    1.991969691008174100,
+  1.991935323133897000, 1.991900882021852200, 1.991866367673306200,
+    1.991831780089527500,
+  1.991797119271788300, 1.991762385221362600, 1.991727577939527600,
+    1.991692697427563300,
+  1.991657743686751700, 1.991622716718378400, 1.991587616523731000,
+    1.991552443104099800,
+  1.991517196460778500, 1.991481876595062800, 1.991446483508251500,
+    1.991411017201645500,
+  1.991375477676549100, 1.991339864934268800, 1.991304178976114100,
+    1.991268419803397200,
+  1.991232587417432600, 1.991196681819537900, 1.991160703011033200,
+    1.991124650993241400,
+  1.991088525767488200, 1.991052327335101300, 1.991016055697411900,
+    1.990979710855753900,
+  1.990943292811463000, 1.990906801565878600, 1.990870237120342400,
+    1.990833599476198800,
+  1.990796888634794400, 1.990760104597479400, 1.990723247365606200,
+    1.990686316940529800,
+  1.990649313323608100, 1.990612236516201300, 1.990575086519673200,
+    1.990537863335389400,
+  1.990500566964718400, 1.990463197409031700, 1.990425754669703100,
+    1.990388238748109100,
+  1.990350649645629600, 1.990312987363646000, 1.990275251903543600,
+    1.990237443266709400,
+  1.990199561454533600, 1.990161606468409300, 1.990123578309731700,
+    1.990085476979899000,
+  1.990047302480312300, 1.990009054812374800, 1.989970733977493000,
+    1.989932339977075900,
+  1.989893872812535000, 1.989855332485284800, 1.989816718996742200,
+    1.989778032348326700,
+  1.989739272541461100, 1.989700439577570400, 1.989661533458082100,
+    1.989622554184426800,
+  1.989583501758037700, 1.989544376180350600, 1.989505177452804100,
+    1.989465905576839600,
+  1.989426560553900500, 1.989387142385433900, 1.989347651072888900,
+    1.989308086617717500,
+  1.989268449021374300, 1.989228738285316900, 1.989188954411005100,
+    1.989149097399901500,
+  1.989109167253472000, 1.989069163973184300, 1.989029087560509700,
+    1.988988938016921000,
+  1.988948715343894900, 1.988908419542910100, 1.988868050615448100,
+    1.988827608562993200,
+  1.988787093387032600, 1.988746505089055600, 1.988705843670554500,
+    1.988665109133024500,
+  1.988624301477963200, 1.988583420706871100, 1.988542466821251000,
+    1.988501439822608900,
+  1.988460339712453200, 1.988419166492295000, 1.988377920163648000,
+    1.988336600728029000,
+  1.988295208186956700, 1.988253742541953800, 1.988212203794544000,
+    1.988170591946255100,
+  1.988128906998616800, 1.988087148953161700, 1.988045317811425700,
+    1.988003413574946000,
+  1.987961436245263800, 1.987919385823922400, 1.987877262312467600,
+    1.987835065712448600,
+  1.987792796025416500, 1.987750453252925500, 1.987708037396532800,
+    1.987665548457797400,
+  1.987622986438281700, 1.987580351339550700, 1.987537643163171700,
+    1.987494861910715100,
+  1.987452007583754100, 1.987409080183863800, 1.987366079712622900,
+    1.987323006171612500,
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+    0.009395597766389905,
+  0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
+    0.007861631292354124,
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+    0.006327660193523208,
+  0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
+    0.004793685372293270,
+  0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
+    0.003259707731061291,
+  0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
+    0.001725728172227238,
+  0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
+    0.000191747598192208,
+
+};
+
+/**    
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.   
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.   
+ * @param[in]     N			 length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingF32Table.gif    
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[4] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048, (float32_t *) Weights_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[4] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 0000000000..c6452fe98a
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4276 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_q15.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 Q15    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
+* \par    
+* C command to generate the table    
+* 
    
+* for(i = 0; i< N; i++)    
+* {    
+*   weights[2*i]= cos(i*c);    
+*   weights[(2*i)+1]= -sin(i * c);    
+* } 
    
+* \par    
+* where N is the Number of weights to be calculated and c is pi/(2*N)    
+* \par    
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is 2*N.    
+*/
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+  0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+  0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+  0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+  0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+  0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+  0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+  0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+  0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+  0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+  0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+  0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+  0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+  0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+  0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+  0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+  0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+  0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+  0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+  0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+  0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+  0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+  0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+  0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+  0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+  0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+  0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+  0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+  0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+  0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+  0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+  0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+  0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+  0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+  0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+  0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+  0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+  0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+  0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+  0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+  0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+  0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+  0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+  0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+  0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+  0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+  0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+  0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+  0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+  0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+  0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+  0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+  0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+  0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+  0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+  0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+  0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+  0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+  0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+  0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+  0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+  0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+  0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+  0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+  0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+  0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+  0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+  0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+  0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+  0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+  0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+  0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+  0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+  0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+  0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+  0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+  0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+  0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+  0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+  0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+  0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+  0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+  0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+  0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+  0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+  0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+  0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+  0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+  0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+  0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+  0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+  0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+  0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+  0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+  0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+  0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+  0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+  0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+  0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+  0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+  0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+  0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+  0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+  0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+  0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+  0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+  0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+  0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+  0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+  0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+  0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+  0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+  0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+  0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+  0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+  0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+  0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+  0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+  0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+  0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+  0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+  0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+  0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+  0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+  0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+  0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+  0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+  0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+  0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+  0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+  0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+  0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+  0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+  0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+  0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+  0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+  0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+  0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+  0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+  0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+  0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+  0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+  0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+  0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+  0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+  0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+  0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+  0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+  0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+  0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+  0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+  0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+  0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+  0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+  0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+  0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+  0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+  0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+  0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+  0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+  0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+  0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+  0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+  0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+  0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+  0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+  0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+  0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+  0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+  0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+  0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+  0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+  0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+  0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+  0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+  0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+  0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+  0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
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+  0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+  0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+  0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+  0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+  0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
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+  0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+  0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+  0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+  0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+  0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+  0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+  0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+  0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+  0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+  0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+  0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+  0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+  0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+  0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+  0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+  0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+  0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+  0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+  0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+  0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+  0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+  0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+  0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+  0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+  0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+  0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+  0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+  0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+  0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+  0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+  0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+  0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+  0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+  0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+  0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+  0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+  0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+  0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+  0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+  0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+  0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+  0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+  0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+  0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+  0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+  0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
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+  0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
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+  0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
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+  0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+  0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+  0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+  0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+  0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+  0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+  0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
+  0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
+  0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
+  0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
+  0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
+  0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
+  0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
+  0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
+  0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
+  0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
+  0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
+  0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
+  0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
+  0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
+  0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
+  0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
+  0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
+  0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
+  0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
+  0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
+  0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
+  0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
+  0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
+  0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
+  0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
+  0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
+  0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
+  0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
+  0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
+  0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
+  0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
+  0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
+  0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
+  0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
+  0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
+  0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
+  0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
+  0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
+  0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
+  0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
+  0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
+  0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
+  0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
+  0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
+  0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
+  0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
+  0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
+  0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
+  0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
+  0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
+  0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
+  0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
+  0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
+  0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
+  0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
+  0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
+  0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
+  0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
+  0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
+  0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
+  0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
+  0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
+  0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
+  0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
+  0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
+  0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
+  0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
+  0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
+  0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
+  0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
+  0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
+  0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
+  0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
+  0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
+  0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
+  0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
+  0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
+  0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
+  0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
+  0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
+  0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
+  0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
+  0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
+  0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
+  0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
+  0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
+  0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
+  0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
+  0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
+  0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
+  0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
+  0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
+  0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
+  0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
+  0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
+  0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
+  0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
+  0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
+  0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
+  0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
+  0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
+  0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
+  0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
+  0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
+  0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
+  0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
+  0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
+  0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
+  0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
+  0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
+  0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
+  0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
+  0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
+  0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
+  0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
+  0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
+  0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
+  0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
+  0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
+  0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
+  0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
+  0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
+  0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
+  0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
+  0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
+  0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
+  0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
+  0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
+  0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
+  0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
+  0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
+  0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
+  0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
+  0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
+  0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
+  0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
+  0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
+  0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
+  0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
+  0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
+  0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
+  0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
+  0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
+  0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
+  0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
+  0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
+  0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
+  0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
+  0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
+  0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
+  0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
+  0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
+  0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
+  0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
+  0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
+  0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
+  0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
+  0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
+  0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
+  0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
+  0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
+  0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
+  0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
+  0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
+  0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
+  0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
+  0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
+  0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
+  0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
+  0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
+  0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
+  0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
+  0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
+  0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
+  0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
+  0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
+  0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
+  0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
+  0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
+  0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
+  0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
+  0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
+  0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
+  0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
+  0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
+  0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
+  0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
+  0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
+  0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
+  0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
+  0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
+  0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
+  0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
+  0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
+  0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
+  0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
+  0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
+  0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
+  0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
+  0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
+  0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
+  0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
+  0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
+  0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
+  0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
+  0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
+  0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
+  0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
+  0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
+  0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
+  0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
+  0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
+  0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
+  0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
+  0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
+  0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
+  0x7e32, 0xea9a, 0x7e31, 0xea94, 0x7e30, 0xea8e, 0x7e2f, 0xea88,
+  0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
+  0x7e2a, 0xea69, 0x7e29, 0xea63, 0x7e28, 0xea5c, 0x7e27, 0xea56,
+  0x7e26, 0xea50, 0x7e25, 0xea4a, 0x7e24, 0xea44, 0x7e22, 0xea3d,
+  0x7e21, 0xea37, 0x7e20, 0xea31, 0x7e1f, 0xea2b, 0x7e1e, 0xea25,
+  0x7e1d, 0xea1e, 0x7e1c, 0xea18, 0x7e1b, 0xea12, 0x7e1a, 0xea0c,
+  0x7e19, 0xea06, 0x7e18, 0xe9ff, 0x7e17, 0xe9f9, 0x7e16, 0xe9f3,
+  0x7e14, 0xe9ed, 0x7e13, 0xe9e7, 0x7e12, 0xe9e1, 0x7e11, 0xe9da,
+  0x7e10, 0xe9d4, 0x7e0f, 0xe9ce, 0x7e0e, 0xe9c8, 0x7e0d, 0xe9c2,
+  0x7e0c, 0xe9bb, 0x7e0b, 0xe9b5, 0x7e0a, 0xe9af, 0x7e08, 0xe9a9,
+  0x7e07, 0xe9a3, 0x7e06, 0xe99c, 0x7e05, 0xe996, 0x7e04, 0xe990,
+  0x7e03, 0xe98a, 0x7e02, 0xe984, 0x7e01, 0xe97e, 0x7e00, 0xe977,
+  0x7dff, 0xe971, 0x7dfd, 0xe96b, 0x7dfc, 0xe965, 0x7dfb, 0xe95f,
+  0x7dfa, 0xe958, 0x7df9, 0xe952, 0x7df8, 0xe94c, 0x7df7, 0xe946,
+  0x7df6, 0xe940, 0x7df5, 0xe93a, 0x7df3, 0xe933, 0x7df2, 0xe92d,
+  0x7df1, 0xe927, 0x7df0, 0xe921, 0x7def, 0xe91b, 0x7dee, 0xe914,
+  0x7ded, 0xe90e, 0x7dec, 0xe908, 0x7dea, 0xe902, 0x7de9, 0xe8fc,
+  0x7de8, 0xe8f6, 0x7de7, 0xe8ef, 0x7de6, 0xe8e9, 0x7de5, 0xe8e3,
+  0x7de4, 0xe8dd, 0x7de2, 0xe8d7, 0x7de1, 0xe8d0, 0x7de0, 0xe8ca,
+  0x7ddf, 0xe8c4, 0x7dde, 0xe8be, 0x7ddd, 0xe8b8, 0x7ddc, 0xe8b2,
+  0x7dda, 0xe8ab, 0x7dd9, 0xe8a5, 0x7dd8, 0xe89f, 0x7dd7, 0xe899,
+  0x7dd6, 0xe893, 0x7dd5, 0xe88c, 0x7dd4, 0xe886, 0x7dd2, 0xe880,
+  0x7dd1, 0xe87a, 0x7dd0, 0xe874, 0x7dcf, 0xe86e, 0x7dce, 0xe867,
+  0x7dcd, 0xe861, 0x7dcc, 0xe85b, 0x7dca, 0xe855, 0x7dc9, 0xe84f,
+  0x7dc8, 0xe849, 0x7dc7, 0xe842, 0x7dc6, 0xe83c, 0x7dc5, 0xe836,
+  0x7dc3, 0xe830, 0x7dc2, 0xe82a, 0x7dc1, 0xe823, 0x7dc0, 0xe81d,
+  0x7dbf, 0xe817, 0x7dbd, 0xe811, 0x7dbc, 0xe80b, 0x7dbb, 0xe805,
+  0x7dba, 0xe7fe, 0x7db9, 0xe7f8, 0x7db8, 0xe7f2, 0x7db6, 0xe7ec,
+  0x7db5, 0xe7e6, 0x7db4, 0xe7e0, 0x7db3, 0xe7d9, 0x7db2, 0xe7d3,
+  0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
+  0x7dac, 0xe7b4, 0x7dab, 0xe7ae, 0x7da9, 0xe7a8, 0x7da8, 0xe7a2,
+  0x7da7, 0xe79c, 0x7da6, 0xe796, 0x7da5, 0xe78f, 0x7da3, 0xe789,
+  0x7da2, 0xe783, 0x7da1, 0xe77d, 0x7da0, 0xe777, 0x7d9f, 0xe771,
+  0x7d9d, 0xe76a, 0x7d9c, 0xe764, 0x7d9b, 0xe75e, 0x7d9a, 0xe758,
+  0x7d98, 0xe752, 0x7d97, 0xe74c, 0x7d96, 0xe745, 0x7d95, 0xe73f,
+  0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
+  0x7d8f, 0xe720, 0x7d8e, 0xe71a, 0x7d8c, 0xe714, 0x7d8b, 0xe70e,
+  0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
+  0x7d85, 0xe6ef, 0x7d84, 0xe6e9, 0x7d82, 0xe6e3, 0x7d81, 0xe6dd,
+  0x7d80, 0xe6d6, 0x7d7f, 0xe6d0, 0x7d7e, 0xe6ca, 0x7d7c, 0xe6c4,
+  0x7d7b, 0xe6be, 0x7d7a, 0xe6b8, 0x7d79, 0xe6b2, 0x7d77, 0xe6ab,
+  0x7d76, 0xe6a5, 0x7d75, 0xe69f, 0x7d74, 0xe699, 0x7d72, 0xe693,
+  0x7d71, 0xe68d, 0x7d70, 0xe686, 0x7d6f, 0xe680, 0x7d6d, 0xe67a,
+  0x7d6c, 0xe674, 0x7d6b, 0xe66e, 0x7d6a, 0xe668, 0x7d68, 0xe661,
+  0x7d67, 0xe65b, 0x7d66, 0xe655, 0x7d65, 0xe64f, 0x7d63, 0xe649,
+  0x7d62, 0xe643, 0x7d61, 0xe63d, 0x7d60, 0xe636, 0x7d5e, 0xe630,
+  0x7d5d, 0xe62a, 0x7d5c, 0xe624, 0x7d5a, 0xe61e, 0x7d59, 0xe618,
+  0x7d58, 0xe611, 0x7d57, 0xe60b, 0x7d55, 0xe605, 0x7d54, 0xe5ff,
+  0x7d53, 0xe5f9, 0x7d52, 0xe5f3, 0x7d50, 0xe5ed, 0x7d4f, 0xe5e6,
+  0x7d4e, 0xe5e0, 0x7d4c, 0xe5da, 0x7d4b, 0xe5d4, 0x7d4a, 0xe5ce,
+  0x7d49, 0xe5c8, 0x7d47, 0xe5c2, 0x7d46, 0xe5bb, 0x7d45, 0xe5b5,
+  0x7d43, 0xe5af, 0x7d42, 0xe5a9, 0x7d41, 0xe5a3, 0x7d3f, 0xe59d,
+  0x7d3e, 0xe596, 0x7d3d, 0xe590, 0x7d3c, 0xe58a, 0x7d3a, 0xe584,
+  0x7d39, 0xe57e, 0x7d38, 0xe578, 0x7d36, 0xe572, 0x7d35, 0xe56b,
+  0x7d34, 0xe565, 0x7d32, 0xe55f, 0x7d31, 0xe559, 0x7d30, 0xe553,
+  0x7d2f, 0xe54d, 0x7d2d, 0xe547, 0x7d2c, 0xe540, 0x7d2b, 0xe53a,
+  0x7d29, 0xe534, 0x7d28, 0xe52e, 0x7d27, 0xe528, 0x7d25, 0xe522,
+  0x7d24, 0xe51c, 0x7d23, 0xe515, 0x7d21, 0xe50f, 0x7d20, 0xe509,
+  0x7d1f, 0xe503, 0x7d1d, 0xe4fd, 0x7d1c, 0xe4f7, 0x7d1b, 0xe4f1,
+  0x7d19, 0xe4ea, 0x7d18, 0xe4e4, 0x7d17, 0xe4de, 0x7d15, 0xe4d8,
+  0x7d14, 0xe4d2, 0x7d13, 0xe4cc, 0x7d11, 0xe4c6, 0x7d10, 0xe4bf,
+  0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
+  0x7d09, 0xe4a1, 0x7d08, 0xe49b, 0x7d07, 0xe494, 0x7d05, 0xe48e,
+  0x7d04, 0xe488, 0x7d03, 0xe482, 0x7d01, 0xe47c, 0x7d00, 0xe476,
+  0x7cff, 0xe470, 0x7cfd, 0xe46a, 0x7cfc, 0xe463, 0x7cfb, 0xe45d,
+  0x7cf9, 0xe457, 0x7cf8, 0xe451, 0x7cf6, 0xe44b, 0x7cf5, 0xe445,
+  0x7cf4, 0xe43f, 0x7cf2, 0xe438, 0x7cf1, 0xe432, 0x7cf0, 0xe42c,
+  0x7cee, 0xe426, 0x7ced, 0xe420, 0x7cec, 0xe41a, 0x7cea, 0xe414,
+  0x7ce9, 0xe40e, 0x7ce7, 0xe407, 0x7ce6, 0xe401, 0x7ce5, 0xe3fb,
+  0x7ce3, 0xe3f5, 0x7ce2, 0xe3ef, 0x7ce1, 0xe3e9, 0x7cdf, 0xe3e3,
+  0x7cde, 0xe3dc, 0x7cdc, 0xe3d6, 0x7cdb, 0xe3d0, 0x7cda, 0xe3ca,
+  0x7cd8, 0xe3c4, 0x7cd7, 0xe3be, 0x7cd5, 0xe3b8, 0x7cd4, 0xe3b2,
+  0x7cd3, 0xe3ab, 0x7cd1, 0xe3a5, 0x7cd0, 0xe39f, 0x7ccf, 0xe399,
+  0x7ccd, 0xe393, 0x7ccc, 0xe38d, 0x7cca, 0xe387, 0x7cc9, 0xe381,
+  0x7cc8, 0xe37a, 0x7cc6, 0xe374, 0x7cc5, 0xe36e, 0x7cc3, 0xe368,
+  0x7cc2, 0xe362, 0x7cc1, 0xe35c, 0x7cbf, 0xe356, 0x7cbe, 0xe350,
+  0x7cbc, 0xe349, 0x7cbb, 0xe343, 0x7cb9, 0xe33d, 0x7cb8, 0xe337,
+  0x7cb7, 0xe331, 0x7cb5, 0xe32b, 0x7cb4, 0xe325, 0x7cb2, 0xe31f,
+  0x7cb1, 0xe318, 0x7cb0, 0xe312, 0x7cae, 0xe30c, 0x7cad, 0xe306,
+  0x7cab, 0xe300, 0x7caa, 0xe2fa, 0x7ca8, 0xe2f4, 0x7ca7, 0xe2ee,
+  0x7ca6, 0xe2e8, 0x7ca4, 0xe2e1, 0x7ca3, 0xe2db, 0x7ca1, 0xe2d5,
+  0x7ca0, 0xe2cf, 0x7c9e, 0xe2c9, 0x7c9d, 0xe2c3, 0x7c9c, 0xe2bd,
+  0x7c9a, 0xe2b7, 0x7c99, 0xe2b0, 0x7c97, 0xe2aa, 0x7c96, 0xe2a4,
+  0x7c94, 0xe29e, 0x7c93, 0xe298, 0x7c91, 0xe292, 0x7c90, 0xe28c,
+  0x7c8f, 0xe286, 0x7c8d, 0xe280, 0x7c8c, 0xe279, 0x7c8a, 0xe273,
+  0x7c89, 0xe26d, 0x7c87, 0xe267, 0x7c86, 0xe261, 0x7c84, 0xe25b,
+  0x7c83, 0xe255, 0x7c82, 0xe24f, 0x7c80, 0xe249, 0x7c7f, 0xe242,
+  0x7c7d, 0xe23c, 0x7c7c, 0xe236, 0x7c7a, 0xe230, 0x7c79, 0xe22a,
+  0x7c77, 0xe224, 0x7c76, 0xe21e, 0x7c74, 0xe218, 0x7c73, 0xe212,
+  0x7c71, 0xe20b, 0x7c70, 0xe205, 0x7c6e, 0xe1ff, 0x7c6d, 0xe1f9,
+  0x7c6c, 0xe1f3, 0x7c6a, 0xe1ed, 0x7c69, 0xe1e7, 0x7c67, 0xe1e1,
+  0x7c66, 0xe1db, 0x7c64, 0xe1d4, 0x7c63, 0xe1ce, 0x7c61, 0xe1c8,
+  0x7c60, 0xe1c2, 0x7c5e, 0xe1bc, 0x7c5d, 0xe1b6, 0x7c5b, 0xe1b0,
+  0x7c5a, 0xe1aa, 0x7c58, 0xe1a4, 0x7c57, 0xe19e, 0x7c55, 0xe197,
+  0x7c54, 0xe191, 0x7c52, 0xe18b, 0x7c51, 0xe185, 0x7c4f, 0xe17f,
+  0x7c4e, 0xe179, 0x7c4c, 0xe173, 0x7c4b, 0xe16d, 0x7c49, 0xe167,
+  0x7c48, 0xe160, 0x7c46, 0xe15a, 0x7c45, 0xe154, 0x7c43, 0xe14e,
+  0x7c42, 0xe148, 0x7c40, 0xe142, 0x7c3f, 0xe13c, 0x7c3d, 0xe136,
+  0x7c3c, 0xe130, 0x7c3a, 0xe12a, 0x7c39, 0xe123, 0x7c37, 0xe11d,
+  0x7c36, 0xe117, 0x7c34, 0xe111, 0x7c33, 0xe10b, 0x7c31, 0xe105,
+  0x7c30, 0xe0ff, 0x7c2e, 0xe0f9, 0x7c2d, 0xe0f3, 0x7c2b, 0xe0ed,
+  0x7c29, 0xe0e7, 0x7c28, 0xe0e0, 0x7c26, 0xe0da, 0x7c25, 0xe0d4,
+  0x7c23, 0xe0ce, 0x7c22, 0xe0c8, 0x7c20, 0xe0c2, 0x7c1f, 0xe0bc,
+  0x7c1d, 0xe0b6, 0x7c1c, 0xe0b0, 0x7c1a, 0xe0aa, 0x7c19, 0xe0a3,
+  0x7c17, 0xe09d, 0x7c16, 0xe097, 0x7c14, 0xe091, 0x7c12, 0xe08b,
+  0x7c11, 0xe085, 0x7c0f, 0xe07f, 0x7c0e, 0xe079, 0x7c0c, 0xe073,
+  0x7c0b, 0xe06d, 0x7c09, 0xe067, 0x7c08, 0xe061, 0x7c06, 0xe05a,
+  0x7c05, 0xe054, 0x7c03, 0xe04e, 0x7c01, 0xe048, 0x7c00, 0xe042,
+  0x7bfe, 0xe03c, 0x7bfd, 0xe036, 0x7bfb, 0xe030, 0x7bfa, 0xe02a,
+  0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
+  0x7bf2, 0xe00b, 0x7bf0, 0xe005, 0x7bef, 0xdfff, 0x7bed, 0xdff9,
+  0x7beb, 0xdff3, 0x7bea, 0xdfed, 0x7be8, 0xdfe7, 0x7be7, 0xdfe1,
+  0x7be5, 0xdfdb, 0x7be4, 0xdfd5, 0x7be2, 0xdfce, 0x7be0, 0xdfc8,
+  0x7bdf, 0xdfc2, 0x7bdd, 0xdfbc, 0x7bdc, 0xdfb6, 0x7bda, 0xdfb0,
+  0x7bd9, 0xdfaa, 0x7bd7, 0xdfa4, 0x7bd5, 0xdf9e, 0x7bd4, 0xdf98,
+  0x7bd2, 0xdf92, 0x7bd1, 0xdf8c, 0x7bcf, 0xdf86, 0x7bcd, 0xdf7f,
+  0x7bcc, 0xdf79, 0x7bca, 0xdf73, 0x7bc9, 0xdf6d, 0x7bc7, 0xdf67,
+  0x7bc5, 0xdf61, 0x7bc4, 0xdf5b, 0x7bc2, 0xdf55, 0x7bc1, 0xdf4f,
+  0x7bbf, 0xdf49, 0x7bbd, 0xdf43, 0x7bbc, 0xdf3d, 0x7bba, 0xdf37,
+  0x7bb9, 0xdf30, 0x7bb7, 0xdf2a, 0x7bb5, 0xdf24, 0x7bb4, 0xdf1e,
+  0x7bb2, 0xdf18, 0x7bb0, 0xdf12, 0x7baf, 0xdf0c, 0x7bad, 0xdf06,
+  0x7bac, 0xdf00, 0x7baa, 0xdefa, 0x7ba8, 0xdef4, 0x7ba7, 0xdeee,
+  0x7ba5, 0xdee8, 0x7ba3, 0xdee2, 0x7ba2, 0xdedb, 0x7ba0, 0xded5,
+  0x7b9f, 0xdecf, 0x7b9d, 0xdec9, 0x7b9b, 0xdec3, 0x7b9a, 0xdebd,
+  0x7b98, 0xdeb7, 0x7b96, 0xdeb1, 0x7b95, 0xdeab, 0x7b93, 0xdea5,
+  0x7b92, 0xde9f, 0x7b90, 0xde99, 0x7b8e, 0xde93, 0x7b8d, 0xde8d,
+  0x7b8b, 0xde87, 0x7b89, 0xde80, 0x7b88, 0xde7a, 0x7b86, 0xde74,
+  0x7b84, 0xde6e, 0x7b83, 0xde68, 0x7b81, 0xde62, 0x7b7f, 0xde5c,
+  0x7b7e, 0xde56, 0x7b7c, 0xde50, 0x7b7a, 0xde4a, 0x7b79, 0xde44,
+  0x7b77, 0xde3e, 0x7b76, 0xde38, 0x7b74, 0xde32, 0x7b72, 0xde2c,
+  0x7b71, 0xde26, 0x7b6f, 0xde1f, 0x7b6d, 0xde19, 0x7b6c, 0xde13,
+  0x7b6a, 0xde0d, 0x7b68, 0xde07, 0x7b67, 0xde01, 0x7b65, 0xddfb,
+  0x7b63, 0xddf5, 0x7b62, 0xddef, 0x7b60, 0xdde9, 0x7b5e, 0xdde3,
+  0x7b5d, 0xdddd, 0x7b5b, 0xddd7, 0x7b59, 0xddd1, 0x7b57, 0xddcb,
+  0x7b56, 0xddc5, 0x7b54, 0xddbf, 0x7b52, 0xddb9, 0x7b51, 0xddb2,
+  0x7b4f, 0xddac, 0x7b4d, 0xdda6, 0x7b4c, 0xdda0, 0x7b4a, 0xdd9a,
+  0x7b48, 0xdd94, 0x7b47, 0xdd8e, 0x7b45, 0xdd88, 0x7b43, 0xdd82,
+  0x7b42, 0xdd7c, 0x7b40, 0xdd76, 0x7b3e, 0xdd70, 0x7b3c, 0xdd6a,
+  0x7b3b, 0xdd64, 0x7b39, 0xdd5e, 0x7b37, 0xdd58, 0x7b36, 0xdd52,
+  0x7b34, 0xdd4c, 0x7b32, 0xdd46, 0x7b31, 0xdd40, 0x7b2f, 0xdd39,
+  0x7b2d, 0xdd33, 0x7b2b, 0xdd2d, 0x7b2a, 0xdd27, 0x7b28, 0xdd21,
+  0x7b26, 0xdd1b, 0x7b25, 0xdd15, 0x7b23, 0xdd0f, 0x7b21, 0xdd09,
+  0x7b1f, 0xdd03, 0x7b1e, 0xdcfd, 0x7b1c, 0xdcf7, 0x7b1a, 0xdcf1,
+  0x7b19, 0xdceb, 0x7b17, 0xdce5, 0x7b15, 0xdcdf, 0x7b13, 0xdcd9,
+  0x7b12, 0xdcd3, 0x7b10, 0xdccd, 0x7b0e, 0xdcc7, 0x7b0c, 0xdcc1,
+  0x7b0b, 0xdcbb, 0x7b09, 0xdcb5, 0x7b07, 0xdcae, 0x7b06, 0xdca8,
+  0x7b04, 0xdca2, 0x7b02, 0xdc9c, 0x7b00, 0xdc96, 0x7aff, 0xdc90,
+  0x7afd, 0xdc8a, 0x7afb, 0xdc84, 0x7af9, 0xdc7e, 0x7af8, 0xdc78,
+  0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
+  0x7aef, 0xdc5a, 0x7aed, 0xdc54, 0x7aeb, 0xdc4e, 0x7aea, 0xdc48,
+  0x7ae8, 0xdc42, 0x7ae6, 0xdc3c, 0x7ae4, 0xdc36, 0x7ae3, 0xdc30,
+  0x7ae1, 0xdc2a, 0x7adf, 0xdc24, 0x7add, 0xdc1e, 0x7adc, 0xdc18,
+  0x7ada, 0xdc12, 0x7ad8, 0xdc0c, 0x7ad6, 0xdc06, 0x7ad5, 0xdbff,
+  0x7ad3, 0xdbf9, 0x7ad1, 0xdbf3, 0x7acf, 0xdbed, 0x7acd, 0xdbe7,
+  0x7acc, 0xdbe1, 0x7aca, 0xdbdb, 0x7ac8, 0xdbd5, 0x7ac6, 0xdbcf,
+  0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
+  0x7abd, 0xdbb1, 0x7abc, 0xdbab, 0x7aba, 0xdba5, 0x7ab8, 0xdb9f,
+  0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
+  0x7aaf, 0xdb81, 0x7aad, 0xdb7b, 0x7aac, 0xdb75, 0x7aaa, 0xdb6f,
+  0x7aa8, 0xdb69, 0x7aa6, 0xdb63, 0x7aa4, 0xdb5d, 0x7aa3, 0xdb57,
+  0x7aa1, 0xdb51, 0x7a9f, 0xdb4b, 0x7a9d, 0xdb45, 0x7a9b, 0xdb3f,
+  0x7a9a, 0xdb39, 0x7a98, 0xdb33, 0x7a96, 0xdb2d, 0x7a94, 0xdb27,
+  0x7a92, 0xdb21, 0x7a91, 0xdb1b, 0x7a8f, 0xdb15, 0x7a8d, 0xdb0f,
+  0x7a8b, 0xdb09, 0x7a89, 0xdb03, 0x7a87, 0xdafd, 0x7a86, 0xdaf7,
+  0x7a84, 0xdaf1, 0x7a82, 0xdaea, 0x7a80, 0xdae4, 0x7a7e, 0xdade,
+  0x7a7d, 0xdad8, 0x7a7b, 0xdad2, 0x7a79, 0xdacc, 0x7a77, 0xdac6,
+  0x7a75, 0xdac0, 0x7a73, 0xdaba, 0x7a72, 0xdab4, 0x7a70, 0xdaae,
+  0x7a6e, 0xdaa8, 0x7a6c, 0xdaa2, 0x7a6a, 0xda9c, 0x7a68, 0xda96,
+  0x7a67, 0xda90, 0x7a65, 0xda8a, 0x7a63, 0xda84, 0x7a61, 0xda7e,
+  0x7a5f, 0xda78, 0x7a5d, 0xda72, 0x7a5c, 0xda6c, 0x7a5a, 0xda66,
+  0x7a58, 0xda60, 0x7a56, 0xda5a, 0x7a54, 0xda54, 0x7a52, 0xda4e,
+  0x7a50, 0xda48, 0x7a4f, 0xda42, 0x7a4d, 0xda3c, 0x7a4b, 0xda36,
+  0x7a49, 0xda30, 0x7a47, 0xda2a, 0x7a45, 0xda24, 0x7a43, 0xda1e,
+  0x7a42, 0xda18, 0x7a40, 0xda12, 0x7a3e, 0xda0c, 0x7a3c, 0xda06,
+  0x7a3a, 0xda00, 0x7a38, 0xd9fa, 0x7a36, 0xd9f4, 0x7a35, 0xd9ee,
+  0x7a33, 0xd9e8, 0x7a31, 0xd9e2, 0x7a2f, 0xd9dc, 0x7a2d, 0xd9d6,
+  0x7a2b, 0xd9d0, 0x7a29, 0xd9ca, 0x7a27, 0xd9c4, 0x7a26, 0xd9be,
+  0x7a24, 0xd9b8, 0x7a22, 0xd9b2, 0x7a20, 0xd9ac, 0x7a1e, 0xd9a6,
+  0x7a1c, 0xd9a0, 0x7a1a, 0xd99a, 0x7a18, 0xd994, 0x7a16, 0xd98e,
+  0x7a15, 0xd988, 0x7a13, 0xd982, 0x7a11, 0xd97c, 0x7a0f, 0xd976,
+  0x7a0d, 0xd970, 0x7a0b, 0xd96a, 0x7a09, 0xd964, 0x7a07, 0xd95e,
+  0x7a05, 0xd958, 0x7a04, 0xd952, 0x7a02, 0xd94c, 0x7a00, 0xd946,
+  0x79fe, 0xd940, 0x79fc, 0xd93a, 0x79fa, 0xd934, 0x79f8, 0xd92e,
+  0x79f6, 0xd928, 0x79f4, 0xd922, 0x79f2, 0xd91c, 0x79f0, 0xd917,
+  0x79ef, 0xd911, 0x79ed, 0xd90b, 0x79eb, 0xd905, 0x79e9, 0xd8ff,
+  0x79e7, 0xd8f9, 0x79e5, 0xd8f3, 0x79e3, 0xd8ed, 0x79e1, 0xd8e7,
+  0x79df, 0xd8e1, 0x79dd, 0xd8db, 0x79db, 0xd8d5, 0x79d9, 0xd8cf,
+  0x79d8, 0xd8c9, 0x79d6, 0xd8c3, 0x79d4, 0xd8bd, 0x79d2, 0xd8b7,
+  0x79d0, 0xd8b1, 0x79ce, 0xd8ab, 0x79cc, 0xd8a5, 0x79ca, 0xd89f,
+  0x79c8, 0xd899, 0x79c6, 0xd893, 0x79c4, 0xd88d, 0x79c2, 0xd887,
+  0x79c0, 0xd881, 0x79be, 0xd87b, 0x79bc, 0xd875, 0x79bb, 0xd86f,
+  0x79b9, 0xd869, 0x79b7, 0xd863, 0x79b5, 0xd85d, 0x79b3, 0xd857,
+  0x79b1, 0xd851, 0x79af, 0xd84b, 0x79ad, 0xd845, 0x79ab, 0xd83f,
+  0x79a9, 0xd839, 0x79a7, 0xd833, 0x79a5, 0xd82d, 0x79a3, 0xd827,
+  0x79a1, 0xd821, 0x799f, 0xd81b, 0x799d, 0xd815, 0x799b, 0xd80f,
+  0x7999, 0xd80a, 0x7997, 0xd804, 0x7995, 0xd7fe, 0x7993, 0xd7f8,
+  0x7992, 0xd7f2, 0x7990, 0xd7ec, 0x798e, 0xd7e6, 0x798c, 0xd7e0,
+  0x798a, 0xd7da, 0x7988, 0xd7d4, 0x7986, 0xd7ce, 0x7984, 0xd7c8,
+  0x7982, 0xd7c2, 0x7980, 0xd7bc, 0x797e, 0xd7b6, 0x797c, 0xd7b0,
+  0x797a, 0xd7aa, 0x7978, 0xd7a4, 0x7976, 0xd79e, 0x7974, 0xd798,
+  0x7972, 0xd792, 0x7970, 0xd78c, 0x796e, 0xd786, 0x796c, 0xd780,
+  0x796a, 0xd77a, 0x7968, 0xd774, 0x7966, 0xd76e, 0x7964, 0xd768,
+  0x7962, 0xd763, 0x7960, 0xd75d, 0x795e, 0xd757, 0x795c, 0xd751,
+  0x795a, 0xd74b, 0x7958, 0xd745, 0x7956, 0xd73f, 0x7954, 0xd739,
+  0x7952, 0xd733, 0x7950, 0xd72d, 0x794e, 0xd727, 0x794c, 0xd721,
+  0x794a, 0xd71b, 0x7948, 0xd715, 0x7946, 0xd70f, 0x7944, 0xd709,
+  0x7942, 0xd703, 0x7940, 0xd6fd, 0x793e, 0xd6f7, 0x793c, 0xd6f1,
+  0x793a, 0xd6eb, 0x7938, 0xd6e5, 0x7936, 0xd6e0, 0x7934, 0xd6da,
+  0x7932, 0xd6d4, 0x7930, 0xd6ce, 0x792e, 0xd6c8, 0x792c, 0xd6c2,
+  0x792a, 0xd6bc, 0x7928, 0xd6b6, 0x7926, 0xd6b0, 0x7924, 0xd6aa,
+  0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
+  0x7919, 0xd68c, 0x7917, 0xd686, 0x7915, 0xd680, 0x7913, 0xd67a,
+  0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
+  0x7909, 0xd65d, 0x7907, 0xd657, 0x7905, 0xd651, 0x7903, 0xd64b,
+  0x7901, 0xd645, 0x78ff, 0xd63f, 0x78fd, 0xd639, 0x78fb, 0xd633,
+  0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
+  0x78f1, 0xd615, 0x78ee, 0xd610, 0x78ec, 0xd60a, 0x78ea, 0xd604,
+  0x78e8, 0xd5fe, 0x78e6, 0xd5f8, 0x78e4, 0xd5f2, 0x78e2, 0xd5ec,
+  0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
+  0x78d8, 0xd5ce, 0x78d6, 0xd5c8, 0x78d4, 0xd5c2, 0x78d2, 0xd5bc,
+  0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
+  0x78c7, 0xd59f, 0x78c5, 0xd599, 0x78c3, 0xd593, 0x78c1, 0xd58d,
+  0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
+  0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
+  0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
+  0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
+  0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
+  0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
+  0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
+  0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
+  0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
+  0x7873, 0xd4b2, 0x7871, 0xd4ac, 0x786f, 0xd4a6, 0x786d, 0xd4a0,
+  0x786b, 0xd49a, 0x7868, 0xd494, 0x7866, 0xd48f, 0x7864, 0xd489,
+  0x7862, 0xd483, 0x7860, 0xd47d, 0x785e, 0xd477, 0x785c, 0xd471,
+  0x7859, 0xd46b, 0x7857, 0xd465, 0x7855, 0xd45f, 0x7853, 0xd459,
+  0x7851, 0xd453, 0x784f, 0xd44e, 0x784d, 0xd448, 0x784a, 0xd442,
+  0x7848, 0xd43c, 0x7846, 0xd436, 0x7844, 0xd430, 0x7842, 0xd42a,
+  0x7840, 0xd424, 0x783e, 0xd41e, 0x783b, 0xd418, 0x7839, 0xd412,
+  0x7837, 0xd40d, 0x7835, 0xd407, 0x7833, 0xd401, 0x7831, 0xd3fb,
+  0x782e, 0xd3f5, 0x782c, 0xd3ef, 0x782a, 0xd3e9, 0x7828, 0xd3e3,
+  0x7826, 0xd3dd, 0x7824, 0xd3d7, 0x7821, 0xd3d2, 0x781f, 0xd3cc,
+  0x781d, 0xd3c6, 0x781b, 0xd3c0, 0x7819, 0xd3ba, 0x7817, 0xd3b4,
+  0x7814, 0xd3ae, 0x7812, 0xd3a8, 0x7810, 0xd3a2, 0x780e, 0xd39d,
+  0x780c, 0xd397, 0x780a, 0xd391, 0x7807, 0xd38b, 0x7805, 0xd385,
+  0x7803, 0xd37f, 0x7801, 0xd379, 0x77ff, 0xd373, 0x77fc, 0xd36d,
+  0x77fa, 0xd368, 0x77f8, 0xd362, 0x77f6, 0xd35c, 0x77f4, 0xd356,
+  0x77f1, 0xd350, 0x77ef, 0xd34a, 0x77ed, 0xd344, 0x77eb, 0xd33e,
+  0x77e9, 0xd338, 0x77e6, 0xd333, 0x77e4, 0xd32d, 0x77e2, 0xd327,
+  0x77e0, 0xd321, 0x77de, 0xd31b, 0x77db, 0xd315, 0x77d9, 0xd30f,
+  0x77d7, 0xd309, 0x77d5, 0xd303, 0x77d3, 0xd2fe, 0x77d0, 0xd2f8,
+  0x77ce, 0xd2f2, 0x77cc, 0xd2ec, 0x77ca, 0xd2e6, 0x77c8, 0xd2e0,
+  0x77c5, 0xd2da, 0x77c3, 0xd2d4, 0x77c1, 0xd2cf, 0x77bf, 0xd2c9,
+  0x77bc, 0xd2c3, 0x77ba, 0xd2bd, 0x77b8, 0xd2b7, 0x77b6, 0xd2b1,
+  0x77b4, 0xd2ab, 0x77b1, 0xd2a5, 0x77af, 0xd2a0, 0x77ad, 0xd29a,
+  0x77ab, 0xd294, 0x77a8, 0xd28e, 0x77a6, 0xd288, 0x77a4, 0xd282,
+  0x77a2, 0xd27c, 0x77a0, 0xd276, 0x779d, 0xd271, 0x779b, 0xd26b,
+  0x7799, 0xd265, 0x7797, 0xd25f, 0x7794, 0xd259, 0x7792, 0xd253,
+  0x7790, 0xd24d, 0x778e, 0xd247, 0x778b, 0xd242, 0x7789, 0xd23c,
+  0x7787, 0xd236, 0x7785, 0xd230, 0x7782, 0xd22a, 0x7780, 0xd224,
+  0x777e, 0xd21e, 0x777c, 0xd219, 0x7779, 0xd213, 0x7777, 0xd20d,
+  0x7775, 0xd207, 0x7773, 0xd201, 0x7770, 0xd1fb, 0x776e, 0xd1f5,
+  0x776c, 0xd1ef, 0x776a, 0xd1ea, 0x7767, 0xd1e4, 0x7765, 0xd1de,
+  0x7763, 0xd1d8, 0x7760, 0xd1d2, 0x775e, 0xd1cc, 0x775c, 0xd1c6,
+  0x775a, 0xd1c1, 0x7757, 0xd1bb, 0x7755, 0xd1b5, 0x7753, 0xd1af,
+  0x7751, 0xd1a9, 0x774e, 0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,
+  0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,
+  0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,
+  0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,
+  0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,
+  0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,
+  0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,
+  0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,
+  0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,
+  0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,
+  0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,
+  0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,
+  0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,
+  0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,
+  0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,
+  0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,
+  0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,
+  0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,
+  0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,
+  0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,
+  0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,
+  0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,
+  0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,
+  0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,
+  0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,
+  0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,
+  0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,
+  0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,
+  0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,
+  0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,
+  0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,
+  0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,
+  0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,
+  0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,
+  0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,
+  0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,
+  0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,
+  0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,
+  0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,
+  0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,
+  0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,
+  0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,
+  0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,
+  0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,
+  0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,
+  0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,
+  0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,
+  0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,
+  0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,
+  0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,
+  0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,
+  0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,
+  0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,
+  0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,
+  0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,
+  0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,
+  0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,
+  0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,
+  0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,
+  0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,
+  0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,
+  0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,
+  0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,
+  0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,
+  0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,
+  0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,
+  0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,
+  0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,
+  0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,
+  0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,
+  0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,
+  0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,
+  0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,
+  0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,
+  0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,
+  0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,
+  0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,
+  0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,
+  0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,
+  0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,
+  0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,
+  0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,
+  0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,
+  0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,
+  0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,
+  0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,
+  0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,
+  0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,
+  0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,
+  0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,
+  0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,
+  0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,
+  0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,
+  0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,
+  0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,
+  0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,
+  0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,
+  0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,
+  0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,
+  0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,
+  0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,
+  0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,
+  0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,
+  0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,
+  0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,
+  0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,
+  0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,
+  0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,
+  0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,
+  0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,
+  0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,
+  0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,
+  0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,
+  0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,
+  0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,
+  0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,
+  0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,
+  0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,
+  0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,
+  0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,
+  0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,
+  0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,
+  0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,
+  0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,
+  0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,
+  0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,
+  0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,
+  0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,
+  0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,
+  0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,
+  0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,
+  0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,
+  0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,
+  0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,
+  0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,
+  0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,
+  0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,
+  0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,
+  0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,
+  0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,
+  0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,
+  0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,
+  0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,
+  0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,
+  0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,
+  0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,
+  0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,
+  0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,
+  0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,
+  0x7141, 0xc45b, 0x713e, 0xc456, 0x713b, 0xc450, 0x7138, 0xc44b,
+  0x7135, 0xc445, 0x7132, 0xc440, 0x712f, 0xc43a, 0x712c, 0xc434,
+  0x7129, 0xc42f, 0x7126, 0xc429, 0x7123, 0xc424, 0x7120, 0xc41e,
+  0x711d, 0xc419, 0x711a, 0xc413, 0x7117, 0xc40e, 0x7114, 0xc408,
+  0x7112, 0xc403, 0x710f, 0xc3fd, 0x710c, 0xc3f7, 0x7109, 0xc3f2,
+  0x7106, 0xc3ec, 0x7103, 0xc3e7, 0x7100, 0xc3e1, 0x70fd, 0xc3dc,
+  0x70fa, 0xc3d6, 0x70f7, 0xc3d1, 0x70f4, 0xc3cb, 0x70f1, 0xc3c5,
+  0x70ee, 0xc3c0, 0x70eb, 0xc3ba, 0x70e8, 0xc3b5, 0x70e5, 0xc3af,
+  0x70e2, 0xc3aa, 0x70df, 0xc3a4, 0x70dc, 0xc39f, 0x70d9, 0xc399,
+  0x70d6, 0xc394, 0x70d3, 0xc38e, 0x70d1, 0xc389, 0x70ce, 0xc383,
+  0x70cb, 0xc37d, 0x70c8, 0xc378, 0x70c5, 0xc372, 0x70c2, 0xc36d,
+  0x70bf, 0xc367, 0x70bc, 0xc362, 0x70b9, 0xc35c, 0x70b6, 0xc357,
+  0x70b3, 0xc351, 0x70b0, 0xc34c, 0x70ad, 0xc346, 0x70aa, 0xc341,
+  0x70a7, 0xc33b, 0x70a4, 0xc336, 0x70a1, 0xc330, 0x709e, 0xc32a,
+  0x709b, 0xc325, 0x7098, 0xc31f, 0x7095, 0xc31a, 0x7092, 0xc314,
+  0x708f, 0xc30f, 0x708c, 0xc309, 0x7089, 0xc304, 0x7086, 0xc2fe,
+  0x7083, 0xc2f9, 0x7080, 0xc2f3, 0x707d, 0xc2ee, 0x707a, 0xc2e8,
+  0x7077, 0xc2e3, 0x7074, 0xc2dd, 0x7071, 0xc2d8, 0x706e, 0xc2d2,
+  0x706b, 0xc2cd, 0x7068, 0xc2c7, 0x7065, 0xc2c2, 0x7062, 0xc2bc,
+  0x705f, 0xc2b7, 0x705c, 0xc2b1, 0x7059, 0xc2ab, 0x7056, 0xc2a6,
+  0x7053, 0xc2a0, 0x7050, 0xc29b, 0x704d, 0xc295, 0x704a, 0xc290,
+  0x7047, 0xc28a, 0x7044, 0xc285, 0x7041, 0xc27f, 0x703e, 0xc27a,
+  0x703b, 0xc274, 0x7038, 0xc26f, 0x7035, 0xc269, 0x7032, 0xc264,
+  0x702f, 0xc25e, 0x702c, 0xc259, 0x7029, 0xc253, 0x7026, 0xc24e,
+  0x7023, 0xc248, 0x7020, 0xc243, 0x701d, 0xc23d, 0x7019, 0xc238,
+  0x7016, 0xc232, 0x7013, 0xc22d, 0x7010, 0xc227, 0x700d, 0xc222,
+  0x700a, 0xc21c, 0x7007, 0xc217, 0x7004, 0xc211, 0x7001, 0xc20c,
+  0x6ffe, 0xc206, 0x6ffb, 0xc201, 0x6ff8, 0xc1fb, 0x6ff5, 0xc1f6,
+  0x6ff2, 0xc1f0, 0x6fef, 0xc1eb, 0x6fec, 0xc1e5, 0x6fe9, 0xc1e0,
+  0x6fe6, 0xc1da, 0x6fe3, 0xc1d5, 0x6fe0, 0xc1cf, 0x6fdd, 0xc1ca,
+  0x6fda, 0xc1c4, 0x6fd6, 0xc1bf, 0x6fd3, 0xc1b9, 0x6fd0, 0xc1b4,
+  0x6fcd, 0xc1ae, 0x6fca, 0xc1a9, 0x6fc7, 0xc1a3, 0x6fc4, 0xc19e,
+  0x6fc1, 0xc198, 0x6fbe, 0xc193, 0x6fbb, 0xc18d, 0x6fb8, 0xc188,
+  0x6fb5, 0xc183, 0x6fb2, 0xc17d, 0x6faf, 0xc178, 0x6fac, 0xc172,
+  0x6fa9, 0xc16d, 0x6fa5, 0xc167, 0x6fa2, 0xc162, 0x6f9f, 0xc15c,
+  0x6f9c, 0xc157, 0x6f99, 0xc151, 0x6f96, 0xc14c, 0x6f93, 0xc146,
+  0x6f90, 0xc141, 0x6f8d, 0xc13b, 0x6f8a, 0xc136, 0x6f87, 0xc130,
+  0x6f84, 0xc12b, 0x6f81, 0xc125, 0x6f7d, 0xc120, 0x6f7a, 0xc11a,
+  0x6f77, 0xc115, 0x6f74, 0xc10f, 0x6f71, 0xc10a, 0x6f6e, 0xc105,
+  0x6f6b, 0xc0ff, 0x6f68, 0xc0fa, 0x6f65, 0xc0f4, 0x6f62, 0xc0ef,
+  0x6f5f, 0xc0e9, 0x6f5b, 0xc0e4, 0x6f58, 0xc0de, 0x6f55, 0xc0d9,
+  0x6f52, 0xc0d3, 0x6f4f, 0xc0ce, 0x6f4c, 0xc0c8, 0x6f49, 0xc0c3,
+  0x6f46, 0xc0bd, 0x6f43, 0xc0b8, 0x6f3f, 0xc0b3, 0x6f3c, 0xc0ad,
+  0x6f39, 0xc0a8, 0x6f36, 0xc0a2, 0x6f33, 0xc09d, 0x6f30, 0xc097,
+  0x6f2d, 0xc092, 0x6f2a, 0xc08c, 0x6f27, 0xc087, 0x6f23, 0xc081,
+  0x6f20, 0xc07c, 0x6f1d, 0xc077, 0x6f1a, 0xc071, 0x6f17, 0xc06c,
+  0x6f14, 0xc066, 0x6f11, 0xc061, 0x6f0e, 0xc05b, 0x6f0b, 0xc056,
+  0x6f07, 0xc050, 0x6f04, 0xc04b, 0x6f01, 0xc045, 0x6efe, 0xc040,
+  0x6efb, 0xc03b, 0x6ef8, 0xc035, 0x6ef5, 0xc030, 0x6ef1, 0xc02a,
+  0x6eee, 0xc025, 0x6eeb, 0xc01f, 0x6ee8, 0xc01a, 0x6ee5, 0xc014,
+  0x6ee2, 0xc00f, 0x6edf, 0xc00a, 0x6edc, 0xc004, 0x6ed8, 0xbfff,
+  0x6ed5, 0xbff9, 0x6ed2, 0xbff4, 0x6ecf, 0xbfee, 0x6ecc, 0xbfe9,
+  0x6ec9, 0xbfe3, 0x6ec6, 0xbfde, 0x6ec2, 0xbfd9, 0x6ebf, 0xbfd3,
+  0x6ebc, 0xbfce, 0x6eb9, 0xbfc8, 0x6eb6, 0xbfc3, 0x6eb3, 0xbfbd,
+  0x6eaf, 0xbfb8, 0x6eac, 0xbfb3, 0x6ea9, 0xbfad, 0x6ea6, 0xbfa8,
+  0x6ea3, 0xbfa2, 0x6ea0, 0xbf9d, 0x6e9c, 0xbf97, 0x6e99, 0xbf92,
+  0x6e96, 0xbf8d, 0x6e93, 0xbf87, 0x6e90, 0xbf82, 0x6e8d, 0xbf7c,
+  0x6e89, 0xbf77, 0x6e86, 0xbf71, 0x6e83, 0xbf6c, 0x6e80, 0xbf67,
+  0x6e7d, 0xbf61, 0x6e7a, 0xbf5c, 0x6e76, 0xbf56, 0x6e73, 0xbf51,
+  0x6e70, 0xbf4b, 0x6e6d, 0xbf46, 0x6e6a, 0xbf41, 0x6e67, 0xbf3b,
+  0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,
+  0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,
+  0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,
+  0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,
+  0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,
+  0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,
+  0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,
+  0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,
+  0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,
+  0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,
+  0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,
+  0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,
+  0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,
+  0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,
+  0x6db0, 0xbe07, 0x6dac, 0xbe02, 0x6da9, 0xbdfd, 0x6da6, 0xbdf7,
+  0x6da3, 0xbdf2, 0x6d9f, 0xbdec, 0x6d9c, 0xbde7, 0x6d99, 0xbde2,
+  0x6d96, 0xbddc, 0x6d92, 0xbdd7, 0x6d8f, 0xbdd1, 0x6d8c, 0xbdcc,
+  0x6d89, 0xbdc7, 0x6d85, 0xbdc1, 0x6d82, 0xbdbc, 0x6d7f, 0xbdb7,
+  0x6d7c, 0xbdb1, 0x6d78, 0xbdac, 0x6d75, 0xbda6, 0x6d72, 0xbda1,
+  0x6d6f, 0xbd9c, 0x6d6b, 0xbd96, 0x6d68, 0xbd91, 0x6d65, 0xbd8c,
+  0x6d62, 0xbd86, 0x6d5e, 0xbd81, 0x6d5b, 0xbd7c, 0x6d58, 0xbd76,
+  0x6d55, 0xbd71, 0x6d51, 0xbd6b, 0x6d4e, 0xbd66, 0x6d4b, 0xbd61,
+  0x6d48, 0xbd5b, 0x6d44, 0xbd56, 0x6d41, 0xbd51, 0x6d3e, 0xbd4b,
+  0x6d3a, 0xbd46, 0x6d37, 0xbd40, 0x6d34, 0xbd3b, 0x6d31, 0xbd36,
+  0x6d2d, 0xbd30, 0x6d2a, 0xbd2b, 0x6d27, 0xbd26, 0x6d23, 0xbd20,
+  0x6d20, 0xbd1b, 0x6d1d, 0xbd16, 0x6d1a, 0xbd10, 0x6d16, 0xbd0b,
+  0x6d13, 0xbd06, 0x6d10, 0xbd00, 0x6d0c, 0xbcfb, 0x6d09, 0xbcf5,
+  0x6d06, 0xbcf0, 0x6d03, 0xbceb, 0x6cff, 0xbce5, 0x6cfc, 0xbce0,
+  0x6cf9, 0xbcdb, 0x6cf5, 0xbcd5, 0x6cf2, 0xbcd0, 0x6cef, 0xbccb,
+  0x6cec, 0xbcc5, 0x6ce8, 0xbcc0, 0x6ce5, 0xbcbb, 0x6ce2, 0xbcb5,
+  0x6cde, 0xbcb0, 0x6cdb, 0xbcab, 0x6cd8, 0xbca5, 0x6cd4, 0xbca0,
+  0x6cd1, 0xbc9b, 0x6cce, 0xbc95, 0x6cca, 0xbc90, 0x6cc7, 0xbc8b,
+  0x6cc4, 0xbc85, 0x6cc1, 0xbc80, 0x6cbd, 0xbc7b, 0x6cba, 0xbc75,
+  0x6cb7, 0xbc70, 0x6cb3, 0xbc6b, 0x6cb0, 0xbc65, 0x6cad, 0xbc60,
+  0x6ca9, 0xbc5b, 0x6ca6, 0xbc55, 0x6ca3, 0xbc50, 0x6c9f, 0xbc4b,
+  0x6c9c, 0xbc45, 0x6c99, 0xbc40, 0x6c95, 0xbc3b, 0x6c92, 0xbc35,
+  0x6c8f, 0xbc30, 0x6c8b, 0xbc2b, 0x6c88, 0xbc25, 0x6c85, 0xbc20,
+  0x6c81, 0xbc1b, 0x6c7e, 0xbc15, 0x6c7b, 0xbc10, 0x6c77, 0xbc0b,
+  0x6c74, 0xbc05, 0x6c71, 0xbc00, 0x6c6d, 0xbbfb, 0x6c6a, 0xbbf5,
+  0x6c67, 0xbbf0, 0x6c63, 0xbbeb, 0x6c60, 0xbbe5, 0x6c5d, 0xbbe0,
+  0x6c59, 0xbbdb, 0x6c56, 0xbbd5, 0x6c53, 0xbbd0, 0x6c4f, 0xbbcb,
+  0x6c4c, 0xbbc5, 0x6c49, 0xbbc0, 0x6c45, 0xbbbb, 0x6c42, 0xbbb5,
+  0x6c3f, 0xbbb0, 0x6c3b, 0xbbab, 0x6c38, 0xbba6, 0x6c34, 0xbba0,
+  0x6c31, 0xbb9b, 0x6c2e, 0xbb96, 0x6c2a, 0xbb90, 0x6c27, 0xbb8b,
+  0x6c24, 0xbb86, 0x6c20, 0xbb80, 0x6c1d, 0xbb7b, 0x6c1a, 0xbb76,
+  0x6c16, 0xbb70, 0x6c13, 0xbb6b, 0x6c0f, 0xbb66, 0x6c0c, 0xbb61,
+  0x6c09, 0xbb5b, 0x6c05, 0xbb56, 0x6c02, 0xbb51, 0x6bff, 0xbb4b,
+  0x6bfb, 0xbb46, 0x6bf8, 0xbb41, 0x6bf5, 0xbb3b, 0x6bf1, 0xbb36,
+  0x6bee, 0xbb31, 0x6bea, 0xbb2c, 0x6be7, 0xbb26, 0x6be4, 0xbb21,
+  0x6be0, 0xbb1c, 0x6bdd, 0xbb16, 0x6bd9, 0xbb11, 0x6bd6, 0xbb0c,
+  0x6bd3, 0xbb06, 0x6bcf, 0xbb01, 0x6bcc, 0xbafc, 0x6bc9, 0xbaf7,
+  0x6bc5, 0xbaf1, 0x6bc2, 0xbaec, 0x6bbe, 0xbae7, 0x6bbb, 0xbae1,
+  0x6bb8, 0xbadc, 0x6bb4, 0xbad7, 0x6bb1, 0xbad2, 0x6bad, 0xbacc,
+  0x6baa, 0xbac7, 0x6ba7, 0xbac2, 0x6ba3, 0xbabc, 0x6ba0, 0xbab7,
+  0x6b9c, 0xbab2, 0x6b99, 0xbaad, 0x6b96, 0xbaa7, 0x6b92, 0xbaa2,
+  0x6b8f, 0xba9d, 0x6b8b, 0xba97, 0x6b88, 0xba92, 0x6b85, 0xba8d,
+  0x6b81, 0xba88, 0x6b7e, 0xba82, 0x6b7a, 0xba7d, 0x6b77, 0xba78,
+  0x6b73, 0xba73, 0x6b70, 0xba6d, 0x6b6d, 0xba68, 0x6b69, 0xba63,
+  0x6b66, 0xba5d, 0x6b62, 0xba58, 0x6b5f, 0xba53, 0x6b5c, 0xba4e,
+  0x6b58, 0xba48, 0x6b55, 0xba43, 0x6b51, 0xba3e, 0x6b4e, 0xba39,
+  0x6b4a, 0xba33, 0x6b47, 0xba2e, 0x6b44, 0xba29, 0x6b40, 0xba23,
+  0x6b3d, 0xba1e, 0x6b39, 0xba19, 0x6b36, 0xba14, 0x6b32, 0xba0e,
+  0x6b2f, 0xba09, 0x6b2c, 0xba04, 0x6b28, 0xb9ff, 0x6b25, 0xb9f9,
+  0x6b21, 0xb9f4, 0x6b1e, 0xb9ef, 0x6b1a, 0xb9ea, 0x6b17, 0xb9e4,
+  0x6b13, 0xb9df, 0x6b10, 0xb9da, 0x6b0d, 0xb9d5, 0x6b09, 0xb9cf,
+  0x6b06, 0xb9ca, 0x6b02, 0xb9c5, 0x6aff, 0xb9c0, 0x6afb, 0xb9ba,
+  0x6af8, 0xb9b5, 0x6af4, 0xb9b0, 0x6af1, 0xb9ab, 0x6aee, 0xb9a5,
+  0x6aea, 0xb9a0, 0x6ae7, 0xb99b, 0x6ae3, 0xb996, 0x6ae0, 0xb990,
+  0x6adc, 0xb98b, 0x6ad9, 0xb986, 0x6ad5, 0xb981, 0x6ad2, 0xb97b,
+  0x6ace, 0xb976, 0x6acb, 0xb971, 0x6ac8, 0xb96c, 0x6ac4, 0xb966,
+  0x6ac1, 0xb961, 0x6abd, 0xb95c, 0x6aba, 0xb957, 0x6ab6, 0xb951,
+  0x6ab3, 0xb94c, 0x6aaf, 0xb947, 0x6aac, 0xb942, 0x6aa8, 0xb93c,
+  0x6aa5, 0xb937, 0x6aa1, 0xb932, 0x6a9e, 0xb92d, 0x6a9a, 0xb928,
+  0x6a97, 0xb922, 0x6a93, 0xb91d, 0x6a90, 0xb918, 0x6a8c, 0xb913,
+  0x6a89, 0xb90d, 0x6a86, 0xb908, 0x6a82, 0xb903, 0x6a7f, 0xb8fe,
+  0x6a7b, 0xb8f8, 0x6a78, 0xb8f3, 0x6a74, 0xb8ee, 0x6a71, 0xb8e9,
+  0x6a6d, 0xb8e4, 0x6a6a, 0xb8de, 0x6a66, 0xb8d9, 0x6a63, 0xb8d4,
+  0x6a5f, 0xb8cf, 0x6a5c, 0xb8c9, 0x6a58, 0xb8c4, 0x6a55, 0xb8bf,
+  0x6a51, 0xb8ba, 0x6a4e, 0xb8b5, 0x6a4a, 0xb8af, 0x6a47, 0xb8aa,
+  0x6a43, 0xb8a5, 0x6a40, 0xb8a0, 0x6a3c, 0xb89b, 0x6a39, 0xb895,
+  0x6a35, 0xb890, 0x6a32, 0xb88b, 0x6a2e, 0xb886, 0x6a2b, 0xb880,
+  0x6a27, 0xb87b, 0x6a24, 0xb876, 0x6a20, 0xb871, 0x6a1d, 0xb86c,
+  0x6a19, 0xb866, 0x6a16, 0xb861, 0x6a12, 0xb85c, 0x6a0e, 0xb857,
+  0x6a0b, 0xb852, 0x6a07, 0xb84c, 0x6a04, 0xb847, 0x6a00, 0xb842,
+  0x69fd, 0xb83d, 0x69f9, 0xb838, 0x69f6, 0xb832, 0x69f2, 0xb82d,
+  0x69ef, 0xb828, 0x69eb, 0xb823, 0x69e8, 0xb81e, 0x69e4, 0xb818,
+  0x69e1, 0xb813, 0x69dd, 0xb80e, 0x69da, 0xb809, 0x69d6, 0xb804,
+  0x69d3, 0xb7fe, 0x69cf, 0xb7f9, 0x69cb, 0xb7f4, 0x69c8, 0xb7ef,
+  0x69c4, 0xb7ea, 0x69c1, 0xb7e4, 0x69bd, 0xb7df, 0x69ba, 0xb7da,
+  0x69b6, 0xb7d5, 0x69b3, 0xb7d0, 0x69af, 0xb7ca, 0x69ac, 0xb7c5,
+  0x69a8, 0xb7c0, 0x69a5, 0xb7bb, 0x69a1, 0xb7b6, 0x699d, 0xb7b1,
+  0x699a, 0xb7ab, 0x6996, 0xb7a6, 0x6993, 0xb7a1, 0x698f, 0xb79c,
+  0x698c, 0xb797, 0x6988, 0xb791, 0x6985, 0xb78c, 0x6981, 0xb787,
+  0x697d, 0xb782, 0x697a, 0xb77d, 0x6976, 0xb778, 0x6973, 0xb772,
+  0x696f, 0xb76d, 0x696c, 0xb768, 0x6968, 0xb763, 0x6964, 0xb75e,
+  0x6961, 0xb758, 0x695d, 0xb753, 0x695a, 0xb74e, 0x6956, 0xb749,
+  0x6953, 0xb744, 0x694f, 0xb73f, 0x694b, 0xb739, 0x6948, 0xb734,
+  0x6944, 0xb72f, 0x6941, 0xb72a, 0x693d, 0xb725, 0x693a, 0xb720,
+  0x6936, 0xb71a, 0x6932, 0xb715, 0x692f, 0xb710, 0x692b, 0xb70b,
+  0x6928, 0xb706, 0x6924, 0xb701, 0x6921, 0xb6fb, 0x691d, 0xb6f6,
+  0x6919, 0xb6f1, 0x6916, 0xb6ec, 0x6912, 0xb6e7, 0x690f, 0xb6e2,
+  0x690b, 0xb6dd, 0x6907, 0xb6d7, 0x6904, 0xb6d2, 0x6900, 0xb6cd,
+  0x68fd, 0xb6c8, 0x68f9, 0xb6c3, 0x68f5, 0xb6be, 0x68f2, 0xb6b8,
+  0x68ee, 0xb6b3, 0x68eb, 0xb6ae, 0x68e7, 0xb6a9, 0x68e3, 0xb6a4,
+  0x68e0, 0xb69f, 0x68dc, 0xb69a, 0x68d9, 0xb694, 0x68d5, 0xb68f,
+  0x68d1, 0xb68a, 0x68ce, 0xb685, 0x68ca, 0xb680, 0x68c7, 0xb67b,
+  0x68c3, 0xb676, 0x68bf, 0xb670, 0x68bc, 0xb66b, 0x68b8, 0xb666,
+  0x68b5, 0xb661, 0x68b1, 0xb65c, 0x68ad, 0xb657, 0x68aa, 0xb652,
+  0x68a6, 0xb64c, 0x68a3, 0xb647, 0x689f, 0xb642, 0x689b, 0xb63d,
+  0x6898, 0xb638, 0x6894, 0xb633, 0x6890, 0xb62e, 0x688d, 0xb628,
+  0x6889, 0xb623, 0x6886, 0xb61e, 0x6882, 0xb619, 0x687e, 0xb614,
+  0x687b, 0xb60f, 0x6877, 0xb60a, 0x6873, 0xb605, 0x6870, 0xb5ff,
+  0x686c, 0xb5fa, 0x6868, 0xb5f5, 0x6865, 0xb5f0, 0x6861, 0xb5eb,
+  0x685e, 0xb5e6, 0x685a, 0xb5e1, 0x6856, 0xb5dc, 0x6853, 0xb5d6,
+  0x684f, 0xb5d1, 0x684b, 0xb5cc, 0x6848, 0xb5c7, 0x6844, 0xb5c2,
+  0x6840, 0xb5bd, 0x683d, 0xb5b8, 0x6839, 0xb5b3, 0x6835, 0xb5ae,
+  0x6832, 0xb5a8, 0x682e, 0xb5a3, 0x682b, 0xb59e, 0x6827, 0xb599,
+  0x6823, 0xb594, 0x6820, 0xb58f, 0x681c, 0xb58a, 0x6818, 0xb585,
+  0x6815, 0xb57f, 0x6811, 0xb57a, 0x680d, 0xb575, 0x680a, 0xb570,
+  0x6806, 0xb56b, 0x6802, 0xb566, 0x67ff, 0xb561, 0x67fb, 0xb55c,
+  0x67f7, 0xb557, 0x67f4, 0xb552, 0x67f0, 0xb54c, 0x67ec, 0xb547,
+  0x67e9, 0xb542, 0x67e5, 0xb53d, 0x67e1, 0xb538, 0x67de, 0xb533,
+  0x67da, 0xb52e, 0x67d6, 0xb529, 0x67d3, 0xb524, 0x67cf, 0xb51f,
+  0x67cb, 0xb519, 0x67c8, 0xb514, 0x67c4, 0xb50f, 0x67c0, 0xb50a,
+  0x67bd, 0xb505, 0x67b9, 0xb500, 0x67b5, 0xb4fb, 0x67b2, 0xb4f6,
+  0x67ae, 0xb4f1, 0x67aa, 0xb4ec, 0x67a6, 0xb4e7, 0x67a3, 0xb4e1,
+  0x679f, 0xb4dc, 0x679b, 0xb4d7, 0x6798, 0xb4d2, 0x6794, 0xb4cd,
+  0x6790, 0xb4c8, 0x678d, 0xb4c3, 0x6789, 0xb4be, 0x6785, 0xb4b9,
+  0x6782, 0xb4b4, 0x677e, 0xb4af, 0x677a, 0xb4aa, 0x6776, 0xb4a4,
+  0x6773, 0xb49f, 0x676f, 0xb49a, 0x676b, 0xb495, 0x6768, 0xb490,
+  0x6764, 0xb48b, 0x6760, 0xb486, 0x675d, 0xb481, 0x6759, 0xb47c,
+  0x6755, 0xb477, 0x6751, 0xb472, 0x674e, 0xb46d, 0x674a, 0xb468,
+  0x6746, 0xb462, 0x6743, 0xb45d, 0x673f, 0xb458, 0x673b, 0xb453,
+  0x6737, 0xb44e, 0x6734, 0xb449, 0x6730, 0xb444, 0x672c, 0xb43f,
+  0x6729, 0xb43a, 0x6725, 0xb435, 0x6721, 0xb430, 0x671d, 0xb42b,
+  0x671a, 0xb426, 0x6716, 0xb421, 0x6712, 0xb41c, 0x670e, 0xb417,
+  0x670b, 0xb411, 0x6707, 0xb40c, 0x6703, 0xb407, 0x6700, 0xb402,
+  0x66fc, 0xb3fd, 0x66f8, 0xb3f8, 0x66f4, 0xb3f3, 0x66f1, 0xb3ee,
+  0x66ed, 0xb3e9, 0x66e9, 0xb3e4, 0x66e5, 0xb3df, 0x66e2, 0xb3da,
+  0x66de, 0xb3d5, 0x66da, 0xb3d0, 0x66d6, 0xb3cb, 0x66d3, 0xb3c6,
+  0x66cf, 0xb3c1, 0x66cb, 0xb3bc, 0x66c8, 0xb3b7, 0x66c4, 0xb3b1,
+  0x66c0, 0xb3ac, 0x66bc, 0xb3a7, 0x66b9, 0xb3a2, 0x66b5, 0xb39d,
+  0x66b1, 0xb398, 0x66ad, 0xb393, 0x66aa, 0xb38e, 0x66a6, 0xb389,
+  0x66a2, 0xb384, 0x669e, 0xb37f, 0x669b, 0xb37a, 0x6697, 0xb375,
+  0x6693, 0xb370, 0x668f, 0xb36b, 0x668b, 0xb366, 0x6688, 0xb361,
+  0x6684, 0xb35c, 0x6680, 0xb357, 0x667c, 0xb352, 0x6679, 0xb34d,
+  0x6675, 0xb348, 0x6671, 0xb343, 0x666d, 0xb33e, 0x666a, 0xb339,
+  0x6666, 0xb334, 0x6662, 0xb32f, 0x665e, 0xb32a, 0x665b, 0xb325,
+  0x6657, 0xb31f, 0x6653, 0xb31a, 0x664f, 0xb315, 0x664b, 0xb310,
+  0x6648, 0xb30b, 0x6644, 0xb306, 0x6640, 0xb301, 0x663c, 0xb2fc,
+  0x6639, 0xb2f7, 0x6635, 0xb2f2, 0x6631, 0xb2ed, 0x662d, 0xb2e8,
+  0x6629, 0xb2e3, 0x6626, 0xb2de, 0x6622, 0xb2d9, 0x661e, 0xb2d4,
+  0x661a, 0xb2cf, 0x6616, 0xb2ca, 0x6613, 0xb2c5, 0x660f, 0xb2c0,
+  0x660b, 0xb2bb, 0x6607, 0xb2b6, 0x6603, 0xb2b1, 0x6600, 0xb2ac,
+  0x65fc, 0xb2a7, 0x65f8, 0xb2a2, 0x65f4, 0xb29d, 0x65f0, 0xb298,
+  0x65ed, 0xb293, 0x65e9, 0xb28e, 0x65e5, 0xb289, 0x65e1, 0xb284,
+  0x65dd, 0xb27f, 0x65da, 0xb27a, 0x65d6, 0xb275, 0x65d2, 0xb270,
+  0x65ce, 0xb26b, 0x65ca, 0xb266, 0x65c7, 0xb261, 0x65c3, 0xb25c,
+  0x65bf, 0xb257, 0x65bb, 0xb252, 0x65b7, 0xb24d, 0x65b4, 0xb248,
+  0x65b0, 0xb243, 0x65ac, 0xb23e, 0x65a8, 0xb239, 0x65a4, 0xb234,
+  0x65a0, 0xb22f, 0x659d, 0xb22a, 0x6599, 0xb225, 0x6595, 0xb220,
+  0x6591, 0xb21b, 0x658d, 0xb216, 0x658a, 0xb211, 0x6586, 0xb20c,
+  0x6582, 0xb207, 0x657e, 0xb202, 0x657a, 0xb1fd, 0x6576, 0xb1f8,
+  0x6573, 0xb1f3, 0x656f, 0xb1ee, 0x656b, 0xb1e9, 0x6567, 0xb1e4,
+  0x6563, 0xb1df, 0x655f, 0xb1da, 0x655c, 0xb1d6, 0x6558, 0xb1d1,
+  0x6554, 0xb1cc, 0x6550, 0xb1c7, 0x654c, 0xb1c2, 0x6548, 0xb1bd,
+  0x6545, 0xb1b8, 0x6541, 0xb1b3, 0x653d, 0xb1ae, 0x6539, 0xb1a9,
+  0x6535, 0xb1a4, 0x6531, 0xb19f, 0x652d, 0xb19a, 0x652a, 0xb195,
+  0x6526, 0xb190, 0x6522, 0xb18b, 0x651e, 0xb186, 0x651a, 0xb181,
+  0x6516, 0xb17c, 0x6513, 0xb177, 0x650f, 0xb172, 0x650b, 0xb16d,
+  0x6507, 0xb168, 0x6503, 0xb163, 0x64ff, 0xb15e, 0x64fb, 0xb159,
+  0x64f7, 0xb154, 0x64f4, 0xb14f, 0x64f0, 0xb14a, 0x64ec, 0xb146,
+  0x64e8, 0xb141, 0x64e4, 0xb13c, 0x64e0, 0xb137, 0x64dc, 0xb132,
+  0x64d9, 0xb12d, 0x64d5, 0xb128, 0x64d1, 0xb123, 0x64cd, 0xb11e,
+  0x64c9, 0xb119, 0x64c5, 0xb114, 0x64c1, 0xb10f, 0x64bd, 0xb10a,
+  0x64ba, 0xb105, 0x64b6, 0xb100, 0x64b2, 0xb0fb, 0x64ae, 0xb0f6,
+  0x64aa, 0xb0f1, 0x64a6, 0xb0ec, 0x64a2, 0xb0e8, 0x649e, 0xb0e3,
+  0x649b, 0xb0de, 0x6497, 0xb0d9, 0x6493, 0xb0d4, 0x648f, 0xb0cf,
+  0x648b, 0xb0ca, 0x6487, 0xb0c5, 0x6483, 0xb0c0, 0x647f, 0xb0bb,
+  0x647b, 0xb0b6, 0x6478, 0xb0b1, 0x6474, 0xb0ac, 0x6470, 0xb0a7,
+  0x646c, 0xb0a2, 0x6468, 0xb09e, 0x6464, 0xb099, 0x6460, 0xb094,
+  0x645c, 0xb08f, 0x6458, 0xb08a, 0x6454, 0xb085, 0x6451, 0xb080,
+  0x644d, 0xb07b, 0x6449, 0xb076, 0x6445, 0xb071, 0x6441, 0xb06c,
+  0x643d, 0xb067, 0x6439, 0xb062, 0x6435, 0xb05e, 0x6431, 0xb059,
+  0x642d, 0xb054, 0x6429, 0xb04f, 0x6426, 0xb04a, 0x6422, 0xb045,
+  0x641e, 0xb040, 0x641a, 0xb03b, 0x6416, 0xb036, 0x6412, 0xb031,
+  0x640e, 0xb02c, 0x640a, 0xb027, 0x6406, 0xb023, 0x6402, 0xb01e,
+  0x63fe, 0xb019, 0x63fa, 0xb014, 0x63f7, 0xb00f, 0x63f3, 0xb00a,
+  0x63ef, 0xb005, 0x63eb, 0xb000, 0x63e7, 0xaffb, 0x63e3, 0xaff6,
+  0x63df, 0xaff1, 0x63db, 0xafed, 0x63d7, 0xafe8, 0x63d3, 0xafe3,
+  0x63cf, 0xafde, 0x63cb, 0xafd9, 0x63c7, 0xafd4, 0x63c3, 0xafcf,
+  0x63c0, 0xafca, 0x63bc, 0xafc5, 0x63b8, 0xafc1, 0x63b4, 0xafbc,
+  0x63b0, 0xafb7, 0x63ac, 0xafb2, 0x63a8, 0xafad, 0x63a4, 0xafa8,
+  0x63a0, 0xafa3, 0x639c, 0xaf9e, 0x6398, 0xaf99, 0x6394, 0xaf94,
+  0x6390, 0xaf90, 0x638c, 0xaf8b, 0x6388, 0xaf86, 0x6384, 0xaf81,
+  0x6380, 0xaf7c, 0x637c, 0xaf77, 0x6378, 0xaf72, 0x6375, 0xaf6d,
+  0x6371, 0xaf69, 0x636d, 0xaf64, 0x6369, 0xaf5f, 0x6365, 0xaf5a,
+  0x6361, 0xaf55, 0x635d, 0xaf50, 0x6359, 0xaf4b, 0x6355, 0xaf46,
+  0x6351, 0xaf41, 0x634d, 0xaf3d, 0x6349, 0xaf38, 0x6345, 0xaf33,
+  0x6341, 0xaf2e, 0x633d, 0xaf29, 0x6339, 0xaf24, 0x6335, 0xaf1f,
+  0x6331, 0xaf1b, 0x632d, 0xaf16, 0x6329, 0xaf11, 0x6325, 0xaf0c,
+  0x6321, 0xaf07, 0x631d, 0xaf02, 0x6319, 0xaefd, 0x6315, 0xaef8,
+  0x6311, 0xaef4, 0x630d, 0xaeef, 0x6309, 0xaeea, 0x6305, 0xaee5,
+  0x6301, 0xaee0, 0x62fd, 0xaedb, 0x62f9, 0xaed6, 0x62f5, 0xaed2,
+  0x62f2, 0xaecd, 0x62ee, 0xaec8, 0x62ea, 0xaec3, 0x62e6, 0xaebe,
+  0x62e2, 0xaeb9, 0x62de, 0xaeb4, 0x62da, 0xaeb0, 0x62d6, 0xaeab,
+  0x62d2, 0xaea6, 0x62ce, 0xaea1, 0x62ca, 0xae9c, 0x62c6, 0xae97,
+  0x62c2, 0xae92, 0x62be, 0xae8e, 0x62ba, 0xae89, 0x62b6, 0xae84,
+  0x62b2, 0xae7f, 0x62ae, 0xae7a, 0x62aa, 0xae75, 0x62a6, 0xae71,
+  0x62a2, 0xae6c, 0x629e, 0xae67, 0x629a, 0xae62, 0x6296, 0xae5d,
+  0x6292, 0xae58, 0x628e, 0xae54, 0x628a, 0xae4f, 0x6286, 0xae4a,
+  0x6282, 0xae45, 0x627e, 0xae40, 0x627a, 0xae3b, 0x6275, 0xae37,
+  0x6271, 0xae32, 0x626d, 0xae2d, 0x6269, 0xae28, 0x6265, 0xae23,
+  0x6261, 0xae1e, 0x625d, 0xae1a, 0x6259, 0xae15, 0x6255, 0xae10,
+  0x6251, 0xae0b, 0x624d, 0xae06, 0x6249, 0xae01, 0x6245, 0xadfd,
+  0x6241, 0xadf8, 0x623d, 0xadf3, 0x6239, 0xadee, 0x6235, 0xade9,
+  0x6231, 0xade4, 0x622d, 0xade0, 0x6229, 0xaddb, 0x6225, 0xadd6,
+  0x6221, 0xadd1, 0x621d, 0xadcc, 0x6219, 0xadc8, 0x6215, 0xadc3,
+  0x6211, 0xadbe, 0x620d, 0xadb9, 0x6209, 0xadb4, 0x6205, 0xadaf,
+  0x6201, 0xadab, 0x61fd, 0xada6, 0x61f9, 0xada1, 0x61f5, 0xad9c,
+  0x61f1, 0xad97, 0x61ec, 0xad93, 0x61e8, 0xad8e, 0x61e4, 0xad89,
+  0x61e0, 0xad84, 0x61dc, 0xad7f, 0x61d8, 0xad7b, 0x61d4, 0xad76,
+  0x61d0, 0xad71, 0x61cc, 0xad6c, 0x61c8, 0xad67, 0x61c4, 0xad63,
+  0x61c0, 0xad5e, 0x61bc, 0xad59, 0x61b8, 0xad54, 0x61b4, 0xad4f,
+  0x61b0, 0xad4b, 0x61ac, 0xad46, 0x61a8, 0xad41, 0x61a3, 0xad3c,
+  0x619f, 0xad37, 0x619b, 0xad33, 0x6197, 0xad2e, 0x6193, 0xad29,
+  0x618f, 0xad24, 0x618b, 0xad1f, 0x6187, 0xad1b, 0x6183, 0xad16,
+  0x617f, 0xad11, 0x617b, 0xad0c, 0x6177, 0xad08, 0x6173, 0xad03,
+  0x616f, 0xacfe, 0x616b, 0xacf9, 0x6166, 0xacf4, 0x6162, 0xacf0,
+  0x615e, 0xaceb, 0x615a, 0xace6, 0x6156, 0xace1, 0x6152, 0xacdd,
+  0x614e, 0xacd8, 0x614a, 0xacd3, 0x6146, 0xacce, 0x6142, 0xacc9,
+  0x613e, 0xacc5, 0x613a, 0xacc0, 0x6135, 0xacbb, 0x6131, 0xacb6,
+  0x612d, 0xacb2, 0x6129, 0xacad, 0x6125, 0xaca8, 0x6121, 0xaca3,
+  0x611d, 0xac9e, 0x6119, 0xac9a, 0x6115, 0xac95, 0x6111, 0xac90,
+  0x610d, 0xac8b, 0x6108, 0xac87, 0x6104, 0xac82, 0x6100, 0xac7d,
+  0x60fc, 0xac78, 0x60f8, 0xac74, 0x60f4, 0xac6f, 0x60f0, 0xac6a,
+  0x60ec, 0xac65, 0x60e8, 0xac61, 0x60e4, 0xac5c, 0x60df, 0xac57,
+  0x60db, 0xac52, 0x60d7, 0xac4e, 0x60d3, 0xac49, 0x60cf, 0xac44,
+  0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,
+  0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,
+  0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,
+  0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,
+  0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,
+  0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,
+  0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,
+  0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,
+  0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,
+  0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,
+  0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,
+  0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,
+  0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,
+  0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,
+  0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,
+  0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,
+  0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,
+  0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,
+  0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,
+  0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,
+  0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,
+  0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,
+  0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,
+  0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,
+  0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,
+  0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,
+  0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,
+  0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,
+  0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,
+  0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,
+  0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,
+  0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,
+  0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,
+  0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,
+  0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,
+  0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,
+  0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,
+  0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,
+  0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,
+  0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,
+  0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,
+  0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,
+  0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,
+  0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,
+  0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,
+  0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
+  0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
+  0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
+  0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
+  0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
+  0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
+  0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
+  0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
+  0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
+  0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
+  0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
+  0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
+  0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
+  0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
+  0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
+  0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
+  0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
+  0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
+  0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
+  0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
+  0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
+  0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
+  0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
+  0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
+  0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
+  0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
+  0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
+  0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
+  0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
+  0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
+  0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
+  0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
+  0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
+  0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
+  0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
+  0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
+  0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
+  0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
+  0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
+  0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
+  0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
+  0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
+  0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
+  0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
+  0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
+  0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
+  0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
+  0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
+  0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
+  0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
+  0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
+  0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
+  0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
+  0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
+  0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
+  0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
+  0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
+  0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
+  0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
+  0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
+  0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
+  0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
+  0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
+  0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
+  0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
+  0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
+  0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
+  0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
+  0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
+  0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
+  0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
+  0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
+  0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
+  0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
+  0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
+  0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
+  0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
+  0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
+  0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
+  0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
+  0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
+  0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
+  0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
+  0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
+  0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
+  0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
+  0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
+  0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
+  0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
+  0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
+  0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
+  0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
+  0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
+  0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
+  0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
+  0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
+  0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
+  0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
+  0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
+  0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
+  0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
+  0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
+  0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
+  0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
+  0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
+  0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
+  0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
+  0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,
+  0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
+  0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
+  0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
+  0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
+  0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
+  0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
+  0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,
+  0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,
+  0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
+  0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
+  0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,
+  0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
+  0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,
+  0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
+  0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,
+  0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,
+  0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,
+  0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,
+  0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,
+  0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,
+  0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,
+  0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,
+  0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
+  0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
+  0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
+  0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
+  0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,
+  0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,
+  0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,
+  0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,
+  0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,
+  0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,
+  0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,
+  0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,
+  0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,
+  0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,
+  0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,
+  0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,
+  0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,
+  0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,
+  0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,
+  0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,
+  0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,
+  0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,
+  0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,
+  0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,
+  0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,
+  0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,
+  0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,
+  0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,
+  0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,
+  0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,
+  0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,
+  0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,
+  0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,
+  0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,
+  0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,
+  0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,
+  0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,
+  0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,
+  0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,
+  0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,
+  0x51bb, 0x9d7e, 0x51b6, 0x9d7a, 0x51b1, 0x9d76, 0x51ac, 0x9d72,
+  0x51a8, 0x9d6e, 0x51a3, 0x9d6a, 0x519e, 0x9d66, 0x5199, 0x9d62,
+  0x5194, 0x9d5e, 0x518f, 0x9d5a, 0x518b, 0x9d56, 0x5186, 0x9d52,
+  0x5181, 0x9d4e, 0x517c, 0x9d4a, 0x5177, 0x9d46, 0x5172, 0x9d42,
+  0x516e, 0x9d3e, 0x5169, 0x9d3a, 0x5164, 0x9d36, 0x515f, 0x9d32,
+  0x515a, 0x9d2e, 0x5155, 0x9d2a, 0x5150, 0x9d26, 0x514c, 0x9d22,
+  0x5147, 0x9d1e, 0x5142, 0x9d1a, 0x513d, 0x9d16, 0x5138, 0x9d12,
+  0x5133, 0x9d0e, 0x512e, 0x9d0b, 0x512a, 0x9d07, 0x5125, 0x9d03,
+  0x5120, 0x9cff, 0x511b, 0x9cfb, 0x5116, 0x9cf7, 0x5111, 0x9cf3,
+  0x510c, 0x9cef, 0x5108, 0x9ceb, 0x5103, 0x9ce7, 0x50fe, 0x9ce3,
+  0x50f9, 0x9cdf, 0x50f4, 0x9cdb, 0x50ef, 0x9cd7, 0x50ea, 0x9cd3,
+  0x50e5, 0x9ccf, 0x50e1, 0x9ccb, 0x50dc, 0x9cc7, 0x50d7, 0x9cc3,
+  0x50d2, 0x9cbf, 0x50cd, 0x9cbb, 0x50c8, 0x9cb7, 0x50c3, 0x9cb3,
+  0x50bf, 0x9caf, 0x50ba, 0x9cab, 0x50b5, 0x9ca7, 0x50b0, 0x9ca3,
+  0x50ab, 0x9c9f, 0x50a6, 0x9c9b, 0x50a1, 0x9c97, 0x509c, 0x9c93,
+  0x5097, 0x9c8f, 0x5093, 0x9c8b, 0x508e, 0x9c88, 0x5089, 0x9c84,
+  0x5084, 0x9c80, 0x507f, 0x9c7c, 0x507a, 0x9c78, 0x5075, 0x9c74,
+  0x5070, 0x9c70, 0x506c, 0x9c6c, 0x5067, 0x9c68, 0x5062, 0x9c64,
+  0x505d, 0x9c60, 0x5058, 0x9c5c, 0x5053, 0x9c58, 0x504e, 0x9c54,
+  0x5049, 0x9c50, 0x5044, 0x9c4c, 0x503f, 0x9c48, 0x503b, 0x9c44,
+  0x5036, 0x9c40, 0x5031, 0x9c3d, 0x502c, 0x9c39, 0x5027, 0x9c35,
+  0x5022, 0x9c31, 0x501d, 0x9c2d, 0x5018, 0x9c29, 0x5013, 0x9c25,
+  0x500f, 0x9c21, 0x500a, 0x9c1d, 0x5005, 0x9c19, 0x5000, 0x9c15,
+  0x4ffb, 0x9c11, 0x4ff6, 0x9c0d, 0x4ff1, 0x9c09, 0x4fec, 0x9c06,
+  0x4fe7, 0x9c02, 0x4fe2, 0x9bfe, 0x4fdd, 0x9bfa, 0x4fd9, 0x9bf6,
+  0x4fd4, 0x9bf2, 0x4fcf, 0x9bee, 0x4fca, 0x9bea, 0x4fc5, 0x9be6,
+  0x4fc0, 0x9be2, 0x4fbb, 0x9bde, 0x4fb6, 0x9bda, 0x4fb1, 0x9bd7,
+  0x4fac, 0x9bd3, 0x4fa7, 0x9bcf, 0x4fa2, 0x9bcb, 0x4f9e, 0x9bc7,
+  0x4f99, 0x9bc3, 0x4f94, 0x9bbf, 0x4f8f, 0x9bbb, 0x4f8a, 0x9bb7,
+  0x4f85, 0x9bb3, 0x4f80, 0x9baf, 0x4f7b, 0x9bac, 0x4f76, 0x9ba8,
+  0x4f71, 0x9ba4, 0x4f6c, 0x9ba0, 0x4f67, 0x9b9c, 0x4f62, 0x9b98,
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+  0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,
+  0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,
+  0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,
+  0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,
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+  0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,
+  0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,
+  0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,
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+  0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,
+  0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,
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+  0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,
+  0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,
+  0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,
+  0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,
+  0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,
+  0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,
+  0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,
+  0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,
+  0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,
+  0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,
+  0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,
+  0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,
+  0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,
+  0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,
+  0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,
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+  0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,
+  0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,
+  0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,
+  0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,
+  0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,
+  0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,
+  0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,
+  0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,
+  0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,
+  0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,
+  0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,
+  0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,
+  0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,
+  0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,
+  0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,
+  0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,
+  0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,
+  0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,
+  0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,
+  0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,
+  0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,
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+  0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,
+  0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,
+  0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,
+  0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,
+  0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,
+  0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,
+  0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,
+  0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,
+  0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,
+  0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,
+  0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,
+  0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,
+  0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,
+  0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,
+  0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,
+  0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,
+  0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,
+  0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,
+  0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,
+  0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,
+  0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,
+  0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,
+  0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,
+  0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,
+  0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,
+  0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,
+  0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,
+  0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,
+  0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,
+  0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,
+  0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,
+  0x2b4e, 0x878d, 0x2b48, 0x878b, 0x2b42, 0x8789, 0x2b3c, 0x8787,
+  0x2b36, 0x8784, 0x2b30, 0x8782, 0x2b2b, 0x8780, 0x2b25, 0x877e,
+  0x2b1f, 0x877c, 0x2b19, 0x877a, 0x2b13, 0x8778, 0x2b0d, 0x8776,
+  0x2b07, 0x8774, 0x2b01, 0x8771, 0x2afb, 0x876f, 0x2af5, 0x876d,
+  0x2aef, 0x876b, 0x2ae9, 0x8769, 0x2ae4, 0x8767, 0x2ade, 0x8765,
+  0x2ad8, 0x8763, 0x2ad2, 0x8761, 0x2acc, 0x875e, 0x2ac6, 0x875c,
+  0x2ac0, 0x875a, 0x2aba, 0x8758, 0x2ab4, 0x8756, 0x2aae, 0x8754,
+  0x2aa8, 0x8752, 0x2aa2, 0x8750, 0x2a9c, 0x874e, 0x2a97, 0x874c,
+  0x2a91, 0x874a, 0x2a8b, 0x8747, 0x2a85, 0x8745, 0x2a7f, 0x8743,
+  0x2a79, 0x8741, 0x2a73, 0x873f, 0x2a6d, 0x873d, 0x2a67, 0x873b,
+  0x2a61, 0x8739, 0x2a5b, 0x8737, 0x2a55, 0x8735, 0x2a4f, 0x8733,
+  0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,
+  0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,
+  0x2a1a, 0x8720, 0x2a14, 0x871e, 0x2a0e, 0x871c, 0x2a08, 0x871a,
+  0x2a02, 0x8718, 0x29fc, 0x8716, 0x29f6, 0x8714, 0x29f0, 0x8712,
+  0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,
+  0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,
+  0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,
+  0x29a3, 0x86f7, 0x299d, 0x86f5, 0x2997, 0x86f3, 0x2991, 0x86f1,
+  0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,
+  0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,
+  0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,
+  0x2944, 0x86d6, 0x293e, 0x86d4, 0x2938, 0x86d2, 0x2932, 0x86d0,
+  0x292c, 0x86ce, 0x2926, 0x86cc, 0x2920, 0x86ca, 0x291b, 0x86c8,
+  0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,
+  0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,
+  0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,
+  0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,
+  0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,
+  0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,
+  0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,
+  0x286e, 0x868e, 0x2868, 0x868c, 0x2862, 0x868a, 0x285c, 0x8688,
+  0x2856, 0x8686, 0x2850, 0x8684, 0x284a, 0x8682, 0x2844, 0x8680,
+  0x283e, 0x867e, 0x2838, 0x867c, 0x2832, 0x867a, 0x282c, 0x8678,
+  0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,
+  0x280e, 0x866e, 0x2808, 0x866d, 0x2802, 0x866b, 0x27fc, 0x8669,
+  0x27f6, 0x8667, 0x27f1, 0x8665, 0x27eb, 0x8663, 0x27e5, 0x8661,
+  0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,
+  0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,
+  0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,
+  0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,
+  0x277f, 0x8640, 0x2779, 0x863e, 0x2773, 0x863c, 0x276d, 0x863a,
+  0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,
+  0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,
+  0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,
+  0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,
+  0x2707, 0x8619, 0x2701, 0x8617, 0x26fb, 0x8615, 0x26f5, 0x8613,
+  0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,
+  0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,
+  0x26c0, 0x8602, 0x26ba, 0x8600, 0x26b4, 0x85fe, 0x26ae, 0x85fc,
+  0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,
+  0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,
+  0x2678, 0x85eb, 0x2672, 0x85ea, 0x266c, 0x85e8, 0x2666, 0x85e6,
+  0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,
+  0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,
+  0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,
+  0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,
+  0x2600, 0x85c6, 0x25fa, 0x85c4, 0x25f4, 0x85c2, 0x25ee, 0x85c0,
+  0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,
+  0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,
+  0x25b8, 0x85b0, 0x25b2, 0x85ae, 0x25ac, 0x85ac, 0x25a6, 0x85aa,
+  0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,
+  0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,
+  0x2570, 0x8599, 0x256a, 0x8598, 0x2564, 0x8596, 0x255e, 0x8594,
+  0x2558, 0x8592, 0x2552, 0x8590, 0x254c, 0x858e, 0x2546, 0x858d,
+  0x2540, 0x858b, 0x253a, 0x8589, 0x2534, 0x8587, 0x252e, 0x8585,
+  0x2528, 0x8583, 0x2522, 0x8582, 0x251c, 0x8580, 0x2516, 0x857e,
+  0x250f, 0x857c, 0x2509, 0x857a, 0x2503, 0x8579, 0x24fd, 0x8577,
+  0x24f7, 0x8575, 0x24f1, 0x8573, 0x24eb, 0x8571, 0x24e5, 0x856f,
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+  0x24c7, 0x8566, 0x24c1, 0x8565, 0x24bb, 0x8563, 0x24b5, 0x8561,
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+  0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,
+  0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,
+  0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,
+  0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,
+  0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,
+  0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,
+  0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,
+  0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,
+  0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,
+  0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,
+  0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,
+  0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,
+  0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,
+  0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,
+  0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,
+  0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,
+  0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,
+  0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,
+  0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,
+  0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,
+  0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,
+  0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,
+  0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,
+  0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,
+  0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,
+  0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,
+  0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,
+  0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,
+  0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,
+  0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,
+  0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,
+  0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,
+  0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,
+  0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,
+  0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,
+  0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,
+  0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,
+  0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,
+  0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,
+  0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,
+  0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,
+  0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,
+  0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,
+  0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,
+  0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,
+  0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,
+  0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,
+  0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,
+  0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,
+  0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,
+  0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,
+  0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,
+  0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,
+  0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,
+  0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,
+  0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,
+  0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,
+  0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,
+  0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,
+  0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,
+  0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,
+  0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,
+  0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,
+  0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,
+  0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,
+  0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,
+  0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,
+  0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,
+  0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,
+  0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,
+  0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,
+  0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,
+  0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,
+  0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,
+  0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,
+  0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,
+  0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,
+  0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,
+  0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,
+  0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,
+  0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,
+  0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,
+  0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,
+  0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,
+  0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,
+  0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,
+  0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,
+  0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,
+  0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,
+  0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,
+  0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,
+  0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,
+  0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,
+  0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,
+  0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,
+  0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,
+  0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,
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+  0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,
+  0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,
+  0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,
+  0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,
+  0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,
+  0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,
+  0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,
+  0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,
+  0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,
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+  0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,
+  0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,
+  0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,
+  0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,
+  0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,
+  0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,
+  0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,
+  0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,
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+  0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,
+  0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,
+  0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,
+  0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,
+  0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,
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+  0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,
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+  0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,
+  0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,
+  0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,
+  0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,
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+  0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,
+  0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,
+  0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,
+  0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,
+  0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,
+  0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,
+  0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,
+  0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,
+  0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,
+  0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,
+  0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,
+  0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,
+  0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,
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+  0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,
+  0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,
+  0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,
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+  0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,
+  0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,
+  0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,
+  0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,
+  0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,
+  0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,
+  0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,
+  0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,
+  0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,
+  0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
+  0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
+  0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
+  0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
+  0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
+  0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
+  0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
+  0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
+  0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
+  0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
+  0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
+  0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
+  0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
+  0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
+  0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
+  0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
+  0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
+  0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
+  0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
+  0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
+  0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
+  0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
+  0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
+  0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
+  0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
+  0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
+  0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
+  0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
+  0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
+  0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
+  0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
+  0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
+  0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
+  0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
+  0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
+  0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
+  0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
+  0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
+  0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
+  0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
+  0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
+  0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
+  0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
+  0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
+  0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
+  0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
+  0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
+  0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
+  0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
+  0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
+  0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
+  0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
+  0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
+  0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
+  0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
+  0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
+  0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
+  0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
+  0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
+  0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
+  0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
+  0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
+  0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
+  0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
+  0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
+  0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
+  0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
+  0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
+  0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
+  0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
+  0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
+  0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
+  0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
+  0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
+  0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
+  0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
+  0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
+  0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
+  0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
+  0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
+  0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
+  0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
+  0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
+  0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
+  0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
+  0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
+  0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
+  0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
+  0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
+  0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
+  0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
+  0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
+  0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
+  0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
+  0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
+  0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
+  0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
+  0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
+  0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
+  0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
+  0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
+  0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
+  0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
+  0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
+  0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
+  0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
+  0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
+  0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
+  0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
+  0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
+  0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
+  0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
+  0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
+  0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
+  0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
+  0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
+  0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
+  0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
+  0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
+  0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
+  0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
+  0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
+  0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
+  0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
+  0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
+  0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
+  0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
+  0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
+  0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
+  0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
+  0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
+  0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
+  0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
+  0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
+  0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
+};
+
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
    
+* \par    
+* C command to generate the table    
+* 
    
+* for(i = 0; i< N; i++)    
+* {    
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } 
    
+* \par    
+* where N is the number of factors to generate and c is pi/(2*N)    
+* \par    
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.    
+    
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+  0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+  0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+  0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+  0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+  0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+  0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+  0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+  0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+  0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+  0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+  0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+  0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+  0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+  0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+  0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+  0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+  0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+  0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+  0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+  0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
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+  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
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+  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
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+  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+  0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+  0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
+  0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
+  0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
+  0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
+  0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
+  0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+  0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
+  0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
+  0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
+  0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
+  0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
+  0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
+  0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
+  0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
+  0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
+  0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
+  0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
+  0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
+  0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
+  0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
+  0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
+  0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
+  0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+  0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
+  0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
+  0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
+  0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
+  0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
+  0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
+  0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
+  0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
+  0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
+  0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
+  0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
+  0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
+  0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
+  0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
+  0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
+  0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
+  0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
+  0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
+  0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
+  0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
+  0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
+  0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
+  0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
+  0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
+  0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
+  0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
+  0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
+  0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,
+  0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
+  0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,
+  0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,
+  0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,
+  0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,
+  0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,
+  0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,
+  0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,
+  0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
+  0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,
+  0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,
+  0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
+  0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
+  0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
+  0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
+  0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
+  0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
+  0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
+  0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
+  0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
+  0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
+  0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
+  0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
+  0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
+  0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
+  0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
+  0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
+  0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
+  0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
+  0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
+  0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
+  0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
+  0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
+  0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
+  0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
+  0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
+  0x7ea4, 0x7ea3, 0x7ea2, 0x7ea1, 0x7ea0, 0x7e9f, 0x7e9e, 0x7e9d,
+  0x7e9c, 0x7e9b, 0x7e9b, 0x7e9a, 0x7e99, 0x7e98, 0x7e97, 0x7e96,
+  0x7e95, 0x7e94, 0x7e93, 0x7e92, 0x7e91, 0x7e90, 0x7e8f, 0x7e8e,
+  0x7e8d, 0x7e8d, 0x7e8c, 0x7e8b, 0x7e8a, 0x7e89, 0x7e88, 0x7e87,
+  0x7e86, 0x7e85, 0x7e84, 0x7e83, 0x7e82, 0x7e81, 0x7e80, 0x7e7f,
+  0x7e7e, 0x7e7d, 0x7e7c, 0x7e7b, 0x7e7a, 0x7e79, 0x7e78, 0x7e77,
+  0x7e77, 0x7e76, 0x7e75, 0x7e74, 0x7e73, 0x7e72, 0x7e71, 0x7e70,
+  0x7e6f, 0x7e6e, 0x7e6d, 0x7e6c, 0x7e6b, 0x7e6a, 0x7e69, 0x7e68,
+  0x7e67, 0x7e66, 0x7e65, 0x7e64, 0x7e63, 0x7e62, 0x7e61, 0x7e60,
+  0x7e5f, 0x7e5e, 0x7e5d, 0x7e5c, 0x7e5b, 0x7e5a, 0x7e59, 0x7e58,
+  0x7e57, 0x7e56, 0x7e55, 0x7e54, 0x7e53, 0x7e52, 0x7e51, 0x7e50,
+  0x7e4f, 0x7e4e, 0x7e4d, 0x7e4c, 0x7e4b, 0x7e4a, 0x7e49, 0x7e48,
+  0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,
+  0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,
+  0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,
+  0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,
+  0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,
+  0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,
+  0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,
+  0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,
+  0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,
+  0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,
+  0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,
+  0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,
+  0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,
+  0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,
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+  0x78d7, 0x78d5, 0x78d3, 0x78d1, 0x78ce, 0x78cc, 0x78ca, 0x78c8,
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+  0x78b5, 0x78b3, 0x78b1, 0x78af, 0x78ad, 0x78ab, 0x78a9, 0x78a7,
+  0x78a5, 0x78a3, 0x78a0, 0x789e, 0x789c, 0x789a, 0x7898, 0x7896,
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+  0x77e8, 0x77e5, 0x77e3, 0x77e1, 0x77df, 0x77dd, 0x77da, 0x77d8,
+  0x77d6, 0x77d4, 0x77d2, 0x77cf, 0x77cd, 0x77cb, 0x77c9, 0x77c6,
+  0x77c4, 0x77c2, 0x77c0, 0x77be, 0x77bb, 0x77b9, 0x77b7, 0x77b5,
+  0x77b2, 0x77b0, 0x77ae, 0x77ac, 0x77aa, 0x77a7, 0x77a5, 0x77a3,
+  0x77a1, 0x779e, 0x779c, 0x779a, 0x7798, 0x7795, 0x7793, 0x7791,
+  0x778f, 0x778c, 0x778a, 0x7788, 0x7786, 0x7783, 0x7781, 0x777f,
+  0x777d, 0x777a, 0x7778, 0x7776, 0x7774, 0x7771, 0x776f, 0x776d,
+  0x776b, 0x7768, 0x7766, 0x7764, 0x7762, 0x775f, 0x775d, 0x775b,
+  0x7759, 0x7756, 0x7754, 0x7752, 0x774f, 0x774d, 0x774b, 0x7749,
+  0x7746, 0x7744, 0x7742, 0x773f, 0x773d, 0x773b, 0x7739, 0x7736,
+  0x7734, 0x7732, 0x772f, 0x772d, 0x772b, 0x7729, 0x7726, 0x7724,
+  0x7722, 0x771f, 0x771d, 0x771b, 0x7719, 0x7716, 0x7714, 0x7712,
+  0x770f, 0x770d, 0x770b, 0x7708, 0x7706, 0x7704, 0x7701, 0x76ff,
+  0x76fd, 0x76fa, 0x76f8, 0x76f6, 0x76f4, 0x76f1, 0x76ef, 0x76ed,
+  0x76ea, 0x76e8, 0x76e6, 0x76e3, 0x76e1, 0x76df, 0x76dc, 0x76da,
+  0x76d8, 0x76d5, 0x76d3, 0x76d1, 0x76ce, 0x76cc, 0x76ca, 0x76c7,
+  0x76c5, 0x76c3, 0x76c0, 0x76be, 0x76bc, 0x76b9, 0x76b7, 0x76b4,
+  0x76b2, 0x76b0, 0x76ad, 0x76ab, 0x76a9, 0x76a6, 0x76a4, 0x76a2,
+  0x769f, 0x769d, 0x769b, 0x7698, 0x7696, 0x7693, 0x7691, 0x768f,
+  0x768c, 0x768a, 0x7688, 0x7685, 0x7683, 0x7681, 0x767e, 0x767c,
+  0x7679, 0x7677, 0x7675, 0x7672, 0x7670, 0x766d, 0x766b, 0x7669,
+  0x7666, 0x7664, 0x7662, 0x765f, 0x765d, 0x765a, 0x7658, 0x7656,
+  0x7653, 0x7651, 0x764e, 0x764c, 0x764a, 0x7647, 0x7645, 0x7642,
+  0x7640, 0x763e, 0x763b, 0x7639, 0x7636, 0x7634, 0x7632, 0x762f,
+  0x762d, 0x762a, 0x7628, 0x7625, 0x7623, 0x7621, 0x761e, 0x761c,
+  0x7619, 0x7617, 0x7615, 0x7612, 0x7610, 0x760d, 0x760b, 0x7608,
+  0x7606, 0x7604, 0x7601, 0x75ff, 0x75fc, 0x75fa, 0x75f7, 0x75f5,
+  0x75f2, 0x75f0, 0x75ee, 0x75eb, 0x75e9, 0x75e6, 0x75e4, 0x75e1,
+  0x75df, 0x75dc, 0x75da, 0x75d8, 0x75d5, 0x75d3, 0x75d0, 0x75ce,
+  0x75cb, 0x75c9, 0x75c6, 0x75c4, 0x75c1, 0x75bf, 0x75bc, 0x75ba,
+  0x75b8, 0x75b5, 0x75b3, 0x75b0, 0x75ae, 0x75ab, 0x75a9, 0x75a6,
+  0x75a4, 0x75a1, 0x759f, 0x759c, 0x759a, 0x7597, 0x7595, 0x7592,
+  0x7590, 0x758d, 0x758b, 0x7588, 0x7586, 0x7584, 0x7581, 0x757f,
+  0x757c, 0x757a, 0x7577, 0x7575, 0x7572, 0x7570, 0x756d, 0x756b,
+  0x7568, 0x7566, 0x7563, 0x7561, 0x755e, 0x755c, 0x7559, 0x7556,
+  0x7554, 0x7551, 0x754f, 0x754c, 0x754a, 0x7547, 0x7545, 0x7542,
+  0x7540, 0x753d, 0x753b, 0x7538, 0x7536, 0x7533, 0x7531, 0x752e,
+  0x752c, 0x7529, 0x7527, 0x7524, 0x7522, 0x751f, 0x751c, 0x751a,
+  0x7517, 0x7515, 0x7512, 0x7510, 0x750d, 0x750b, 0x7508, 0x7506,
+  0x7503, 0x7501, 0x74fe, 0x74fb, 0x74f9, 0x74f6, 0x74f4, 0x74f1,
+  0x74ef, 0x74ec, 0x74ea, 0x74e7, 0x74e4, 0x74e2, 0x74df, 0x74dd,
+  0x74da, 0x74d8, 0x74d5, 0x74d2, 0x74d0, 0x74cd, 0x74cb, 0x74c8,
+  0x74c6, 0x74c3, 0x74c0, 0x74be, 0x74bb, 0x74b9, 0x74b6, 0x74b4,
+  0x74b1, 0x74ae, 0x74ac, 0x74a9, 0x74a7, 0x74a4, 0x74a1, 0x749f,
+  0x749c, 0x749a, 0x7497, 0x7495, 0x7492, 0x748f, 0x748d, 0x748a,
+  0x7488, 0x7485, 0x7482, 0x7480, 0x747d, 0x747b, 0x7478, 0x7475,
+  0x7473, 0x7470, 0x746d, 0x746b, 0x7468, 0x7466, 0x7463, 0x7460,
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+  0x61ce, 0x61ca, 0x61c6, 0x61c2, 0x61be, 0x61ba, 0x61b6, 0x61b2,
+  0x61ae, 0x61aa, 0x61a6, 0x61a1, 0x619d, 0x6199, 0x6195, 0x6191,
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+  0x60a8, 0x60a4, 0x60a0, 0x609c, 0x6097, 0x6093, 0x608f, 0x608b,
+  0x6087, 0x6083, 0x607f, 0x607b, 0x6076, 0x6072, 0x606e, 0x606a,
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+  0x5fe1, 0x5fdd, 0x5fd9, 0x5fd5, 0x5fd0, 0x5fcc, 0x5fc8, 0x5fc4,
+  0x5fc0, 0x5fbc, 0x5fb7, 0x5fb3, 0x5faf, 0x5fab, 0x5fa7, 0x5fa3,
+  0x5f9e, 0x5f9a, 0x5f96, 0x5f92, 0x5f8e, 0x5f8a, 0x5f85, 0x5f81,
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+  0x5ed5, 0x5ed1, 0x5ecc, 0x5ec8, 0x5ec4, 0x5ec0, 0x5ebc, 0x5eb7,
+  0x5eb3, 0x5eaf, 0x5eab, 0x5ea6, 0x5ea2, 0x5e9e, 0x5e9a, 0x5e95,
+  0x5e91, 0x5e8d, 0x5e89, 0x5e85, 0x5e80, 0x5e7c, 0x5e78, 0x5e74,
+  0x5e6f, 0x5e6b, 0x5e67, 0x5e63, 0x5e5e, 0x5e5a, 0x5e56, 0x5e52,
+  0x5e4d, 0x5e49, 0x5e45, 0x5e41, 0x5e3c, 0x5e38, 0x5e34, 0x5e30,
+  0x5e2b, 0x5e27, 0x5e23, 0x5e1f, 0x5e1a, 0x5e16, 0x5e12, 0x5e0e,
+  0x5e09, 0x5e05, 0x5e01, 0x5dfd, 0x5df8, 0x5df4, 0x5df0, 0x5deb,
+  0x5de7, 0x5de3, 0x5ddf, 0x5dda, 0x5dd6, 0x5dd2, 0x5dce, 0x5dc9,
+  0x5dc5, 0x5dc1, 0x5dbc, 0x5db8, 0x5db4, 0x5db0, 0x5dab, 0x5da7,
+  0x5da3, 0x5d9e, 0x5d9a, 0x5d96, 0x5d92, 0x5d8d, 0x5d89, 0x5d85,
+  0x5d80, 0x5d7c, 0x5d78, 0x5d74, 0x5d6f, 0x5d6b, 0x5d67, 0x5d62,
+  0x5d5e, 0x5d5a, 0x5d55, 0x5d51, 0x5d4d, 0x5d49, 0x5d44, 0x5d40,
+  0x5d3c, 0x5d37, 0x5d33, 0x5d2f, 0x5d2a, 0x5d26, 0x5d22, 0x5d1e,
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+  0x5cf7, 0x5cf2, 0x5cee, 0x5cea, 0x5ce5, 0x5ce1, 0x5cdd, 0x5cd8,
+  0x5cd4, 0x5cd0, 0x5ccb, 0x5cc7, 0x5cc3, 0x5cbe, 0x5cba, 0x5cb6,
+  0x5cb1, 0x5cad, 0x5ca9, 0x5ca4, 0x5ca0, 0x5c9c, 0x5c97, 0x5c93,
+  0x5c8f, 0x5c8a, 0x5c86, 0x5c82, 0x5c7d, 0x5c79, 0x5c75, 0x5c70,
+  0x5c6c, 0x5c68, 0x5c63, 0x5c5f, 0x5c5b, 0x5c56, 0x5c52, 0x5c4e,
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+  0x5c26, 0x5c22, 0x5c1e, 0x5c19, 0x5c15, 0x5c11, 0x5c0c, 0x5c08,
+  0x5c03, 0x5bff, 0x5bfb, 0x5bf6, 0x5bf2, 0x5bee, 0x5be9, 0x5be5,
+  0x5be0, 0x5bdc, 0x5bd8, 0x5bd3, 0x5bcf, 0x5bcb, 0x5bc6, 0x5bc2,
+  0x5bbd, 0x5bb9, 0x5bb5, 0x5bb0, 0x5bac, 0x5ba8, 0x5ba3, 0x5b9f,
+  0x5b9a, 0x5b96, 0x5b92, 0x5b8d, 0x5b89, 0x5b84, 0x5b80, 0x5b7c,
+  0x5b77, 0x5b73, 0x5b6e, 0x5b6a, 0x5b66, 0x5b61, 0x5b5d, 0x5b58,
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+  0x5aea, 0x5ae6, 0x5ae1, 0x5add, 0x5ad8, 0x5ad4, 0x5ad0, 0x5acb,
+  0x5ac7, 0x5ac2, 0x5abe, 0x5ab9, 0x5ab5, 0x5ab1, 0x5aac, 0x5aa8,
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+  0x5a15, 0x5a10, 0x5a0c, 0x5a07, 0x5a03, 0x59ff, 0x59fa, 0x59f6,
+  0x59f1, 0x59ed, 0x59e8, 0x59e4, 0x59df, 0x59db, 0x59d6, 0x59d2,
+  0x59cd, 0x59c9, 0x59c4, 0x59c0, 0x59bb, 0x59b7, 0x59b2, 0x59ae,
+  0x59a9, 0x59a5, 0x59a1, 0x599c, 0x5998, 0x5993, 0x598f, 0x598a,
+  0x5986, 0x5981, 0x597d, 0x5978, 0x5974, 0x596f, 0x596b, 0x5966,
+  0x5962, 0x595d, 0x5959, 0x5954, 0x5950, 0x594b, 0x5947, 0x5942,
+  0x593e, 0x5939, 0x5935, 0x5930, 0x592c, 0x5927, 0x5923, 0x591e,
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+  0x58f5, 0x58f1, 0x58ec, 0x58e8, 0x58e3, 0x58df, 0x58da, 0x58d6,
+  0x58d1, 0x58cd, 0x58c8, 0x58c4, 0x58bf, 0x58bb, 0x58b6, 0x58b2,
+  0x58ad, 0x58a9, 0x58a4, 0x589f, 0x589b, 0x5896, 0x5892, 0x588d,
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+  0x5864, 0x5860, 0x585b, 0x5857, 0x5852, 0x584e, 0x5849, 0x5845,
+  0x5840, 0x583c, 0x5837, 0x5832, 0x582e, 0x5829, 0x5825, 0x5820,
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+  0x57ae, 0x57a9, 0x57a5, 0x57a0, 0x579c, 0x5797, 0x5793, 0x578e,
+  0x5789, 0x5785, 0x5780, 0x577c, 0x5777, 0x5772, 0x576e, 0x5769,
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+  0x56d1, 0x56cd, 0x56c8, 0x56c4, 0x56bf, 0x56ba, 0x56b6, 0x56b1,
+  0x56ac, 0x56a8, 0x56a3, 0x569f, 0x569a, 0x5695, 0x5691, 0x568c,
+  0x5687, 0x5683, 0x567e, 0x5679, 0x5675, 0x5670, 0x566c, 0x5667,
+  0x5662, 0x565e, 0x5659, 0x5654, 0x5650, 0x564b, 0x5646, 0x5642,
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+  0x55f3, 0x55ee, 0x55ea, 0x55e5, 0x55e0, 0x55dc, 0x55d7, 0x55d2,
+  0x55ce, 0x55c9, 0x55c4, 0x55c0, 0x55bb, 0x55b6, 0x55b2, 0x55ad,
+  0x55a8, 0x55a4, 0x559f, 0x559a, 0x5596, 0x5591, 0x558c, 0x5588,
+  0x5583, 0x557e, 0x5579, 0x5575, 0x5570, 0x556b, 0x5567, 0x5562,
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+  0x5538, 0x5533, 0x552f, 0x552a, 0x5525, 0x5520, 0x551c, 0x5517,
+  0x5512, 0x550e, 0x5509, 0x5504, 0x5500, 0x54fb, 0x54f6, 0x54f2,
+  0x54ed, 0x54e8, 0x54e3, 0x54df, 0x54da, 0x54d5, 0x54d1, 0x54cc,
+  0x54c7, 0x54c2, 0x54be, 0x54b9, 0x54b4, 0x54b0, 0x54ab, 0x54a6,
+  0x54a2, 0x549d, 0x5498, 0x5493, 0x548f, 0x548a, 0x5485, 0x5480,
+  0x547c, 0x5477, 0x5472, 0x546e, 0x5469, 0x5464, 0x545f, 0x545b,
+  0x5456, 0x5451, 0x544d, 0x5448, 0x5443, 0x543e, 0x543a, 0x5435,
+  0x5430, 0x542b, 0x5427, 0x5422, 0x541d, 0x5418, 0x5414, 0x540f,
+  0x540a, 0x5406, 0x5401, 0x53fc, 0x53f7, 0x53f3, 0x53ee, 0x53e9,
+  0x53e4, 0x53e0, 0x53db, 0x53d6, 0x53d1, 0x53cd, 0x53c8, 0x53c3,
+  0x53be, 0x53ba, 0x53b5, 0x53b0, 0x53ab, 0x53a7, 0x53a2, 0x539d,
+  0x5398, 0x5394, 0x538f, 0x538a, 0x5385, 0x5380, 0x537c, 0x5377,
+  0x5372, 0x536d, 0x5369, 0x5364, 0x535f, 0x535a, 0x5356, 0x5351,
+  0x534c, 0x5347, 0x5343, 0x533e, 0x5339, 0x5334, 0x532f, 0x532b,
+  0x5326, 0x5321, 0x531c, 0x5318, 0x5313, 0x530e, 0x5309, 0x5304,
+  0x5300, 0x52fb, 0x52f6, 0x52f1, 0x52ec, 0x52e8, 0x52e3, 0x52de,
+  0x52d9, 0x52d5, 0x52d0, 0x52cb, 0x52c6, 0x52c1, 0x52bd, 0x52b8,
+  0x52b3, 0x52ae, 0x52a9, 0x52a5, 0x52a0, 0x529b, 0x5296, 0x5291,
+  0x528d, 0x5288, 0x5283, 0x527e, 0x5279, 0x5275, 0x5270, 0x526b,
+  0x5266, 0x5261, 0x525d, 0x5258, 0x5253, 0x524e, 0x5249, 0x5244,
+  0x5240, 0x523b, 0x5236, 0x5231, 0x522c, 0x5228, 0x5223, 0x521e,
+  0x5219, 0x5214, 0x520f, 0x520b, 0x5206, 0x5201, 0x51fc, 0x51f7,
+  0x51f3, 0x51ee, 0x51e9, 0x51e4, 0x51df, 0x51da, 0x51d6, 0x51d1,
+  0x51cc, 0x51c7, 0x51c2, 0x51bd, 0x51b9, 0x51b4, 0x51af, 0x51aa,
+  0x51a5, 0x51a0, 0x519c, 0x5197, 0x5192, 0x518d, 0x5188, 0x5183,
+  0x517e, 0x517a, 0x5175, 0x5170, 0x516b, 0x5166, 0x5161, 0x515d,
+  0x5158, 0x5153, 0x514e, 0x5149, 0x5144, 0x513f, 0x513b, 0x5136,
+  0x5131, 0x512c, 0x5127, 0x5122, 0x511d, 0x5119, 0x5114, 0x510f,
+  0x510a, 0x5105, 0x5100, 0x50fb, 0x50f7, 0x50f2, 0x50ed, 0x50e8,
+  0x50e3, 0x50de, 0x50d9, 0x50d4, 0x50d0, 0x50cb, 0x50c6, 0x50c1,
+  0x50bc, 0x50b7, 0x50b2, 0x50ad, 0x50a9, 0x50a4, 0x509f, 0x509a,
+  0x5095, 0x5090, 0x508b, 0x5086, 0x5082, 0x507d, 0x5078, 0x5073,
+  0x506e, 0x5069, 0x5064, 0x505f, 0x505a, 0x5056, 0x5051, 0x504c,
+  0x5047, 0x5042, 0x503d, 0x5038, 0x5033, 0x502e, 0x5029, 0x5025,
+  0x5020, 0x501b, 0x5016, 0x5011, 0x500c, 0x5007, 0x5002, 0x4ffd,
+  0x4ff8, 0x4ff4, 0x4fef, 0x4fea, 0x4fe5, 0x4fe0, 0x4fdb, 0x4fd6,
+  0x4fd1, 0x4fcc, 0x4fc7, 0x4fc2, 0x4fbe, 0x4fb9, 0x4fb4, 0x4faf,
+  0x4faa, 0x4fa5, 0x4fa0, 0x4f9b, 0x4f96, 0x4f91, 0x4f8c, 0x4f87,
+  0x4f82, 0x4f7e, 0x4f79, 0x4f74, 0x4f6f, 0x4f6a, 0x4f65, 0x4f60,
+  0x4f5b, 0x4f56, 0x4f51, 0x4f4c, 0x4f47, 0x4f42, 0x4f3d, 0x4f39,
+  0x4f34, 0x4f2f, 0x4f2a, 0x4f25, 0x4f20, 0x4f1b, 0x4f16, 0x4f11,
+  0x4f0c, 0x4f07, 0x4f02, 0x4efd, 0x4ef8, 0x4ef3, 0x4eee, 0x4ee9,
+  0x4ee5, 0x4ee0, 0x4edb, 0x4ed6, 0x4ed1, 0x4ecc, 0x4ec7, 0x4ec2,
+  0x4ebd, 0x4eb8, 0x4eb3, 0x4eae, 0x4ea9, 0x4ea4, 0x4e9f, 0x4e9a,
+  0x4e95, 0x4e90, 0x4e8b, 0x4e86, 0x4e81, 0x4e7c, 0x4e78, 0x4e73,
+  0x4e6e, 0x4e69, 0x4e64, 0x4e5f, 0x4e5a, 0x4e55, 0x4e50, 0x4e4b,
+  0x4e46, 0x4e41, 0x4e3c, 0x4e37, 0x4e32, 0x4e2d, 0x4e28, 0x4e23,
+  0x4e1e, 0x4e19, 0x4e14, 0x4e0f, 0x4e0a, 0x4e05, 0x4e00, 0x4dfb,
+  0x4df6, 0x4df1, 0x4dec, 0x4de7, 0x4de2, 0x4ddd, 0x4dd8, 0x4dd3,
+  0x4dce, 0x4dc9, 0x4dc4, 0x4dbf, 0x4dba, 0x4db5, 0x4db0, 0x4dab,
+  0x4da6, 0x4da1, 0x4d9c, 0x4d97, 0x4d92, 0x4d8d, 0x4d88, 0x4d83,
+  0x4d7e, 0x4d79, 0x4d74, 0x4d6f, 0x4d6a, 0x4d65, 0x4d60, 0x4d5b,
+  0x4d56, 0x4d51, 0x4d4c, 0x4d47, 0x4d42, 0x4d3d, 0x4d38, 0x4d33,
+  0x4d2e, 0x4d29, 0x4d24, 0x4d1f, 0x4d1a, 0x4d15, 0x4d10, 0x4d0b,
+  0x4d06, 0x4d01, 0x4cfc, 0x4cf7, 0x4cf2, 0x4ced, 0x4ce8, 0x4ce3,
+  0x4cde, 0x4cd9, 0x4cd4, 0x4ccf, 0x4cca, 0x4cc5, 0x4cc0, 0x4cbb,
+  0x4cb6, 0x4cb1, 0x4cac, 0x4ca7, 0x4ca2, 0x4c9d, 0x4c98, 0x4c93,
+  0x4c8e, 0x4c88, 0x4c83, 0x4c7e, 0x4c79, 0x4c74, 0x4c6f, 0x4c6a,
+  0x4c65, 0x4c60, 0x4c5b, 0x4c56, 0x4c51, 0x4c4c, 0x4c47, 0x4c42,
+  0x4c3d, 0x4c38, 0x4c33, 0x4c2e, 0x4c29, 0x4c24, 0x4c1f, 0x4c1a,
+  0x4c14, 0x4c0f, 0x4c0a, 0x4c05, 0x4c00, 0x4bfb, 0x4bf6, 0x4bf1,
+  0x4bec, 0x4be7, 0x4be2, 0x4bdd, 0x4bd8, 0x4bd3, 0x4bce, 0x4bc9,
+  0x4bc4, 0x4bbe, 0x4bb9, 0x4bb4, 0x4baf, 0x4baa, 0x4ba5, 0x4ba0,
+  0x4b9b, 0x4b96, 0x4b91, 0x4b8c, 0x4b87, 0x4b82, 0x4b7d, 0x4b77,
+  0x4b72, 0x4b6d, 0x4b68, 0x4b63, 0x4b5e, 0x4b59, 0x4b54, 0x4b4f,
+  0x4b4a, 0x4b45, 0x4b40, 0x4b3b, 0x4b35, 0x4b30, 0x4b2b, 0x4b26,
+  0x4b21, 0x4b1c, 0x4b17, 0x4b12, 0x4b0d, 0x4b08, 0x4b03, 0x4afd,
+  0x4af8, 0x4af3, 0x4aee, 0x4ae9, 0x4ae4, 0x4adf, 0x4ada, 0x4ad5,
+  0x4ad0, 0x4acb, 0x4ac5, 0x4ac0, 0x4abb, 0x4ab6, 0x4ab1, 0x4aac,
+  0x4aa7, 0x4aa2, 0x4a9d, 0x4a97, 0x4a92, 0x4a8d, 0x4a88, 0x4a83,
+  0x4a7e, 0x4a79, 0x4a74, 0x4a6f, 0x4a6a, 0x4a64, 0x4a5f, 0x4a5a,
+  0x4a55, 0x4a50, 0x4a4b, 0x4a46, 0x4a41, 0x4a3b, 0x4a36, 0x4a31,
+  0x4a2c, 0x4a27, 0x4a22, 0x4a1d, 0x4a18, 0x4a12, 0x4a0d, 0x4a08,
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+  0x49da, 0x49d5, 0x49d0, 0x49cb, 0x49c6, 0x49c0, 0x49bb, 0x49b6,
+  0x49b1, 0x49ac, 0x49a7, 0x49a2, 0x499c, 0x4997, 0x4992, 0x498d,
+  0x4988, 0x4983, 0x497e, 0x4978, 0x4973, 0x496e, 0x4969, 0x4964,
+  0x495f, 0x495a, 0x4954, 0x494f, 0x494a, 0x4945, 0x4940, 0x493b,
+  0x4936, 0x4930, 0x492b, 0x4926, 0x4921, 0x491c, 0x4917, 0x4911,
+  0x490c, 0x4907, 0x4902, 0x48fd, 0x48f8, 0x48f2, 0x48ed, 0x48e8,
+  0x48e3, 0x48de, 0x48d9, 0x48d3, 0x48ce, 0x48c9, 0x48c4, 0x48bf,
+  0x48ba, 0x48b4, 0x48af, 0x48aa, 0x48a5, 0x48a0, 0x489b, 0x4895,
+  0x4890, 0x488b, 0x4886, 0x4881, 0x487c, 0x4876, 0x4871, 0x486c,
+  0x4867, 0x4862, 0x485c, 0x4857, 0x4852, 0x484d, 0x4848, 0x4843,
+  0x483d, 0x4838, 0x4833, 0x482e, 0x4829, 0x4823, 0x481e, 0x4819,
+  0x4814, 0x480f, 0x4809, 0x4804, 0x47ff, 0x47fa, 0x47f5, 0x47ef,
+  0x47ea, 0x47e5, 0x47e0, 0x47db, 0x47d5, 0x47d0, 0x47cb, 0x47c6,
+  0x47c1, 0x47bb, 0x47b6, 0x47b1, 0x47ac, 0x47a7, 0x47a1, 0x479c,
+  0x4797, 0x4792, 0x478d, 0x4787, 0x4782, 0x477d, 0x4778, 0x4773,
+  0x476d, 0x4768, 0x4763, 0x475e, 0x4758, 0x4753, 0x474e, 0x4749,
+  0x4744, 0x473e, 0x4739, 0x4734, 0x472f, 0x4729, 0x4724, 0x471f,
+  0x471a, 0x4715, 0x470f, 0x470a, 0x4705, 0x4700, 0x46fa, 0x46f5,
+  0x46f0, 0x46eb, 0x46e6, 0x46e0, 0x46db, 0x46d6, 0x46d1, 0x46cb,
+  0x46c6, 0x46c1, 0x46bc, 0x46b6, 0x46b1, 0x46ac, 0x46a7, 0x46a1,
+  0x469c, 0x4697, 0x4692, 0x468d, 0x4687, 0x4682, 0x467d, 0x4678,
+  0x4672, 0x466d, 0x4668, 0x4663, 0x465d, 0x4658, 0x4653, 0x464e,
+  0x4648, 0x4643, 0x463e, 0x4639, 0x4633, 0x462e, 0x4629, 0x4624,
+  0x461e, 0x4619, 0x4614, 0x460e, 0x4609, 0x4604, 0x45ff, 0x45f9,
+  0x45f4, 0x45ef, 0x45ea, 0x45e4, 0x45df, 0x45da, 0x45d5, 0x45cf,
+  0x45ca, 0x45c5, 0x45c0, 0x45ba, 0x45b5, 0x45b0, 0x45aa, 0x45a5,
+  0x45a0, 0x459b, 0x4595, 0x4590, 0x458b, 0x4586, 0x4580, 0x457b,
+  0x4576, 0x4570, 0x456b, 0x4566, 0x4561, 0x455b, 0x4556, 0x4551,
+  0x454b, 0x4546, 0x4541, 0x453c, 0x4536, 0x4531, 0x452c, 0x4526,
+  0x4521, 0x451c, 0x4517, 0x4511, 0x450c, 0x4507, 0x4501, 0x44fc,
+  0x44f7, 0x44f2, 0x44ec, 0x44e7, 0x44e2, 0x44dc, 0x44d7, 0x44d2,
+  0x44cd, 0x44c7, 0x44c2, 0x44bd, 0x44b7, 0x44b2, 0x44ad, 0x44a7,
+  0x44a2, 0x449d, 0x4497, 0x4492, 0x448d, 0x4488, 0x4482, 0x447d,
+  0x4478, 0x4472, 0x446d, 0x4468, 0x4462, 0x445d, 0x4458, 0x4452,
+  0x444d, 0x4448, 0x4443, 0x443d, 0x4438, 0x4433, 0x442d, 0x4428,
+  0x4423, 0x441d, 0x4418, 0x4413, 0x440d, 0x4408, 0x4403, 0x43fd,
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+  0x43cd, 0x43c8, 0x43c3, 0x43bd, 0x43b8, 0x43b3, 0x43ad, 0x43a8,
+  0x43a3, 0x439d, 0x4398, 0x4393, 0x438d, 0x4388, 0x4383, 0x437d,
+  0x4378, 0x4373, 0x436d, 0x4368, 0x4363, 0x435d, 0x4358, 0x4353,
+  0x434d, 0x4348, 0x4343, 0x433d, 0x4338, 0x4333, 0x432d, 0x4328,
+  0x4323, 0x431d, 0x4318, 0x4313, 0x430d, 0x4308, 0x4302, 0x42fd,
+  0x42f8, 0x42f2, 0x42ed, 0x42e8, 0x42e2, 0x42dd, 0x42d8, 0x42d2,
+  0x42cd, 0x42c8, 0x42c2, 0x42bd, 0x42b7, 0x42b2, 0x42ad, 0x42a7,
+  0x42a2, 0x429d, 0x4297, 0x4292, 0x428d, 0x4287, 0x4282, 0x427c,
+  0x4277, 0x4272, 0x426c, 0x4267, 0x4262, 0x425c, 0x4257, 0x4251,
+  0x424c, 0x4247, 0x4241, 0x423c, 0x4237, 0x4231, 0x422c, 0x4226,
+  0x4221, 0x421c, 0x4216, 0x4211, 0x420c, 0x4206, 0x4201, 0x41fb,
+  0x41f6, 0x41f1, 0x41eb, 0x41e6, 0x41e0, 0x41db, 0x41d6, 0x41d0,
+  0x41cb, 0x41c6, 0x41c0, 0x41bb, 0x41b5, 0x41b0, 0x41ab, 0x41a5,
+  0x41a0, 0x419a, 0x4195, 0x4190, 0x418a, 0x4185, 0x417f, 0x417a,
+  0x4175, 0x416f, 0x416a, 0x4164, 0x415f, 0x415a, 0x4154, 0x414f,
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+  0x40f3, 0x40ed, 0x40e8, 0x40e3, 0x40dd, 0x40d8, 0x40d2, 0x40cd,
+  0x40c8, 0x40c2, 0x40bd, 0x40b7, 0x40b2, 0x40ac, 0x40a7, 0x40a2,
+  0x409c, 0x4097, 0x4091, 0x408c, 0x4086, 0x4081, 0x407c, 0x4076,
+  0x4071, 0x406b, 0x4066, 0x4060, 0x405b, 0x4056, 0x4050, 0x404b,
+  0x4045, 0x4040, 0x403a, 0x4035, 0x4030, 0x402a, 0x4025, 0x401f,
+  0x401a, 0x4014, 0x400f, 0x4009, 0x4004, 0x3fff, 0x3ff9, 0x3ff4,
+  0x3fee, 0x3fe9, 0x3fe3, 0x3fde, 0x3fd8, 0x3fd3, 0x3fce, 0x3fc8,
+  0x3fc3, 0x3fbd, 0x3fb8, 0x3fb2, 0x3fad, 0x3fa7, 0x3fa2, 0x3f9d,
+  0x3f97, 0x3f92, 0x3f8c, 0x3f87, 0x3f81, 0x3f7c, 0x3f76, 0x3f71,
+  0x3f6b, 0x3f66, 0x3f61, 0x3f5b, 0x3f56, 0x3f50, 0x3f4b, 0x3f45,
+  0x3f40, 0x3f3a, 0x3f35, 0x3f2f, 0x3f2a, 0x3f24, 0x3f1f, 0x3f1a,
+  0x3f14, 0x3f0f, 0x3f09, 0x3f04, 0x3efe, 0x3ef9, 0x3ef3, 0x3eee,
+  0x3ee8, 0x3ee3, 0x3edd, 0x3ed8, 0x3ed2, 0x3ecd, 0x3ec7, 0x3ec2,
+  0x3ebd, 0x3eb7, 0x3eb2, 0x3eac, 0x3ea7, 0x3ea1, 0x3e9c, 0x3e96,
+  0x3e91, 0x3e8b, 0x3e86, 0x3e80, 0x3e7b, 0x3e75, 0x3e70, 0x3e6a,
+  0x3e65, 0x3e5f, 0x3e5a, 0x3e54, 0x3e4f, 0x3e49, 0x3e44, 0x3e3e,
+  0x3e39, 0x3e33, 0x3e2e, 0x3e28, 0x3e23, 0x3e1d, 0x3e18, 0x3e12,
+  0x3e0d, 0x3e07, 0x3e02, 0x3dfc, 0x3df7, 0x3df1, 0x3dec, 0x3de6,
+  0x3de1, 0x3ddb, 0x3dd6, 0x3dd0, 0x3dcb, 0x3dc5, 0x3dc0, 0x3dba,
+  0x3db5, 0x3daf, 0x3daa, 0x3da4, 0x3d9f, 0x3d99, 0x3d94, 0x3d8e,
+  0x3d89, 0x3d83, 0x3d7e, 0x3d78, 0x3d73, 0x3d6d, 0x3d68, 0x3d62,
+  0x3d5d, 0x3d57, 0x3d52, 0x3d4c, 0x3d47, 0x3d41, 0x3d3c, 0x3d36,
+  0x3d31, 0x3d2b, 0x3d26, 0x3d20, 0x3d1b, 0x3d15, 0x3d10, 0x3d0a,
+  0x3d04, 0x3cff, 0x3cf9, 0x3cf4, 0x3cee, 0x3ce9, 0x3ce3, 0x3cde,
+  0x3cd8, 0x3cd3, 0x3ccd, 0x3cc8, 0x3cc2, 0x3cbd, 0x3cb7, 0x3cb2,
+  0x3cac, 0x3ca7, 0x3ca1, 0x3c9b, 0x3c96, 0x3c90, 0x3c8b, 0x3c85,
+  0x3c80, 0x3c7a, 0x3c75, 0x3c6f, 0x3c6a, 0x3c64, 0x3c5f, 0x3c59,
+  0x3c53, 0x3c4e, 0x3c48, 0x3c43, 0x3c3d, 0x3c38, 0x3c32, 0x3c2d,
+  0x3c27, 0x3c22, 0x3c1c, 0x3c16, 0x3c11, 0x3c0b, 0x3c06, 0x3c00,
+  0x3bfb, 0x3bf5, 0x3bf0, 0x3bea, 0x3be5, 0x3bdf, 0x3bd9, 0x3bd4,
+  0x3bce, 0x3bc9, 0x3bc3, 0x3bbe, 0x3bb8, 0x3bb3, 0x3bad, 0x3ba7,
+  0x3ba2, 0x3b9c, 0x3b97, 0x3b91, 0x3b8c, 0x3b86, 0x3b80, 0x3b7b,
+  0x3b75, 0x3b70, 0x3b6a, 0x3b65, 0x3b5f, 0x3b5a, 0x3b54, 0x3b4e,
+  0x3b49, 0x3b43, 0x3b3e, 0x3b38, 0x3b33, 0x3b2d, 0x3b27, 0x3b22,
+  0x3b1c, 0x3b17, 0x3b11, 0x3b0c, 0x3b06, 0x3b00, 0x3afb, 0x3af5,
+  0x3af0, 0x3aea, 0x3ae4, 0x3adf, 0x3ad9, 0x3ad4, 0x3ace, 0x3ac9,
+  0x3ac3, 0x3abd, 0x3ab8, 0x3ab2, 0x3aad, 0x3aa7, 0x3aa2, 0x3a9c,
+  0x3a96, 0x3a91, 0x3a8b, 0x3a86, 0x3a80, 0x3a7a, 0x3a75, 0x3a6f,
+  0x3a6a, 0x3a64, 0x3a5e, 0x3a59, 0x3a53, 0x3a4e, 0x3a48, 0x3a42,
+  0x3a3d, 0x3a37, 0x3a32, 0x3a2c, 0x3a26, 0x3a21, 0x3a1b, 0x3a16,
+  0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,
+  0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,
+  0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,
+  0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,
+  0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,
+  0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,
+  0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,
+  0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,
+  0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,
+  0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,
+  0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,
+  0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,
+  0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,
+  0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,
+  0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,
+  0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,
+  0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,
+  0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,
+  0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,
+  0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,
+  0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,
+  0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,
+  0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,
+  0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,
+  0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,
+  0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,
+  0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,
+  0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,
+  0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,
+  0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,
+  0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,
+  0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,
+  0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,
+  0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,
+  0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,
+  0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,
+  0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,
+  0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,
+  0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,
+  0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,
+  0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,
+  0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,
+  0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,
+  0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,
+  0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,
+  0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,
+  0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,
+  0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,
+  0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,
+  0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,
+  0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,
+  0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,
+  0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,
+  0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,
+  0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,
+  0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,
+  0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,
+  0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,
+  0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,
+  0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,
+  0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,
+  0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,
+  0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,
+  0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,
+  0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,
+  0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,
+  0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,
+  0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,
+  0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,
+  0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,
+  0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,
+  0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,
+  0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,
+  0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,
+  0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,
+  0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,
+  0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,
+  0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,
+  0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,
+  0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,
+  0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,
+  0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,
+  0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,
+  0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,
+  0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,
+  0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,
+  0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,
+  0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,
+  0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,
+  0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,
+  0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,
+  0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,
+  0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,
+  0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,
+  0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,
+  0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,
+  0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,
+  0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,
+  0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,
+  0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,
+  0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,
+  0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,
+  0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,
+  0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,
+  0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,
+  0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,
+  0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,
+  0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,
+  0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,
+  0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,
+  0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,
+  0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,
+  0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,
+  0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,
+  0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,
+  0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,
+  0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,
+  0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,
+  0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,
+  0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,
+  0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,
+  0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,
+  0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,
+  0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,
+  0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,
+  0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,
+  0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,
+  0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,
+  0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,
+  0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,
+  0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
+  0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
+  0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
+  0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
+  0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
+  0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
+  0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
+  0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
+  0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
+  0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
+  0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
+  0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
+  0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
+  0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
+  0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
+  0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
+  0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
+  0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
+  0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
+  0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
+  0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
+  0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
+  0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
+  0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
+  0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
+  0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
+  0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
+  0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
+  0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
+  0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
+  0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
+  0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
+  0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
+  0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
+  0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
+  0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
+  0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
+  0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
+  0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
+  0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
+  0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
+  0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
+  0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
+  0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
+  0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
+  0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
+  0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
+  0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
+  0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
+  0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
+  0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
+  0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
+  0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
+  0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
+  0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
+  0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
+  0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
+  0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
+  0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
+  0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
+  0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
+  0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
+  0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
+  0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
+  0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
+  0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
+  0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
+  0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
+  0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
+  0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
+  0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
+  0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
+  0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
+  0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
+  0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
+  0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
+  0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
+  0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
+  0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
+  0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
+  0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
+  0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
+  0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
+  0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
+  0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
+  0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
+  0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
+  0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
+  0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
+  0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
+  0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
+  0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
+  0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
+  0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
+  0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
+  0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
+  0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
+  0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
+  0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
+  0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
+  0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
+  0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
+  0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
+  0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
+  0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
+  0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
+  0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
+  0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
+  0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
+  0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
+  0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
+  0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
+  0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
+  0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
+  0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
+  0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
+  0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
+  0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
+  0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
+  0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
+  0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
+  0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
+  0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
+  0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
+  0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
+  0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
+  0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
+  0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
+  0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
+  0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
+  0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
+  0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
+  0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
+  0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
+  0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
+  0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
+  0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
+  0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
+  0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
+  0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
+  0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
+  0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
+  0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
+  0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
+  0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
+  0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
+  0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
+  0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
+  0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
+  0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
+  0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
+  0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
+  0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
+  0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
+  0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
+  0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
+  0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
+  0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
+  0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
+  0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
+  0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
+  0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
+  0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
+  0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
+  0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
+  0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
+  0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
+  0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
+  0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
+  0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
+  0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
+  0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
+  0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
+  0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
+  0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
+  0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
+  0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
+};
+
+/**    
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.   
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.   
+ * @param[in]     N          length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingQ15Table.gif    
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[4] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 0000000000..211cdadf38
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,8356 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_init_q31.c    
+*    
+* Description:	Initialization function of DCT-4 & IDCT4 Q31    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/*    
+* @brief  Weights Table    
+*/
+
+/**    
+* \par    
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
+* \par    
+* C command to generate the table    
+* 
    
+* for(i = 0; i< N; i++)    
+* {    
+*   weights[2*i]= cos(i*c);    
+*   weights[(2*i)+1]= -sin(i * c);    
+* } 
    
+* \par    
+* where N is the Number of weights to be calculated and c is pi/(2*N)    
+* \par    
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.    
+* \par    
+* In the tables below the real and imaginary values are placed alternatively, hence the    
+* array length is 2*N.    
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+  0xfb49e6a3,
+  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+  0x7f872bf3, 0xf50497fb,
+  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+  0x7ed5e5c6, 0xeec60f31,
+  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+  0x7dd6668f, 0xe8922622,
+  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+  0x7c894bde, 0xe26cb01b,
+  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+  0x7aef6323, 0xdc597781,
+  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+  0x7909a92d, 0xd65c3b7b,
+  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+  0x76d94989, 0xd078ad9e,
+  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+  0x745f9dd1, 0xcab26fa9,
+  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+  0x719e2cd2, 0xc50d1149,
+  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+  0x6e96a99d, 0xbf8c0de3,
+  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+  0x6b4af279, 0xba32ca71,
+  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+  0x67bd0fbd, 0xb5049368,
+  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+  0x63ef3290, 0xb0049ab3,
+  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+  0x5fe3b38d, 0xab35f5b5,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+  0x5b9d1154, 0xa69b9b68,
+  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+  0x571deefa, 0xa2386284,
+  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+  0x5269126e, 0x9e0effc1,
+  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+  0x4d8162c4, 0x9a22042d,
+  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+  0x4869e665, 0x9673db94,
+  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+  0x4325c135, 0x9306cb04,
+  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+  0x3db832a6, 0x8fdcef66,
+  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+  0x382493b0, 0x8cf83c30,
+  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+  0x326e54c7, 0x8a5a7a31,
+  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+  0x2c98fbba, 0x88054677,
+  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+  0x26a82186, 0x85fa1153,
+  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+  0x209f701c, 0x843a1d70,
+  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+  0x1a82a026, 0x82c67f14,
+  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+  0x145576b1, 0x81a01b6d,
+  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+  0xe1bc2e4, 0x80c7a80a,
+  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+  0x7d95b9e, 0x803daa6a,
+  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+  0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+  0xfed2694f,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+  0x7ff871a2, 0xfd40565c,
+  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+  0x7fed5791, 0xfbae5e89,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+  0x7fdd4eec, 0xfa1c9157,
+  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+  0x7fc85854, 0xf88afe42,
+  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+  0x7fae7495, 0xf6f9b4c6,
+  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+  0x7f8fa4b0, 0xf568c45b,
+  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+  0x7f6be9d4, 0xf3d83c77,
+  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+  0x7f434563, 0xf2482c8a,
+  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+  0x7f15b8ee, 0xf0b8a401,
+  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+  0x7ee34636, 0xef29b243,
+  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+  0x7eabef2c, 0xed9b66b2,
+  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+  0x7e6fb5f4, 0xec0dd0a8,
+  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+  0x7e2e9cdf, 0xea80ff7a,
+  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+  0x7de8a670, 0xe8f50273,
+  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+  0x7d9dd55a, 0xe769e8d8,
+  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+  0x7d4e2c7f, 0xe5dfc1e5,
+  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+  0x7cf9aef0, 0xe4569ccb,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+  0x7ca05ff1, 0xe2ce88b3,
+  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+  0x7c4242f2, 0xe14794ba,
+  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+  0x7bdf5b94, 0xdfc1cff3,
+  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+  0x7b77ada8, 0xde3d4964,
+  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+  0x7b0b3d2c, 0xdcba1008,
+  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+  0x7a9a0e50, 0xdb3832cd,
+  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+  0x7a24256f, 0xd9b7c094,
+  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+  0x79a98715, 0xd838c82d,
+  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+  0x792a37fe, 0xd6bb585e,
+  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+  0x78a63d11, 0xd53f7fda,
+  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+  0x781d9b65, 0xd3c54d47,
+  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+  0x7790583e, 0xd24ccf39,
+  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+  0x76fe790e, 0xd0d61434,
+  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+  0x76680376, 0xcf612aaa,
+  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+  0x75ccfd42, 0xcdee20fc,
+  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+  0x752d6c6c, 0xcc7d0578,
+  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+  0x7489571c, 0xcb0de658,
+  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+  0x73e0c3a3, 0xc9a0d1c5,
+  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+  0x7333b883, 0xc835d5d0,
+  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+  0x72823c67, 0xc6cd0079,
+  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+  0x71cc5626, 0xc5665fa9,
+  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+  0x71120cc5, 0xc4020133,
+  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+  0x70536771, 0xc29ff2d4,
+  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+  0x6f906d84, 0xc1404233,
+  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+  0x6ec92683, 0xbfe2fcdf,
+  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+  0x6dfd9a1c, 0xbe88304f,
+  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+  0x6d2dd027, 0xbd2fe9e2,
+  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+  0x6c59d0a9, 0xbbda36dd,
+  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+  0x6b81a3cd, 0xba87246d,
+  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+  0x6aa551e9, 0xb936bfa4,
+  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+  0x69c4e37a, 0xb7e9157a,
+  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+  0x68e06129, 0xb69e32cd,
+  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+  0x67f7d3c5, 0xb556245e,
+  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+  0x670b4444, 0xb410f6d3,
+  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+  0x661abbc5, 0xb2ceb6b5,
+  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+  0x6526438f, 0xb18f7071,
+  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+  0x642de50d, 0xb0533055,
+  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+  0x6331a9d4, 0xaf1a0293,
+  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+  0x62319b9d, 0xade3f33e,
+  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+  0x612dc447, 0xacb10e4b,
+  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+  0x60262dd6, 0xab815f8d,
+  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+  0x5f1ae274, 0xaa54f2ba,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+  0x5e0bec6e, 0xa92bd367,
+  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+  0x5cf95638, 0xa8060d08,
+  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+  0x5be32a67, 0xa6e3aaf2,
+  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+  0x5ac973b5, 0xa5c4b855,
+  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+  0x59ac3cfd, 0xa4a94043,
+  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+  0x588b9140, 0xa3914da8,
+  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+  0x57677b9d, 0xa27ceb4f,
+  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+  0x56400758, 0xa16c23e1,
+  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+  0x55153fd4, 0xa05f01e1,
+  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+  0x53e73097, 0x9f558fb0,
+  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+  0x52b5e546, 0x9e4fd78a,
+  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+  0x518169a5, 0x9d4de385,
+  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+  0x5049c999, 0x9c4fbd93,
+  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+  0x4f0f1126, 0x9b556f81,
+  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+  0x4dd14c6e, 0x9a5f02f5,
+  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+  0x4c9087b1, 0x996c816f,
+  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+  0x4b4ccf4d, 0x987df449,
+  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+  0x4a062fbd, 0x979364b5,
+  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+  0x48bcb599, 0x96acdbbe,
+  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+  0x47706d93, 0x95ca6247,
+  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+  0x4621647d, 0x94ec010b,
+  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+  0x44cfa740, 0x9411c09e,
+  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+  0x437b42e1, 0x933ba968,
+  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+  0x42244481, 0x9269c3ac,
+  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+  0x40cab958, 0x919c1781,
+  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+  0x3f6eaeb8, 0x90d2acd4,
+  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+  0x3e10320d, 0x900d8b69,
+  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+  0x3caf50da, 0x8f4cbadb,
+  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+  0x3b4c18ba, 0x8e904298,
+  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+  0x39e6975e, 0x8dd829e4,
+  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+  0x387eda8e, 0x8d2477d8,
+  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+  0x3714f02a, 0x8c753362,
+  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+  0x35a8e625, 0x8bca6343,
+  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+  0x343aca87, 0x8b240e11,
+  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+  0x32caab6f, 0x8a823a36,
+  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+  0x3158970e, 0x89e4edef,
+  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+  0x2fe49ba7, 0x894c2f4c,
+  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+  0x2e6ec792, 0x88b80432,
+  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+  0x2cf72939, 0x88287256,
+  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+  0x2b7dcf17, 0x879d7f41,
+  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+  0x2a02c7b8, 0x8717304e,
+  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+  0x288621b9, 0x86958aac,
+  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+  0x2707ebc7, 0x86189359,
+  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+  0x2588349d, 0x85a04f28,
+  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+  0x24070b08, 0x852cc2bb,
+  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+  0x22847de0, 0x84bdf286,
+  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+  0x21009c0c, 0x8453e2cf,
+  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+  0x1f7b7481, 0x83ee97ad,
+  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+  0x1df5163f, 0x838e1507,
+  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+  0x1c6d9053, 0x83325e97,
+  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+  0x1ae4f1d6, 0x82db77e5,
+  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+  0x195b49ea, 0x8289644b,
+  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+  0x17d0a7bc, 0x823c26f3,
+  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+  0x16451a83, 0x81f3c2d7,
+  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+  0x14b8b17f, 0x81b03ac2,
+  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+  0x132b7bf9, 0x8171914e,
+  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+  0x119d8941, 0x8137c8e6,
+  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+  0x100ee8ad, 0x8102e3c4,
+  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+  0xe7fa99e, 0x80d2e3f2,
+  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+  0xcefdb76, 0x80a7cb49,
+  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+  0xb5f8d9f, 0x80819b74,
+  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+  0x9cecf89, 0x806055eb,
+  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+  0x83db0a7, 0x8043fbf6,
+  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+  0x6ac406f, 0x802c8ead,
+  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+  0x51a8e5c, 0x801a0ef8,
+  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+  0x388a9ea, 0x800c7d8c,
+  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+  0x1f6a297, 0x8003daf1,
+  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+  0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+  0xffb49a12,
+  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+  0x7fff8719, 0xff501258,
+  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+  0x7ffed572, 0xfeeb8b0a,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+  0x7ffdd4d7, 0xfe870467,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+  0x7ffc8549, 0xfe227eac,
+  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+  0x7ffae6c7, 0xfdbdfa18,
+  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+  0x7ff8f954, 0xfd5976e9,
+  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+  0x7ff6bcf0, 0xfcf4f55c,
+  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+  0x7ff4319d, 0xfc9075af,
+  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+  0x7ff1575d, 0xfc2bf821,
+  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+  0x7fee2e30, 0xfbc77cf0,
+  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+  0x7feab61a, 0xfb630459,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+  0x7fe6ef1c, 0xfafe8e9b,
+  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+  0x7fe2d938, 0xfa9a1bf3,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+  0x7fde7471, 0xfa35ac9f,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+  0x7fd9c0ca, 0xf9d140de,
+  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+  0x7fd4be46, 0xf96cd8ed,
+  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+  0x7fcf6ce8, 0xf908750a,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+  0x7fc9ccb2, 0xf8a41574,
+  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+  0x7fc3dda9, 0xf83fba68,
+  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+  0x7fbd9fd0, 0xf7db6423,
+  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+  0x7fb7132b, 0xf77712e5,
+  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+  0x7fb037bf, 0xf712c6ea,
+  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+  0x7fa90d8e, 0xf6ae8071,
+  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+  0x7fa1949e, 0xf64a3fb8,
+  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+  0x7f99ccf4, 0xf5e604fc,
+  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+  0x7f91b694, 0xf581d07b,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+  0x7f895182, 0xf51da273,
+  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+  0x7f809dc5, 0xf4b97b21,
+  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+  0x7f779b62, 0xf4555ac5,
+  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+  0x7f6e4a5e, 0xf3f1419a,
+  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+  0x7f64aabf, 0xf38d2fe0,
+  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+  0x7f5abc8a, 0xf32925d3,
+  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+  0x7f507fc7, 0xf2c523b2,
+  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+  0x7f45f47b, 0xf26129ba,
+  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+  0x7f3b1aad, 0xf1fd3829,
+  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+  0x7f2ff263, 0xf1994f3d,
+  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+  0x7f247ba5, 0xf1356f32,
+  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+  0x7f18b679, 0xf0d19848,
+  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+  0x7f0ca2e7, 0xf06dcaba,
+  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+  0x7f0040f6, 0xf00a06c8,
+  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+  0x7ef390ae, 0xefa64cae,
+  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+  0x7ee69217, 0xef429caa,
+  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+  0x7ed94538, 0xeedef6f9,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+  0x7ecbaa1a, 0xee7b5bd9,
+  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+  0x7ebdc0c6, 0xee17cb88,
+  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+  0x7eaf8943, 0xedb44642,
+  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+  0x7ea1039b, 0xed50cc46,
+  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+  0x7e922fd6, 0xeced5dd0,
+  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+  0x7e830dff, 0xec89fb1e,
+  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+  0x7e739e1d, 0xec26a46d,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+  0x7e63e03b, 0xebc359fb,
+  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+  0x7e53d462, 0xeb601c04,
+  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+  0x7e437a9c, 0xeafceac6,
+  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+  0x7e32d2f4, 0xea99c67e,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+  0x7e21dd73, 0xea36af69,
+  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+  0x7e109a24, 0xe9d3a5c5,
+  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+  0x7dff0911, 0xe970a9ce,
+  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+  0x7ded2a47, 0xe90dbbc2,
+  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+  0x7ddafdce, 0xe8aadbde,
+  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+  0x7dc883b4, 0xe8480a5d,
+  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+  0x7db5bc02, 0xe7e5477f,
+  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+  0x7da2a6c6, 0xe782937e,
+  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+  0x7d8f4409, 0xe71fee99,
+  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+  0x7d7b93da, 0xe6bd590d,
+  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+  0x7d679642, 0xe65ad315,
+  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+  0x7d534b50, 0xe5f85cef,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+  0x7d3eb30f, 0xe595f6d7,
+  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+  0x7d29cd8c, 0xe533a10a,
+  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+  0x7d149ad5, 0xe4d15bc6,
+  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+  0x7cff1af5, 0xe46f2745,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+  0x7ce94dfb, 0xe40d03c6,
+  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+  0x7cd333f3, 0xe3aaf184,
+  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+  0x7cbcccec, 0xe348f0bd,
+  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+  0x7ca618f3, 0xe2e701ac,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+  0x7c8f1817, 0xe285248d,
+  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+  0x7c77ca65, 0xe223599e,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+  0x7c602fec, 0xe1c1a11b,
+  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+  0x7c4848ba, 0xe15ffb3f,
+  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+  0x7c3014de, 0xe0fe6848,
+  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+  0x7c179467, 0xe09ce871,
+  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+  0x7bfec765, 0xe03b7bf6,
+  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+  0x7be5ade6, 0xdfda2314,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+  0x7bcc47fa, 0xdf78de07,
+  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+  0x7bb295b0, 0xdf17ad0a,
+  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+  0x7b989719, 0xdeb69059,
+  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+  0x7b7e4c45, 0xde558831,
+  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+  0x7b63b543, 0xddf494ce,
+  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+  0x7b48d225, 0xdd93b66a,
+  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+  0x7b2da2fa, 0xdd32ed43,
+  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+  0x7b1227d3, 0xdcd23993,
+  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+  0x7af660c2, 0xdc719b96,
+  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+  0x7ada4dd8, 0xdc111388,
+  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+  0x7abdef25, 0xdbb0a1a4,
+  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+  0x7aa144bc, 0xdb504626,
+  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+  0x7a844eae, 0xdaf00149,
+  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+  0x7a670d0d, 0xda8fd349,
+  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+  0x7a497feb, 0xda2fbc61,
+  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+  0x7a2ba75a, 0xd9cfbccd,
+  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+  0x7a0d836d, 0xd96fd4c7,
+  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+  0x79ef1436, 0xd910048a,
+  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+  0x79d059c8, 0xd8b04c52,
+  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+  0x79b15435, 0xd850ac5a,
+  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+  0x79920392, 0xd7f124dd,
+  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+  0x797267f2, 0xd791b616,
+  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+  0x79528167, 0xd732603f,
+  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+  0x79325006, 0xd6d32393,
+  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+  0x7911d3e2, 0xd674004e,
+  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+  0x78f10d0f, 0xd614f6a9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+  0x78cffba3, 0xd5b606e0,
+  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+  0x78ae9fb0, 0xd557312d,
+  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+  0x788cf94c, 0xd4f875ca,
+  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+  0x786b088c, 0xd499d4f2,
+  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+  0x7848cd83, 0xd43b4ee0,
+  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+  0x78264849, 0xd3dce3cd,
+  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+  0x780378f1, 0xd37e93f4,
+  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+  0x77e05f91, 0xd3205f8f,
+  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+  0x77bcfc3f, 0xd2c246d8,
+  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+  0x77994f11, 0xd2644a0a,
+  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+  0x7775581d, 0xd206695d,
+  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+  0x77511778, 0xd1a8a50d,
+  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+  0x772c8d3a, 0xd14afd52,
+  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+  0x7707b979, 0xd0ed7267,
+  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+  0x76e29c4b, 0xd0900486,
+  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+  0x76bd35c7, 0xd032b3e7,
+  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+  0x76978605, 0xcfd580c6,
+  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+  0x76718d1c, 0xcf786b5a,
+  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+  0x764b4b23, 0xcf1b73de,
+  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+  0x7624c031, 0xcebe9a8a,
+  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+  0x75fdec60, 0xce61df99,
+  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+  0x75d6cfc5, 0xce054343,
+  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+  0x75af6a7b, 0xcda8c5c1,
+  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+  0x7587bc98, 0xcd4c674d,
+  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+  0x755fc635, 0xccf0281f,
+  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+  0x7537876c, 0xcc940871,
+  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+  0x750f0054, 0xcc38087b,
+  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+  0x74e63108, 0xcbdc2876,
+  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+  0x74bd199f, 0xcb80689a,
+  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+  0x7493ba34, 0xcb24c921,
+  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+  0x746a12df, 0xcac94a42,
+  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+  0x744023bc, 0xca6dec37,
+  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+  0x7415ece2, 0xca12af37,
+  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+  0x73eb6e6e, 0xc9b7937a,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+  0x73c0a878, 0xc95c993a,
+  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+  0x73959b1b, 0xc901c0ae,
+  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+  0x736a4671, 0xc8a70a0e,
+  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+  0x733eaa96, 0xc84c7593,
+  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+  0x7312c7a5, 0xc7f20373,
+  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+  0x72e69db7, 0xc797b3e7,
+  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+  0x72ba2cea, 0xc73d8727,
+  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+  0x728d7557, 0xc6e37d69,
+  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+  0x7260771b, 0xc68996e7,
+  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+  0x72333251, 0xc62fd3d6,
+  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+  0x7205a716, 0xc5d6346f,
+  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+  0x71d7d585, 0xc57cb8e9,
+  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+  0x71a9bdba, 0xc523617a,
+  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+  0x717b5fd3, 0xc4ca2e5b,
+  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+  0x714cbbeb, 0xc4711fc2,
+  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+  0x711dd220, 0xc41835e6,
+  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+  0x70eea28e, 0xc3bf70fd,
+  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+  0x70bf2d53, 0xc366d140,
+  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+  0x708f728b, 0xc30e56e4,
+  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+  0x705f7255, 0xc2b6021f,
+  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+  0x702f2ccd, 0xc25dd329,
+  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+  0x6ffea212, 0xc205ca38,
+  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+  0x6fcdd241, 0xc1ade781,
+  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+  0x6f9cbd79, 0xc1562b3d,
+  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+  0x6f6b63d8, 0xc0fe959f,
+  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+  0x6f39c57d, 0xc0a726df,
+  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+  0x6f07e285, 0xc04fdf32,
+  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+  0x6ed5bb10, 0xbff8bece,
+  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+  0x6ea34f3d, 0xbfa1c5ea,
+  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+  0x6e709f2a, 0xbf4af4ba,
+  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+  0x6e3daaf8, 0xbef44b74,
+  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+  0x6e0a72c5, 0xbe9dca4e,
+  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+  0x6dd6f6b1, 0xbe47717c,
+  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+  0x6da336dc, 0xbdf14135,
+  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+  0x6d6f3365, 0xbd9b39ad,
+  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+  0x6d3aec6e, 0xbd455b1a,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+  0x6d066215, 0xbcefa5b0,
+  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+  0x6cd1947c, 0xbc9a19a5,
+  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+  0x6c9c83c3, 0xbc44b72c,
+  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+  0x6c67300b, 0xbbef7e7c,
+  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+  0x6c319975, 0xbb9a6fc7,
+  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+  0x6bfbc021, 0xbb458b43,
+  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+  0x6bc5a431, 0xbaf0d125,
+  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+  0x6b8f45c7, 0xba9c41a0,
+  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+  0x6b58a503, 0xba47dce8,
+  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+  0x6b21c208, 0xb9f3a332,
+  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+  0x6aea9cf8, 0xb99f94b2,
+  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+  0x6ab335f4, 0xb94bb19b,
+  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+  0x6a7b8d1e, 0xb8f7fa21,
+  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+  0x6a43a29a, 0xb8a46e78,
+  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+  0x6a0b7689, 0xb8510ed4,
+  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+  0x69d3090e, 0xb7fddb67,
+  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+  0x699a5a4c, 0xb7aad465,
+  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+  0x69616a65, 0xb757fa01,
+  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+  0x6928397e, 0xb7054c6f,
+  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+  0x68eec7b9, 0xb6b2cbe2,
+  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+  0x68b5153a, 0xb660788c,
+  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+  0x687b2224, 0xb60e529f,
+  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+  0x6840ee9b, 0xb5bc5a50,
+  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+  0x68067ac3, 0xb56a8fd0,
+  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+  0x67cbc6c0, 0xb518f351,
+  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+  0x6790d2b6, 0xb4c78507,
+  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+  0x67559eca, 0xb4764523,
+  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+  0x671a2b20, 0xb42533d8,
+  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+  0x66de77dc, 0xb3d45157,
+  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+  0x66a28524, 0xb3839dd3,
+  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+  0x6666531d, 0xb333197c,
+  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+  0x6629e1ec, 0xb2e2c486,
+  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+  0x65ed31b5, 0xb2929f21,
+  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+  0x65b0429f, 0xb242a97e,
+  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+  0x657314cf, 0xb1f2e3d0,
+  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+  0x6535a86b, 0xb1a34e47,
+  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+  0x64f7fd98, 0xb153e915,
+  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+  0x64ba147d, 0xb104b46a,
+  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+  0x647bed3f, 0xb0b5b077,
+  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+  0x643d8806, 0xb066dd6d,
+  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+  0x63fee4f8, 0xb0183b7d,
+  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+  0x63c0043b, 0xafc9cad7,
+  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+  0x6380e5f6, 0xaf7b8bac,
+  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+  0x63418a50, 0xaf2d7e2b,
+  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+  0x6301f171, 0xaedfa285,
+  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+  0x62c21b7e, 0xae91f8eb,
+  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+  0x628208a1, 0xae44818b,
+  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+  0x6241b8ff, 0xadf73c96,
+  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+  0x62012cc2, 0xadaa2a3b,
+  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+  0x61c06410, 0xad5d4aaa,
+  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+  0x617f5f12, 0xad109e12,
+  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+  0x613e1df0, 0xacc424a3,
+  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+  0x60fca0d2, 0xac77de8b,
+  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+  0x60bae7e1, 0xac2bcbfa,
+  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+  0x6078f344, 0xabdfed1f,
+  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+  0x6036c325, 0xab944229,
+  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+  0x5ff457ad, 0xab48cb46,
+  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+  0x5fb1b104, 0xaafd88a4,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+  0x5f6ecf53, 0xaab27a73,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+  0x5f2bb2c5, 0xaa67a0e0,
+  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+  0x5ee85b82, 0xaa1cfc1a,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+  0x5ea4c9b3, 0xa9d28c4e,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+  0x5e60fd84, 0xa98851ac,
+  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+  0x5e1cf71c, 0xa93e4c5f,
+  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+  0x5dd8b6a7, 0xa8f47c97,
+  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+  0x5d943c4e, 0xa8aae280,
+  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+  0x5d4f883b, 0xa8617e48,
+  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+  0x5d0a9a9a, 0xa818501c,
+  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+  0x5cc57394, 0xa7cf582a,
+  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+  0x5c801354, 0xa786969e,
+  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+  0x5c3a7a05, 0xa73e0ba5,
+  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+  0x5bf4a7d2, 0xa6f5b76d,
+  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+  0x5bae9ce7, 0xa6ad9a21,
+  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+  0x5b68596d, 0xa665b3ee,
+  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+  0x5b21dd90, 0xa61e0501,
+  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+  0x5adb297d, 0xa5d68d85,
+  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+  0x5a943d5e, 0xa58f4da8,
+  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+  0x5a4d1960, 0xa5484594,
+  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+  0x5a05bdae, 0xa5017575,
+  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+  0x59be2a74, 0xa4badd78,
+  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+  0x59765fde, 0xa4747dc7,
+  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+  0x592e5e19, 0xa42e568f,
+  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+  0x58e62552, 0xa3e867fa,
+  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+  0x589db5b3, 0xa3a2b234,
+  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+  0x58550f6c, 0xa35d3567,
+  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+  0x580c32a7, 0xa317f1bf,
+  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+  0x57c31f92, 0xa2d2e766,
+  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+  0x5779d65b, 0xa28e1687,
+  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+  0x5730572e, 0xa2497f4c,
+  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+  0x56e6a239, 0xa20521e0,
+  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+  0x569cb7a8, 0xa1c0fe6c,
+  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+  0x565297ab, 0xa17d151b,
+  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+  0x5608426e, 0xa1396617,
+  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+  0x55bdb81f, 0xa0f5f189,
+  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+  0x5572f8ed, 0xa0b2b79b,
+  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+  0x55280505, 0xa06fb876,
+  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+  0x54dcdc96, 0xa02cf444,
+  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+  0x54917fce, 0x9fea6b2f,
+  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+  0x5445eedb, 0x9fa81d5e,
+  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+  0x53fa29ed, 0x9f660afb,
+  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+  0x53ae3131, 0x9f24342f,
+  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+  0x536204d7, 0x9ee29922,
+  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+  0x5315a50e, 0x9ea139fd,
+  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+  0x52c91204, 0x9e6016e8,
+  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+  0x527c4bea, 0x9e1f300b,
+  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+  0x522f52ee, 0x9dde858e,
+  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+  0x51e22740, 0x9d9e179a,
+  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+  0x5194c910, 0x9d5de656,
+  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+  0x5147388c, 0x9d1df1e9,
+  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+  0x50f975e6, 0x9cde3a7b,
+  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+  0x50ab814d, 0x9c9ec033,
+  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+  0x505d5af1, 0x9c5f8339,
+  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+  0x500f0302, 0x9c2083b3,
+  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+  0x4fc079b1, 0x9be1c1c8,
+  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+  0x4f71bf2e, 0x9ba33da0,
+  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+  0x4f22d3aa, 0x9b64f760,
+  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+  0x4ed3b755, 0x9b26ef2f,
+  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+  0x4e846a60, 0x9ae92533,
+  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+  0x4e34ecfc, 0x9aab9993,
+  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+  0x4de53f5a, 0x9a6e4c74,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+  0x4d9561ac, 0x9a313dfc,
+  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+  0x4d455422, 0x99f46e51,
+  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+  0x4cf516ee, 0x99b7dd99,
+  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+  0x4ca4aa41, 0x997b8bf8,
+  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+  0x4c540e4e, 0x993f7993,
+  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+  0x4c034345, 0x9903a691,
+  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+  0x4bb24958, 0x98c81316,
+  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+  0x4b6120bb, 0x988cbf46,
+  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+  0x4b0fc99d, 0x9851ab46,
+  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+  0x4abe4433, 0x9816d73b,
+  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+  0x4a6c90ad, 0x97dc4349,
+  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+  0x4a1aaf3f, 0x97a1ef94,
+  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+  0x49c8a01b, 0x9767dc41,
+  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+  0x49766373, 0x972e0971,
+  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+  0x4923f97b, 0x96f4774b,
+  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+  0x48d16265, 0x96bb25f0,
+  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+  0x487e9e64, 0x96821585,
+  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+  0x482badab, 0x9649462d,
+  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+  0x47d8906d, 0x9610b80a,
+  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+  0x478546de, 0x95d86b3f,
+  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+  0x4731d131, 0x95a05ff0,
+  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+  0x46de2f99, 0x9568963f,
+  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+  0x468a624a, 0x95310e4e,
+  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+  0x46366978, 0x94f9c83f,
+  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+  0x45e24556, 0x94c2c435,
+  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+  0x458df619, 0x948c0252,
+  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+  0x45397bf4, 0x945582b7,
+  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+  0x44e4d71c, 0x941f4585,
+  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+  0x449007c4, 0x93e94adf,
+  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+  0x443b0e21, 0x93b392e6,
+  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+  0x43e5ea68, 0x937e1dbb,
+  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+  0x43909ccd, 0x9348eb7e,
+  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+  0x433b2585, 0x9313fc51,
+  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+  0x42e584c3, 0x92df5054,
+  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+  0x428fbabe, 0x92aae7a8,
+  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+  0x4239c7aa, 0x9276c26d,
+  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+  0x41e3abbc, 0x9242e0c4,
+  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+  0x418d6729, 0x920f42cb,
+  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+  0x4136fa27, 0x91dbe8a4,
+  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+  0x40e064ea, 0x91a8d26d,
+  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+  0x4089a7a8, 0x91760047,
+  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+  0x4032c297, 0x91437250,
+  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+  0x3fdbb5ec, 0x911128a8,
+  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+  0x3f8481dd, 0x90df236e,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+  0x3f2d26a0, 0x90ad62c0,
+  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+  0x3ed5a46b, 0x907be6be,
+  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+  0x3e7dfb73, 0x904aaf86,
+  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+  0x3e262bee, 0x9019bd36,
+  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+  0x3dce3614, 0x8fe90fec,
+  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+  0x3d761a19, 0x8fb8a7c7,
+  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+  0x3d1dd835, 0x8f8884e4,
+  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+  0x3cc5709e, 0x8f58a761,
+  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+  0x3c6ce38a, 0x8f290f5c,
+  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+  0x3c143130, 0x8ef9bcf2,
+  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+  0x3bbb59c7, 0x8ecab040,
+  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+  0x3b625d86, 0x8e9be963,
+  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+  0x3b093ca3, 0x8e6d6877,
+  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+  0x3aaff755, 0x8e3f2d9b,
+  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+  0x3a568dd4, 0x8e1138ea,
+  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+  0x39fd0056, 0x8de38a80,
+  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+  0x39a34f13, 0x8db6227a,
+  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+  0x39497a43, 0x8d8900f3,
+  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+  0x38ef821c, 0x8d5c2609,
+  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+  0x389566d6, 0x8d2f91d5,
+  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+  0x383b28a9, 0x8d034474,
+  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+  0x37e0c7cc, 0x8cd73e01,
+  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+  0x37864477, 0x8cab7e98,
+  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+  0x372b9ee3, 0x8c800652,
+  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+  0x36d0d746, 0x8c54d54c,
+  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+  0x3675edd9, 0x8c29eb9f,
+  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+  0x361ae2d3, 0x8bff4966,
+  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+  0x35bfb66e, 0x8bd4eebc,
+  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+  0x356468e2, 0x8baadbba,
+  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+  0x3508fa66, 0x8b81107b,
+  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+  0x34ad6b32, 0x8b578d18,
+  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+  0x3451bb81, 0x8b2e51ab,
+  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+  0x33f5eb89, 0x8b055e4d,
+  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+  0x3399fb85, 0x8adcb318,
+  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+  0x333debab, 0x8ab45024,
+  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+  0x32e1bc36, 0x8a8c358b,
+  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+  0x32856d5e, 0x8a646365,
+  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+  0x3228ff5c, 0x8a3cd9cc,
+  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+  0x31cc7269, 0x8a1598d6,
+  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+  0x316fc6be, 0x89eea09d,
+  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+  0x3112fc95, 0x89c7f138,
+  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+  0x30b61426, 0x89a18ac0,
+  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+  0x30590dab, 0x897b6d4c,
+  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+  0x2ffbe95d, 0x895598f3,
+  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+  0x2f9ea775, 0x89300dce,
+  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+  0x2f41482e, 0x890acbf2,
+  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+  0x2ee3cbc1, 0x88e5d378,
+  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+  0x2e863267, 0x88c12475,
+  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+  0x2e287c5a, 0x889cbf01,
+  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+  0x2dcaa9d5, 0x8878a332,
+  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+  0x2d6cbb10, 0x8854d11e,
+  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+  0x2d0eb046, 0x883148db,
+  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+  0x2cb089b1, 0x880e0a7f,
+  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+  0x2c52478a, 0x87eb1621,
+  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+  0x2bf3ea0d, 0x87c86bd5,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+  0x2b957173, 0x87a60bb1,
+  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+  0x2b36ddf7, 0x8783f5ca,
+  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+  0x2ad82fd2, 0x87622a35,
+  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+  0x2a796740, 0x8740a907,
+  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+  0x2a1a847b, 0x871f7255,
+  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+  0x29bb87bc, 0x86fe8633,
+  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+  0x295c7140, 0x86dde4b5,
+  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+  0x28fd4140, 0x86bd8df0,
+  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+  0x289df7f8, 0x869d81f8,
+  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+  0x283e95a1, 0x867dc0e0,
+  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+  0x27df1a77, 0x865e4abb,
+  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+  0x277f86b5, 0x863f1f9e,
+  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+  0x271fda96, 0x86203f9c,
+  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+  0x26c01655, 0x8601aac7,
+  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+  0x26603a2c, 0x85e36132,
+  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+  0x26004657, 0x85c562f1,
+  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+  0x25a03b11, 0x85a7b015,
+  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+  0x25401896, 0x858a48b1,
+  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+  0x24dfdf20, 0x856d2cd7,
+  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+  0x247f8eec, 0x85505c99,
+  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+  0x241f2833, 0x8533d809,
+  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+  0x23beab33, 0x85179f39,
+  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+  0x235e1826, 0x84fbb239,
+  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+  0x22fd6f48, 0x84e0111b,
+  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+  0x229cb0d5, 0x84c4bbf0,
+  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+  0x223bdd08, 0x84a9b2ca,
+  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+  0x21daf41d, 0x848ef5b7,
+  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+  0x2179f64f, 0x847484ca,
+  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+  0x2118e3dc, 0x845a6012,
+  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+  0x20b7bcfe, 0x844087a0,
+  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+  0x205681f1, 0x8426fb84,
+  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+  0x1ff532f2, 0x840dbbcc,
+  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+  0x1f93d03c, 0x83f4c889,
+  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+  0x1f325a0b, 0x83dc21cb,
+  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+  0x1ed0d09d, 0x83c3c7a0,
+  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+  0x1e6f342c, 0x83abba17,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+  0x1e0d84f5, 0x8393f940,
+  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+  0x1dabc334, 0x837c8528,
+  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+  0x1d49ef26, 0x83655ddf,
+  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+  0x1ce80906, 0x834e8373,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+  0x1c861113, 0x8337f5f1,
+  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+  0x1c240786, 0x8321b568,
+  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+  0x1bc1ec9e, 0x830bc1e6,
+  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+  0x1b5fc097, 0x82f61b77,
+  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+  0x1afd83ad, 0x82e0c22a,
+  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+  0x1a9b361d, 0x82cbb60b,
+  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+  0x1a38d823, 0x82b6f727,
+  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+  0x19d669fc, 0x82a2858c,
+  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+  0x1973ebe6, 0x828e6146,
+  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+  0x19115e1c, 0x827a8a61,
+  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+  0x18aec0db, 0x826700e9,
+  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+  0x184c1461, 0x8253c4eb,
+  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+  0x17e958ea, 0x8240d673,
+  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+  0x17868eb3, 0x822e358b,
+  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+  0x1723b5f9, 0x821be240,
+  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+  0x16c0cef9, 0x8209dc9e,
+  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+  0x165dd9f0, 0x81f824ae,
+  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+  0x15fad71b, 0x81e6ba7c,
+  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+  0x1597c6b7, 0x81d59e13,
+  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+  0x1534a901, 0x81c4cf7d,
+  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+  0x14d17e36, 0x81b44ec4,
+  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+  0x146e4694, 0x81a41bf4,
+  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+  0x140b0258, 0x81943715,
+  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+  0x13a7b1bf, 0x8184a032,
+  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+  0x13445505, 0x81755754,
+  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+  0x12e0ec6a, 0x81665c84,
+  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+  0x127d7829, 0x8157afcd,
+  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+  0x1219f880, 0x81495136,
+  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+  0x11b66dad, 0x813b40ca,
+  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+  0x1152d7ed, 0x812d7e8f,
+  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+  0x10ef377d, 0x81200a90,
+  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+  0x108b8c9b, 0x8112e4d4,
+  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+  0x1027d784, 0x81060d63,
+  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+  0xfc41876, 0x80f98446,
+  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+  0xf604faf, 0x80ed4984,
+  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+  0xefc7d6b, 0x80e15d24,
+  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+  0xe98a1e9, 0x80d5bf2e,
+  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+  0xe34bd66, 0x80ca6fa9,
+  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+  0xdd0d01f, 0x80bf6e9c,
+  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+  0xd6cda53, 0x80b4bc0e,
+  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+  0xd08dc3f, 0x80aa5806,
+  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+  0xca4d620, 0x80a04289,
+  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+  0xc40c835, 0x80967b9f,
+  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+  0xbdcb2bb, 0x808d034c,
+  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+  0xb7895f0, 0x8083d998,
+  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+  0xb147211, 0x807afe87,
+  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+  0xab0475c, 0x8072721f,
+  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+  0xa4c1610, 0x806a3466,
+  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+  0x9e7de6a, 0x80624560,
+  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+  0x983a0a7, 0x805aa512,
+  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+  0x91f5d06, 0x80535381,
+  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+  0x8bb13c5, 0x804c50b2,
+  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+  0x856c520, 0x80459ca9,
+  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+  0x7f27157, 0x803f376a,
+  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+  0x78e18a7, 0x803920f8,
+  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+  0x729bb4e, 0x80335959,
+  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+  0x6c5598a, 0x802de08e,
+  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+  0x660f398, 0x8028b69c,
+  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+  0x5fc89b8, 0x8023db86,
+  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+  0x5981c26, 0x801f4f4f,
+  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+  0x533ab20, 0x801b11fa,
+  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+  0x4cf36e5, 0x80172388,
+  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+  0x46abfb3, 0x801383fe,
+  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+  0x40645c7, 0x8010335c,
+  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+  0x3a1c960, 0x800d31a5,
+  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+  0x33d4abb, 0x800a7edb,
+  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+  0x2d8ca16, 0x80081b00,
+  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+  0x27447b0, 0x80060614,
+  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+  0x20fc3c6, 0x8004401a,
+  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+  0x1ab3e97, 0x8002c912,
+  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+  0x146b860, 0x8001a0fd,
+  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+  0xe23160, 0x8000c7dc,
+  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+  0x80003daf,
+  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+  0x80000278,
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+  0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
+    0xffed2684,
+  0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
+    0x7ffff872, 0xffd40489,
+  0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
+    0x7fffed57, 0xffbae290,
+  0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
+    0x7fffdd4d, 0xffa1c09a,
+  0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
+    0x7fffc854, 0xff889ea7,
+  0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
+    0x7fffae6c, 0xff6f7cba,
+  0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
+    0x7fff8f94, 0xff565ad1,
+  0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
+    0x7fff6bcd, 0xff3d38ef,
+  0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
+    0x7fff4317, 0xff241715,
+  0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
+    0x7fff1572, 0xff0af543,
+  0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
+    0x7ffee2dd, 0xfef1d37b,
+  0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
+    0x7ffeab59, 0xfed8b1bd,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
+    0x7ffe6ee5, 0xfebf900a,
+  0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
+    0x7ffe2d83, 0xfea66e64,
+  0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
+    0x7ffde731, 0xfe8d4ccb,
+  0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
+    0x7ffd9bf0, 0xfe742b41,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
+    0x7ffd4bc0, 0xfe5b09c5,
+  0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
+    0x7ffcf6a0, 0xfe41e85a,
+  0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
+    0x7ffc9c92, 0xfe28c700,
+  0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
+    0x7ffc3d94, 0xfe0fa5b8,
+  0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
+    0x7ffbd9a7, 0xfdf68484,
+  0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
+    0x7ffb70cb, 0xfddd6363,
+  0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
+    0x7ffb0300, 0xfdc44258,
+  0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
+    0x7ffa9045, 0xfdab2162,
+  0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
+    0x7ffa189c, 0xfd920084,
+  0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
+    0x7ff99c03, 0xfd78dfbd,
+  0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
+    0x7ff91a7b, 0xfd5fbf10,
+  0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
+    0x7ff89405, 0xfd469e7c,
+  0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
+    0x7ff8089f, 0xfd2d7e04,
+  0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
+    0x7ff7784a, 0xfd145da7,
+  0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
+    0x7ff6e307, 0xfcfb3d67,
+  0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
+    0x7ff648d4, 0xfce21d45,
+  0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
+    0x7ff5a9b2, 0xfcc8fd41,
+  0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
+    0x7ff505a2, 0xfcafdd5e,
+  0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
+    0x7ff45ca3, 0xfc96bd9b,
+  0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
+    0x7ff3aeb4, 0xfc7d9df9,
+  0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
+    0x7ff2fbd7, 0xfc647e7b,
+  0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
+    0x7ff2440b, 0xfc4b5f20,
+  0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
+    0x7ff18751, 0xfc323fe9,
+  0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
+    0x7ff0c5a7, 0xfc1920d8,
+  0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
+    0x7fefff0f, 0xfc0001ee,
+  0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
+    0x7fef3388, 0xfbe6e32b,
+  0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
+    0x7fee6313, 0xfbcdc490,
+  0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
+    0x7fed8daf, 0xfbb4a61f,
+  0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
+    0x7fecb35c, 0xfb9b87d8,
+  0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
+    0x7febd41b, 0xfb8269bd,
+  0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
+    0x7feaefeb, 0xfb694bce,
+  0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
+    0x7fea06cd, 0xfb502e0c,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
+    0x7fe918c0, 0xfb371078,
+  0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
+    0x7fe825c5, 0xfb1df314,
+  0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
+    0x7fe72ddb, 0xfb04d5e0,
+  0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
+    0x7fe63103, 0xfaebb8dd,
+  0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
+    0x7fe52f3d, 0xfad29c0c,
+  0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
+    0x7fe42889, 0xfab97f6e,
+  0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
+    0x7fe31ce6, 0xfaa06305,
+  0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
+    0x7fe20c55, 0xfa8746d0,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
+    0x7fe0f6d6, 0xfa6e2ad1,
+  0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
+    0x7fdfdc69, 0xfa550f0a,
+  0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
+    0x7fdebd0d, 0xfa3bf37a,
+  0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
+    0x7fdd98c4, 0xfa22d823,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
+    0x7fdc6f8d, 0xfa09bd06,
+  0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
+    0x7fdb4167, 0xf9f0a224,
+  0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
+    0x7fda0e54, 0xf9d7877e,
+  0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
+    0x7fd8d653, 0xf9be6d15,
+  0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
+    0x7fd79965, 0xf9a552e9,
+  0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
+    0x7fd65788, 0xf98c38fc,
+  0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
+    0x7fd510be, 0xf9731f4e,
+  0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
+    0x7fd3c506, 0xf95a05e2,
+  0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
+    0x7fd27460, 0xf940ecb7,
+  0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
+    0x7fd11ecd, 0xf927d3ce,
+  0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
+    0x7fcfc44d, 0xf90ebb29,
+  0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
+    0x7fce64df, 0xf8f5a2c9,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
+    0x7fcd0083, 0xf8dc8aae,
+  0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
+    0x7fcb973b, 0xf8c372d9,
+  0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
+    0x7fca2905, 0xf8aa5b4c,
+  0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
+    0x7fc8b5e1, 0xf8914407,
+  0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
+    0x7fc73dd1, 0xf8782d0c,
+  0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
+    0x7fc5c0d3, 0xf85f165b,
+  0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
+    0x7fc43ee9, 0xf845fff5,
+  0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
+    0x7fc2b811, 0xf82ce9dc,
+  0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
+    0x7fc12c4d, 0xf813d410,
+  0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
+    0x7fbf9b9b, 0xf7fabe92,
+  0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
+    0x7fbe05fd, 0xf7e1a963,
+  0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
+    0x7fbc6b72, 0xf7c89484,
+  0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
+    0x7fbacbfa, 0xf7af7ff6,
+  0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
+    0x7fb92796, 0xf7966bbb,
+  0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
+    0x7fb77e45, 0xf77d57d2,
+  0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
+    0x7fb5d007, 0xf764443d,
+  0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
+    0x7fb41cdd, 0xf74b30fe,
+  0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
+    0x7fb264c7, 0xf7321e14,
+  0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
+    0x7fb0a7c4, 0xf7190b81,
+  0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
+    0x7faee5d5, 0xf6fff946,
+  0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
+    0x7fad1efa, 0xf6e6e764,
+  0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
+    0x7fab5333, 0xf6cdd5dc,
+  0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
+    0x7fa98280, 0xf6b4c4ae,
+  0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
+    0x7fa7ace1, 0xf69bb3dd,
+  0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
+    0x7fa5d256, 0xf682a367,
+  0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
+    0x7fa3f2df, 0xf6699350,
+  0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
+    0x7fa20e7c, 0xf6508397,
+  0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
+    0x7fa0252e, 0xf637743e,
+  0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
+    0x7f9e36f4, 0xf61e6545,
+  0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
+    0x7f9c43ce, 0xf60556ae,
+  0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
+    0x7f9a4bbd, 0xf5ec4879,
+  0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
+    0x7f984ec1, 0xf5d33aa8,
+  0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
+    0x7f964cd9, 0xf5ba2d3b,
+  0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
+    0x7f944606, 0xf5a12034,
+  0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
+    0x7f923a48, 0xf5881393,
+  0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
+    0x7f90299f, 0xf56f0759,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
+    0x7f8e140a, 0xf555fb88,
+  0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
+    0x7f8bf98b, 0xf53cf01f,
+  0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
+    0x7f89da21, 0xf523e521,
+  0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
+    0x7f87b5cd, 0xf50ada8f,
+  0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
+    0x7f858c8d, 0xf4f1d068,
+  0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
+    0x7f835e64, 0xf4d8c6ae,
+  0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
+    0x7f812b4f, 0xf4bfbd63,
+  0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
+    0x7f7ef350, 0xf4a6b486,
+  0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
+    0x7f7cb667, 0xf48dac1a,
+  0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
+    0x7f7a7494, 0xf474a41f,
+  0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
+    0x7f782dd6, 0xf45b9c95,
+  0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
+    0x7f75e22e, 0xf442957e,
+  0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
+    0x7f73919d, 0xf4298edc,
+  0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
+    0x7f713c21, 0xf41088ae,
+  0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
+    0x7f6ee1bc, 0xf3f782f6,
+  0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
+    0x7f6c826d, 0xf3de7db4,
+  0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
+    0x7f6a1e34, 0xf3c578eb,
+  0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
+    0x7f67b512, 0xf3ac749a,
+  0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
+    0x7f654706, 0xf39370c2,
+  0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
+    0x7f62d411, 0xf37a6d66,
+  0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
+    0x7f605c33, 0xf3616a85,
+  0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
+    0x7f5ddf6b, 0xf3486820,
+  0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
+    0x7f5b5dbb, 0xf32f6639,
+  0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
+    0x7f58d721, 0xf31664d1,
+  0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
+    0x7f564b9f, 0xf2fd63e8,
+  0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
+    0x7f53bb34, 0xf2e4637f,
+  0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
+    0x7f5125e0, 0xf2cb6398,
+  0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
+    0x7f4e8ba4, 0xf2b26433,
+  0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
+    0x7f4bec7f, 0xf2996551,
+  0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
+    0x7f494872, 0xf28066f4,
+  0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
+    0x7f469f7d, 0xf267691b,
+  0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
+    0x7f43f19f, 0xf24e6bc9,
+  0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
+    0x7f413ed9, 0xf2356efe,
+  0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
+    0x7f3e872c, 0xf21c72bc,
+  0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
+    0x7f3bca96, 0xf2037702,
+  0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
+    0x7f390919, 0xf1ea7bd2,
+  0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
+    0x7f3642b4, 0xf1d1812e,
+  0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
+    0x7f337768, 0xf1b88715,
+  0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
+    0x7f30a734, 0xf19f8d89,
+  0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
+    0x7f2dd219, 0xf186948c,
+  0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
+    0x7f2af817, 0xf16d9c1d,
+  0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
+    0x7f28192d, 0xf154a43d,
+  0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
+    0x7f25355d, 0xf13bacef,
+  0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
+    0x7f224ca6, 0xf122b632,
+  0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
+    0x7f1f5f08, 0xf109c009,
+  0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
+    0x7f1c6c83, 0xf0f0ca72,
+  0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
+    0x7f197518, 0xf0d7d571,
+  0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
+    0x7f1678c6, 0xf0bee105,
+  0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
+    0x7f13778e, 0xf0a5ed2f,
+  0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
+    0x7f107170, 0xf08cf9f1,
+  0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
+    0x7f0d666c, 0xf074074c,
+  0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
+    0x7f0a5682, 0xf05b1540,
+  0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
+    0x7f0741b2, 0xf04223ce,
+  0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
+    0x7f0427fc, 0xf02932f8,
+  0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
+    0x7f010961, 0xf01042be,
+  0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
+    0x7efde5e0, 0xeff75321,
+  0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
+    0x7efabd7a, 0xefde6423,
+  0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
+    0x7ef7902f, 0xefc575c3,
+  0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
+    0x7ef45dfe, 0xefac8804,
+  0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
+    0x7ef126e9, 0xef939ae6,
+  0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
+    0x7eedeaee, 0xef7aae6b,
+  0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
+    0x7eeaaa0f, 0xef61c292,
+  0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
+    0x7ee7644c, 0xef48d75d,
+  0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
+    0x7ee419a3, 0xef2feccd,
+  0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
+    0x7ee0ca17, 0xef1702e4,
+  0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
+    0x7edd75a6, 0xeefe19a1,
+  0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
+    0x7eda1c51, 0xeee53105,
+  0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
+    0x7ed6be18, 0xeecc4913,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
+    0x7ed35afb, 0xeeb361cb,
+  0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
+    0x7ecff2fb, 0xee9a7b2d,
+  0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
+    0x7ecc8617, 0xee81953b,
+  0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
+    0x7ec9144f, 0xee68aff6,
+  0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
+    0x7ec59da5, 0xee4fcb5e,
+  0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
+    0x7ec22217, 0xee36e775,
+  0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
+    0x7ebea1a6, 0xee1e043b,
+  0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
+    0x7ebb1c52, 0xee0521b2,
+  0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
+    0x7eb7921b, 0xedec3fda,
+  0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
+    0x7eb40301, 0xedd35eb5,
+  0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
+    0x7eb06f05, 0xedba7e43,
+  0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
+    0x7eacd627, 0xeda19e85,
+  0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
+    0x7ea93867, 0xed88bf7d,
+  0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
+    0x7ea595c4, 0xed6fe12b,
+  0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
+    0x7ea1ee3f, 0xed570390,
+  0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
+    0x7e9e41d9, 0xed3e26ad,
+  0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
+    0x7e9a9091, 0xed254a84,
+  0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
+    0x7e96da67, 0xed0c6f14,
+  0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
+    0x7e931f5c, 0xecf39460,
+  0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
+    0x7e8f5f70, 0xecdaba67,
+  0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
+    0x7e8b9aa3, 0xecc1e12c,
+  0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
+    0x7e87d0f5, 0xeca908ae,
+  0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
+    0x7e840265, 0xec9030f0,
+  0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
+    0x7e802ef6, 0xec7759f1,
+  0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
+    0x7e7c56a5, 0xec5e83b3,
+  0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
+    0x7e787975, 0xec45ae36,
+  0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
+    0x7e749764, 0xec2cd97d,
+  0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
+    0x7e70b073, 0xec140587,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
+    0x7e6cc4a2, 0xebfb3256,
+  0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
+    0x7e68d3f2, 0xebe25fea,
+  0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
+    0x7e64de62, 0xebc98e45,
+  0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
+    0x7e60e3f2, 0xebb0bd67,
+  0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
+    0x7e5ce4a3, 0xeb97ed52,
+  0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
+    0x7e58e075, 0xeb7f1e06,
+  0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
+    0x7e54d768, 0xeb664f84,
+  0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
+    0x7e50c97c, 0xeb4d81ce,
+  0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
+    0x7e4cb6b1, 0xeb34b4e4,
+  0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
+    0x7e489f08, 0xeb1be8c8,
+  0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
+    0x7e448281, 0xeb031d79,
+  0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
+    0x7e40611b, 0xeaea52fa,
+  0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
+    0x7e3c3ad7, 0xead1894b,
+  0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
+    0x7e380fb5, 0xeab8c06c,
+  0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
+    0x7e33dfb6, 0xea9ff860,
+  0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
+    0x7e2faad9, 0xea873127,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
+    0x7e2b711f, 0xea6e6ac2,
+  0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
+    0x7e273287, 0xea55a531,
+  0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
+    0x7e22ef12, 0xea3ce077,
+  0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
+    0x7e1ea6c1, 0xea241c93,
+  0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
+    0x7e1a5992, 0xea0b5987,
+  0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
+    0x7e160787, 0xe9f29753,
+  0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
+    0x7e11b0a0, 0xe9d9d5fa,
+  0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
+    0x7e0d54dc, 0xe9c1157a,
+  0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
+    0x7e08f43d, 0xe9a855d7,
+  0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
+    0x7e048ec1, 0xe98f9710,
+  0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
+    0x7e00246a, 0xe976d926,
+  0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
+    0x7dfbb537, 0xe95e1c1b,
+  0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
+    0x7df74128, 0xe9455fef,
+  0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
+    0x7df2c83f, 0xe92ca4a4,
+  0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
+    0x7dee4a7a, 0xe913ea39,
+  0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
+    0x7de9c7da, 0xe8fb30b1,
+  0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
+    0x7de54060, 0xe8e2780d,
+  0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
+    0x7de0b40b, 0xe8c9c04c,
+  0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
+    0x7ddc22dc, 0xe8b10971,
+  0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
+    0x7dd78cd3, 0xe898537b,
+  0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
+    0x7dd2f1f0, 0xe87f9e6c,
+  0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
+    0x7dce5232, 0xe866ea46,
+  0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
+    0x7dc9ad9c, 0xe84e3708,
+  0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
+    0x7dc5042b, 0xe83584b4,
+  0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
+    0x7dc055e2, 0xe81cd34b,
+  0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
+    0x7dbba2bf, 0xe80422ce,
+  0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
+    0x7db6eac3, 0xe7eb733e,
+  0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
+    0x7db22def, 0xe7d2c49b,
+  0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
+    0x7dad6c42, 0xe7ba16e7,
+  0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
+    0x7da8a5bc, 0xe7a16a22,
+  0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
+    0x7da3da5f, 0xe788be4e,
+  0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
+    0x7d9f0a29, 0xe770136b,
+  0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
+    0x7d9a351c, 0xe757697b,
+  0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
+    0x7d955b37, 0xe73ec07e,
+  0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
+    0x7d907c7a, 0xe7261875,
+  0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
+    0x7d8b98e6, 0xe70d7162,
+  0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
+    0x7d86b07c, 0xe6f4cb45,
+  0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
+    0x7d81c33a, 0xe6dc261f,
+  0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
+    0x7d7cd121, 0xe6c381f1,
+  0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
+    0x7d77da32, 0xe6aadebc,
+  0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
+    0x7d72de6d, 0xe6923c82,
+  0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
+    0x7d6dddd2, 0xe6799b42,
+  0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
+    0x7d68d860, 0xe660fafe,
+  0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
+    0x7d63ce19, 0xe6485bb7,
+  0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
+    0x7d5ebefc, 0xe62fbd6e,
+  0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
+    0x7d59ab0a, 0xe6172024,
+  0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
+    0x7d549243, 0xe5fe83d9,
+  0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
+    0x7d4f74a7, 0xe5e5e88f,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
+    0x7d4a5236, 0xe5cd4e47,
+  0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
+    0x7d452af1, 0xe5b4b501,
+  0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
+    0x7d3ffed7, 0xe59c1cbf,
+  0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
+    0x7d3acde9, 0xe5838581,
+  0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
+    0x7d359827, 0xe56aef49,
+  0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
+    0x7d305d91, 0xe5525a17,
+  0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
+    0x7d2b1e28, 0xe539c5ec,
+  0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
+    0x7d25d9eb, 0xe52132c9,
+  0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
+    0x7d2090db, 0xe508a0b0,
+  0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
+    0x7d1b42f9, 0xe4f00fa1,
+  0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
+    0x7d15f043, 0xe4d77f9d,
+  0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
+    0x7d1098bb, 0xe4bef0a5,
+  0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
+    0x7d0b3c60, 0xe4a662ba,
+  0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
+    0x7d05db34, 0xe48dd5dd,
+  0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
+    0x7d007535, 0xe4754a0e,
+  0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
+    0x7cfb0a65, 0xe45cbf50,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
+    0x7cf59ac4, 0xe44435a2,
+  0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
+    0x7cf02651, 0xe42bad07,
+  0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
+    0x7ceaad0c, 0xe413257d,
+  0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
+    0x7ce52ef7, 0xe3fa9f08,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
+    0x7cdfac12, 0xe3e219a7,
+  0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
+    0x7cda245c, 0xe3c9955b,
+  0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
+    0x7cd497d5, 0xe3b11226,
+  0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
+    0x7ccf067f, 0xe3989008,
+  0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
+    0x7cc97059, 0xe3800f03,
+  0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
+    0x7cc3d563, 0xe3678f17,
+  0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
+    0x7cbe359e, 0xe34f1045,
+  0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
+    0x7cb8910a, 0xe336928e,
+  0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
+    0x7cb2e7a6, 0xe31e15f4,
+  0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
+    0x7cad3974, 0xe3059a76,
+  0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
+    0x7ca78674, 0xe2ed2017,
+  0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
+    0x7ca1cea5, 0xe2d4a6d6,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
+    0x7c9c1208, 0xe2bc2eb5,
+  0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
+    0x7c96509d, 0xe2a3b7b5,
+  0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
+    0x7c908a65, 0xe28b41d7,
+  0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
+    0x7c8abf5f, 0xe272cd1c,
+  0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
+    0x7c84ef8c, 0xe25a5984,
+  0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
+    0x7c7f1aed, 0xe241e711,
+  0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
+    0x7c794180, 0xe22975c4,
+  0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
+    0x7c736347, 0xe211059d,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
+    0x7c6d8041, 0xe1f8969d,
+  0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
+    0x7c679870, 0xe1e028c6,
+  0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
+    0x7c61abd3, 0xe1c7bc18,
+  0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
+    0x7c5bba6a, 0xe1af5094,
+  0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
+    0x7c55c436, 0xe196e63c,
+  0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
+    0x7c4fc936, 0xe17e7d0f,
+  0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
+    0x7c49c96c, 0xe1661510,
+  0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
+    0x7c43c4d7, 0xe14dae3f,
+  0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
+    0x7c3dbb78, 0xe135489d,
+  0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
+    0x7c37ad4e, 0xe11ce42a,
+  0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
+    0x7c319a5a, 0xe10480e9,
+  0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
+    0x7c2b829d, 0xe0ec1ed9,
+  0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
+    0x7c256616, 0xe0d3bdfc,
+  0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
+    0x7c1f44c6, 0xe0bb5e53,
+  0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
+    0x7c191ead, 0xe0a2ffde,
+  0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
+    0x7c12f3cb, 0xe08aa29f,
+  0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
+    0x7c0cc421, 0xe0724696,
+  0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
+    0x7c068fae, 0xe059ebc5,
+  0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
+    0x7c005673, 0xe041922c,
+  0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
+    0x7bfa1870, 0xe02939cc,
+  0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
+    0x7bf3d5a6, 0xe010e2a7,
+  0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
+    0x7bed8e14, 0xdff88cbc,
+  0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
+    0x7be741bb, 0xdfe0380e,
+  0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
+    0x7be0f09b, 0xdfc7e49d,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
+    0x7bda9ab5, 0xdfaf926a,
+  0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
+    0x7bd44008, 0xdf974176,
+  0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
+    0x7bcde095, 0xdf7ef1c2,
+  0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
+    0x7bc77c5d, 0xdf66a34e,
+  0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
+    0x7bc1135e, 0xdf4e561c,
+  0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
+    0x7bbaa59a, 0xdf360a2d,
+  0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
+    0x7bb43311, 0xdf1dbf82,
+  0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
+    0x7badbbc3, 0xdf05761b,
+  0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
+    0x7ba73fb1, 0xdeed2dfa,
+  0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
+    0x7ba0beda, 0xded4e71f,
+  0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
+    0x7b9a393f, 0xdebca18b,
+  0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
+    0x7b93aee0, 0xdea45d40,
+  0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
+    0x7b8d1fbd, 0xde8c1a3e,
+  0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
+    0x7b868bd7, 0xde73d886,
+  0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
+    0x7b7ff32e, 0xde5b9819,
+  0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
+    0x7b7955c2, 0xde4358f8,
+  0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
+    0x7b72b393, 0xde2b1b24,
+  0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
+    0x7b6c0ca2, 0xde12de9e,
+  0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
+    0x7b6560ee, 0xddfaa367,
+  0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
+    0x7b5eb079, 0xdde26980,
+  0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
+    0x7b57fb42, 0xddca30e9,
+  0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
+    0x7b51414a, 0xddb1f9a4,
+  0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
+    0x7b4a8291, 0xdd99c3b2,
+  0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
+    0x7b43bf17, 0xdd818f13,
+  0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
+    0x7b3cf6dc, 0xdd695bc9,
+  0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
+    0x7b3629e1, 0xdd5129d4,
+  0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
+    0x7b2f5826, 0xdd38f935,
+  0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
+    0x7b2881ac, 0xdd20c9ed,
+  0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
+    0x7b21a671, 0xdd089bfe,
+  0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
+    0x7b1ac678, 0xdcf06f68,
+  0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
+    0x7b13e1bf, 0xdcd8442b,
+  0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
+    0x7b0cf848, 0xdcc01a4a,
+  0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
+    0x7b060a12, 0xdca7f1c5,
+  0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
+    0x7aff171e, 0xdc8fca9c,
+  0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
+    0x7af81f6c, 0xdc77a4d2,
+  0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
+    0x7af122fd, 0xdc5f8066,
+  0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
+    0x7aea21d0, 0xdc475d59,
+  0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
+    0x7ae31be6, 0xdc2f3bad,
+  0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
+    0x7adc113f, 0xdc171b63,
+  0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
+    0x7ad501dc, 0xdbfefc7b,
+  0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
+    0x7acdedbc, 0xdbe6def6,
+  0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
+    0x7ac6d4e0, 0xdbcec2d6,
+  0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
+    0x7abfb749, 0xdbb6a81b,
+  0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
+    0x7ab894f6, 0xdb9e8ec6,
+  0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
+    0x7ab16de7, 0xdb8676d8,
+  0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
+    0x7aaa421e, 0xdb6e6052,
+  0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
+    0x7aa3119a, 0xdb564b35,
+  0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
+    0x7a9bdc5c, 0xdb3e3781,
+  0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
+    0x7a94a264, 0xdb262539,
+  0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
+    0x7a8d63b2, 0xdb0e145c,
+  0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
+    0x7a862046, 0xdaf604ec,
+  0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
+    0x7a7ed821, 0xdaddf6ea,
+  0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
+    0x7a778b43, 0xdac5ea56,
+  0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
+    0x7a7039ad, 0xdaaddf31,
+  0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
+    0x7a68e35e, 0xda95d57d,
+  0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
+    0x7a618857, 0xda7dcd3a,
+  0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
+    0x7a5a2898, 0xda65c669,
+  0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
+    0x7a52c421, 0xda4dc10b,
+  0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
+    0x7a4b5af3, 0xda35bd22,
+  0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
+    0x7a43ed0e, 0xda1dbaad,
+  0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
+    0x7a3c7a73, 0xda05b9ae,
+  0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
+    0x7a350321, 0xd9edba26,
+  0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
+    0x7a2d8719, 0xd9d5bc16,
+  0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
+    0x7a26065b, 0xd9bdbf7e,
+  0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
+    0x7a1e80e7, 0xd9a5c461,
+  0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
+    0x7a16f6be, 0xd98dcabd,
+  0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
+    0x7a0f67e0, 0xd975d295,
+  0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
+    0x7a07d44e, 0xd95ddbea,
+  0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
+    0x7a003c07, 0xd945e6bb,
+  0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
+    0x79f89f0c, 0xd92df30b,
+  0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
+    0x79f0fd5d, 0xd91600da,
+  0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
+    0x79e956fb, 0xd8fe1029,
+  0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
+    0x79e1abe6, 0xd8e620fa,
+  0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
+    0x79d9fc1d, 0xd8ce334c,
+  0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
+    0x79d247a2, 0xd8b64720,
+  0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
+    0x79ca8e75, 0xd89e5c79,
+  0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
+    0x79c2d095, 0xd8867356,
+  0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
+    0x79bb0e04, 0xd86e8bb9,
+  0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
+    0x79b346c2, 0xd856a5a3,
+  0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
+    0x79ab7ace, 0xd83ec114,
+  0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
+    0x79a3aa29, 0xd826de0d,
+  0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
+    0x799bd4d4, 0xd80efc8f,
+  0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
+    0x7993facf, 0xd7f71c9c,
+  0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
+    0x798c1c1a, 0xd7df3e34,
+  0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
+    0x798438b5, 0xd7c76158,
+  0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
+    0x797c50a1, 0xd7af8609,
+  0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
+    0x797463de, 0xd797ac48,
+  0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
+    0x796c726c, 0xd77fd415,
+  0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
+    0x79647c4c, 0xd767fd72,
+  0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
+    0x795c817d, 0xd7502860,
+  0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
+    0x79548201, 0xd73854e0,
+  0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
+    0x794c7dd7, 0xd72082f2,
+  0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
+    0x79447500, 0xd708b297,
+  0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
+    0x793c677d, 0xd6f0e3d1,
+  0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
+    0x7934554d, 0xd6d916a0,
+  0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
+    0x792c3e70, 0xd6c14b05,
+  0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
+    0x792422e8, 0xd6a98101,
+  0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
+    0x791c02b4, 0xd691b895,
+  0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
+    0x7913ddd4, 0xd679f1c2,
+  0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
+    0x790bb44a, 0xd6622c89,
+  0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
+    0x79038615, 0xd64a68eb,
+  0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
+    0x78fb5336, 0xd632a6e8,
+  0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
+    0x78f31bac, 0xd61ae682,
+  0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
+    0x78eadf79, 0xd60327b9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
+    0x78e29e9d, 0xd5eb6a8f,
+  0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
+    0x78da5917, 0xd5d3af04,
+  0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
+    0x78d20ee9, 0xd5bbf519,
+  0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
+    0x78c9c012, 0xd5a43cd0,
+  0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
+    0x78c16c93, 0xd58c8628,
+  0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
+    0x78b9146c, 0xd574d124,
+  0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
+    0x78b0b79e, 0xd55d1dc3,
+  0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
+    0x78a85628, 0xd5456c07,
+  0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
+    0x789ff00c, 0xd52dbbf1,
+  0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
+    0x78978549, 0xd5160d82,
+  0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
+    0x788f15e0, 0xd4fe60ba,
+  0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
+    0x7886a1d1, 0xd4e6b59a,
+  0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
+    0x787e291d, 0xd4cf0c24,
+  0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
+    0x7875abc3, 0xd4b76458,
+  0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
+    0x786d29c5, 0xd49fbe37,
+  0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
+    0x7864a322, 0xd48819c3,
+  0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
+    0x785c17db, 0xd47076fb,
+  0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
+    0x785387ef, 0xd458d5e2,
+  0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
+    0x784af361, 0xd4413677,
+  0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
+    0x78425a2f, 0xd42998bc,
+  0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
+    0x7839bc5a, 0xd411fcb2,
+  0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
+    0x783119e2, 0xd3fa6259,
+  0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
+    0x782872c8, 0xd3e2c9b2,
+  0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
+    0x781fc70d, 0xd3cb32c0,
+  0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
+    0x781716b0, 0xd3b39d81,
+  0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
+    0x780e61b1, 0xd39c09f7,
+  0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
+    0x7805a812, 0xd3847824,
+  0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
+    0x77fce9d2, 0xd36ce808,
+  0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
+    0x77f426f2, 0xd35559a4,
+  0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
+    0x77eb5f71, 0xd33dccf8,
+  0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
+    0x77e29352, 0xd3264206,
+  0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
+    0x77d9c293, 0xd30eb8cf,
+  0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
+    0x77d0ed35, 0xd2f73154,
+  0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
+    0x77c81339, 0xd2dfab95,
+  0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
+    0x77bf349f, 0xd2c82793,
+  0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
+    0x77b65166, 0xd2b0a54f,
+  0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
+    0x77ad6990, 0xd29924cb,
+  0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
+    0x77a47d1d, 0xd281a607,
+  0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
+    0x779b8c0e, 0xd26a2904,
+  0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
+    0x77929661, 0xd252adc3,
+  0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
+    0x77899c19, 0xd23b3444,
+  0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
+    0x77809d35, 0xd223bc8a,
+  0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
+    0x777799b5, 0xd20c4694,
+  0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
+    0x776e919a, 0xd1f4d263,
+  0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
+    0x776584e5, 0xd1dd5ff9,
+  0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
+    0x775c7395, 0xd1c5ef56,
+  0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
+    0x77535dab, 0xd1ae807c,
+  0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
+    0x774a4327, 0xd197136b,
+  0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
+    0x7741240a, 0xd17fa823,
+  0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
+    0x77380054, 0xd1683ea7,
+  0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
+    0x772ed805, 0xd150d6f6,
+  0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
+    0x7725ab1f, 0xd1397113,
+  0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
+    0x771c79a0, 0xd1220cfc,
+  0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
+    0x77134389, 0xd10aaab5,
+  0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
+    0x770a08dc, 0xd0f34a3d,
+  0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
+    0x7700c997, 0xd0dbeb95,
+  0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
+    0x76f785bc, 0xd0c48ebf,
+  0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
+    0x76ee3d4b, 0xd0ad33ba,
+  0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
+    0x76e4f044, 0xd095da89,
+  0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
+    0x76db9ea7, 0xd07e832c,
+  0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
+    0x76d24876, 0xd0672da3,
+  0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
+    0x76c8edb0, 0xd04fd9f1,
+  0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
+    0x76bf8e55, 0xd0388815,
+  0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
+    0x76b62a66, 0xd0213810,
+  0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
+    0x76acc1e4, 0xd009e9e4,
+  0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
+    0x76a354cf, 0xcff29d92,
+  0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
+    0x7699e326, 0xcfdb531a,
+  0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
+    0x76906ceb, 0xcfc40a7c,
+  0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
+    0x7686f21e, 0xcfacc3bb,
+  0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
+    0x767d72bf, 0xcf957ed7,
+  0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
+    0x7673eecf, 0xcf7e3bd1,
+  0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
+    0x766a664d, 0xcf66faa9,
+  0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
+    0x7660d93b, 0xcf4fbb61,
+  0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
+    0x76574798, 0xcf387dfa,
+  0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
+    0x764db166, 0xcf214274,
+  0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
+    0x764416a4, 0xcf0a08d0,
+  0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
+    0x763a7752, 0xcef2d110,
+  0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
+    0x7630d372, 0xcedb9b33,
+  0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
+    0x76272b03, 0xcec4673c,
+  0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
+    0x761d7e06, 0xcead352b,
+  0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
+    0x7613cc7c, 0xce960500,
+  0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
+    0x760a1664, 0xce7ed6bd,
+  0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
+    0x76005bbf, 0xce67aa63,
+  0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
+    0x75f69c8d, 0xce507ff2,
+  0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
+    0x75ecd8cf, 0xce39576c,
+  0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
+    0x75e31086, 0xce2230d0,
+  0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
+    0x75d943b0, 0xce0b0c21,
+  0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
+    0x75cf7250, 0xcdf3e95f,
+  0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
+    0x75c59c65, 0xcddcc88b,
+  0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
+    0x75bbc1ef, 0xcdc5a9a6,
+  0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
+    0x75b1e2f0, 0xcdae8cb1,
+  0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
+    0x75a7ff67, 0xcd9771ac,
+  0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
+    0x759e1755, 0xcd805899,
+  0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
+    0x75942ab9, 0xcd694178,
+  0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
+    0x758a3996, 0xcd522c4a,
+  0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
+    0x758043ea, 0xcd3b1911,
+  0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
+    0x757649b7, 0xcd2407cc,
+  0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
+    0x756c4afc, 0xcd0cf87e,
+  0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
+    0x756247bb, 0xccf5eb26,
+  0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
+    0x75583ff3, 0xccdedfc7,
+  0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
+    0x754e33a4, 0xccc7d65f,
+  0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
+    0x754422d0, 0xccb0cef2,
+  0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
+    0x753a0d77, 0xcc99c97e,
+  0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
+    0x752ff399, 0xcc82c607,
+  0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
+    0x7525d536, 0xcc6bc48b,
+  0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
+    0x751bb24f, 0xcc54c50c,
+  0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
+    0x75118ae4, 0xcc3dc78b,
+  0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
+    0x75075ef5, 0xcc26cc09,
+  0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
+    0x74fd2e84, 0xcc0fd287,
+  0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
+    0x74f2f990, 0xcbf8db05,
+  0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
+    0x74e8c01a, 0xcbe1e585,
+  0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
+    0x74de8221, 0xcbcaf208,
+  0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
+    0x74d43fa8, 0xcbb4008d,
+  0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
+    0x74c9f8ad, 0xcb9d1117,
+  0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
+    0x74bfad32, 0xcb8623a5,
+  0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
+    0x74b55d36, 0xcb6f383a,
+  0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
+    0x74ab08bb, 0xcb584ed6,
+  0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
+    0x74a0afc0, 0xcb416779,
+  0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
+    0x74965246, 0xcb2a8224,
+  0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
+    0x748bf04d, 0xcb139ed9,
+  0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
+    0x748189d7, 0xcafcbd99,
+  0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
+    0x74771ee2, 0xcae5de64,
+  0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
+    0x746caf70, 0xcacf013a,
+  0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
+    0x74623b80, 0xcab8261e,
+  0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
+    0x7457c314, 0xcaa14d10,
+  0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
+    0x744d462c, 0xca8a7610,
+  0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
+    0x7442c4c8, 0xca73a120,
+  0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
+    0x74383ee9, 0xca5cce40,
+  0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
+    0x742db48e, 0xca45fd72,
+  0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
+    0x742325b9, 0xca2f2eb6,
+  0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
+    0x74189269, 0xca18620e,
+  0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
+    0x740dfaa0, 0xca019779,
+  0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
+    0x74035e5d, 0xc9eacef9,
+  0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
+    0x73f8bda2, 0xc9d4088f,
+  0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
+    0x73ee186e, 0xc9bd443c,
+  0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
+    0x73e36ec1, 0xc9a68200,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
+    0x73d8c09d, 0xc98fc1dc,
+  0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
+    0x73ce0e01, 0xc97903d2,
+  0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
+    0x73c356ef, 0xc96247e2,
+  0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
+    0x73b89b66, 0xc94b8e0d,
+  0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
+    0x73addb67, 0xc934d654,
+  0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
+    0x73a316f2, 0xc91e20b8,
+  0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
+    0x73984e07, 0xc9076d39,
+  0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
+    0x738d80a8, 0xc8f0bbd9,
+  0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
+    0x7382aed5, 0xc8da0c99,
+  0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
+    0x7377d88d, 0xc8c35f78,
+  0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
+    0x736cfdd2, 0xc8acb479,
+  0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
+    0x73621ea4, 0xc8960b9c,
+  0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
+    0x73573b03, 0xc87f64e2,
+  0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
+    0x734c52ef, 0xc868c04b,
+  0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
+    0x7341666a, 0xc8521dd9,
+  0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
+    0x73367572, 0xc83b7d8d,
+  0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
+    0x732b800a, 0xc824df67,
+  0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
+    0x73208632, 0xc80e4369,
+  0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
+    0x731587e8, 0xc7f7a992,
+  0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
+    0x730a8530, 0xc7e111e5,
+  0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
+    0x72ff7e07, 0xc7ca7c61,
+  0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
+    0x72f47270, 0xc7b3e909,
+  0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
+    0x72e9626a, 0xc79d57db,
+  0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
+    0x72de4df6, 0xc786c8db,
+  0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
+    0x72d33514, 0xc7703c08,
+  0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
+    0x72c817c6, 0xc759b163,
+  0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
+    0x72bcf60a, 0xc74328ed,
+  0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
+    0x72b1cfe1, 0xc72ca2a7,
+  0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
+    0x72a6a54d, 0xc7161e92,
+  0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
+    0x729b764d, 0xc6ff9cae,
+  0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
+    0x729042e3, 0xc6e91cfd,
+  0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
+    0x72850b0d, 0xc6d29f80,
+  0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
+    0x7279cecd, 0xc6bc2437,
+  0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
+    0x726e8e23, 0xc6a5ab23,
+  0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
+    0x72634910, 0xc68f3446,
+  0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
+    0x7257ff94, 0xc678bf9f,
+  0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
+    0x724cb1b0, 0xc6624d30,
+  0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
+    0x72415f63, 0xc64bdcf9,
+  0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
+    0x723608af, 0xc6356efc,
+  0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
+    0x722aad93, 0xc61f033a,
+  0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
+    0x721f4e11, 0xc60899b2,
+  0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
+    0x7213ea28, 0xc5f23267,
+  0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
+    0x720881d9, 0xc5dbcd59,
+  0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
+    0x71fd1525, 0xc5c56a89,
+  0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
+    0x71f1a40c, 0xc5af09f7,
+  0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
+    0x71e62e8f, 0xc598aba5,
+  0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
+    0x71dab4ad, 0xc5824f93,
+  0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
+    0x71cf3667, 0xc56bf5c2,
+  0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
+    0x71c3b3bf, 0xc5559e34,
+  0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
+    0x71b82cb3, 0xc53f48e9,
+  0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
+    0x71aca145, 0xc528f5e1,
+  0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
+    0x71a11175, 0xc512a51f,
+  0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
+    0x71957d44, 0xc4fc56a2,
+  0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
+    0x7189e4b2, 0xc4e60a6b,
+  0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
+    0x717e47bf, 0xc4cfc07c,
+  0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
+    0x7172a66c, 0xc4b978d4,
+  0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
+    0x716700b9, 0xc4a33376,
+  0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
+    0x715b56a7, 0xc48cf062,
+  0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
+    0x714fa836, 0xc476af98,
+  0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
+    0x7143f567, 0xc460711b,
+  0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
+    0x71383e3a, 0xc44a34e9,
+  0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
+    0x712c82b0, 0xc433fb05,
+  0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
+    0x7120c2c8, 0xc41dc36f,
+  0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
+    0x7114fe84, 0xc4078e28,
+  0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
+    0x710935e4, 0xc3f15b31,
+  0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
+    0x70fd68e9, 0xc3db2a8b,
+  0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
+    0x70f19792, 0xc3c4fc36,
+  0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
+    0x70e5c1e1, 0xc3aed034,
+  0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
+    0x70d9e7d5, 0xc398a685,
+  0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
+    0x70ce096f, 0xc3827f2a,
+  0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
+    0x70c226b0, 0xc36c5a24,
+  0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
+    0x70b63f99, 0xc3563774,
+  0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
+    0x70aa5428, 0xc340171b,
+  0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
+    0x709e6460, 0xc329f919,
+  0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
+    0x70927041, 0xc313dd70,
+  0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
+    0x708677ca, 0xc2fdc420,
+  0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
+    0x707a7afd, 0xc2e7ad2a,
+  0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
+    0x706e79d9, 0xc2d1988f,
+  0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
+    0x70627460, 0xc2bb8650,
+  0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
+    0x70566a92, 0xc2a5766e,
+  0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
+    0x704a5c6f, 0xc28f68e9,
+  0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
+    0x703e49f8, 0xc2795dc3,
+  0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
+    0x7032332d, 0xc26354fc,
+  0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
+    0x7026180e, 0xc24d4e95,
+  0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
+    0x7019f89d, 0xc2374a8f,
+  0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
+    0x700dd4da, 0xc22148ea,
+  0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
+    0x7001acc4, 0xc20b49a9,
+  0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
+    0x6ff5805d, 0xc1f54cca,
+  0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
+    0x6fe94fa5, 0xc1df5251,
+  0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
+    0x6fdd1a9c, 0xc1c95a3c,
+  0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
+    0x6fd0e144, 0xc1b3648d,
+  0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
+    0x6fc4a39c, 0xc19d7145,
+  0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
+    0x6fb861a4, 0xc1878065,
+  0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
+    0x6fac1b5f, 0xc17191ee,
+  0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
+    0x6f9fd0cb, 0xc15ba5df,
+  0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
+    0x6f9381e9, 0xc145bc3c,
+  0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
+    0x6f872eba, 0xc12fd503,
+  0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
+    0x6f7ad73e, 0xc119f036,
+  0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
+    0x6f6e7b76, 0xc1040dd6,
+  0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
+    0x6f621b62, 0xc0ee2de3,
+  0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
+    0x6f55b703, 0xc0d8505f,
+  0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
+    0x6f494e5a, 0xc0c2754b,
+  0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
+    0x6f3ce165, 0xc0ac9ca6,
+  0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
+    0x6f307027, 0xc096c673,
+  0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
+    0x6f23faa0, 0xc080f2b1,
+  0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
+    0x6f1780cf, 0xc06b2162,
+  0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
+    0x6f0b02b6, 0xc0555287,
+  0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
+    0x6efe8056, 0xc03f8620,
+  0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
+    0x6ef1f9ad, 0xc029bc2e,
+  0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
+    0x6ee56ebe, 0xc013f4b2,
+  0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
+    0x6ed8df88, 0xbffe2fad,
+  0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
+    0x6ecc4c0d, 0xbfe86d20,
+  0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
+    0x6ebfb44b, 0xbfd2ad0b,
+  0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
+    0x6eb31845, 0xbfbcef70,
+  0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
+    0x6ea677fa, 0xbfa7344f,
+  0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
+    0x6e99d36b, 0xbf917ba9,
+  0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
+    0x6e8d2a99, 0xbf7bc57f,
+  0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
+    0x6e807d83, 0xbf6611d2,
+  0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
+    0x6e73cc2b, 0xbf5060a2,
+  0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
+    0x6e671690, 0xbf3ab1f1,
+  0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
+    0x6e5a5cb4, 0xbf2505bf,
+  0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
+    0x6e4d9e97, 0xbf0f5c0d,
+  0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
+    0x6e40dc39, 0xbef9b4dc,
+  0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
+    0x6e34159b, 0xbee4102d,
+  0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
+    0x6e274abe, 0xbece6e00,
+  0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
+    0x6e1a7ba1, 0xbeb8ce57,
+  0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
+    0x6e0da845, 0xbea33132,
+  0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
+    0x6e00d0ac, 0xbe8d9692,
+  0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
+    0x6df3f4d4, 0xbe77fe78,
+  0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
+    0x6de714c0, 0xbe6268e5,
+  0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
+    0x6dda306f, 0xbe4cd5da,
+  0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
+    0x6dcd47e1, 0xbe374557,
+  0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
+    0x6dc05b18, 0xbe21b75d,
+  0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
+    0x6db36a14, 0xbe0c2bed,
+  0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
+    0x6da674d5, 0xbdf6a309,
+  0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
+    0x6d997b5b, 0xbde11cb0,
+  0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
+    0x6d8c7da8, 0xbdcb98e3,
+  0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
+    0x6d7f7bbc, 0xbdb617a4,
+  0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
+    0x6d727597, 0xbda098f3,
+  0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
+    0x6d656b3a, 0xbd8b1cd2,
+  0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
+    0x6d585ca6, 0xbd75a340,
+  0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
+    0x6d4b49da, 0xbd602c3f,
+  0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
+    0x6d3e32d7, 0xbd4ab7cf,
+  0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
+    0x6d31179e, 0xbd3545f2,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
+    0x6d23f830, 0xbd1fd6a8,
+  0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
+    0x6d16d48c, 0xbd0a69f2,
+  0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
+    0x6d09acb4, 0xbcf4ffd1,
+  0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
+    0x6cfc80a7, 0xbcdf9846,
+  0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
+    0x6cef5067, 0xbcca3351,
+  0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
+    0x6ce21bf4, 0xbcb4d0f4,
+  0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
+    0x6cd4e34e, 0xbc9f712e,
+  0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
+    0x6cc7a676, 0xbc8a1402,
+  0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
+    0x6cba656c, 0xbc74b96f,
+  0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
+    0x6cad2031, 0xbc5f6177,
+  0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
+    0x6c9fd6c6, 0xbc4a0c1b,
+  0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
+    0x6c92892a, 0xbc34b95b,
+  0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
+    0x6c85375f, 0xbc1f6938,
+  0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
+    0x6c77e165, 0xbc0a1bb3,
+  0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
+    0x6c6a873d, 0xbbf4d0cc,
+  0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
+    0x6c5d28e6, 0xbbdf8885,
+  0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
+    0x6c4fc662, 0xbbca42df,
+  0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
+    0x6c425fb1, 0xbbb4ffda,
+  0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
+    0x6c34f4d3, 0xbb9fbf77,
+  0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
+    0x6c2785ca, 0xbb8a81b6,
+  0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
+    0x6c1a1295, 0xbb754699,
+  0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
+    0x6c0c9b35, 0xbb600e21,
+  0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
+    0x6bff1faa, 0xbb4ad84e,
+  0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
+    0x6bf19ff6, 0xbb35a521,
+  0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
+    0x6be41c18, 0xbb20749c,
+  0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
+    0x6bd69412, 0xbb0b46bd,
+  0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
+    0x6bc907e3, 0xbaf61b88,
+  0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
+    0x6bbb778d, 0xbae0f2fc,
+  0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
+    0x6bade30f, 0xbacbcd1a,
+  0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
+    0x6ba04a6a, 0xbab6a9e3,
+  0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
+    0x6b92ada0, 0xbaa18958,
+  0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
+    0x6b850caf, 0xba8c6b79,
+  0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
+    0x6b776799, 0xba775048,
+  0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
+    0x6b69be5f, 0xba6237c5,
+  0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
+    0x6b5c1101, 0xba4d21f2,
+  0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
+    0x6b4e5f7f, 0xba380ece,
+  0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
+    0x6b40a9d9, 0xba22fe5b,
+  0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
+    0x6b32f012, 0xba0df099,
+  0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
+    0x6b253228, 0xb9f8e58a,
+  0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
+    0x6b17701d, 0xb9e3dd2e,
+  0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
+    0x6b09a9f1, 0xb9ced786,
+  0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
+    0x6afbdfa4, 0xb9b9d493,
+  0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
+    0x6aee1138, 0xb9a4d455,
+  0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
+    0x6ae03eac, 0xb98fd6cd,
+  0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
+    0x6ad26802, 0xb97adbfd,
+  0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
+    0x6ac48d39, 0xb965e3e5,
+  0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
+    0x6ab6ae52, 0xb950ee86,
+  0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
+    0x6aa8cb4e, 0xb93bfbe0,
+  0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
+    0x6a9ae42e, 0xb9270bf5,
+  0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
+    0x6a8cf8f1, 0xb9121ec5,
+  0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
+    0x6a7f0999, 0xb8fd3451,
+  0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
+    0x6a711625, 0xb8e84c99,
+  0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
+    0x6a631e97, 0xb8d367a0,
+  0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
+    0x6a5522ef, 0xb8be8565,
+  0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
+    0x6a47232e, 0xb8a9a5e9,
+  0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
+    0x6a391f54, 0xb894c92d,
+  0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
+    0x6a2b1761, 0xb87fef33,
+  0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
+    0x6a1d0b57, 0xb86b17f9,
+  0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
+    0x6a0efb35, 0xb8564383,
+  0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
+    0x6a00e6fc, 0xb84171cf,
+  0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
+    0x69f2cead, 0xb82ca2e0,
+  0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
+    0x69e4b249, 0xb817d6b6,
+  0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
+    0x69d691cf, 0xb8030d51,
+  0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
+    0x69c86d41, 0xb7ee46b3,
+  0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
+    0x69ba449f, 0xb7d982dc,
+  0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
+    0x69ac17e9, 0xb7c4c1cd,
+  0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
+    0x699de721, 0xb7b00387,
+  0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
+    0x698fb246, 0xb79b480b,
+  0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
+    0x69817959, 0xb7868f59,
+  0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
+    0x69733c5b, 0xb771d972,
+  0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
+    0x6964fb4c, 0xb75d2658,
+  0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
+    0x6956b62d, 0xb748760b,
+  0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
+    0x69486cfe, 0xb733c88b,
+  0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
+    0x693a1fc0, 0xb71f1dd9,
+  0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
+    0x692bce73, 0xb70a75f7,
+  0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
+    0x691d7919, 0xb6f5d0e5,
+  0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
+    0x690f1fb1, 0xb6e12ea4,
+  0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
+    0x6900c23c, 0xb6cc8f35,
+  0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
+    0x68f260bb, 0xb6b7f298,
+  0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
+    0x68e3fb2e, 0xb6a358ce,
+  0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
+    0x68d59196, 0xb68ec1d9,
+  0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
+    0x68c723f3, 0xb67a2db8,
+  0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
+    0x68b8b247, 0xb6659c6d,
+  0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
+    0x68aa3c90, 0xb6510df8,
+  0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
+    0x689bc2d1, 0xb63c825b,
+  0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
+    0x688d4509, 0xb627f995,
+  0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
+    0x687ec339, 0xb61373a9,
+  0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
+    0x68703d62, 0xb5fef095,
+  0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
+    0x6861b384, 0xb5ea705d,
+  0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
+    0x685325a0, 0xb5d5f2ff,
+  0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
+    0x684493b6, 0xb5c1787e,
+  0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
+    0x6835fdc7, 0xb5ad00d9,
+  0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
+    0x682763d4, 0xb5988c12,
+  0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
+    0x6818c5dd, 0xb5841a29,
+  0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
+    0x680a23e2, 0xb56fab1f,
+  0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
+    0x67fb7de5, 0xb55b3ef5,
+  0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
+    0x67ecd3e5, 0xb546d5ac,
+  0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
+    0x67de25e3, 0xb5326f45,
+  0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
+    0x67cf73e1, 0xb51e0bbf,
+  0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
+    0x67c0bddd, 0xb509ab1d,
+  0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
+    0x67b203da, 0xb4f54d5f,
+  0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
+    0x67a345d8, 0xb4e0f285,
+  0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
+    0x679483d6, 0xb4cc9a90,
+  0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
+    0x6785bdd6, 0xb4b84582,
+  0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
+    0x6776f3d9, 0xb4a3f35b,
+  0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
+    0x676825de, 0xb48fa41c,
+  0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
+    0x675953e7, 0xb47b57c5,
+  0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
+    0x674a7df4, 0xb4670e57,
+  0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
+    0x673ba405, 0xb452c7d4,
+  0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
+    0x672cc61c, 0xb43e843b,
+  0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
+    0x671de438, 0xb42a438e,
+  0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
+    0x670efe5a, 0xb41605ce,
+  0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
+    0x67001483, 0xb401cafb,
+  0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
+    0x66f126b4, 0xb3ed9316,
+  0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
+    0x66e234ed, 0xb3d95e1f,
+  0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
+    0x66d33f2e, 0xb3c52c19,
+  0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
+    0x66c44579, 0xb3b0fd02,
+  0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
+    0x66b547cd, 0xb39cd0dd,
+  0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
+    0x66a6462b, 0xb388a7aa,
+  0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
+    0x66974095, 0xb3748169,
+  0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
+    0x66883709, 0xb3605e1c,
+  0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
+    0x6679298a, 0xb34c3dc3,
+  0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
+    0x666a1818, 0xb338205f,
+  0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
+    0x665b02b3, 0xb32405f1,
+  0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
+    0x664be95b, 0xb30fee79,
+  0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
+    0x663ccc12, 0xb2fbd9f9,
+  0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
+    0x662daad8, 0xb2e7c871,
+  0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
+    0x661e85ad, 0xb2d3b9e2,
+  0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
+    0x660f5c93, 0xb2bfae4c,
+  0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
+    0x66002f89, 0xb2aba5b1,
+  0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
+    0x65f0fe91, 0xb297a011,
+  0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
+    0x65e1c9aa, 0xb2839d6d,
+  0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
+    0x65d290d6, 0xb26f9dc6,
+  0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
+    0x65c35415, 0xb25ba11d,
+  0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
+    0x65b41367, 0xb247a771,
+  0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
+    0x65a4cece, 0xb233b0c5,
+  0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
+    0x6595864a, 0xb21fbd19,
+  0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
+    0x658639db, 0xb20bcc6d,
+  0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
+    0x6576e982, 0xb1f7dec2,
+  0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
+    0x6567953f, 0xb1e3f41a,
+  0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
+    0x65583d14, 0xb1d00c75,
+  0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
+    0x6548e101, 0xb1bc27d3,
+  0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
+    0x65398105, 0xb1a84636,
+  0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
+    0x652a1d23, 0xb194679e,
+  0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
+    0x651ab55b, 0xb1808c0c,
+  0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
+    0x650b49ac, 0xb16cb380,
+  0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
+    0x64fbda18, 0xb158ddfd,
+  0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
+    0x64ec66a0, 0xb1450b81,
+  0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
+    0x64dcef44, 0xb1313c0e,
+  0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
+    0x64cd7404, 0xb11d6fa6,
+  0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
+    0x64bdf4e1, 0xb109a648,
+  0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
+    0x64ae71dc, 0xb0f5dff5,
+  0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
+    0x649eeaf5, 0xb0e21cae,
+  0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
+    0x648f602d, 0xb0ce5c74,
+  0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
+    0x647fd185, 0xb0ba9f48,
+  0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
+    0x64703efc, 0xb0a6e52a,
+  0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
+    0x6460a895, 0xb0932e1b,
+  0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
+    0x64510e4e, 0xb07f7a1c,
+  0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
+    0x6441702a, 0xb06bc92e,
+  0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
+    0x6431ce28, 0xb0581b51,
+  0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
+    0x6422284a, 0xb0447087,
+  0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
+    0x64127e8f, 0xb030c8cf,
+  0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
+    0x6402d0f8, 0xb01d242b,
+  0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
+    0x63f31f86, 0xb009829c,
+  0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
+    0x63e36a3a, 0xaff5e421,
+  0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
+    0x63d3b114, 0xafe248bd,
+  0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
+    0x63c3f415, 0xafceb06f,
+  0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
+    0x63b4333d, 0xafbb1b39,
+  0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
+    0x63a46e8d, 0xafa7891b,
+  0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
+    0x6394a606, 0xaf93fa16,
+  0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
+    0x6384d9a7, 0xaf806e2b,
+  0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
+    0x63750973, 0xaf6ce55a,
+  0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
+    0x63653569, 0xaf595fa4,
+  0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
+    0x63555d8a, 0xaf45dd0b,
+  0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
+    0x634581d6, 0xaf325d8e,
+  0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
+    0x6335a24f, 0xaf1ee12e,
+  0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
+    0x6325bef5, 0xaf0b67ed,
+  0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
+    0x6315d7c8, 0xaef7f1cb,
+  0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
+    0x6305ecc9, 0xaee47ec9,
+  0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
+    0x62f5fdf9, 0xaed10ee7,
+  0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
+    0x62e60b58, 0xaebda227,
+  0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
+    0x62d614e7, 0xaeaa3888,
+  0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
+    0x62c61aa7, 0xae96d20c,
+  0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
+    0x62b61c98, 0xae836eb4,
+  0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
+    0x62a61aba, 0xae700e80,
+  0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
+    0x6296150f, 0xae5cb171,
+  0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
+    0x62860b97, 0xae495787,
+  0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
+    0x6275fe52, 0xae3600c4,
+  0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
+    0x6265ed42, 0xae22ad29,
+  0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
+    0x6255d866, 0xae0f5cb5,
+  0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
+    0x6245bfc0, 0xadfc0f6a,
+  0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
+    0x6235a351, 0xade8c548,
+  0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
+    0x62258317, 0xadd57e51,
+  0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
+    0x62155f16, 0xadc23a85,
+  0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
+    0x6205374c, 0xadaef9e4,
+  0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
+    0x61f50bba, 0xad9bbc70,
+  0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
+    0x61e4dc62, 0xad888229,
+  0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
+    0x61d4a944, 0xad754b0f,
+  0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
+    0x61c47260, 0xad621725,
+  0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
+    0x61b437b7, 0xad4ee66a,
+  0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
+    0x61a3f94a, 0xad3bb8df,
+  0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
+    0x6193b719, 0xad288e85,
+  0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
+    0x61837126, 0xad15675c,
+  0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
+    0x61732770, 0xad024366,
+  0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
+    0x6162d9f8, 0xacef22a3,
+  0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
+    0x615288be, 0xacdc0514,
+  0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
+    0x614233c5, 0xacc8eab9,
+  0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
+    0x6131db0b, 0xacb5d394,
+  0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
+    0x61217e92, 0xaca2bfa4,
+  0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
+    0x61111e5b, 0xac8faeec,
+  0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
+    0x6100ba65, 0xac7ca16b,
+  0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
+    0x60f052b2, 0xac699722,
+  0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
+    0x60dfe743, 0xac569012,
+  0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
+    0x60cf7817, 0xac438c3c,
+  0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
+    0x60bf0530, 0xac308ba0,
+  0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
+    0x60ae8e8d, 0xac1d8e40,
+  0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
+    0x609e1431, 0xac0a941b,
+  0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
+    0x608d961b, 0xabf79d33,
+  0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
+    0x607d144c, 0xabe4a988,
+  0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
+    0x606c8ec5, 0xabd1b91c,
+  0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
+    0x605c0587, 0xabbecbee,
+  0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
+    0x604b7891, 0xababe200,
+  0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
+    0x603ae7e5, 0xab98fb52,
+  0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
+    0x602a5383, 0xab8617e6,
+  0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
+    0x6019bb6b, 0xab7337bb,
+  0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
+    0x60091fa0, 0xab605ad2,
+  0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
+    0x5ff88021, 0xab4d812d,
+  0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
+    0x5fe7dcee, 0xab3aaacb,
+  0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
+    0x5fd73609, 0xab27d7ae,
+  0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
+    0x5fc68b72, 0xab1507d7,
+  0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
+    0x5fb5dd29, 0xab023b46,
+  0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
+    0x5fa52b31, 0xaaef71fb,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
+    0x5f947588, 0xaadcabf8,
+  0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
+    0x5f83bc2f, 0xaac9e93e,
+  0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
+    0x5f72ff28, 0xaab729cc,
+  0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
+    0x5f623e73, 0xaaa46da4,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
+    0x5f517a11, 0xaa91b4c7,
+  0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
+    0x5f40b202, 0xaa7eff34,
+  0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
+    0x5f2fe647, 0xaa6c4cee,
+  0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
+    0x5f1f16e0, 0xaa599df4,
+  0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
+    0x5f0e43ce, 0xaa46f248,
+  0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
+    0x5efd6d13, 0xaa3449e9,
+  0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
+    0x5eec92ae, 0xaa21a4d9,
+  0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
+    0x5edbb49f, 0xaa0f0319,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
+    0x5ecad2e9, 0xa9fc64a9,
+  0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
+    0x5eb9ed8b, 0xa9e9c98a,
+  0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
+    0x5ea90487, 0xa9d731bd,
+  0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
+    0x5e9817dc, 0xa9c49d42,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
+    0x5e87278b, 0xa9b20c1a,
+  0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
+    0x5e763395, 0xa99f7e46,
+  0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
+    0x5e653bfc, 0xa98cf3c6,
+  0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
+    0x5e5440be, 0xa97a6c9c,
+  0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
+    0x5e4341de, 0xa967e8c7,
+  0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
+    0x5e323f5b, 0xa9556849,
+  0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
+    0x5e213936, 0xa942eb23,
+  0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
+    0x5e102f71, 0xa9307155,
+  0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
+    0x5dff220b, 0xa91dfadf,
+  0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
+    0x5dee1105, 0xa90b87c3,
+  0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
+    0x5ddcfc61, 0xa8f91801,
+  0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
+    0x5dcbe41d, 0xa8e6ab9a,
+  0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
+    0x5dbac83d, 0xa8d4428f,
+  0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
+    0x5da9a8bf, 0xa8c1dce0,
+  0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
+    0x5d9885a5, 0xa8af7a8e,
+  0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
+    0x5d875eef, 0xa89d1b99,
+  0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
+    0x5d76349d, 0xa88ac004,
+  0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
+    0x5d6506b2, 0xa87867cd,
+  0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
+    0x5d53d52d, 0xa86612f6,
+  0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
+    0x5d42a00e, 0xa853c180,
+  0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
+    0x5d316757, 0xa841736c,
+  0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
+    0x5d202b09, 0xa82f28b9,
+  0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
+    0x5d0eeb23, 0xa81ce169,
+  0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
+    0x5cfda7a7, 0xa80a9d7c,
+  0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
+    0x5cec6095, 0xa7f85cf3,
+  0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
+    0x5cdb15ed, 0xa7e61fd0,
+  0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
+    0x5cc9c7b2, 0xa7d3e611,
+  0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
+    0x5cb875e3, 0xa7c1afb9,
+  0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
+    0x5ca72080, 0xa7af7cc8,
+  0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
+    0x5c95c78b, 0xa79d4d3f,
+  0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
+    0x5c846b05, 0xa78b211e,
+  0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
+    0x5c730aed, 0xa778f866,
+  0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
+    0x5c61a745, 0xa766d317,
+  0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
+    0x5c50400d, 0xa754b134,
+  0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
+    0x5c3ed545, 0xa74292bb,
+  0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
+    0x5c2d66f0, 0xa73077ae,
+  0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
+    0x5c1bf50d, 0xa71e600d,
+  0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
+    0x5c0a7f9c, 0xa70c4bda,
+  0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
+    0x5bf906a0, 0xa6fa3b15,
+  0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
+    0x5be78a17, 0xa6e82dbe,
+  0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
+    0x5bd60a03, 0xa6d623d7,
+  0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
+    0x5bc48666, 0xa6c41d60,
+  0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
+    0x5bb2ff3e, 0xa6b21a59,
+  0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
+    0x5ba1748d, 0xa6a01ac4,
+  0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
+    0x5b8fe654, 0xa68e1ea1,
+  0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
+    0x5b7e5493, 0xa67c25f0,
+  0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
+    0x5b6cbf4c, 0xa66a30b3,
+  0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
+    0x5b5b267e, 0xa6583eeb,
+  0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
+    0x5b498a2a, 0xa6465097,
+  0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
+    0x5b37ea51, 0xa63465b9,
+  0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
+    0x5b2646f4, 0xa6227e50,
+  0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
+    0x5b14a014, 0xa6109a5f,
+  0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
+    0x5b02f5b0, 0xa5feb9e6,
+  0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
+    0x5af147ca, 0xa5ecdce5,
+  0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
+    0x5adf9663, 0xa5db035c,
+  0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
+    0x5acde17b, 0xa5c92d4e,
+  0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
+    0x5abc2912, 0xa5b75aba,
+  0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
+    0x5aaa6d2b, 0xa5a58ba1,
+  0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
+    0x5a98adc4, 0xa593c004,
+  0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
+    0x5a86eadf, 0xa581f7e3,
+  0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
+    0x5a75247c, 0xa570333f,
+  0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
+    0x5a635a9d, 0xa55e7219,
+  0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
+    0x5a518d42, 0xa54cb472,
+  0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
+    0x5a3fbc6b, 0xa53afa49,
+  0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
+    0x5a2de81a, 0xa52943a1,
+  0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
+    0x5a1c104f, 0xa5179079,
+  0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
+    0x5a0a350a, 0xa505e0d2,
+  0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
+    0x59f8564c, 0xa4f434ae,
+  0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
+    0x59e67417, 0xa4e28c0c,
+  0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
+    0x59d48e6a, 0xa4d0e6ed,
+  0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
+    0x59c2a547, 0xa4bf4552,
+  0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
+    0x59b0b8ae, 0xa4ada73c,
+  0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
+    0x599ec8a0, 0xa49c0cab,
+  0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
+    0x598cd51d, 0xa48a75a0,
+  0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
+    0x597ade26, 0xa478e21b,
+  0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
+    0x5968e3bc, 0xa467521e,
+  0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
+    0x5956e5e0, 0xa455c5a9,
+  0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
+    0x5944e492, 0xa4443cbd,
+  0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
+    0x5932dfd3, 0xa432b75a,
+  0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
+    0x5920d7a3, 0xa4213581,
+  0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
+    0x590ecc04, 0xa40fb733,
+  0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
+    0x58fcbcf6, 0xa3fe3c71,
+  0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
+    0x58eaaa7a, 0xa3ecc53a,
+  0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
+    0x58d89490, 0xa3db5190,
+  0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
+    0x58c67b39, 0xa3c9e174,
+  0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
+    0x58b45e76, 0xa3b874e5,
+  0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
+    0x58a23e48, 0xa3a70be6,
+  0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
+    0x58901aaf, 0xa395a675,
+  0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
+    0x587df3ab, 0xa3844495,
+  0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
+    0x586bc93f, 0xa372e646,
+  0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
+    0x58599b69, 0xa3618b88,
+  0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
+    0x58476a2c, 0xa350345c,
+  0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
+    0x58353587, 0xa33ee0c3,
+  0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
+    0x5822fd7c, 0xa32d90be,
+  0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
+    0x5810c20b, 0xa31c444c,
+  0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
+    0x57fe8335, 0xa30afb70,
+  0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
+    0x57ec40fa, 0xa2f9b629,
+  0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
+    0x57d9fb5c, 0xa2e87477,
+  0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
+    0x57c7b25a, 0xa2d7365d,
+  0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
+    0x57b565f6, 0xa2c5fbda,
+  0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
+    0x57a31631, 0xa2b4c4f0,
+  0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
+    0x5790c30a, 0xa2a3919e,
+  0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
+    0x577e6c84, 0xa29261e5,
+  0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
+    0x576c129d, 0xa28135c7,
+  0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
+    0x5759b558, 0xa2700d43,
+  0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
+    0x574754b5, 0xa25ee85b,
+  0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
+    0x5734f0b5, 0xa24dc70f,
+  0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
+    0x57228957, 0xa23ca95f,
+  0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
+    0x57101e9e, 0xa22b8f4d,
+  0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
+    0x56fdb08a, 0xa21a78d9,
+  0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
+    0x56eb3f1a, 0xa2096604,
+  0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
+    0x56d8ca51, 0xa1f856ce,
+  0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
+    0x56c6522f, 0xa1e74b38,
+  0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
+    0x56b3d6b5, 0xa1d64343,
+  0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
+    0x56a157e3, 0xa1c53ef0,
+  0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
+    0x568ed5b9, 0xa1b43e3e,
+  0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
+    0x567c503a, 0xa1a3412f,
+  0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
+    0x5669c765, 0xa19247c3,
+  0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
+    0x56573b3b, 0xa18151fb,
+  0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
+    0x5644abbc, 0xa1705fd8,
+  0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
+    0x563218eb, 0xa15f715a,
+  0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
+    0x561f82c7, 0xa14e8682,
+  0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
+    0x560ce950, 0xa13d9f51,
+  0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
+    0x55fa4c89, 0xa12cbbc7,
+  0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
+    0x55e7ac71, 0xa11bdbe4,
+  0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
+    0x55d50909, 0xa10affab,
+  0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
+    0x55c26251, 0xa0fa271a,
+  0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
+    0x55afb84c, 0xa0e95234,
+  0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
+    0x559d0af9, 0xa0d880f7,
+  0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
+    0x558a5a58, 0xa0c7b366,
+  0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
+    0x5577a66c, 0xa0b6e981,
+  0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
+    0x5564ef34, 0xa0a62348,
+  0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
+    0x555234b1, 0xa09560bc,
+  0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
+    0x553f76e4, 0xa084a1de,
+  0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
+    0x552cb5ce, 0xa073e6af,
+  0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
+    0x5519f16f, 0xa0632f2e,
+  0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
+    0x550729c9, 0xa0527b5d,
+  0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
+    0x54f45edb, 0xa041cb3c,
+  0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
+    0x54e190a6, 0xa0311ecd,
+  0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
+    0x54cebf2c, 0xa020760e,
+  0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
+    0x54bbea6d, 0xa00fd102,
+  0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
+    0x54a91269, 0x9fff2fa9,
+  0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
+    0x54963722, 0x9fee9204,
+  0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
+    0x54835898, 0x9fddf812,
+  0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
+    0x547076cc, 0x9fcd61d6,
+  0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
+    0x545d91bf, 0x9fbccf4f,
+  0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
+    0x544aa971, 0x9fac407e,
+  0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
+    0x5437bde3, 0x9f9bb563,
+  0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
+    0x5424cf16, 0x9f8b2e00,
+  0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
+    0x5411dd0a, 0x9f7aaa55,
+  0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
+    0x53fee7c1, 0x9f6a2a63,
+  0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
+    0x53ebef3a, 0x9f59ae29,
+  0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
+    0x53d8f378, 0x9f4935aa,
+  0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
+    0x53c5f479, 0x9f38c0e5,
+  0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
+    0x53b2f240, 0x9f284fdc,
+  0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
+    0x539feccd, 0x9f17e28e,
+  0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
+    0x538ce421, 0x9f0778fd,
+  0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
+    0x5379d83c, 0x9ef71328,
+  0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
+    0x5366c91f, 0x9ee6b112,
+  0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
+    0x5353b6cb, 0x9ed652ba,
+  0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
+    0x5340a140, 0x9ec5f820,
+  0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
+    0x532d8880, 0x9eb5a146,
+  0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
+    0x531a6c8b, 0x9ea54e2d,
+  0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
+    0x53074d62, 0x9e94fed4,
+  0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
+    0x52f42b05, 0x9e84b33d,
+  0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
+    0x52e10576, 0x9e746b68,
+  0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
+    0x52cddcb5, 0x9e642756,
+  0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
+    0x52bab0c2, 0x9e53e707,
+  0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
+    0x52a7819f, 0x9e43aa7c,
+  0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
+    0x52944f4c, 0x9e3371b5,
+  0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
+    0x528119ca, 0x9e233cb4,
+  0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
+    0x526de11a, 0x9e130b79,
+  0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
+    0x525aa53c, 0x9e02de04,
+  0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
+    0x52476631, 0x9df2b456,
+  0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
+    0x523423fb, 0x9de28e70,
+  0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
+    0x5220de99, 0x9dd26c53,
+  0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
+    0x520d960c, 0x9dc24dfe,
+  0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
+    0x51fa4a56, 0x9db23373,
+  0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
+    0x51e6fb76, 0x9da21cb2,
+  0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
+    0x51d3a96f, 0x9d9209bd,
+  0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
+    0x51c0543f, 0x9d81fa92,
+  0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
+    0x51acfbe9, 0x9d71ef34,
+  0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
+    0x5199a06d, 0x9d61e7a2,
+  0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
+    0x518641cb, 0x9d51e3dd,
+  0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
+    0x5172e005, 0x9d41e3e7,
+  0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
+    0x515f7b1a, 0x9d31e7bf,
+  0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
+    0x514c130d, 0x9d21ef66,
+  0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
+    0x5138a7dd, 0x9d11fadd,
+  0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
+    0x5125398c, 0x9d020a25,
+  0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
+    0x5111c81a, 0x9cf21d3d,
+  0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
+    0x50fe5388, 0x9ce23427,
+  0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
+    0x50eadbd6, 0x9cd24ee4,
+  0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
+    0x50d76106, 0x9cc26d73,
+  0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
+    0x50c3e317, 0x9cb28fd5,
+  0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
+    0x50b0620c, 0x9ca2b60c,
+  0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
+    0x509cdde4, 0x9c92e017,
+  0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
+    0x508956a1, 0x9c830df8,
+  0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
+    0x5075cc43, 0x9c733faf,
+  0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
+    0x50623ecb, 0x9c63753c,
+  0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
+    0x504eae39, 0x9c53aea0,
+  0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
+    0x503b1a8f, 0x9c43ebdc,
+  0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
+    0x502783cd, 0x9c342cf0,
+  0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
+    0x5013e9f4, 0x9c2471de,
+  0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
+    0x50004d04, 0x9c14baa4,
+  0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
+    0x4fecacff, 0x9c050745,
+  0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
+    0x4fd909e5, 0x9bf557c1,
+  0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
+    0x4fc563b7, 0x9be5ac18,
+  0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
+    0x4fb1ba76, 0x9bd6044b,
+  0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
+    0x4f9e0e22, 0x9bc6605b,
+  0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
+    0x4f8a5ebd, 0x9bb6c048,
+  0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
+    0x4f76ac46, 0x9ba72413,
+  0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
+    0x4f62f6bf, 0x9b978bbc,
+  0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
+    0x4f4f3e29, 0x9b87f744,
+  0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
+    0x4f3b8284, 0x9b7866ab,
+  0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
+    0x4f27c3d1, 0x9b68d9f3,
+  0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
+    0x4f140210, 0x9b59511c,
+  0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
+    0x4f003d43, 0x9b49cc26,
+  0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
+    0x4eec756b, 0x9b3a4b11,
+  0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
+    0x4ed8aa87, 0x9b2acde0,
+  0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
+    0x4ec4dc99, 0x9b1b5492,
+  0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
+    0x4eb10ba2, 0x9b0bdf27,
+  0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
+    0x4e9d37a3, 0x9afc6da1,
+  0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
+    0x4e89609b, 0x9aed0000,
+  0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
+    0x4e75868c, 0x9add9644,
+  0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
+    0x4e61a977, 0x9ace306f,
+  0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
+    0x4e4dc95c, 0x9abece80,
+  0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
+    0x4e39e63d, 0x9aaf7079,
+  0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
+    0x4e260019, 0x9aa01659,
+  0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
+    0x4e1216f2, 0x9a90c022,
+  0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
+    0x4dfe2ac9, 0x9a816dd5,
+  0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
+    0x4dea3b9d, 0x9a721f71,
+  0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
+    0x4dd64971, 0x9a62d4f7,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
+    0x4dc25445, 0x9a538e68,
+  0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
+    0x4dae5c19, 0x9a444bc5,
+  0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
+    0x4d9a60ee, 0x9a350d0d,
+  0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
+    0x4d8662c6, 0x9a25d243,
+  0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
+    0x4d7261a0, 0x9a169b65,
+  0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
+    0x4d5e5d7e, 0x9a076875,
+  0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
+    0x4d4a5661, 0x99f83974,
+  0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
+    0x4d364c48, 0x99e90e62,
+  0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
+    0x4d223f36, 0x99d9e73f,
+  0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
+    0x4d0e2f2a, 0x99cac40d,
+  0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
+    0x4cfa1c26, 0x99bba4cb,
+  0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
+    0x4ce6062a, 0x99ac897b,
+  0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
+    0x4cd1ed37, 0x999d721c,
+  0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
+    0x4cbdd14e, 0x998e5eb1,
+  0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
+    0x4ca9b26f, 0x997f4f38,
+  0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
+    0x4c95909c, 0x997043b2,
+  0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
+    0x4c816bd5, 0x99613c22,
+  0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
+    0x4c6d441b, 0x99523885,
+  0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
+    0x4c59196f, 0x994338df,
+  0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
+    0x4c44ebd1, 0x99343d2e,
+  0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
+    0x4c30bb42, 0x99254574,
+  0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
+    0x4c1c87c3, 0x991651b1,
+  0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
+    0x4c085156, 0x990761e5,
+  0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
+    0x4bf417f9, 0x98f87612,
+  0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
+    0x4bdfdbaf, 0x98e98e38,
+  0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
+    0x4bcb9c79, 0x98daaa57,
+  0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
+    0x4bb75a56, 0x98cbca70,
+  0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
+    0x4ba31548, 0x98bcee84,
+  0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
+    0x4b8ecd4f, 0x98ae1693,
+  0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
+    0x4b7a826d, 0x989f429e,
+  0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
+    0x4b6634a2, 0x989072a5,
+  0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
+    0x4b51e3ee, 0x9881a6a9,
+  0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
+    0x4b3d9053, 0x9872deaa,
+  0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
+    0x4b2939d2, 0x98641aa9,
+  0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
+    0x4b14e06b, 0x98555aa7,
+  0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
+    0x4b00841f, 0x98469ea4,
+  0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
+    0x4aec24ee, 0x9837e6a1,
+  0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
+    0x4ad7c2da, 0x9829329e,
+  0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
+    0x4ac35de4, 0x981a829c,
+  0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
+    0x4aaef60b, 0x980bd69b,
+  0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
+    0x4a9a8b52, 0x97fd2e9c,
+  0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
+    0x4a861db8, 0x97ee8aa0,
+  0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
+    0x4a71ad3e, 0x97dfeaa7,
+  0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
+    0x4a5d39e6, 0x97d14eb2,
+  0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
+    0x4a48c3b0, 0x97c2b6c1,
+  0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
+    0x4a344a9d, 0x97b422d4,
+  0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
+    0x4a1fcead, 0x97a592ed,
+  0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
+    0x4a0b4fe2, 0x9797070c,
+  0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
+    0x49f6ce3c, 0x97887f32,
+  0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
+    0x49e249bc, 0x9779fb5e,
+  0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
+    0x49cdc263, 0x976b7b92,
+  0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
+    0x49b93832, 0x975cffcf,
+  0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
+    0x49a4ab28, 0x974e8813,
+  0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
+    0x49901b48, 0x97401462,
+  0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
+    0x497b8892, 0x9731a4ba,
+  0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
+    0x4966f307, 0x9723391c,
+  0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
+    0x49525aa7, 0x9714d18a,
+  0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
+    0x493dbf74, 0x97066e03,
+  0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
+    0x4929216e, 0x96f80e88,
+  0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
+    0x49148095, 0x96e9b319,
+  0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
+    0x48ffdcec, 0x96db5bb8,
+  0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
+    0x48eb3672, 0x96cd0865,
+  0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
+    0x48d68d28, 0x96beb91f,
+  0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
+    0x48c1e10f, 0x96b06de9,
+  0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
+    0x48ad3228, 0x96a226c2,
+  0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
+    0x48988074, 0x9693e3ab,
+  0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
+    0x4883cbf4, 0x9685a4a4,
+  0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
+    0x486f14a8, 0x967769af,
+  0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
+    0x485a5a90, 0x966932cb,
+  0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
+    0x48459daf, 0x965afff9,
+  0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
+    0x4830de05, 0x964cd139,
+  0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
+    0x481c1b92, 0x963ea68d,
+  0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
+    0x48075657, 0x96307ff5,
+  0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
+    0x47f28e56, 0x96225d71,
+  0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
+    0x47ddc38e, 0x96143f02,
+  0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
+    0x47c8f601, 0x960624a9,
+  0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
+    0x47b425af, 0x95f80e65,
+  0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
+    0x479f529a, 0x95e9fc38,
+  0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
+    0x478a7cc2, 0x95dbee21,
+  0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
+    0x4775a428, 0x95cde423,
+  0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
+    0x4760c8cd, 0x95bfde3c,
+  0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
+    0x474beab1, 0x95b1dc6e,
+  0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
+    0x473709d5, 0x95a3deb9,
+  0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
+    0x4722263b, 0x9595e51e,
+  0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
+    0x470d3fe3, 0x9587ef9e,
+  0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
+    0x46f856cd, 0x9579fe38,
+  0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
+    0x46e36afb, 0x956c10ed,
+  0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
+    0x46ce7c6d, 0x955e27bf,
+  0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
+    0x46b98b24, 0x955042ac,
+  0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
+    0x46a49722, 0x954261b7,
+  0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
+    0x468fa066, 0x953484df,
+  0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
+    0x467aa6f2, 0x9526ac25,
+  0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
+    0x4665aac6, 0x9518d78a,
+  0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
+    0x4650abe3, 0x950b070e,
+  0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
+    0x463baa4a, 0x94fd3ab1,
+  0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
+    0x4626a5fd, 0x94ef7275,
+  0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
+    0x46119efa, 0x94e1ae59,
+  0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
+    0x45fc9545, 0x94d3ee5f,
+  0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
+    0x45e788dc, 0x94c63286,
+  0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
+    0x45d279c2, 0x94b87ad0,
+  0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
+    0x45bd67f6, 0x94aac73c,
+  0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
+    0x45a8537a, 0x949d17cc,
+  0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
+    0x45933c4f, 0x948f6c7f,
+  0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
+    0x457e2275, 0x9481c557,
+  0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
+    0x456905ed, 0x94742254,
+  0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
+    0x4553e6b8, 0x94668376,
+  0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
+    0x453ec4d7, 0x9458e8bf,
+  0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
+    0x4529a04b, 0x944b522d,
+  0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
+    0x45147913, 0x943dbfc3,
+  0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
+    0x44ff4f32, 0x94303180,
+  0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
+    0x44ea22a9, 0x9422a766,
+  0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
+    0x44d4f376, 0x94152174,
+  0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
+    0x44bfc19d, 0x94079fab,
+  0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
+    0x44aa8d1d, 0x93fa220b,
+  0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
+    0x449555f7, 0x93eca896,
+  0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
+    0x44801c2d, 0x93df334c,
+  0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
+    0x446adfbe, 0x93d1c22c,
+  0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
+    0x4455a0ac, 0x93c45539,
+  0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
+    0x44405ef8, 0x93b6ec71,
+  0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
+    0x442b1aa2, 0x93a987d6,
+  0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
+    0x4415d3ab, 0x939c2769,
+  0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
+    0x44008a14, 0x938ecb29,
+  0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
+    0x43eb3ddf, 0x93817318,
+  0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
+    0x43d5ef0a, 0x93741f35,
+  0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
+    0x43c09d99, 0x9366cf82,
+  0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
+    0x43ab498a, 0x935983ff,
+  0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
+    0x4395f2e0, 0x934c3cab,
+  0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
+    0x4380999b, 0x933ef989,
+  0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
+    0x436b3dbb, 0x9331ba98,
+  0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
+    0x4355df42, 0x93247fd9,
+  0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
+    0x43407e31, 0x9317494c,
+  0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
+    0x432b1a87, 0x930a16f3,
+  0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
+    0x4315b447, 0x92fce8cc,
+  0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
+    0x43004b71, 0x92efbeda,
+  0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
+    0x42eae005, 0x92e2991c,
+  0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
+    0x42d57205, 0x92d57792,
+  0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
+    0x42c00172, 0x92c85a3f,
+  0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
+    0x42aa8e4b, 0x92bb4121,
+  0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
+    0x42951893, 0x92ae2c3a,
+  0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
+    0x427fa049, 0x92a11b89,
+  0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
+    0x426a256f, 0x92940f10,
+  0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
+    0x4254a806, 0x928706cf,
+  0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
+    0x423f280e, 0x927a02c7,
+  0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
+    0x4229a588, 0x926d02f7,
+  0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
+    0x42142075, 0x92600761,
+  0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
+    0x41fe98d6, 0x92531005,
+  0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
+    0x41e90eac, 0x92461ce3,
+  0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
+    0x41d381f7, 0x92392dfc,
+  0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
+    0x41bdf2b9, 0x922c4351,
+  0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
+    0x41a860f1, 0x921f5ce1,
+  0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
+    0x4192cca2, 0x92127aae,
+  0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
+    0x417d35cb, 0x92059cb8,
+  0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
+    0x41679c6f, 0x91f8c300,
+  0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
+    0x4152008c, 0x91ebed85,
+  0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
+    0x413c6225, 0x91df1c49,
+  0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
+    0x4126c13a, 0x91d24f4c,
+  0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
+    0x41111dcc, 0x91c5868e,
+  0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
+    0x40fb77dc, 0x91b8c210,
+  0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
+    0x40e5cf6a, 0x91ac01d2,
+  0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
+    0x40d02478, 0x919f45d6,
+  0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
+    0x40ba7706, 0x91928e1a,
+  0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
+    0x40a4c716, 0x9185daa1,
+  0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
+    0x408f14a7, 0x91792b6a,
+  0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
+    0x40795fbc, 0x916c8076,
+  0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
+    0x4063a854, 0x915fd9c5,
+  0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
+    0x404dee70, 0x91533758,
+  0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
+    0x40383212, 0x9146992f,
+  0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
+    0x4022733a, 0x9139ff4b,
+  0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
+    0x400cb1e9, 0x912d69ad,
+  0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
+    0x3ff6ee1f, 0x9120d854,
+  0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
+    0x3fe127df, 0x91144b41,
+  0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
+    0x3fcb5f28, 0x9107c276,
+  0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
+    0x3fb593fb, 0x90fb3df1,
+  0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
+    0x3f9fc65a, 0x90eebdb4,
+  0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
+    0x3f89f645, 0x90e241bf,
+  0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
+    0x3f7423bc, 0x90d5ca13,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
+    0x3f5e4ec2, 0x90c956b1,
+  0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
+    0x3f487755, 0x90bce797,
+  0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
+    0x3f329d79, 0x90b07cc8,
+  0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
+    0x3f1cc12c, 0x90a41644,
+  0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
+    0x3f06e271, 0x9097b40a,
+  0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
+    0x3ef10148, 0x908b561c,
+  0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
+    0x3edb1db1, 0x907efc7a,
+  0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
+    0x3ec537ae, 0x9072a725,
+  0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
+    0x3eaf4f40, 0x9066561d,
+  0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
+    0x3e996467, 0x905a0962,
+  0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
+    0x3e837724, 0x904dc0f5,
+  0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
+    0x3e6d8778, 0x90417cd6,
+  0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
+    0x3e579564, 0x90353d06,
+  0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
+    0x3e41a0e8, 0x90290186,
+  0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
+    0x3e2baa07, 0x901cca55,
+  0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
+    0x3e15b0bf, 0x90109775,
+  0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
+    0x3dffb513, 0x900468e5,
+  0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
+    0x3de9b703, 0x8ff83ea7,
+  0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
+    0x3dd3b690, 0x8fec18ba,
+  0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
+    0x3dbdb3ba, 0x8fdff720,
+  0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
+    0x3da7ae84, 0x8fd3d9d8,
+  0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
+    0x3d91a6ed, 0x8fc7c0e3,
+  0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
+    0x3d7b9cf6, 0x8fbbac42,
+  0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
+    0x3d6590a0, 0x8faf9bf5,
+  0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
+    0x3d4f81ec, 0x8fa38ffc,
+  0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
+    0x3d3970dc, 0x8f978859,
+  0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
+    0x3d235d6f, 0x8f8b850a,
+  0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
+    0x3d0d47a6, 0x8f7f8612,
+  0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
+    0x3cf72f83, 0x8f738b70,
+  0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
+    0x3ce11507, 0x8f679525,
+  0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
+    0x3ccaf831, 0x8f5ba331,
+  0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
+    0x3cb4d904, 0x8f4fb595,
+  0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
+    0x3c9eb77f, 0x8f43cc50,
+  0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
+    0x3c8893a4, 0x8f37e765,
+  0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
+    0x3c726d73, 0x8f2c06d3,
+  0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
+    0x3c5c44ee, 0x8f202a9a,
+  0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
+    0x3c461a16, 0x8f1452bb,
+  0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
+    0x3c2fecea, 0x8f087f37,
+  0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
+    0x3c19bd6c, 0x8efcb00e,
+  0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
+    0x3c038b9e, 0x8ef0e540,
+  0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
+    0x3bed577e, 0x8ee51ece,
+  0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
+    0x3bd72110, 0x8ed95cb8,
+  0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
+    0x3bc0e853, 0x8ecd9eff,
+  0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
+    0x3baaad48, 0x8ec1e5a4,
+  0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
+    0x3b946ff0, 0x8eb630a6,
+  0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
+    0x3b7e304c, 0x8eaa8006,
+  0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
+    0x3b67ee5d, 0x8e9ed3c4,
+  0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
+    0x3b51aa24, 0x8e932be2,
+  0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
+    0x3b3b63a1, 0x8e87885f,
+  0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
+    0x3b251ad6, 0x8e7be93c,
+  0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
+    0x3b0ecfc3, 0x8e704e79,
+  0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
+    0x3af88269, 0x8e64b817,
+  0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
+    0x3ae232c9, 0x8e592617,
+  0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
+    0x3acbe0e3, 0x8e4d9878,
+  0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
+    0x3ab58cba, 0x8e420f3b,
+  0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
+    0x3a9f364d, 0x8e368a61,
+  0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
+    0x3a88dd9d, 0x8e2b09e9,
+  0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
+    0x3a7282ac, 0x8e1f8dd6,
+  0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
+    0x3a5c257a, 0x8e141626,
+  0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
+    0x3a45c608, 0x8e08a2db,
+  0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
+    0x3a2f6457, 0x8dfd33f4,
+  0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
+    0x3a190068, 0x8df1c973,
+  0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
+    0x3a029a3b, 0x8de66357,
+  0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
+    0x39ec31d1, 0x8ddb01a1,
+  0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
+    0x39d5c72c, 0x8dcfa452,
+  0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
+    0x39bf5a4d, 0x8dc44b6a,
+  0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
+    0x39a8eb33, 0x8db8f6ea,
+  0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
+    0x399279e0, 0x8dada6d1,
+  0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
+    0x397c0655, 0x8da25b21,
+  0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
+    0x39659092, 0x8d9713d9,
+  0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
+    0x394f1899, 0x8d8bd0fb,
+  0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
+    0x39389e6b, 0x8d809286,
+  0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
+    0x39222208, 0x8d75587b,
+  0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
+    0x390ba371, 0x8d6a22db,
+  0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
+    0x38f522a6, 0x8d5ef1a5,
+  0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
+    0x38de9faa, 0x8d53c4db,
+  0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
+    0x38c81a7c, 0x8d489c7d,
+  0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
+    0x38b1931e, 0x8d3d788b,
+  0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
+    0x389b0991, 0x8d325905,
+  0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
+    0x38847dd5, 0x8d273ded,
+  0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
+    0x386defeb, 0x8d1c2742,
+  0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
+    0x38575fd4, 0x8d111505,
+  0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
+    0x3840cd90, 0x8d060737,
+  0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
+    0x382a3922, 0x8cfafdd7,
+  0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
+    0x3813a28a, 0x8ceff8e6,
+  0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
+    0x37fd09c8, 0x8ce4f865,
+  0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
+    0x37e66edd, 0x8cd9fc54,
+  0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
+    0x37cfd1cb, 0x8ccf04b3,
+  0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
+    0x37b93292, 0x8cc41184,
+  0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
+    0x37a29132, 0x8cb922c6,
+  0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
+    0x378bedae, 0x8cae3879,
+  0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
+    0x37754806, 0x8ca3529f,
+  0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
+    0x375ea03a, 0x8c987137,
+  0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
+    0x3747f64c, 0x8c8d9442,
+  0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
+    0x37314a3c, 0x8c82bbc0,
+  0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
+    0x371a9c0b, 0x8c77e7b3,
+  0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
+    0x3703ebbb, 0x8c6d181a,
+  0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
+    0x36ed394b, 0x8c624cf5,
+  0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
+    0x36d684be, 0x8c578645,
+  0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
+    0x36bfce13, 0x8c4cc40b,
+  0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
+    0x36a9154c, 0x8c420647,
+  0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
+    0x36925a69, 0x8c374cf9,
+  0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
+    0x367b9d6c, 0x8c2c9822,
+  0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
+    0x3664de55, 0x8c21e7c2,
+  0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
+    0x364e1d25, 0x8c173bda,
+  0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
+    0x363759de, 0x8c0c9469,
+  0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
+    0x3620947f, 0x8c01f171,
+  0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
+    0x3609cd0a, 0x8bf752f2,
+  0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
+    0x35f3037f, 0x8becb8ec,
+  0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
+    0x35dc37e0, 0x8be22360,
+  0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
+    0x35c56a2e, 0x8bd7924d,
+  0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
+    0x35ae9a69, 0x8bcd05b5,
+  0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
+    0x3597c892, 0x8bc27d98,
+  0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
+    0x3580f4aa, 0x8bb7f9f6,
+  0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
+    0x356a1eb2, 0x8bad7ad0,
+  0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
+    0x355346ab, 0x8ba30026,
+  0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
+    0x353c6c95, 0x8b9889f8,
+  0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
+    0x35259073, 0x8b8e1848,
+  0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
+    0x350eb243, 0x8b83ab14,
+  0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
+    0x34f7d208, 0x8b79425e,
+  0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
+    0x34e0efc2, 0x8b6ede26,
+  0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
+    0x34ca0b73, 0x8b647e6d,
+  0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
+    0x34b3251a, 0x8b5a2333,
+  0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
+    0x349c3cb9, 0x8b4fcc77,
+  0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
+    0x34855251, 0x8b457a3c,
+  0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
+    0x346e65e3, 0x8b3b2c80,
+  0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
+    0x3457776f, 0x8b30e345,
+  0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
+    0x344086f6, 0x8b269e8b,
+  0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
+    0x3429947a, 0x8b1c5e52,
+  0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
+    0x34129ffb, 0x8b12229b,
+  0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
+    0x33fba97a, 0x8b07eb66,
+  0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
+    0x33e4b0f8, 0x8afdb8b3,
+  0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
+    0x33cdb676, 0x8af38a83,
+  0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
+    0x33b6b9f4, 0x8ae960d6,
+  0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
+    0x339fbb74, 0x8adf3bad,
+  0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
+    0x3388baf7, 0x8ad51b08,
+  0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
+    0x3371b87d, 0x8acafee8,
+  0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
+    0x335ab407, 0x8ac0e74c,
+  0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
+    0x3343ad97, 0x8ab6d435,
+  0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
+    0x332ca52c, 0x8aacc5a4,
+  0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
+    0x33159ac8, 0x8aa2bb99,
+  0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
+    0x32fe8e6d, 0x8a98b614,
+  0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
+    0x32e7801a, 0x8a8eb516,
+  0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
+    0x32d06fd0, 0x8a84b89e,
+  0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
+    0x32b95d91, 0x8a7ac0af,
+  0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
+    0x32a2495d, 0x8a70cd47,
+  0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
+    0x328b3336, 0x8a66de68,
+  0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
+    0x32741b1c, 0x8a5cf411,
+  0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
+    0x325d0110, 0x8a530e43,
+  0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
+    0x3245e512, 0x8a492cff,
+  0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
+    0x322ec725, 0x8a3f5045,
+  0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
+    0x3217a748, 0x8a357814,
+  0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
+    0x3200857d, 0x8a2ba46e,
+  0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
+    0x31e961c5, 0x8a21d554,
+  0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
+    0x31d23c1f, 0x8a180ac4,
+  0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
+    0x31bb148f, 0x8a0e44c0,
+  0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
+    0x31a3eb13, 0x8a048348,
+  0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
+    0x318cbfad, 0x89fac65d,
+  0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
+    0x3175925e, 0x89f10dff,
+  0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
+    0x315e6328, 0x89e75a2d,
+  0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
+    0x31473209, 0x89ddaae9,
+  0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
+    0x312fff05, 0x89d40033,
+  0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
+    0x3118ca1b, 0x89ca5a0c,
+  0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
+    0x3101934d, 0x89c0b873,
+  0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
+    0x30ea5a9a, 0x89b71b69,
+  0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
+    0x30d32006, 0x89ad82ef,
+  0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
+    0x30bbe38f, 0x89a3ef04,
+  0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
+    0x30a4a537, 0x899a5faa,
+  0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
+    0x308d64ff, 0x8990d4e0,
+  0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
+    0x307622e8, 0x89874ea7,
+  0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
+    0x305edef3, 0x897dccff,
+  0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
+    0x30479920, 0x89744fe9,
+  0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
+    0x30305171, 0x896ad765,
+  0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
+    0x301907e6, 0x89616373,
+  0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
+    0x3001bc80, 0x8957f414,
+  0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
+    0x2fea6f41, 0x894e8948,
+  0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
+    0x2fd32028, 0x89452310,
+  0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
+    0x2fbbcf38, 0x893bc16b,
+  0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
+    0x2fa47c71, 0x8932645b,
+  0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
+    0x2f8d27d3, 0x89290bdf,
+  0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
+    0x2f75d160, 0x891fb7f8,
+  0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
+    0x2f5e7919, 0x891668a6,
+  0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
+    0x2f471efe, 0x890d1dea,
+  0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
+    0x2f2fc310, 0x8903d7c4,
+  0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
+    0x2f186551, 0x88fa9634,
+  0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
+    0x2f0105c1, 0x88f1593b,
+  0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
+    0x2ee9a461, 0x88e820d9,
+  0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
+    0x2ed24132, 0x88deed0e,
+  0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
+    0x2ebadc35, 0x88d5bddb,
+  0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
+    0x2ea3756b, 0x88cc9340,
+  0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
+    0x2e8c0cd4, 0x88c36d3e,
+  0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
+    0x2e74a272, 0x88ba4bd4,
+  0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
+    0x2e5d3646, 0x88b12f04,
+  0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
+    0x2e45c850, 0x88a816cd,
+  0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
+    0x2e2e5891, 0x889f0330,
+  0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
+    0x2e16e70b, 0x8895f42d,
+  0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
+    0x2dff73bd, 0x888ce9c5,
+  0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
+    0x2de7feaa, 0x8883e3f8,
+  0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
+    0x2dd087d1, 0x887ae2c6,
+  0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
+    0x2db90f35, 0x8871e630,
+  0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
+    0x2da194d5, 0x8868ee35,
+  0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
+    0x2d8a18b3, 0x885ffad7,
+  0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
+    0x2d729acf, 0x88570c16,
+  0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
+    0x2d5b1b2b, 0x884e21f1,
+  0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
+    0x2d4399c7, 0x88453c6a,
+  0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
+    0x2d2c16a4, 0x883c5b81,
+  0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
+    0x2d1491c4, 0x88337f35,
+  0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
+    0x2cfd0b26, 0x882aa788,
+  0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
+    0x2ce582cd, 0x8821d47a,
+  0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
+    0x2ccdf8b8, 0x8819060a,
+  0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
+    0x2cb66ce9, 0x88103c3b,
+  0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
+    0x2c9edf61, 0x8807770a,
+  0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
+    0x2c875021, 0x87feb67a,
+  0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
+    0x2c6fbf29, 0x87f5fa8b,
+  0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
+    0x2c582c7b, 0x87ed433c,
+  0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
+    0x2c409816, 0x87e4908e,
+  0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
+    0x2c2901fd, 0x87dbe281,
+  0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
+    0x2c116a31, 0x87d33916,
+  0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
+    0x2bf9d0b1, 0x87ca944e,
+  0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
+    0x2be2357f, 0x87c1f427,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
+    0x2bca989d, 0x87b958a4,
+  0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
+    0x2bb2fa0a, 0x87b0c1c4,
+  0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
+    0x2b9b59c7, 0x87a82f87,
+  0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
+    0x2b83b7d7, 0x879fa1ed,
+  0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
+    0x2b6c1438, 0x879718f8,
+  0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
+    0x2b546eee, 0x878e94a7,
+  0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
+    0x2b3cc7f7, 0x878614fb,
+  0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
+    0x2b251f56, 0x877d99f4,
+  0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
+    0x2b0d750b, 0x87752392,
+  0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
+    0x2af5c917, 0x876cb1d6,
+  0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
+    0x2ade1b7c, 0x876444c1,
+  0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
+    0x2ac66c39, 0x875bdc51,
+  0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
+    0x2aaebb50, 0x87537888,
+  0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
+    0x2a9708c1, 0x874b1966,
+  0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
+    0x2a7f548e, 0x8742beec,
+  0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
+    0x2a679eb8, 0x873a6919,
+  0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
+    0x2a4fe740, 0x873217ee,
+  0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
+    0x2a382e25, 0x8729cb6b,
+  0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
+    0x2a20736a, 0x87218391,
+  0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
+    0x2a08b710, 0x87194060,
+  0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
+    0x29f0f916, 0x871101d8,
+  0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
+    0x29d9397f, 0x8708c7fa,
+  0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
+    0x29c1784a, 0x870092c5,
+  0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
+    0x29a9b579, 0x86f8623b,
+  0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
+    0x2991f10e, 0x86f0365c,
+  0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
+    0x297a2b07, 0x86e80f27,
+  0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
+    0x29626368, 0x86dfec9d,
+  0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
+    0x294a9a30, 0x86d7cebf,
+  0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
+    0x2932cf60, 0x86cfb58c,
+  0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
+    0x291b02fa, 0x86c7a106,
+  0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
+    0x290334ff, 0x86bf912c,
+  0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
+    0x28eb656e, 0x86b785ff,
+  0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
+    0x28d3944a, 0x86af7f7e,
+  0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
+    0x28bbc192, 0x86a77dab,
+  0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
+    0x28a3ed49, 0x869f8086,
+  0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
+    0x288c176e, 0x8697880f,
+  0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
+    0x28744004, 0x868f9445,
+  0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
+    0x285c670a, 0x8687a52b,
+  0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
+    0x28448c81, 0x867fbabf,
+  0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
+    0x282cb06c, 0x8677d503,
+  0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
+    0x2814d2c9, 0x866ff3f6,
+  0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
+    0x27fcf39c, 0x86681798,
+  0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
+    0x27e512e3, 0x86603feb,
+  0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
+    0x27cd30a1, 0x86586cee,
+  0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
+    0x27b54cd6, 0x86509ea2,
+  0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
+    0x279d6783, 0x8648d507,
+  0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
+    0x278580a9, 0x8641101d,
+  0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
+    0x276d9849, 0x86394fe5,
+  0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
+    0x2755ae64, 0x8631945e,
+  0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
+    0x273dc2fa, 0x8629dd8a,
+  0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
+    0x2725d60e, 0x86222b68,
+  0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
+    0x270de79f, 0x861a7df9,
+  0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
+    0x26f5f7ae, 0x8612d53d,
+  0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
+    0x26de063d, 0x860b3135,
+  0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
+    0x26c6134d, 0x860391e0,
+  0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
+    0x26ae1edd, 0x85fbf73f,
+  0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
+    0x269628f0, 0x85f46152,
+  0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
+    0x267e3186, 0x85ecd01a,
+  0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
+    0x266638a1, 0x85e54397,
+  0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
+    0x264e3e40, 0x85ddbbc9,
+  0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
+    0x26364265, 0x85d638b0,
+  0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
+    0x261e4511, 0x85ceba4d,
+  0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
+    0x26064645, 0x85c740a0,
+  0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
+    0x25ee4601, 0x85bfcba9,
+  0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
+    0x25d64447, 0x85b85b68,
+  0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
+    0x25be4118, 0x85b0efdf,
+  0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
+    0x25a63c74, 0x85a9890d,
+  0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
+    0x258e365d, 0x85a226f2,
+  0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
+    0x25762ed3, 0x859ac98f,
+  0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
+    0x255e25d7, 0x859370e4,
+  0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
+    0x25461b6b, 0x858c1cf1,
+  0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
+    0x252e0f8e, 0x8584cdb7,
+  0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
+    0x25160243, 0x857d8335,
+  0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
+    0x24fdf389, 0x85763d6d,
+  0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
+    0x24e5e363, 0x856efc5e,
+  0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
+    0x24cdd1d0, 0x8567c009,
+  0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
+    0x24b5bed2, 0x8560886d,
+  0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
+    0x249daa6a, 0x8559558c,
+  0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
+    0x24859498, 0x85522766,
+  0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
+    0x246d7d5e, 0x854afdfa,
+  0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
+    0x245564bd, 0x8543d949,
+  0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
+    0x243d4ab4, 0x853cb954,
+  0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
+    0x24252f47, 0x85359e1a,
+  0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
+    0x240d1274, 0x852e879d,
+  0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
+    0x23f4f43e, 0x852775db,
+  0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
+    0x23dcd4a4, 0x852068d6,
+  0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
+    0x23c4b3a9, 0x8519608d,
+  0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
+    0x23ac914d, 0x85125d02,
+  0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
+    0x23946d90, 0x850b5e34,
+  0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
+    0x237c4875, 0x85046423,
+  0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
+    0x236421fb, 0x84fd6ed0,
+  0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
+    0x234bfa24, 0x84f67e3b,
+  0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
+    0x2333d0f1, 0x84ef9265,
+  0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
+    0x231ba662, 0x84e8ab4d,
+  0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
+    0x23037a78, 0x84e1c8f3,
+  0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
+    0x22eb4d36, 0x84daeb5a,
+  0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
+    0x22d31e9a, 0x84d4127f,
+  0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
+    0x22baeea7, 0x84cd3e64,
+  0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
+    0x22a2bd5d, 0x84c66f09,
+  0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
+    0x228a8abd, 0x84bfa46e,
+  0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
+    0x227256c8, 0x84b8de94,
+  0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
+    0x225a217f, 0x84b21d7a,
+  0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
+    0x2241eae3, 0x84ab6122,
+  0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
+    0x2229b2f6, 0x84a4a98a,
+  0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
+    0x221179b7, 0x849df6b4,
+  0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
+    0x21f93f27, 0x849748a0,
+  0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
+    0x21e10349, 0x84909f4e,
+  0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
+    0x21c8c61c, 0x8489fabe,
+  0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
+    0x21b087a1, 0x84835af0,
+  0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
+    0x219847da, 0x847cbfe5,
+  0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
+    0x218006c8, 0x8476299e,
+  0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
+    0x2167c46b, 0x846f9819,
+  0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
+    0x214f80c4, 0x84690b58,
+  0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
+    0x21373bd4, 0x8462835b,
+  0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
+    0x211ef59d, 0x845c0022,
+  0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
+    0x2106ae1e, 0x845581ad,
+  0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
+    0x20ee655a, 0x844f07fd,
+  0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
+    0x20d61b51, 0x84489311,
+  0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
+    0x20bdd003, 0x844222eb,
+  0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
+    0x20a58373, 0x843bb78a,
+  0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
+    0x208d35a0, 0x843550ee,
+  0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
+    0x2074e68c, 0x842eef18,
+  0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
+    0x205c9638, 0x84289209,
+  0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
+    0x204444a4, 0x842239bf,
+  0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
+    0x202bf1d2, 0x841be63c,
+  0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
+    0x20139dc2, 0x84159780,
+  0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
+    0x1ffb4876, 0x840f4d8a,
+  0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
+    0x1fe2f1ee, 0x8409085c,
+  0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
+    0x1fca9a2b, 0x8402c7f6,
+  0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
+    0x1fb2412f, 0x83fc8c57,
+  0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
+    0x1f99e6fa, 0x83f65580,
+  0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
+    0x1f818b8d, 0x83f02371,
+  0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
+    0x1f692ee9, 0x83e9f62b,
+  0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
+    0x1f50d10e, 0x83e3cdad,
+  0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
+    0x1f3871ff, 0x83dda9f9,
+  0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
+    0x1f2011bc, 0x83d78b0d,
+  0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
+    0x1f07b045, 0x83d170eb,
+  0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
+    0x1eef4d9d, 0x83cb5b93,
+  0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
+    0x1ed6e9c3, 0x83c54b04,
+  0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
+    0x1ebe84b8, 0x83bf3f3f,
+  0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
+    0x1ea61e7e, 0x83b93845,
+  0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
+    0x1e8db716, 0x83b33616,
+  0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
+    0x1e754e80, 0x83ad38b1,
+  0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
+    0x1e5ce4be, 0x83a74017,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
+    0x1e4479cf, 0x83a14c48,
+  0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
+    0x1e2c0db6, 0x839b5d45,
+  0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
+    0x1e13a074, 0x8395730e,
+  0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
+    0x1dfb3208, 0x838f8da2,
+  0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
+    0x1de2c275, 0x8389ad03,
+  0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
+    0x1dca51ba, 0x8383d130,
+  0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
+    0x1db1dfda, 0x837dfa2a,
+  0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
+    0x1d996cd4, 0x837827f0,
+  0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
+    0x1d80f8ab, 0x83725a84,
+  0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
+    0x1d68835e, 0x836c91e5,
+  0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
+    0x1d500cef, 0x8366ce14,
+  0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
+    0x1d37955e, 0x83610f10,
+  0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
+    0x1d1f1cae, 0x835b54da,
+  0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
+    0x1d06a2dd, 0x83559f72,
+  0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
+    0x1cee27ef, 0x834feed9,
+  0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
+    0x1cd5abe3, 0x834a430e,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
+    0x1cbd2eba, 0x83449c12,
+  0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
+    0x1ca4b075, 0x833ef9e6,
+  0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
+    0x1c8c3116, 0x83395c88,
+  0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
+    0x1c73b09d, 0x8333c3fa,
+  0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
+    0x1c5b2f0c, 0x832e303c,
+  0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
+    0x1c42ac62, 0x8328a14d,
+  0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
+    0x1c2a28a2, 0x8323172f,
+  0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
+    0x1c11a3cb, 0x831d91e1,
+  0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
+    0x1bf91de0, 0x83181164,
+  0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
+    0x1be096e0, 0x831295b7,
+  0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
+    0x1bc80ece, 0x830d1edc,
+  0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
+    0x1baf85a9, 0x8307acd1,
+  0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
+    0x1b96fb73, 0x83023f98,
+  0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
+    0x1b7e702c, 0x82fcd731,
+  0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
+    0x1b65e3d7, 0x82f7739c,
+  0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
+    0x1b4d5672, 0x82f214d8,
+  0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
+    0x1b34c801, 0x82ecbae7,
+  0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
+    0x1b1c3883, 0x82e765c8,
+  0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
+    0x1b03a7f9, 0x82e2157c,
+  0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
+    0x1aeb1665, 0x82dcca02,
+  0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
+    0x1ad283c7, 0x82d7835c,
+  0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
+    0x1ab9f020, 0x82d24189,
+  0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
+    0x1aa15b71, 0x82cd048a,
+  0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
+    0x1a88c5bc, 0x82c7cc5e,
+  0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
+    0x1a702f01, 0x82c29906,
+  0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
+    0x1a579741, 0x82bd6a82,
+  0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
+    0x1a3efe7c, 0x82b840d2,
+  0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
+    0x1a2664b5, 0x82b31bf7,
+  0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
+    0x1a0dc9ec, 0x82adfbf0,
+  0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
+    0x19f52e22, 0x82a8e0bf,
+  0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
+    0x19dc9157, 0x82a3ca62,
+  0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
+    0x19c3f38d, 0x829eb8db,
+  0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
+    0x19ab54c5, 0x8299ac29,
+  0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
+    0x1992b4ff, 0x8294a44c,
+  0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
+    0x197a143e, 0x828fa146,
+  0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
+    0x19617280, 0x828aa316,
+  0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
+    0x1948cfc8, 0x8285a9bb,
+  0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
+    0x19302c17, 0x8280b538,
+  0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
+    0x1917876d, 0x827bc58a,
+  0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
+    0x18fee1cb, 0x8276dab4,
+  0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
+    0x18e63b33, 0x8271f4b5,
+  0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
+    0x18cd93a5, 0x826d138d,
+  0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
+    0x18b4eb22, 0x8268373c,
+  0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
+    0x189c41ab, 0x82635fc2,
+  0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
+    0x18839742, 0x825e8d21,
+  0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
+    0x186aebe6, 0x8259bf57,
+  0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
+    0x18523f9a, 0x8254f666,
+  0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
+    0x1839925d, 0x8250324d,
+  0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
+    0x1820e431, 0x824b730c,
+  0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
+    0x18083518, 0x8246b8a4,
+  0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
+    0x17ef8511, 0x82420315,
+  0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
+    0x17d6d41d, 0x823d525e,
+  0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
+    0x17be223f, 0x8238a681,
+  0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
+    0x17a56f76, 0x8233ff7e,
+  0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
+    0x178cbbc4, 0x822f5d54,
+  0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
+    0x17740729, 0x822ac004,
+  0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
+    0x175b51a7, 0x8226278d,
+  0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
+    0x17429b3e, 0x822193f1,
+  0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
+    0x1729e3f0, 0x821d052f,
+  0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
+    0x17112bbd, 0x82187b47,
+  0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
+    0x16f872a7, 0x8213f63a,
+  0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
+    0x16dfb8ae, 0x820f7608,
+  0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
+    0x16c6fdd3, 0x820afab1,
+  0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
+    0x16ae4217, 0x82068435,
+  0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
+    0x1695857b, 0x82021294,
+  0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
+    0x167cc801, 0x81fda5cf,
+  0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
+    0x166409a8, 0x81f93de6,
+  0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
+    0x164b4a73, 0x81f4dad8,
+  0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
+    0x16328a61, 0x81f07ca6,
+  0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
+    0x1619c975, 0x81ec2351,
+  0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
+    0x160107ae, 0x81e7ced8,
+  0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
+    0x15e8450e, 0x81e37f3b,
+  0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
+    0x15cf8196, 0x81df347b,
+  0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
+    0x15b6bd47, 0x81daee98,
+  0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
+    0x159df821, 0x81d6ad92,
+  0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
+    0x15853226, 0x81d27169,
+  0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
+    0x156c6b57, 0x81ce3a1d,
+  0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
+    0x1553a3b4, 0x81ca07af,
+  0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
+    0x153adb3f, 0x81c5da1e,
+  0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
+    0x152211f8, 0x81c1b16b,
+  0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
+    0x150947e1, 0x81bd8d97,
+  0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
+    0x14f07cf9, 0x81b96ea0,
+  0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
+    0x14d7b144, 0x81b55488,
+  0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
+    0x14bee4c0, 0x81b13f4e,
+  0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
+    0x14a61770, 0x81ad2ef2,
+  0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
+    0x148d4954, 0x81a92376,
+  0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
+    0x14747a6d, 0x81a51cd8,
+  0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
+    0x145baabd, 0x81a11b1a,
+  0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
+    0x1442da43, 0x819d1e3a,
+  0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
+    0x142a0902, 0x8199263a,
+  0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
+    0x141136f9, 0x8195331a,
+  0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
+    0x13f8642a, 0x819144d9,
+  0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
+    0x13df9097, 0x818d5b78,
+  0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
+    0x13c6bc3f, 0x818976f8,
+  0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
+    0x13ade724, 0x81859757,
+  0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
+    0x13951146, 0x8181bc96,
+  0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
+    0x137c3aa8, 0x817de6b6,
+  0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
+    0x13636349, 0x817a15b7,
+  0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
+    0x134a8b2b, 0x81764998,
+  0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
+    0x1331b24e, 0x8172825a,
+  0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
+    0x1318d8b4, 0x816ebffe,
+  0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
+    0x12fffe5d, 0x816b0282,
+  0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
+    0x12e7234b, 0x816749e8,
+  0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
+    0x12ce477f, 0x8163962f,
+  0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
+    0x12b56af9, 0x815fe758,
+  0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
+    0x129c8dba, 0x815c3d62,
+  0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
+    0x1283afc3, 0x8158984e,
+  0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
+    0x126ad116, 0x8154f81d,
+  0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
+    0x1251f1b3, 0x81515ccd,
+  0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
+    0x1239119b, 0x814dc660,
+  0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
+    0x122030cf, 0x814a34d6,
+  0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
+    0x12074f50, 0x8146a82e,
+  0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
+    0x11ee6d20, 0x81432068,
+  0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
+    0x11d58a3e, 0x813f9d86,
+  0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
+    0x11bca6ad, 0x813c1f86,
+  0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
+    0x11a3c26c, 0x8138a66a,
+  0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
+    0x118add7d, 0x81353230,
+  0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
+    0x1171f7e2, 0x8131c2db,
+  0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
+    0x1159119a, 0x812e5868,
+  0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
+    0x11402aa6, 0x812af2da,
+  0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
+    0x11274309, 0x8127922f,
+  0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
+    0x110e5ac2, 0x81243668,
+  0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
+    0x10f571d3, 0x8120df85,
+  0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
+    0x10dc883c, 0x811d8d86,
+  0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
+    0x10c39dff, 0x811a406c,
+  0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
+    0x10aab31d, 0x8116f836,
+  0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
+    0x1091c796, 0x8113b4e5,
+  0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
+    0x1078db6c, 0x81107678,
+  0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
+    0x105fee9f, 0x810d3cf0,
+  0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
+    0x10470130, 0x810a084d,
+  0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
+    0x102e1321, 0x8106d88f,
+  0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
+    0x10152472, 0x8103adb6,
+  0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
+    0xffc3524, 0x810087c3,
+  0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
+    0xfe34539, 0x80fd66b5,
+  0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
+    0xfca54b1, 0x80fa4a8c,
+  0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
+    0xfb1638d, 0x80f73349,
+  0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
+    0xf9871ce, 0x80f420ec,
+  0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
+    0xf7f7f75, 0x80f11375,
+  0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
+    0xf668c83, 0x80ee0ae4,
+  0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
+    0xf4d98f9, 0x80eb0739,
+  0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
+    0xf34a4d8, 0x80e80874,
+  0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
+    0xf1bb021, 0x80e50e96,
+  0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
+    0xf02bad5, 0x80e2199e,
+  0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
+    0xee9c4f5, 0x80df298c,
+  0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
+    0xed0ce82, 0x80dc3e62,
+  0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
+    0xeb7d77c, 0x80d9581e,
+  0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
+    0xe9edfe5, 0x80d676c1,
+  0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
+    0xe85e7be, 0x80d39a4b,
+  0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
+    0xe6cef07, 0x80d0c2bc,
+  0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
+    0xe53f5c2, 0x80cdf015,
+  0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
+    0xe3afbf0, 0x80cb2255,
+  0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
+    0xe220191, 0x80c8597c,
+  0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
+    0xe0906a7, 0x80c5958b,
+  0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
+    0xdf00b32, 0x80c2d682,
+  0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
+    0xdd70f34, 0x80c01c60,
+  0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
+    0xdbe12ad, 0x80bd6727,
+  0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
+    0xda5159f, 0x80bab6d5,
+  0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
+    0xd8c1809, 0x80b80b6c,
+  0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
+    0xd7319ee, 0x80b564ea,
+  0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
+    0xd5a1b4f, 0x80b2c351,
+  0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
+    0xd411c2b, 0x80b026a1,
+  0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
+    0xd281c85, 0x80ad8ed9,
+  0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
+    0xd0f1c5d, 0x80aafbf9,
+  0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
+    0xcf61bb4, 0x80a86e03,
+  0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
+    0xcdd1a8b, 0x80a5e4f5,
+  0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
+    0xcc418e3, 0x80a360d0,
+  0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
+    0xcab16bd, 0x80a0e194,
+  0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
+    0xc92141a, 0x809e6741,
+  0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
+    0xc7910fb, 0x809bf1d7,
+  0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
+    0xc600d61, 0x80998157,
+  0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
+    0xc47094d, 0x809715c0,
+  0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
+    0xc2e04c0, 0x8094af13,
+  0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
+    0xc14ffba, 0x80924d4f,
+  0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
+    0xbfbfa3d, 0x808ff074,
+  0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
+    0xbe2f44a, 0x808d9884,
+  0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
+    0xbc9ede2, 0x808b457d,
+  0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
+    0xbb0e705, 0x8088f761,
+  0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
+    0xb97dfb5, 0x8086ae2e,
+  0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
+    0xb7ed7f2, 0x808469e5,
+  0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
+    0xb65cfbe, 0x80822a87,
+  0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
+    0xb4cc719, 0x807ff013,
+  0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
+    0xb33be05, 0x807dba89,
+  0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
+    0xb1ab483, 0x807b89ea,
+  0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
+    0xb01aa92, 0x80795e36,
+  0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
+    0xae8a036, 0x8077376c,
+  0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
+    0xacf956d, 0x8075158c,
+  0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
+    0xab68a3a, 0x8072f898,
+  0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
+    0xa9d7e9d, 0x8070e08e,
+  0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
+    0xa847297, 0x806ecd6f,
+  0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
+    0xa6b662a, 0x806cbf3c,
+  0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
+    0xa525955, 0x806ab5f3,
+  0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
+    0xa394c1b, 0x8068b196,
+  0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
+    0xa203e7c, 0x8066b224,
+  0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
+    0xa073079, 0x8064b79d,
+  0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
+    0x9ee2213, 0x8062c202,
+  0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
+    0x9d5134b, 0x8060d152,
+  0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
+    0x9bc0421, 0x805ee58e,
+  0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
+    0x9a2f498, 0x805cfeb5,
+  0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
+    0x989e4b0, 0x805b1cc8,
+  0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
+    0x970d46a, 0x80593fc7,
+  0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
+    0x957c3c6, 0x805767b2,
+  0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
+    0x93eb2c6, 0x80559489,
+  0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
+    0x925a16b, 0x8053c64c,
+  0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
+    0x90c8fb6, 0x8051fcfb,
+  0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
+    0x8f37da7, 0x80503896,
+  0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
+    0x8da6b40, 0x804e791d,
+  0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
+    0x8c15882, 0x804cbe90,
+  0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
+    0x8a8456d, 0x804b08f0,
+  0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
+    0x88f3203, 0x8049583d,
+  0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
+    0x8761e44, 0x8047ac75,
+  0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
+    0x85d0a32, 0x8046059b,
+  0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
+    0x843f5cd, 0x804463ad,
+  0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
+    0x82ae117, 0x8042c6ab,
+  0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
+    0x811cc10, 0x80412e96,
+  0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
+    0x7f8b6b9, 0x803f9b6f,
+  0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
+    0x7dfa114, 0x803e0d34,
+  0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
+    0x7c68b21, 0x803c83e5,
+  0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
+    0x7ad74e1, 0x803aff84,
+  0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
+    0x7945e56, 0x80398010,
+  0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
+    0x77b4780, 0x80380589,
+  0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
+    0x762305f, 0x80368fef,
+  0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
+    0x74918f6, 0x80351f43,
+  0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
+    0x7300145, 0x8033b383,
+  0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
+    0x716e94e, 0x80324cb1,
+  0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
+    0x6fdd110, 0x8030eacd,
+  0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
+    0x6e4b88d, 0x802f8dd5,
+  0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
+    0x6cb9fc6, 0x802e35cb,
+  0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
+    0x6b286bc, 0x802ce2af,
+  0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
+    0x6996d70, 0x802b9480,
+  0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
+    0x68053e3, 0x802a4b3f,
+  0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
+    0x6673a16, 0x802906ec,
+  0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
+    0x64e2009, 0x8027c786,
+  0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
+    0x63505be, 0x80268d0e,
+  0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
+    0x61beb36, 0x80255784,
+  0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
+    0x602d072, 0x802426e8,
+  0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
+    0x5e9b572, 0x8022fb3a,
+  0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
+    0x5d09a38, 0x8021d47a,
+  0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
+    0x5b77ec5, 0x8020b2a7,
+  0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
+    0x59e6319, 0x801f95c3,
+  0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
+    0x5854736, 0x801e7dcd,
+  0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
+    0x56c2b1c, 0x801d6ac5,
+  0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
+    0x5530ecd, 0x801c5cab,
+  0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
+    0x539f249, 0x801b537f,
+  0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
+    0x520d592, 0x801a4f42,
+  0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
+    0x507b8a8, 0x80194ff3,
+  0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
+    0x4ee9b8c, 0x80185592,
+  0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
+    0x4d57e40, 0x80176020,
+  0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
+    0x4bc60c4, 0x80166f9c,
+  0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
+    0x4a34319, 0x80158406,
+  0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
+    0x48a2540, 0x80149d5f,
+  0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
+    0x471073b, 0x8013bba7,
+  0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
+    0x457e90a, 0x8012dedd,
+  0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
+    0x43ecaae, 0x80120701,
+  0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
+    0x425ac28, 0x80113414,
+  0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
+    0x40c8d79, 0x80106616,
+  0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
+    0x3f36ea2, 0x800f9d07,
+  0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
+    0x3da4fa4, 0x800ed8e6,
+  0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
+    0x3c13080, 0x800e19b4,
+  0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
+    0x3a81137, 0x800d5f71,
+  0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
+    0x38ef1ca, 0x800caa1c,
+  0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
+    0x375d23a, 0x800bf9b7,
+  0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
+    0x35cb288, 0x800b4e40,
+  0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
+    0x34392b4, 0x800aa7b8,
+  0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
+    0x32a72c1, 0x800a061f,
+  0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
+    0x31152ae, 0x80096975,
+  0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
+    0x2f8327d, 0x8008d1ba,
+  0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
+    0x2df122e, 0x80083eed,
+  0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
+    0x2c5f1c3, 0x8007b110,
+  0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
+    0x2acd13d, 0x80072822,
+  0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
+    0x293b09c, 0x8006a423,
+  0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
+    0x27a8fe2, 0x80062513,
+  0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
+    0x2616f10, 0x8005aaf2,
+  0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
+    0x2484e26, 0x800535c0,
+  0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
+    0x22f2d25, 0x8004c57d,
+  0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
+    0x2160c0f, 0x80045a29,
+  0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
+    0x1fceae4, 0x8003f3c5,
+  0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
+    0x1e3c9a6, 0x8003924f,
+  0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
+    0x1caa855, 0x800335c9,
+  0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
+    0x1b186f3, 0x8002de32,
+  0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
+    0x198657f, 0x80028b8a,
+  0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
+    0x17f43fc, 0x80023dd2,
+  0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
+    0x166226a, 0x8001f508,
+  0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
+    0x14d00ca, 0x8001b12e,
+  0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
+    0x133df1e, 0x80017243,
+  0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
+    0x11abd66, 0x80013847,
+  0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
+    0x1019ba2, 0x8001033b,
+  0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
+    0x8000d31e,
+  0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
+    0x8000a7f0,
+  0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
+    0x800081b1,
+  0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
+    0x80006062,
+  0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
+    0x80004402,
+  0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
+    0x80002c91,
+  0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
+    0x80001a10,
+  0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
+    0x80000c7e,
+  0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
+    0x800003db,
+  0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
+    0x80000027,
+
+};
+
+/**    
+* \par    
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
+* \par    
+* C command to generate the table    
+* 
    
+* for(i = 0; i< N; i++)    
+* {    
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+* } 
    
+* \par    
+* where N is the number of factors to generate and c is pi/(2*N)    
+* \par    
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.    
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+  0x7f97cebd, 0x7f754e80,
+  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+  0x7dfa98a8, 0x7db0fdf8,
+  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+  0x7b26cb4f, 0x7ab6cba4,
+  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+  0x77235f2d, 0x768e0ea6,
+  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+  0x71fa3949, 0x71410805,
+  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+  0x6bb812d1, 0x6adcc964,
+  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+  0x646c59bf, 0x637114cc,
+  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+  0x5c290acc, 0x5b1035cf,
+  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+  0x53028518, 0x51ced46e,
+  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+  0x490f57ee, 0x47c3c22f,
+  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+  0x3e680b2c, 0x3d07c1d6,
+  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+  0x3326e2c3, 0x31b54a5e,
+  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+  0x27679df4, 0x25e845b6,
+  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+  0x1b4732ef, 0x19bdcbf3,
+  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+  0xee38766, 0xd53db92,
+  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+  0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+  0x7ff97c18, 0x7ff75370,
+  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+  0x7fdf9508, 0x7fdaf519,
+  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+  0x7fb1f5fc, 0x7faadf7c,
+  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+  0x7f70a5fe, 0x7f671a05,
+  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+  0x7f1baf1e, 0x7f0faf25,
+  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+  0x7eb31e78, 0x7ea4ac58,
+  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+  0x7e37042a, 0x7e26221f,
+  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+  0x7da77359, 0x7d9423fc,
+  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+  0x7d048228, 0x7ceec873,
+  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+  0x7c4e49b7, 0x7c362904,
+  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+  0x7b84e61f, 0x7b6a6227,
+  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+  0x7aa8766f, 0x7a8b9348,
+  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+  0x79b91ca4, 0x7999dec4,
+  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+  0x78b6fda8, 0x789569df,
+  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+  0x77a24148, 0x777e5cc3,
+  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+  0x767b1231, 0x7654e279,
+  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+  0x75419de7, 0x751928e0,
+  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+  0x73f614c0, 0x73cb60a8,
+  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+  0x7298a9dd, 0x726bbd48,
+  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+  0x7129931f, 0x70fa74fc,
+  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+  0x6fa90921, 0x6f77c0b3,
+  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+  0x6e174730, 0x6de3dc11,
+  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+  0x6c748b3f, 0x6c3f055d,
+  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+  0x6ac115e2, 0x6a897d7d,
+  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+  0x68fd2a3d, 0x68c387e9,
+  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+  0x67290e02, 0x66ed6aa1,
+  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+  0x6545095f, 0x65076e25,
+  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+  0x635166f9, 0x6311dd64,
+  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+  0x614e73da, 0x610d05b7,
+  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+  0x5f3c7f6b, 0x5ef936d1,
+  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+  0x5d1bdb65, 0x5cd6c2b5,
+  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+  0x5aecdbc5, 0x5aa5fda5,
+  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+  0x58afd6bd, 0x58673e1b,
+  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+  0x566524aa, 0x561adcb9,
+  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+  0x540d2005, 0x53c13439,
+  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+  0x51a82555, 0x515aa162,
+  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+  0x4f369320, 0x4ee782fb,
+  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+  0x4cb8c9dd, 0x4c6839b7,
+  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+  0x4a2f2be6, 0x49dd282a,
+  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+  0x479a1d67, 0x4746b2bc,
+  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+  0x44fa0450, 0x44a53f93,
+  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+  0x424f4845, 0x41f93689,
+  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+  0x3f9a5290, 0x3f430119,
+  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+  0x3cdb8e09, 0x3c830a50,
+  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+  0x3a136712, 0x39b9bebc,
+  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+  0x37424b7b, 0x36e78c5b,
+  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+  0x3468aa76, 0x340ce28b,
+  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+  0x3186f487, 0x312a31f8,
+  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+  0x2e9d9b70, 0x2e3fec8b,
+  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+  0x2bad1221, 0x2b4e8558,
+  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+  0x28b5cca5, 0x2856708d,
+  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+  0x25b84012, 0x2558235f,
+  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+  0x22b4e274, 0x225413f8,
+  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+  0x1fac2abf, 0x1f4ab968,
+  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+  0x1c9e90b8, 0x1c3c8b8c,
+  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+  0x198c8ce7, 0x192a0304,
+  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+  0x1676987f, 0x16139918,
+  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+  0x135d2d53, 0x12f9c7aa,
+  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+  0x1040c5bb, 0xfdd0926,
+  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+  0xcbdd865,
+  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+  0x99cb0a7,
+  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+  0x67a0d76,
+  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+  0x3566a96,
+  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+  0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+  0x7fff97c1, 0x7fff7536,
+  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+  0x7ffdf93c, 0x7ffdaf37,
+  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+  0x7ffb1ee9, 0x7ffaad6a,
+  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+  0x7ff708ce, 0x7ff66fd7,
+  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+  0x7ff1b6f6, 0x7ff0f688,
+  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+  0x7feb296d, 0x7fea418b,
+  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+  0x7fe36045, 0x7fe250ef,
+  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+  0x7fda5b8f, 0x7fd924ca,
+  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+  0x7fd01b63, 0x7fcebd31,
+  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+  0x7fc49fda, 0x7fc31a3d,
+  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+  0x7fb7e90f, 0x7fb63c0d,
+  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+  0x7fa9f723, 0x7fa822bf,
+  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+  0x7f9aca37, 0x7f98ce76,
+  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+  0x7f8a6272, 0x7f883f58,
+  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+  0x7f78bffb, 0x7f76758e,
+  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+  0x7f65e2ff, 0x7f637144,
+  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+  0x7f51cbab, 0x7f4f32a9,
+  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+  0x7f3c7a31, 0x7f39b9ee,
+  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+  0x7f25eec7, 0x7f230749,
+  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+  0x7f0e29a3, 0x7f0b1af2,
+  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+  0x7ef52b00, 0x7ef1f524,
+  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+  0x7edaf31c, 0x7ed7961c,
+  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+  0x7ebf8237, 0x7ebbfe1c,
+  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+  0x7ea2d896, 0x7e9f2d68,
+  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+  0x7e84f67e, 0x7e812447,
+  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+  0x7e65dc3b, 0x7e61e303,
+  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+  0x7e458a17, 0x7e4169e9,
+  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+  0x7e240064, 0x7e1fb94a,
+  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+  0x7e013f74, 0x7dfcd178,
+  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+  0x7ddd479d, 0x7dd8b2ca,
+  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+  0x7db81936, 0x7db35d98,
+  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+  0x7d91b49e, 0x7d8cd240,
+  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+  0x7d6a1a31, 0x7d65111f,
+  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+  0x7d414a51, 0x7d3c1a98,
+  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+  0x7d174564, 0x7d11ef11,
+  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+  0x7cec0bd1, 0x7ce68ef0,
+  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+  0x7cbf9e03, 0x7cb9faa2,
+  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+  0x7c91fc66, 0x7c8c3294,
+  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+  0x7c63276d, 0x7c5d3737,
+  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+  0x7c331f8a, 0x7c2d08ff,
+  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+  0x7c01e534, 0x7bfba863,
+  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+  0x7bcf78e5, 0x7bc915dd,
+  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+  0x7b9bdb18, 0x7b9551ea,
+  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+  0x7b670c4d, 0x7b605d09,
+  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+  0x7b310d07, 0x7b2a37bc,
+  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+  0x7af9ddcb, 0x7af2e28b,
+  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+  0x7ac17f20, 0x7aba5dfc,
+  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+  0x7a87f192, 0x7a80aa9c,
+  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+  0x7a4d35b0, 0x7a45c8f9,
+  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+  0x7a114c09, 0x7a09b9a4,
+  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+  0x79d43532, 0x79cc7d31,
+  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+  0x7995f1c1, 0x798e1438,
+  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+  0x79568250, 0x794e7f52,
+  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+  0x7915e77c, 0x790dbf1d,
+  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+  0x78d421e4, 0x78cbd437,
+  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+  0x7891322a, 0x7888bf45,
+  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+  0x784d18f4, 0x784480ea,
+  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+  0x7807d6e9, 0x77ff19d1,
+  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+  0x77c16cb4, 0x77b88aa3,
+  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+  0x7779db03, 0x7770d40f,
+  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+  0x77312287, 0x7727f6c6,
+  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+  0x76e743f4, 0x76ddf37c,
+  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+  0x769c3ffe, 0x7692cae8,
+  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+  0x76501760, 0x76467dc2,
+  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+  0x7602cad5, 0x75f90cc7,
+  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+  0x75b45b1d, 0x75aa78b6,
+  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+  0x7564c8f8, 0x755ac251,
+  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+  0x7514152b, 0x7509ea5d,
+  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+  0x74c2407d, 0x74b7f1a1,
+  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+  0x746f4bb8, 0x7464d8e8,
+  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+  0x741b37a9, 0x7410a0fe,
+  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+  0x73c6051f, 0x73bb4ab3,
+  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+  0x736fb4ec, 0x7364d6da,
+  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+  0x731847e5, 0x730d4648,
+  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+  0x72bfbee3, 0x72b499d6,
+  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+  0x72661abf, 0x725ad25d,
+  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+  0x720b5c57, 0x71fff0bc,
+  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+  0x71af848a, 0x71a3f5d2,
+  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+  0x7152943b, 0x7146e284,
+  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+  0x70f48c50, 0x70e8b7b5,
+  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+  0x70956db1, 0x70897650,
+  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+  0x70353947, 0x70291f3e,
+  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+  0x6fd3f001, 0x6fc7b36d,
+  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+  0x6f7192cf, 0x6f6533ce,
+  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+  0x6f0e22a3, 0x6f01a155,
+  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+  0x6ea9a073, 0x6e9cfcf5,
+  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+  0x6e440d37, 0x6e3747a9,
+  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+  0x6ddd69e9, 0x6dd0826a,
+  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+  0x6d75b786, 0x6d68ae37,
+  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+  0x6d0cf70f, 0x6cffcc0f,
+  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+  0x6ca32985, 0x6c95dcf6,
+  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+  0x6c384fef, 0x6c2ae1f0,
+  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+  0x6bcc6b53, 0x6bbedc06,
+  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+  0x6b5f7cbc, 0x6b51cc42,
+  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+  0x6af18536, 0x6ae3b3b2,
+  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+  0x6a8285d1, 0x6a749365,
+  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+  0x6a127f9f, 0x6a046c6c,
+  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+  0x69a173b5, 0x69933fde,
+  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+  0x692f6328, 0x69210ed1,
+  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+  0x68bc4f13, 0x68adda5f,
+  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+  0x68483891, 0x6839a3a4,
+  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+  0x67d320c1, 0x67c46bbe,
+  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+  0x675d08c4, 0x674e33d0,
+  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+  0x66e5f1be, 0x66d6fcfd,
+  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+  0x666ddcd3, 0x665ec86b,
+  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+  0x65f4cb2d, 0x65e59742,
+  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+  0x657abdf6, 0x656b6aae,
+  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+  0x64ffb65b, 0x64f043dc,
+  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+  0x6483b58c, 0x647423fb,
+  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+  0x6406bcba, 0x63f70c3f,
+  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+  0x6388cd1b, 0x6378fddc,
+  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+  0x6309e7e4, 0x62f9fa09,
+  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+  0x628a0e50, 0x627a01fe,
+  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+  0x62094199, 0x61f916f9,
+  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+  0x618782fd, 0x61773a37,
+  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+  0x6104d3bc, 0x60f46cf9,
+  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+  0x60813519, 0x6070b080,
+  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+  0x5ffca859, 0x5fec0613,
+  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+  0x5f772ec2, 0x5f666ef9,
+  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+  0x5ef0c99f, 0x5edfec7b,
+  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+  0x5e697a39, 0x5e587fe5,
+  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+  0x5de141e1, 0x5dd02a85,
+  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+  0x5d5821e4, 0x5d46edac,
+  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+  0x5cce1b97, 0x5cbccaac,
+  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+  0x5c43304d, 0x5c31c2db,
+  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+  0x5bb7615d, 0x5ba5d78e,
+  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+  0x5b2ab020, 0x5b190a20,
+  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+  0x5a9d1df1, 0x5a8b5bec,
+  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+  0x5a0eac2e, 0x59fcce4f,
+  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+  0x597f5c36, 0x596d62a9,
+  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+  0x58ef2f6b, 0x58dd1a5d,
+  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+  0x585e2730, 0x584bf6cd,
+  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+  0x57cc44ec, 0x57b9f960,
+  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+  0x57398a05, 0x5727237f,
+  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+  0x56a5f7e7, 0x56937694,
+  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+  0x56118ffe, 0x55fef40a,
+  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+  0x557c53b6, 0x55699d51,
+  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+  0x54e64482, 0x54d373d9,
+  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+  0x544f63d2, 0x543c7914,
+  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+  0x53b7b31c, 0x53a4ae77,
+  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+  0x531f33d5, 0x530c1579,
+  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+  0x5285e777, 0x5272af92,
+  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+  0x51ebcf7a, 0x51d87e3c,
+  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+  0x5150ed5c, 0x513d82f4,
+  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+  0x50b5429a, 0x50a1bf39,
+  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+  0x5018d0b4, 0x5005348a,
+  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+  0x4f7b992d, 0x4f67e46a,
+  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+  0x4edd9d89, 0x4ec9d05e,
+  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+  0x4e3edf4d, 0x4e2af9ea,
+  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+  0x4d9f6001, 0x4d8b6298,
+  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+  0x4cff212e, 0x4ceb0bf0,
+  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+  0x4c5e2460, 0x4c49f77f,
+  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+  0x4bbc6b25, 0x4ba826d1,
+  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+  0x4b19f70a, 0x4b059b77,
+  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+  0x4a76c9a2, 0x4a625701,
+  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+  0x49d2e47e, 0x49be5b02,
+  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+  0x492e4933, 0x4919a90f,
+  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+  0x4888f957, 0x487442be,
+  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+  0x47e2f682, 0x47ce29a7,
+  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+  0x473c424e, 0x47275f63,
+  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+  0x4694de56, 0x467fe590,
+  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+  0x45eccc37, 0x45d7bdc9,
+  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+  0x45440d90, 0x452ee9ae,
+  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+  0x449aa400, 0x44856adf,
+  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+  0x43f0912b, 0x43db42fe,
+  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+  0x4345d6b3, 0x433073b0,
+  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+  0x429a763f, 0x4284fe99,
+  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+  0x41ee7174, 0x41d8e561,
+  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+  0x4141c9fb, 0x412c29b1,
+  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+  0x4094817f, 0x407ecd32,
+  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+  0x3fe699aa, 0x3fd0d191,
+  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+  0x3f38142a, 0x3f22387a,
+  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+  0x3e88f2ae, 0x3e73039d,
+  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+  0x3dd936e6, 0x3dc334a9,
+  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+  0x3d28e282, 0x3d12cd51,
+  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+  0x3c77f737, 0x3c61cf48,
+  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+  0x3bc676b9, 0x3bb03c42,
+  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+  0x3b1462be, 0x3afe15f6,
+  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+  0x3a61bcfd, 0x3a4b5e1b,
+  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+  0x39ae872f, 0x3998166a,
+  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+  0x38fac30e, 0x38e4409e,
+  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+  0x38467255, 0x382fde72,
+  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+  0x379196c3, 0x377af1a3,
+  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+  0x36dc3214, 0x36c57bf0,
+  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+  0x36264609, 0x360f7f19,
+  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+  0x356fd461, 0x3558fcde,
+  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+  0x34b8dee1, 0x34a1f702,
+  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+  0x3401674a, 0x33ea6f48,
+  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+  0x33496f62, 0x33326776,
+  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+  0x3290f8ef, 0x3279e151,
+  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+  0x31d805b7, 0x31c0dea1,
+  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+  0x311e9783, 0x3107612e,
+  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+  0x3064b01d, 0x304d6ac1,
+  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+  0x2faa514f, 0x2f92fd26,
+  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+  0x2eef7ce5, 0x2ed81a29,
+  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+  0x2e3434ac, 0x2e1cc397,
+  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+  0x2d787a72, 0x2d60fb3e,
+  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+  0x2cbc5006, 0x2ca4c2ed,
+  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+  0x2bffb73a, 0x2be81c74,
+  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+  0x2b42b1dd, 0x2b2b09a6,
+  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+  0x2a8541c3, 0x2a6d8c55,
+  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+  0x29c768be, 0x29afa654,
+  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+  0x290928a3, 0x28f15978,
+  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+  0x284a8349, 0x2832a796,
+  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+  0x278b7a84, 0x27739285,
+  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+  0x26cc102d, 0x26b41c1d,
+  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+  0x260c461b, 0x25f44635,
+  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+  0x254c1e28, 0x253412a8,
+  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+  0x248b9a2f, 0x2473834f,
+  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+  0x23cabc09, 0x23b29a05,
+  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+  0x23098593, 0x22f158a7,
+  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+  0x2247f8aa, 0x222fc111,
+  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+  0x2186172b, 0x216dd521,
+  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+  0x20c3e2f5, 0x20ab96b5,
+  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+  0x20015de7, 0x1fe907ae,
+  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+  0x1f3e89e0, 0x1f2629ea,
+  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+  0x1e7b68c2, 0x1e62ff4a,
+  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+  0x1db7fc6d, 0x1d9f89b1,
+  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+  0x1cf446c5, 0x1cdbcb00,
+  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+  0x1c3049ac, 0x1c17c51b,
+  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+  0x1b6c0705, 0x1b5379e5,
+  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+  0x1aa780b6, 0x1a8eeb42,
+  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+  0x19e2b8a2, 0x19ca1b17,
+  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+  0x191db0af, 0x19050b4b,
+  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+  0x18586ac3, 0x183fbdc3,
+  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+  0x1792e8c6, 0x177a3466,
+  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+  0x16cd2c9f, 0x16b4711b,
+  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+  0x16073834, 0x15ee75cb,
+  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+  0x15410d70, 0x1528445d,
+  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+  0x147aae3a, 0x1461debc,
+  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+  0x13b41c7d, 0x139b46d0,
+  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+  0x12ed5a21, 0x12d47e83,
+  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+  0x12266913, 0x120d87c1,
+  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+  0x115f4b3c, 0x11466473,
+  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+  0x10980287, 0x107f1686,
+  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+  0xfd090e1, 0xfb79fe4,
+  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+  0xef0027b,
+  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+  0xe284036,
+  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+  0xd605b03,
+  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+  0xc9854cf,
+  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+  0xbd02f87,
+  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+  0xb07ed19,
+  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+  0xa3f8f73,
+  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+  0x9771884,
+  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+  0x8ae8a3a,
+  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+  0x7e5e685,
+  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+  0x71d2f52,
+  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+  0x6546692,
+  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+  0x58b8e34,
+  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+  0x4c2a827,
+  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+  0x3f9b65b,
+  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+  0x330bac1,
+  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+  0x267b747,
+  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+  0x19eaddd,
+  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+  0xd5a075,
+  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+  0xc90fe,
+
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+  0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
+    0x7ffff97c, 0x7ffff753,
+  0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
+    0x7fffdf94, 0x7fffdaf3,
+  0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
+    0x7fffb1ee, 0x7fffaad6,
+  0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
+    0x7fff708b, 0x7fff66fc,
+  0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
+    0x7fff1b6b, 0x7fff0f64,
+  0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
+    0x7ffeb28e, 0x7ffea40f,
+  0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
+    0x7ffe35f4, 0x7ffe24fe,
+  0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
+    0x7ffda59d, 0x7ffd922f,
+  0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
+    0x7ffd0189, 0x7ffceba4,
+  0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
+    0x7ffc49b9, 0x7ffc315b,
+  0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
+    0x7ffb7e2b, 0x7ffb6356,
+  0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
+    0x7ffa9ee2, 0x7ffa8195,
+  0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
+    0x7ff9abdb, 0x7ff98c17,
+  0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
+    0x7ff8a519, 0x7ff882dd,
+  0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
+    0x7ff78a9a, 0x7ff765e7,
+  0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
+    0x7ff65c5f, 0x7ff63535,
+  0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
+    0x7ff51a69, 0x7ff4f0c7,
+  0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
+    0x7ff3c4b7, 0x7ff3989e,
+  0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
+    0x7ff25b4a, 0x7ff22cb9,
+  0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
+    0x7ff0de22, 0x7ff0ad19,
+  0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
+    0x7fef4d3e, 0x7fef19bf,
+  0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
+    0x7feda8a0, 0x7fed72aa,
+  0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
+    0x7febf048, 0x7febb7da,
+  0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
+    0x7fea2436, 0x7fe9e950,
+  0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
+    0x7fe84469, 0x7fe8070d,
+  0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
+    0x7fe650e3, 0x7fe61110,
+  0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
+    0x7fe449a4, 0x7fe40759,
+  0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
+    0x7fe22eac, 0x7fe1e9ea,
+  0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
+    0x7fdffffb, 0x7fdfb8c2,
+  0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
+    0x7fddbd92, 0x7fdd73e2,
+  0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
+    0x7fdb6771, 0x7fdb1b4a,
+  0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
+    0x7fd8fd98, 0x7fd8aefa,
+  0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
+    0x7fd68009, 0x7fd62ef4,
+  0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
+    0x7fd3eec2, 0x7fd39b36,
+  0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
+    0x7fd149c5, 0x7fd0f3c2,
+  0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
+    0x7fce9112, 0x7fce3898,
+  0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
+    0x7fcbc4a9, 0x7fcb69b9,
+  0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
+    0x7fc8e48b, 0x7fc88724,
+  0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
+    0x7fc5f0b8, 0x7fc590db,
+  0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
+    0x7fc2e931, 0x7fc286de,
+  0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
+    0x7fbfcdf6, 0x7fbf692c,
+  0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
+    0x7fbc9f08, 0x7fbc37c8,
+  0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
+    0x7fb95c67, 0x7fb8f2b0,
+  0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
+    0x7fb60614, 0x7fb599e7,
+  0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
+    0x7fb29c0f, 0x7fb22d6c,
+  0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
+    0x7faf1e58, 0x7faead3f,
+  0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
+    0x7fab8cf1, 0x7fab1962,
+  0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
+    0x7fa7e7d9, 0x7fa771d4,
+  0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
+    0x7fa42f12, 0x7fa3b697,
+  0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
+    0x7fa0629c, 0x7f9fe7ab,
+  0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
+    0x7f9c8278, 0x7f9c0511,
+  0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
+    0x7f988ea5, 0x7f980ec8,
+  0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
+    0x7f948725, 0x7f9404d3,
+  0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
+    0x7f906bf9, 0x7f8fe731,
+  0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
+    0x7f8c3d20, 0x7f8bb5e3,
+  0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
+    0x7f87fa9c, 0x7f8770ea,
+  0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
+    0x7f83a46e, 0x7f831846,
+  0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
+    0x7f7f3a95, 0x7f7eabf8,
+  0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
+    0x7f7abd13, 0x7f7a2c01,
+  0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
+    0x7f762be8, 0x7f759861,
+  0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
+    0x7f718715, 0x7f70f119,
+  0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
+    0x7f6cce9b, 0x7f6c362a,
+  0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
+    0x7f68027b, 0x7f676795,
+  0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
+    0x7f6322b4, 0x7f62855a,
+  0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
+    0x7f5e2f49, 0x7f5d8f7a,
+  0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
+    0x7f592839, 0x7f5885f6,
+  0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
+    0x7f540d86, 0x7f5368ce,
+  0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
+    0x7f4edf30, 0x7f4e3804,
+  0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
+    0x7f499d38, 0x7f48f398,
+  0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
+    0x7f44479f, 0x7f439b8b,
+  0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
+    0x7f3ede66, 0x7f3e2fde,
+  0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
+    0x7f39618e, 0x7f38b091,
+  0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
+    0x7f33d116, 0x7f331da6,
+  0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
+    0x7f2e2d01, 0x7f2d771e,
+  0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
+    0x7f28754f, 0x7f27bcf8,
+  0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
+    0x7f22aa01, 0x7f21ef37,
+  0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
+    0x7f1ccb18, 0x7f1c0dda,
+  0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
+    0x7f16d895, 0x7f1618e4,
+  0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
+    0x7f10d279, 0x7f101054,
+  0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
+    0x7f0ab8c4, 0x7f09f42d,
+  0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
+    0x7f048b78, 0x7f03c46d,
+  0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
+    0x7efe4a95, 0x7efd8118,
+  0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
+    0x7ef7f61d, 0x7ef72a2d,
+  0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
+    0x7ef18e10, 0x7ef0bfae,
+  0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
+    0x7eeb1270, 0x7eea419b,
+  0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
+    0x7ee4833d, 0x7ee3aff6,
+  0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
+    0x7edde079, 0x7edd0ac0,
+  0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
+    0x7ed72a24, 0x7ed651f9,
+  0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
+    0x7ed0603f, 0x7ecf85a3,
+  0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
+    0x7ec982cd, 0x7ec8a5bf,
+  0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
+    0x7ec291cd, 0x7ec1b24d,
+  0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
+    0x7ebb8d40, 0x7ebaab4f,
+  0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
+    0x7eb47529, 0x7eb390c6,
+  0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
+    0x7ead4987, 0x7eac62b3,
+  0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
+    0x7ea60a5d, 0x7ea52118,
+  0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
+    0x7e9eb7aa, 0x7e9dcbf4,
+  0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
+    0x7e975171, 0x7e96634a,
+  0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
+    0x7e8fd7b2, 0x7e8ee71b,
+  0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
+    0x7e884a6f, 0x7e875767,
+  0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
+    0x7e80a9a8, 0x7e7fb430,
+  0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
+    0x7e78f55f, 0x7e77fd77,
+  0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
+    0x7e712d96, 0x7e70333d,
+  0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
+    0x7e69524c, 0x7e685584,
+  0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
+    0x7e616384, 0x7e60644c,
+  0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
+    0x7e59613f, 0x7e585f97,
+  0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
+    0x7e514b7e, 0x7e504767,
+  0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
+    0x7e492241, 0x7e481bbb,
+  0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
+    0x7e40e58c, 0x7e3fdc97,
+  0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
+    0x7e38955e, 0x7e3789fa,
+  0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
+    0x7e3031b9, 0x7e2f23e6,
+  0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
+    0x7e27ba9e, 0x7e26aa5d,
+  0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
+    0x7e1f300f, 0x7e1e1d5f,
+  0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
+    0x7e16920d, 0x7e157cee,
+  0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
+    0x7e0de099, 0x7e0cc90c,
+  0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
+    0x7e051bb4, 0x7e0401ba,
+  0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
+    0x7dfc4361, 0x7dfb26f9,
+  0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
+    0x7df357a0, 0x7df238ca,
+  0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
+    0x7dea5872, 0x7de9372f,
+  0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
+    0x7de145da, 0x7de02229,
+  0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
+    0x7dd81fd8, 0x7dd6f9ba,
+  0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
+    0x7dcee66e, 0x7dcdbde3,
+  0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
+    0x7dc5999d, 0x7dc46ea6,
+  0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
+    0x7dbc3967, 0x7dbb0c03,
+  0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
+    0x7db2c5cd, 0x7db195fd,
+  0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
+    0x7da93ed1, 0x7da80c95,
+  0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
+    0x7d9fa474, 0x7d9e6fcb,
+  0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
+    0x7d95f6b7, 0x7d94bfa3,
+  0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
+    0x7d8c359d, 0x7d8afc1d,
+  0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
+    0x7d826126, 0x7d81253a,
+  0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
+    0x7d787954, 0x7d773afd,
+  0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
+    0x7d6e7e29, 0x7d6d3d67,
+  0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
+    0x7d646fa6, 0x7d632c79,
+  0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
+    0x7d5a4dcc, 0x7d590835,
+  0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
+    0x7d50189e, 0x7d4ed09d,
+  0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
+    0x7d45d01d, 0x7d4485b1,
+  0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
+    0x7d3b744a, 0x7d3a2774,
+  0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
+    0x7d310527, 0x7d2fb5e7,
+  0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
+    0x7d2682b6, 0x7d25310d,
+  0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
+    0x7d1becf8, 0x7d1a98e5,
+  0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
+    0x7d1143ef, 0x7d0fed73,
+  0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
+    0x7d06879d, 0x7d052eb8,
+  0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
+    0x7cfbb803, 0x7cfa5cb4,
+  0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
+    0x7cf0d522, 0x7cef776b,
+  0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
+    0x7ce5defd, 0x7ce47ede,
+  0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
+    0x7cdad596, 0x7cd9730e,
+  0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
+    0x7ccfb8ed, 0x7cce53fe,
+  0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
+    0x7cc48905, 0x7cc321ae,
+  0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
+    0x7cb945df, 0x7cb7dc20,
+  0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
+    0x7cadef7e, 0x7cac8358,
+  0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
+    0x7ca285e2, 0x7ca11755,
+  0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
+    0x7c97090e, 0x7c95981a,
+  0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
+    0x7c8b7903, 0x7c8a05a8,
+  0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
+    0x7c7fd5c4, 0x7c7e6002,
+  0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
+    0x7c741f51, 0x7c72a729,
+  0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
+    0x7c6855ad, 0x7c66db1f,
+  0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
+    0x7c5c78da, 0x7c5afbe6,
+  0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
+    0x7c5088d9, 0x7c4f0980,
+  0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
+    0x7c4485ad, 0x7c4303ee,
+  0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
+    0x7c386f56, 0x7c36eb33,
+  0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
+    0x7c2c45d8, 0x7c2abf4f,
+  0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
+    0x7c200933, 0x7c1e8046,
+  0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
+    0x7c13b96a, 0x7c122e19,
+  0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
+    0x7c07567f, 0x7c05c8c9,
+  0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
+    0x7bfae073, 0x7bf9505a,
+  0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
+    0x7bee5749, 0x7becc4cc,
+  0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
+    0x7be1bb02, 0x7be02621,
+  0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
+    0x7bd50ba1, 0x7bd3745d,
+  0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
+    0x7bc84927, 0x7bc6af80,
+  0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
+    0x7bbb7396, 0x7bb9d78c,
+  0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
+    0x7bae8af0, 0x7bacec84,
+  0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
+    0x7ba18f38, 0x7b9fee69,
+  0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
+    0x7b94806e, 0x7b92dd3e,
+  0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
+    0x7b875e96, 0x7b85b904,
+  0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
+    0x7b7a29b2, 0x7b7881be,
+  0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
+    0x7b6ce1c2, 0x7b6b376e,
+  0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
+    0x7b5f86ca, 0x7b5dda15,
+  0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
+    0x7b5218cc, 0x7b5069b6,
+  0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
+    0x7b4497c9, 0x7b42e652,
+  0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
+    0x7b3703c3, 0x7b354fed,
+  0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
+    0x7b295cbe, 0x7b27a687,
+  0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
+    0x7b1ba2b9, 0x7b19ea23,
+  0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
+    0x7b0dd5b9, 0x7b0c1ac4,
+  0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
+    0x7afff5bf, 0x7afe386a,
+  0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
+    0x7af202cd, 0x7af0431a,
+  0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
+    0x7ae3fce6, 0x7ae23ad4,
+  0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
+    0x7ad5e40a, 0x7ad41f9a,
+  0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
+    0x7ac7b83e, 0x7ac5f170,
+  0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
+    0x7ab97982, 0x7ab7b056,
+  0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
+    0x7aab27da, 0x7aa95c50,
+  0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
+    0x7a9cc346, 0x7a9af55f,
+  0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
+    0x7a8e4bca, 0x7a8c7b87,
+  0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
+    0x7a7fc168, 0x7a7deec8,
+  0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
+    0x7a712422, 0x7a6f4f25,
+  0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
+    0x7a6273fa, 0x7a609ca1,
+  0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
+    0x7a53b0f2, 0x7a51d73d,
+  0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
+    0x7a44db0d, 0x7a42fefd,
+  0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
+    0x7a35f24d, 0x7a3413e2,
+  0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
+    0x7a26f6b4, 0x7a2515ee,
+  0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
+    0x7a17e845, 0x7a160524,
+  0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
+    0x7a08c702, 0x7a06e187,
+  0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
+    0x79f992ed, 0x79f7ab18,
+  0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
+    0x79ea4c09, 0x79e861da,
+  0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
+    0x79daf258, 0x79d905d0,
+  0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
+    0x79cb85dc, 0x79c996fb,
+  0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
+    0x79bc0698, 0x79ba155e,
+  0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
+    0x79ac748e, 0x79aa80fb,
+  0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
+    0x799ccfc1, 0x799ad9d5,
+  0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
+    0x798d1832, 0x798b1fef,
+  0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
+    0x797d4de5, 0x797b534a,
+  0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
+    0x796d70dc, 0x796b73e9,
+  0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
+    0x795d8118, 0x795b81cf,
+  0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
+    0x794d7e9e, 0x794b7cfe,
+  0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
+    0x793d696f, 0x793b6578,
+  0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
+    0x792d418d, 0x792b3b40,
+  0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
+    0x791d06fb, 0x791afe59,
+  0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
+    0x790cb9bd, 0x790aaec5,
+  0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
+    0x78fc59d3, 0x78fa4c86,
+  0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
+    0x78ebe741, 0x78e9d79f,
+  0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
+    0x78db6209, 0x78d95012,
+  0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
+    0x78caca2e, 0x78c8b5e3,
+  0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
+    0x78ba1fb2, 0x78b80913,
+  0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
+    0x78a96298, 0x78a749a6,
+  0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
+    0x789892e3, 0x7896779d,
+  0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
+    0x7887b094, 0x788592fc,
+  0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
+    0x7876bbb0, 0x78749bc5,
+  0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
+    0x7865b437, 0x786391fa,
+  0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
+    0x78549a2e, 0x7852759e,
+  0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
+    0x78436d96, 0x784146b5,
+  0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
+    0x78322e72, 0x78300540,
+  0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
+    0x7820dcc5, 0x781eb142,
+  0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
+    0x780f7892, 0x780d4abe,
+  0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
+    0x77fe01db, 0x77fbd1b6,
+  0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
+    0x77ec78a2, 0x77ea462e,
+  0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
+    0x77dadcec, 0x77d8a828,
+  0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
+    0x77c92eb9, 0x77c6f7a6,
+  0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
+    0x77b76e0e, 0x77b534ac,
+  0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
+    0x77a59aec, 0x77a35f3c,
+  0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
+    0x7793b557, 0x77917759,
+  0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
+    0x7781bd52, 0x777f7d05,
+  0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
+    0x776fb2de, 0x776d7044,
+  0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
+    0x775d95ff, 0x775b5118,
+  0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
+    0x774b66b8, 0x77491f84,
+  0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
+    0x7739250b, 0x7736db8b,
+  0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
+    0x7726d0fc, 0x7724852f,
+  0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
+    0x77146a8c, 0x77121c74,
+  0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
+    0x7701f1c0, 0x76ffa15c,
+  0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
+    0x76ef6699, 0x76ed13ea,
+  0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
+    0x76dcc91b, 0x76da7421,
+  0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
+    0x76ca1948, 0x76c7c204,
+  0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
+    0x76b75724, 0x76b4fd96,
+  0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
+    0x76a482b1, 0x76a226da,
+  0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
+    0x76919bf3, 0x768f3dd2,
+  0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
+    0x767ea2eb, 0x767c4281,
+  0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
+    0x766b979d, 0x766934eb,
+  0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
+    0x76587a0d, 0x76561512,
+  0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
+    0x76454a3c, 0x7642e2f9,
+  0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
+    0x7632082e, 0x762f9ea4,
+  0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
+    0x761eb3e6, 0x761c4815,
+  0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
+    0x760b4d67, 0x7608df4f,
+  0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
+    0x75f7d4b3, 0x75f56455,
+  0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
+    0x75e449ce, 0x75e1d72b,
+  0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
+    0x75d0acbc, 0x75ce37d2,
+  0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
+    0x75bcfd7e, 0x75ba864f,
+  0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
+    0x75a93c18, 0x75a6c2a4,
+  0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
+    0x7595688c, 0x7592ecd4,
+  0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
+    0x758182df, 0x757f04e3,
+  0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
+    0x756d8b13, 0x756b0ad3,
+  0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
+    0x7559812b, 0x7556fea8,
+  0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
+    0x7545652a, 0x7542e065,
+  0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
+    0x75313714, 0x752eb00c,
+  0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
+    0x751cf6eb, 0x751a6da0,
+  0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
+    0x7508a4b2, 0x75061926,
+  0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
+    0x74f4406d, 0x74f1b2a0,
+  0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
+    0x74dfca20, 0x74dd3a11,
+  0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
+    0x74cb41cc, 0x74c8af7d,
+  0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
+    0x74b6a775, 0x74b412e6,
+  0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
+    0x74a1fb1e, 0x749f6450,
+  0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
+    0x748d3ccb, 0x748aa3be,
+  0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
+    0x74786c7f, 0x7475d132,
+  0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
+    0x74638a3d, 0x7460ecb2,
+  0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
+    0x744e9608, 0x744bf63e,
+  0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
+    0x74398fe3, 0x7436eddc,
+  0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
+    0x742477d2, 0x7421d38e,
+  0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
+    0x740f4dd8, 0x740ca756,
+  0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
+    0x73fa11f8, 0x73f7693a,
+  0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
+    0x73e4c435, 0x73e2193b,
+  0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
+    0x73cf6493, 0x73ccb75d,
+  0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
+    0x73b9f315, 0x73b743a4,
+  0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
+    0x73a46fbf, 0x73a1be13,
+  0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
+    0x738eda93, 0x738c26ac,
+  0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
+    0x73793395, 0x73767d74,
+  0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
+    0x73637ac8, 0x7360c26e,
+  0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
+    0x734db030, 0x734af59d,
+  0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
+    0x7337d3d0, 0x73351704,
+  0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
+    0x7321e5ab, 0x731f26a7,
+  0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
+    0x730be5c5, 0x73092489,
+  0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
+    0x72f5d421, 0x72f310ad,
+  0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
+    0x72dfb0c3, 0x72dceb18,
+  0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
+    0x72c97bad, 0x72c6b3cc,
+  0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
+    0x72b334e4, 0x72b06acd,
+  0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
+    0x729cdc6b, 0x729a101e,
+  0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
+    0x72867245, 0x7283a3c3,
+  0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
+    0x726ff676, 0x726d25bf,
+  0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
+    0x72596901, 0x72569615,
+  0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
+    0x7242c9ea, 0x723ff4ca,
+  0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
+    0x722c1934, 0x722941e0,
+  0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
+    0x721556e3, 0x72127d5c,
+  0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
+    0x71fe82f9, 0x71fba740,
+  0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
+    0x71e79d7c, 0x71e4bf90,
+  0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
+    0x71d0a66d, 0x71cdc650,
+  0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
+    0x71b99dd2, 0x71b6bb83,
+  0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
+    0x71a283ad, 0x719f9f2c,
+  0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
+    0x718b5801, 0x71887151,
+  0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
+    0x71741ad3, 0x717131f3,
+  0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
+    0x715ccc26, 0x7159e116,
+  0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
+    0x71456bfe, 0x71427ebf,
+  0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
+    0x712dfa5e, 0x712b0af0,
+  0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
+    0x7116774a, 0x711385ad,
+  0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
+    0x70fee2c5, 0x70fbeefb,
+  0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
+    0x70e73cd4, 0x70e446dc,
+  0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
+    0x70cf8579, 0x70cc8d54,
+  0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
+    0x70b7bcb8, 0x70b4c267,
+  0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
+    0x709fe296, 0x709ce619,
+  0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
+    0x7087f715, 0x7084f86d,
+  0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
+    0x706ffa3a, 0x706cf967,
+  0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
+    0x7057ec08, 0x7054e90a,
+  0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
+    0x703fcc83, 0x703cc75b,
+  0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
+    0x70279baf, 0x7024945d,
+  0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
+    0x700f598e, 0x700c5013,
+  0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
+    0x6ff70626, 0x6ff3fa82,
+  0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
+    0x6fdea17a, 0x6fdb93ae,
+  0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
+    0x6fc62b8d, 0x6fc31b99,
+  0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
+    0x6fada464, 0x6faa9248,
+  0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
+    0x6f950c01, 0x6f91f7bf,
+  0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
+    0x6f7c626a, 0x6f794c01,
+  0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
+    0x6f63a7a1, 0x6f608f13,
+  0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
+    0x6f4adbab, 0x6f47c0f7,
+  0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
+    0x6f31fe8b, 0x6f2ee1b2,
+  0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
+    0x6f191045, 0x6f15f148,
+  0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
+    0x6f0010de, 0x6efcefbd,
+  0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
+    0x6ee70058, 0x6ee3dd13,
+  0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
+    0x6ecddeb8, 0x6ecab950,
+  0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
+    0x6eb4ac02, 0x6eb18477,
+  0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
+    0x6e9b6839, 0x6e983e8d,
+  0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
+    0x6e821361, 0x6e7ee794,
+  0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
+    0x6e68ad7f, 0x6e657f90,
+  0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
+    0x6e4f3696, 0x6e4c0687,
+  0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
+    0x6e35aeab, 0x6e327c7b,
+  0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
+    0x6e1c15c0, 0x6e18e171,
+  0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
+    0x6e026bda, 0x6dff356c,
+  0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
+    0x6de8b0fe, 0x6de57871,
+  0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
+    0x6dcee52e, 0x6dcbaa83,
+  0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
+    0x6db5086f, 0x6db1cba7,
+  0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
+    0x6d9b1ac6, 0x6d97dbe0,
+  0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
+    0x6d811c35, 0x6d7ddb33,
+  0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
+    0x6d670cc1, 0x6d63c9a3,
+  0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
+    0x6d4cec6e, 0x6d49a734,
+  0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
+    0x6d32bb40, 0x6d2f73eb,
+  0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
+    0x6d18793b, 0x6d152fcc,
+  0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
+    0x6cfe2663, 0x6cfadada,
+  0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
+    0x6ce3c2bd, 0x6ce0751a,
+  0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
+    0x6cc94e4b, 0x6cc5fe8f,
+  0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
+    0x6caec913, 0x6cab773e,
+  0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
+    0x6c943318, 0x6c90df2c,
+  0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
+    0x6c798c5f, 0x6c76365b,
+  0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
+    0x6c5ed4eb, 0x6c5b7cd0,
+  0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
+    0x6c440cc1, 0x6c40b28f,
+  0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
+    0x6c2933e5, 0x6c25d79d,
+  0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
+    0x6c0e4a5b, 0x6c0aebfe,
+  0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
+    0x6bf35027, 0x6befefb5,
+  0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
+    0x6bd8454d, 0x6bd4e2c6,
+  0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
+    0x6bbd29d2, 0x6bb9c537,
+  0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
+    0x6ba1fdb9, 0x6b9e970b,
+  0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
+    0x6b86c107, 0x6b835846,
+  0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
+    0x6b6b73c0, 0x6b6808ed,
+  0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
+    0x6b5015e9, 0x6b4ca904,
+  0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
+    0x6b34a785, 0x6b31388e,
+  0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
+    0x6b192898, 0x6b15b791,
+  0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
+    0x6afd9928, 0x6afa2610,
+  0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
+    0x6ae1f937, 0x6ade8410,
+  0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
+    0x6ac648cb, 0x6ac2d195,
+  0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
+    0x6aaa87e8, 0x6aa70ea4,
+  0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
+    0x6a8eb692, 0x6a8b3b3f,
+  0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
+    0x6a72d4cd, 0x6a6f576d,
+  0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
+    0x6a56e29e, 0x6a536331,
+  0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
+    0x6a3ae008, 0x6a375e8f,
+  0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
+    0x6a1ecd11, 0x6a1b498c,
+  0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
+    0x6a02a9bc, 0x69ff242b,
+  0x69fb9e59, 0x69f81845, 0x69f491f0, 0x69f10b5a, 0x69ed8482, 0x69e9fd69,
+    0x69e6760f, 0x69e2ee73,
+  0x69df6696, 0x69dbde77, 0x69d85618, 0x69d4cd77, 0x69d14494, 0x69cdbb71,
+    0x69ca320c, 0x69c6a866,
+  0x69c31e7f, 0x69bf9456, 0x69bc09ec, 0x69b87f41, 0x69b4f455, 0x69b16928,
+    0x69adddb9, 0x69aa5209,
+  0x69a6c618, 0x69a339e6, 0x699fad73, 0x699c20be, 0x699893c9, 0x69950692,
+    0x6991791a, 0x698deb61,
+  0x698a5d67, 0x6986cf2c, 0x698340af, 0x697fb1f2, 0x697c22f3, 0x697893b4,
+    0x69750433, 0x69717472,
+  0x696de46f, 0x696a542b, 0x6966c3a6, 0x696332e1, 0x695fa1da, 0x695c1092,
+    0x69587f09, 0x6954ed40,
+  0x69515b35, 0x694dc8e9, 0x694a365c, 0x6946a38f, 0x69431080, 0x693f7d31,
+    0x693be9a0, 0x693855cf,
+  0x6934c1bd, 0x69312d6a, 0x692d98d6, 0x692a0401, 0x69266eeb, 0x6922d995,
+    0x691f43fd, 0x691bae25,
+  0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
+    0x69028e24, 0x68fef645,
+  0x68fb5e25, 0x68f7c5c5, 0x68f42d24, 0x68f09442, 0x68ecfb20, 0x68e961bd,
+    0x68e5c819, 0x68e22e34,
+  0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
+    0x68c8f1e0, 0x68c555f6,
+  0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
+    0x68ac0b7f, 0x68a86d91,
+  0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
+    0x688f14fa, 0x688b7507,
+  0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
+    0x68720e55, 0x686e6c5e,
+  0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
+    0x6854f795, 0x6851539b,
+  0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
+    0x6837d0bd, 0x68342ac1,
+  0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
+    0x681a99d4, 0x6816f1d6,
+  0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
+    0x67fd52dc, 0x67f9a8dd,
+  0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
+    0x67dffbdc, 0x67dc4fdb,
+  0x67d8a39a, 0x67d4f71a, 0x67d14a59, 0x67cd9d58, 0x67c9f017, 0x67c64297,
+    0x67c294d6, 0x67bee6d5,
+  0x67bb3894, 0x67b78a13, 0x67b3db53, 0x67b02c52, 0x67ac7d11, 0x67a8cd91,
+    0x67a51dd0, 0x67a16dcf,
+  0x679dbd8f, 0x679a0d0f, 0x67965c4e, 0x6792ab4e, 0x678efa0e, 0x678b488e,
+    0x678796ce, 0x6783e4cf,
+  0x6780328f, 0x677c8010, 0x6778cd50, 0x67751a51, 0x67716713, 0x676db394,
+    0x6769ffd5, 0x67664bd7,
+  0x67629799, 0x675ee31b, 0x675b2e5e, 0x67577960, 0x6753c423, 0x67500ea7,
+    0x674c58ea, 0x6748a2ee,
+  0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
+    0x672ea210, 0x672aea17,
+  0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
+    0x6710db4d, 0x670d2157,
+  0x67096721, 0x6705acab, 0x6701f1f6, 0x66fe3701, 0x66fa7bcd, 0x66f6c059,
+    0x66f304a6, 0x66ef48b3,
+  0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
+    0x66d51e1d, 0x66d1602f,
+  0x66cda201, 0x66c9e393, 0x66c624e7, 0x66c265fa, 0x66bea6cf, 0x66bae764,
+    0x66b727ba, 0x66b367d0,
+  0x66afa7a7, 0x66abe73f, 0x66a82697, 0x66a465b0, 0x66a0a489, 0x669ce324,
+    0x6699217f, 0x66955f9b,
+  0x66919d77, 0x668ddb14, 0x668a1872, 0x66865591, 0x66829270, 0x667ecf11,
+    0x667b0b72, 0x66774793,
+  0x66738376, 0x666fbf19, 0x666bfa7d, 0x666835a2, 0x66647088, 0x6660ab2f,
+    0x665ce596, 0x66591fbf,
+  0x665559a8, 0x66519352, 0x664dccbd, 0x664a05e9, 0x66463ed6, 0x66427784,
+    0x663eaff2, 0x663ae822,
+  0x66372012, 0x663357c4, 0x662f8f36, 0x662bc66a, 0x6627fd5e, 0x66243413,
+    0x66206a8a, 0x661ca0c1,
+  0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
+    0x66021561, 0x65fe49a1,
+  0x65fa7da2, 0x65f6b164, 0x65f2e4e7, 0x65ef182b, 0x65eb4b30, 0x65e77df6,
+    0x65e3b07e, 0x65dfe2c6,
+  0x65dc14d0, 0x65d8469b, 0x65d47827, 0x65d0a975, 0x65ccda83, 0x65c90b53,
+    0x65c53be4, 0x65c16c36,
+  0x65bd9c49, 0x65b9cc1e, 0x65b5fbb4, 0x65b22b0b, 0x65ae5a23, 0x65aa88fd,
+    0x65a6b798, 0x65a2e5f4,
+  0x659f1412, 0x659b41f1, 0x65976f91, 0x65939cf3, 0x658fca15, 0x658bf6fa,
+    0x6588239f, 0x65845006,
+  0x65807c2f, 0x657ca818, 0x6578d3c4, 0x6574ff30, 0x65712a5e, 0x656d554d,
+    0x65697ffe, 0x6565aa71,
+  0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
+    0x654accba, 0x6546f538,
+  0x65431d77, 0x653f4579, 0x653b6d3b, 0x653794c0, 0x6533bc06, 0x652fe30d,
+    0x652c09d6, 0x65283061,
+  0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
+    0x650d3759, 0x65095bf0,
+  0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
+    0x64ee5546, 0x64ea77eb,
+  0x64e69a52, 0x64e2bc7b, 0x64dede66, 0x64db0012, 0x64d72180, 0x64d342b0,
+    0x64cf63a2, 0x64cb8456,
+  0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
+    0x64b06273, 0x64ac8135,
+  0x64a89fba, 0x64a4be00, 0x64a0dc08, 0x649cf9d2, 0x6499175e, 0x649534ac,
+    0x649151bc, 0x648d6e8e,
+  0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
+    0x64723184, 0x646e4c66,
+  0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
+    0x645301cd, 0x644f1ac0,
+  0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
+    0x6433c29f, 0x642fd9a3,
+  0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
+    0x641473fc, 0x64108912,
+  0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
+    0x63f515eb, 0x63f12913,
+  0x63ed3bfd, 0x63e94eaa, 0x63e5611a, 0x63e1734b, 0x63dd853f, 0x63d996f6,
+    0x63d5a86f, 0x63d1b9aa,
+  0x63cdcaa8, 0x63c9db68, 0x63c5ebeb, 0x63c1fc30, 0x63be0c37, 0x63ba1c01,
+    0x63b62b8e, 0x63b23add,
+  0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
+    0x63969f4c, 0x6392acaf,
+  0x638eb9d5, 0x638ac6be, 0x6386d369, 0x6382dfd6, 0x637eec07, 0x637af7fa,
+    0x637703af, 0x63730f27,
+  0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
+    0x635758bb, 0x63536249,
+  0x634f6b99, 0x634b74ad, 0x63477d82, 0x6343861b, 0x633f8e76, 0x633b9695,
+    0x63379e76, 0x6333a619,
+  0x632fad80, 0x632bb4a9, 0x6327bb96, 0x6323c245, 0x631fc8b7, 0x631bceeb,
+    0x6317d4e3, 0x6313da9e,
+  0x630fe01b, 0x630be55b, 0x6307ea5e, 0x6303ef25, 0x62fff3ae, 0x62fbf7fa,
+    0x62f7fc08, 0x62f3ffda,
+  0x62f0036f, 0x62ec06c7, 0x62e809e2, 0x62e40cbf, 0x62e00f60, 0x62dc11c4,
+    0x62d813eb, 0x62d415d4,
+  0x62d01781, 0x62cc18f1, 0x62c81a24, 0x62c41b1a, 0x62c01bd3, 0x62bc1c4f,
+    0x62b81c8f, 0x62b41c91,
+  0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
+    0x629815fa, 0x62941415,
+  0x629011f4, 0x628c0f96, 0x62880cfb, 0x62840a23, 0x6280070f, 0x627c03be,
+    0x62780030, 0x6273fc65,
+  0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
+    0x6257db37, 0x6253d587,
+  0x624fcf9a, 0x624bc970, 0x6247c30a, 0x6243bc68, 0x623fb588, 0x623bae6c,
+    0x6237a714, 0x62339f7e,
+  0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
+    0x621763cb, 0x62135a51,
+  0x620f509b, 0x620b46a9, 0x62073c7a, 0x6203320e, 0x61ff2766, 0x61fb1c82,
+    0x61f71161, 0x61f30604,
+  0x61eefa6b, 0x61eaee95, 0x61e6e282, 0x61e2d633, 0x61dec9a8, 0x61dabce0,
+    0x61d6afdd, 0x61d2a29c,
+  0x61ce9520, 0x61ca8767, 0x61c67971, 0x61c26b40, 0x61be5cd2, 0x61ba4e28,
+    0x61b63f41, 0x61b2301e,
+  0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
+    0x6195bf94, 0x6191ae90,
+  0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
+    0x617530db, 0x61711df5,
+  0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
+    0x6154931a, 0x61507e54,
+  0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
+    0x6133e657, 0x612fcfb0,
+  0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
+    0x61132a96, 0x610f1210,
+  0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
+    0x60f25fdd, 0x60ee4579,
+  0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
+    0x60d18631, 0x60cd69ee,
+  0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
+    0x60b09d96, 0x60ac7f76,
+  0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
+    0x608fa612, 0x608b8616,
+  0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
+    0x606e9faa, 0x606a7dd2,
+  0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
+    0x604d8a63, 0x604966af,
+  0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
+    0x602c6643, 0x602840b4,
+  0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
+    0x600b334d, 0x60070be4,
+  0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
+    0x5fe9f188, 0x5fe5c845,
+  0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
+    0x5fc8a0f8, 0x5fc475dc,
+  0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
+    0x5fa741a3, 0x5fa314af,
+  0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
+    0x5f85d38e, 0x5f81a4c2,
+  0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
+    0x5f6456be, 0x5f60261b,
+  0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
+    0x5f42cb37, 0x5f3e98be,
+  0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
+    0x5f213100, 0x5f1cfcb1,
+  0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
+    0x5eff881d, 0x5efb51f9,
+  0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
+    0x5eddd094, 0x5ed9989c,
+  0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
+    0x5ebc0a6a, 0x5eb7d09e,
+  0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
+    0x5e9a35a4, 0x5e95fa05,
+  0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
+    0x5e785247, 0x5e7414d5,
+  0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
+    0x5e566059, 0x5e522115,
+  0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
+    0x5e345fde, 0x5e301ec9,
+  0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
+    0x5e1250dc, 0x5e0e0df7,
+  0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
+    0x5df03359, 0x5debeea3,
+  0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
+    0x5dce0759, 0x5dc9c0d4,
+  0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
+    0x5dabcce1, 0x5da7848e,
+  0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
+    0x5d8983f8, 0x5d8539d7,
+  0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
+    0x5d672ca2, 0x5d62e0b4,
+  0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
+    0x5d44c6e4, 0x5d40792a,
+  0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
+    0x5d2252c5, 0x5d1e033e,
+  0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
+    0x5cffd048, 0x5cfb7ef7,
+  0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
+    0x5cdd3f75, 0x5cd8ec58,
+  0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
+    0x5cbaa04f, 0x5cb64b68,
+  0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
+    0x5c97f2dc, 0x5c939c2c,
+  0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
+    0x5c753722, 0x5c70deaa,
+  0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
+    0x5c526d25, 0x5c4e12e5,
+  0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
+    0x5c2f94ec, 0x5c2b38e5,
+  0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
+    0x5c0cae7c, 0x5c0850ae,
+  0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
+    0x5be9b9da, 0x5be55a46,
+  0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
+    0x5bc6b70b, 0x5bc255b2,
+  0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
+    0x5ba3a615, 0x5b9f42f7,
+  0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
+    0x5b8086fd, 0x5b7c221c,
+  0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
+    0x5b5d59c9, 0x5b58f324,
+  0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
+    0x5b3a1e7e, 0x5b35b617,
+  0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
+    0x5b16d521, 0x5b126af8,
+  0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
+    0x5af37db8, 0x5aef11cf,
+  0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
+    0x5ad01849, 0x5acbaa9f,
+  0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
+    0x5aaca4d8, 0x5aa8356f,
+  0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
+    0x5a89236c, 0x5a84b243,
+  0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
+    0x5a65940a, 0x5a612123,
+  0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
+    0x5a41f6b7, 0x5a3d8212,
+  0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
+    0x5a1e4b79, 0x5a19d517,
+  0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
+    0x59fa9255, 0x59f61a36,
+  0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
+    0x59d6cb50, 0x59d25176,
+  0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
+    0x59b2f671, 0x59ae7add,
+  0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
+    0x598f13bd, 0x598a966e,
+  0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
+    0x596b233a, 0x5966a431,
+  0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
+    0x594724ec, 0x5942a42a,
+  0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
+    0x592318d9, 0x591e9660,
+  0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
+    0x58feff08, 0x58fa7ad7,
+  0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
+    0x58dad77d, 0x58d65195,
+  0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
+    0x58b6a23e, 0x58b21aa0,
+  0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
+    0x58925f52, 0x588dd5fe,
+  0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
+    0x586e0ebc, 0x586983b4,
+  0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
+    0x5849b083, 0x584523c7,
+  0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
+    0x582544ad, 0x5820b63e,
+  0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
+    0x5800cb3f, 0x57fc3b1d,
+  0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
+    0x57dc443f, 0x57d7b26b,
+  0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
+    0x57b7afb2, 0x57b31c2d,
+  0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
+    0x57930d9e, 0x578e7869,
+  0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
+    0x576e5e09, 0x5769c724,
+  0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
+    0x5749a0f9, 0x57450864,
+  0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
+    0x5724d672, 0x57203c2f,
+  0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
+    0x56fffe7b, 0x56fb628b,
+  0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
+    0x56db1919, 0x56d67b7c,
+  0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
+    0x56b62653, 0x56b18709,
+  0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
+    0x5691262d, 0x568c8538,
+  0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
+    0x566c18ae, 0x5667760e,
+  0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
+    0x5646fddb, 0x56425991,
+  0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
+    0x5621d5ba, 0x561d2fc6,
+  0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
+    0x55fca050, 0x55f7f8b4,
+  0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
+    0x55d75da4, 0x55d2b460,
+  0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
+    0x55b20dbb, 0x55ad62d0,
+  0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
+    0x558cb09b, 0x55880409,
+  0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
+    0x55674649, 0x55629812,
+  0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
+    0x5541cecc, 0x553d1ef0,
+  0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
+    0x551c4a29, 0x551798a8,
+  0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
+    0x54f6b866, 0x54f20542,
+  0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
+    0x54d11989, 0x54cc64c2,
+  0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
+    0x54ab6d97, 0x54a6b72e,
+  0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
+    0x5485b497, 0x5480fc8c,
+  0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
+    0x545fee8e, 0x545b34e3,
+  0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
+    0x543a1b82, 0x54356037,
+  0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
+    0x54143b79, 0x540f7e8e,
+  0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
+    0x53ee4e78, 0x53e98fef,
+  0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
+    0x53c85486, 0x53c3945f,
+  0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
+    0x53a24da9, 0x539d8be5,
+  0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
+    0x537c39e6, 0x53777685,
+  0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
+    0x53561942, 0x53515447,
+  0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
+    0x532febc5, 0x532b252f,
+  0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
+    0x5309b174, 0x5304e943,
+  0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
+    0x52e36a55, 0x52dea08a,
+  0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
+    0x52bd166d, 0x52b84b0a,
+  0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
+    0x5296b5c3, 0x5291e8c8,
+  0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
+    0x5270485c, 0x526b79ca,
+  0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
+    0x5249ce3f, 0x5244fe17,
+  0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
+    0x52234771, 0x521e75b3,
+  0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
+    0x51fcb3f9, 0x51f7e0a6,
+  0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
+    0x51d613dc, 0x51d13ef5,
+  0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
+    0x51af6720, 0x51aa90a5,
+  0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
+    0x5188adcb, 0x5183d5be,
+  0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
+    0x5161e7e4, 0x515d0e45,
+  0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
+    0x513b156f, 0x51363a3f,
+  0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
+    0x51143674, 0x510f59b3,
+  0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
+    0x50ed4af8, 0x50e86ca8,
+  0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
+    0x50c65301, 0x50c17322,
+  0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
+    0x509f4e95, 0x509a6d28,
+  0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
+    0x50783dba, 0x50735abf,
+  0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
+    0x50512077, 0x504c3bef,
+  0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
+    0x5029f6d1, 0x502510bd,
+  0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
+    0x5002c0cd, 0x4ffdd92f,
+  0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
+    0x4fdb7e74, 0x4fd6954b,
+  0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
+    0x4fb42fc9, 0x4faf4517,
+  0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
+    0x4f8cd4d4, 0x4f87e899,
+  0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
+    0x4f656d9b, 0x4f607fd7,
+  0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
+    0x4f3dfa23, 0x4f390ad8,
+  0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
+    0x4f167a73, 0x4f1189a1,
+  0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
+    0x4eeeee90, 0x4ee9fc39,
+  0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
+    0x4ec75682, 0x4ec262a5,
+  0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
+    0x4e9fb24d, 0x4e9abcec,
+  0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
+    0x4e7801f8, 0x4e730b14,
+  0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
+    0x4e50458a, 0x4e4b4d22,
+  0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
+    0x4e287d08, 0x4e23831e,
+  0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
+    0x4e00a878, 0x4dfbad0d,
+  0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
+    0x4dd8c7e1, 0x4dd3caf6,
+  0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
+    0x4db0db48, 0x4dabdcdd,
+  0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
+    0x4d88e2b5, 0x4d83e2cb,
+  0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
+    0x4d60de2c, 0x4d5bdcc4,
+  0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
+    0x4d38cdb5, 0x4d33cad0,
+  0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
+    0x4d10b155, 0x4d0bacf3,
+  0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
+    0x4ce88913, 0x4ce38335,
+  0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
+    0x4cc054f4, 0x4cbb4d9b,
+  0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
+    0x4c981500, 0x4c930c2d,
+  0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
+    0x4c6fc93b, 0x4c6abeef,
+  0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
+    0x4c4771ae, 0x4c4265e8,
+  0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
+    0x4c1f0e5c, 0x4c1a011f,
+  0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
+    0x4bf69f4e, 0x4bf19099,
+  0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
+    0x4bce2488, 0x4bc9145d,
+  0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
+    0x4ba59e12, 0x4ba08c72,
+  0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
+    0x4b7d0bf2, 0x4b77f8dc,
+  0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
+    0x4b546e2d, 0x4b4f59a4,
+  0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
+    0x4b2bc4cb, 0x4b26aece,
+  0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
+    0x4b030fd1, 0x4afdf861,
+  0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
+    0x4ada4f45, 0x4ad53664,
+  0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
+    0x4ab1832f, 0x4aac68dc,
+  0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
+    0x4a88ab93, 0x4a838fd1,
+  0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
+    0x4a5fc879, 0x4a5aab48,
+  0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
+    0x4a36d9e7, 0x4a31bb47,
+  0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
+    0x4a0ddfe4, 0x4a08bfd5,
+  0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
+    0x49e4da74, 0x49dfb8f9,
+  0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
+    0x49bbc9a0, 0x49b6a6b8,
+  0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
+    0x4992ad6c, 0x498d8919,
+  0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
+    0x496985e0, 0x49646023,
+  0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
+    0x49405302, 0x493b2bdb,
+  0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
+    0x491714d8, 0x4911ec47,
+  0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
+    0x48edcb68, 0x48e8a170,
+  0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
+    0x48c476b9, 0x48bf4b59,
+  0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
+    0x489b16d2, 0x4895ea0b,
+  0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
+    0x4871abb8, 0x486c7d8c,
+  0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
+    0x48483572, 0x484305e1,
+  0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
+    0x481eb407, 0x48198311,
+  0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
+    0x47f5277d, 0x47eff523,
+  0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
+    0x47cb8fd9, 0x47c65c1d,
+  0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
+    0x47a1ed24, 0x479cb806,
+  0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
+    0x47783f62, 0x477308e3,
+  0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
+    0x474e869b, 0x47494ebc,
+  0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
+    0x4724c2d5, 0x471f8996,
+  0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
+    0x46faf416, 0x46f5b979,
+  0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
+    0x46d11a65, 0x46cbde6a,
+  0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
+    0x46a735c8, 0x46a1f870,
+  0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
+    0x467d4646, 0x46780792,
+  0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
+    0x46534be5, 0x464e0bd6,
+  0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
+    0x462946ac, 0x46240542,
+  0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
+    0x45ff36a1, 0x45f9f3dd,
+  0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
+    0x45d51bcb, 0x45cfd7ae,
+  0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
+    0x45aaf630, 0x45a5b0bb,
+  0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
+    0x4580c5d6, 0x457b7f0a,
+  0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
+    0x45568ac4, 0x455142a2,
+  0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
+    0x452c4502, 0x4526fb89,
+  0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
+    0x4501f494, 0x44fca9c6,
+  0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
+    0x44d79982, 0x44d24d60,
+  0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
+    0x44ad33d2, 0x44a7e65d,
+  0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
+    0x4482c38b, 0x447d74c4,
+  0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
+    0x445848b3, 0x4452f89b,
+  0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
+    0x442dc351, 0x442871e8,
+  0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
+    0x4403336c, 0x43fde0b2,
+  0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
+    0x43d8990a, 0x43d34501,
+  0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
+    0x43adf431, 0x43a89ed9,
+  0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
+    0x438344e8, 0x437dee43,
+  0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
+    0x43588b36, 0x43533344,
+  0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
+    0x432dc721, 0x43286de4,
+  0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
+    0x4302f8b0, 0x42fd9e28,
+  0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
+    0x42d81fe9, 0x42d2c417,
+  0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
+    0x42ad3cd4, 0x42a7dfb8,
+  0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
+    0x42824f76, 0x427cf112,
+  0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
+    0x425757d7, 0x4251f82b,
+  0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
+    0x422c55fd, 0x4226f50a,
+  0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
+    0x420149ee, 0x41fbe7b5,
+  0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
+    0x41d633b1, 0x41d0d033,
+  0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
+    0x41ab134e, 0x41a5ae8b,
+  0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
+    0x417fe8ca, 0x417a82c3,
+  0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
+    0x4154b42c, 0x414f4ce2,
+  0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
+    0x4129757b, 0x41240cef,
+  0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
+    0x40fe2cbd, 0x40f8c2f1,
+  0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
+    0x40d2d9f9, 0x40cd6eed,
+  0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
+    0x40a77d37, 0x40a210eb,
+  0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
+    0x407c167c, 0x4076a8f1,
+  0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
+    0x4050a5cf, 0x404b3707,
+  0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
+    0x40252b37, 0x401fbb32,
+  0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
+    0x3ff9a6bb, 0x3ff4357a,
+  0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
+    0x3fce1861, 0x3fc8a5e5,
+  0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
+    0x3fa28031, 0x3f9d0c7a,
+  0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
+    0x3f76de30, 0x3f71693f,
+  0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
+    0x3f4b3265, 0x3f45bc3c,
+  0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
+    0x3f1f7cd8, 0x3f1a0577,
+  0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
+    0x3ef3bd8f, 0x3eee44f7,
+  0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
+    0x3ec7f491, 0x3ec27ac2,
+  0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
+    0x3e9c21e4, 0x3e96a6e0,
+  0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
+    0x3e70458f, 0x3e6ac957,
+  0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
+    0x3e445f99, 0x3e3ee22e,
+  0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
+    0x3e18700a, 0x3e12f16b,
+  0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
+    0x3dec76e6, 0x3de6f716,
+  0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
+    0x3dc07436, 0x3dbaf335,
+  0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
+    0x3d946801, 0x3d8ee5cf,
+  0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
+    0x3d68524c, 0x3d62ceeb,
+  0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
+    0x3d3c331f, 0x3d36ae8f,
+  0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
+    0x3d100a80, 0x3d0a84c3,
+  0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
+    0x3ce3d877, 0x3cde518d,
+  0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
+    0x3cb79d0a, 0x3cb214f4,
+  0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
+    0x3c8b5840, 0x3c85cefe,
+  0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
+    0x3c5f0a20, 0x3c597fb4,
+  0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
+    0x3c32b2b0, 0x3c2d271b,
+  0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
+    0x3c0651f8, 0x3c00c53a,
+  0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
+    0x3bd9e7fe, 0x3bd45a19,
+  0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
+    0x3bad74c9, 0x3ba7e5bd,
+  0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
+    0x3b80f861, 0x3b7b682e,
+  0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
+    0x3b5472cb, 0x3b4ee173,
+  0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
+    0x3b27e40f, 0x3b225193,
+  0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
+    0x3afb4c34, 0x3af5b894,
+  0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
+    0x3aceab40, 0x3ac9167e,
+  0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
+    0x3aa2013a, 0x3a9c6b57,
+  0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
+    0x3a754e2a, 0x3a6fb726,
+  0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
+    0x3a489216, 0x3a42f9f2,
+  0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
+    0x3a1bcd05, 0x3a1633c1,
+  0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
+    0x39eefefe, 0x39e9649c,
+  0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
+    0x39c22808, 0x39bc8c89,
+  0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
+    0x39954829, 0x398fab8e,
+  0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
+    0x39685f6a, 0x3962c1b2,
+  0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
+    0x393b6dd0, 0x3935cefd,
+  0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
+    0x390e7362, 0x3908d376,
+  0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
+    0x38e17028, 0x38dbcf23,
+  0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
+    0x38b46429, 0x38aec20b,
+  0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
+    0x38874f6b, 0x3881ac36,
+  0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
+    0x385a31f5, 0x38548daa,
+  0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
+    0x382d0bce, 0x3827666d,
+  0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
+    0x37ffdcfe, 0x37fa3688,
+  0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
+    0x37d2a58b, 0x37ccfe02,
+  0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
+    0x37a5657c, 0x379fbce0,
+  0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
+    0x37781cd9, 0x3772732a,
+  0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
+    0x374acba7, 0x374520e7,
+  0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
+    0x371d71ef, 0x3717c61f,
+  0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
+    0x36f00fb7, 0x36ea62d7,
+  0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
+    0x36c2a506, 0x36bcf718,
+  0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
+    0x369531e3, 0x368f82e7,
+  0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
+    0x3667b655, 0x3662064c,
+  0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
+    0x363a3264, 0x3634814f,
+  0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
+    0x360ca615, 0x3606f3f5,
+  0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
+    0x35df1171, 0x35d95e47,
+  0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
+    0x35b1747e, 0x35abc04b,
+  0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
+    0x3583cf44, 0x357e1a08,
+  0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
+    0x355621c9, 0x35506b85,
+  0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
+    0x35286c14, 0x3522b4c9,
+  0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
+    0x34faae2c, 0x34f4f5dc,
+  0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
+    0x34cce819, 0x34c72ec4,
+  0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
+    0x349f19e2, 0x34995f88,
+  0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
+    0x3471438d, 0x346b8830,
+  0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
+    0x34436521, 0x343da8c3,
+  0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
+    0x34157ea7, 0x340fc147,
+  0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
+    0x33e79024, 0x33e1d1c4,
+  0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
+    0x33b999a0, 0x33b3da40,
+  0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
+    0x338b9b22, 0x3385dac4,
+  0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
+    0x335d94b2, 0x3357d355,
+  0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
+    0x332f8655, 0x3329c3fb,
+  0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
+    0x33017014, 0x32fbacbe,
+  0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
+    0x32d351f5, 0x32cd8da4,
+  0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
+    0x32a52bff, 0x329f66b4,
+  0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
+    0x3276fe3a, 0x327137f6,
+  0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
+    0x3248c8ad, 0x32430170,
+  0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
+    0x321a8b5f, 0x3214c32a,
+  0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
+    0x31ec4657, 0x31e67d2b,
+  0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
+    0x31bdf99b, 0x31b82f7a,
+  0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
+    0x318fa535, 0x3189da1e,
+  0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
+    0x31614929, 0x315b7d1e,
+  0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
+    0x3132e580, 0x312d1882,
+  0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
+    0x31047a41, 0x30feac51,
+  0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
+    0x30d60772, 0x30d03891,
+  0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
+    0x30a78d1c, 0x30a1bd4a,
+  0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
+    0x30790b45, 0x30733a83,
+  0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
+    0x304a81f4, 0x3044b044,
+  0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
+    0x301bf131, 0x30161e93,
+  0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
+    0x2fed5902, 0x2fe78577,
+  0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
+    0x2fbeb970, 0x2fb8e4f9,
+  0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
+    0x2f901280, 0x2f8a3d1e,
+  0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
+    0x2f61643b, 0x2f5b8def,
+  0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
+    0x2f32aea8, 0x2f2cd772,
+  0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
+    0x2f03f1cd, 0x2efe19ae,
+  0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
+    0x2ed52db1, 0x2ecf54ac,
+  0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
+    0x2ea6625d, 0x2ea08871,
+  0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
+    0x2e778fd8, 0x2e71b506,
+  0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
+    0x2e48b628, 0x2e42da71,
+  0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
+    0x2e19d554, 0x2e13f8ba,
+  0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
+    0x2deaed65, 0x2de50fe8,
+  0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
+    0x2dbbfe61, 0x2db62001,
+  0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
+    0x2d8d084f, 0x2d87290f,
+  0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
+    0x2d5e0b38, 0x2d582b17,
+  0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
+    0x2d2f0721, 0x2d292620,
+  0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
+    0x2cfffc12, 0x2cfa1a33,
+  0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
+    0x2cd0ea13, 0x2ccb0756,
+  0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
+    0x2ca1d12a, 0x2c9bed91,
+  0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
+    0x2c72b160, 0x2c6ccceb,
+  0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
+    0x2c438abb, 0x2c3da56b,
+  0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
+    0x2c145d42, 0x2c0e7719,
+  0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
+    0x2be528fd, 0x2bdf41fb,
+  0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
+    0x2bb5edf4, 0x2bb00619,
+  0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
+    0x2b86ac2c, 0x2b80c37a,
+  0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
+    0x2b5763ae, 0x2b517a26,
+  0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
+    0x2b281482, 0x2b222a24,
+  0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
+    0x2af8bead, 0x2af2d37b,
+  0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
+    0x2ac96238, 0x2ac37633,
+  0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
+    0x2a99ff2a, 0x2a941252,
+  0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
+    0x2a6a958a, 0x2a64a7e0,
+  0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
+    0x2a3b2560, 0x2a3536e5,
+  0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
+    0x2a0baeb2, 0x2a05bf67,
+  0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
+    0x29dc3188, 0x29d6416f,
+  0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
+    0x29acadea, 0x29a6bd02,
+  0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
+    0x297d23df, 0x2977322a,
+  0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
+    0x294d936d, 0x2947a0ec,
+  0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
+    0x291dfc9d, 0x29180951,
+  0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
+    0x28ee5f76, 0x28e86b5f,
+  0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
+    0x28bebbff, 0x28b8c71f,
+  0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
+    0x288f123f, 0x28891c97,
+  0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
+    0x285f623f, 0x28596bce,
+  0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
+    0x282fac04, 0x2829b4cd,
+  0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
+    0x27ffef97, 0x27f9f79a,
+  0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
+    0x27d02cff, 0x27ca343d,
+  0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
+    0x27a06443, 0x279a6abd,
+  0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
+    0x2770956a, 0x276a9b21,
+  0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
+    0x2740c07d, 0x273ac572,
+  0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
+    0x2710e582, 0x270ae9b6,
+  0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
+    0x26e10480, 0x26db07f4,
+  0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
+    0x26b11d80, 0x26ab2034,
+  0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
+    0x26813088, 0x267b327e,
+  0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
+    0x26513da1, 0x264b3ed9,
+  0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
+    0x262144d0, 0x261b454c,
+  0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
+    0x25f1461e, 0x25eb45de,
+  0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
+    0x25c14192, 0x25bb4098,
+  0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
+    0x25913734, 0x258b3580,
+  0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
+    0x2561270b, 0x255b249e,
+  0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
+    0x2531111e, 0x252b0df9,
+  0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
+    0x2500f574, 0x24faf198,
+  0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
+    0x24d0d416, 0x24cacf84,
+  0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
+    0x24a0ad0b, 0x249aa7c4,
+  0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
+    0x24708059, 0x246a7a5e,
+  0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
+    0x24404e09, 0x243a475a,
+  0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
+    0x24101622, 0x240a0ec1,
+  0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
+    0x23dfd8ab, 0x23d9d098,
+  0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
+    0x23af95ac, 0x23a98ce8,
+  0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
+    0x237f4d2b, 0x237943b9,
+  0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
+    0x234eff32, 0x2348f511,
+  0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
+    0x231eabc7, 0x2318a0f8,
+  0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
+    0x22ee52f1, 0x22e84775,
+  0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
+    0x22bdf4b8, 0x22b7e890,
+  0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
+    0x228d9123, 0x22878451,
+  0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
+    0x225d283b, 0x22571abe,
+  0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
+    0x222cba06, 0x2226abe0,
+  0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
+    0x21fc468b, 0x21f637be,
+  0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
+    0x21cbcdd3, 0x21c5be5e,
+  0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
+    0x219b4fe5, 0x21953fca,
+  0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
+    0x216accc8, 0x2164bc08,
+  0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
+    0x213a4484, 0x2134331f,
+  0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
+    0x2109b720, 0x2103a518,
+  0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
+    0x20d924a4, 0x20d311f9,
+  0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
+    0x20a88d17, 0x20a279ca,
+  0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
+    0x2077f080, 0x2071dc93,
+  0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
+    0x20474ee8, 0x20413a5b,
+  0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
+    0x2016a856, 0x2010932a,
+  0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
+    0x1fe5fcd0, 0x1fdfe707,
+  0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
+    0x1fb54c60, 0x1faf35f9,
+  0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
+    0x1f84970b, 0x1f7e8009,
+  0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
+    0x1f53dcdb, 0x1f4dc53d,
+  0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
+    0x1f231dd5, 0x1f1d059e,
+  0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
+    0x1ef25a03, 0x1eec4132,
+  0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
+    0x1ec1916a, 0x1ebb7802,
+  0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
+    0x1e90c414, 0x1e8aaa14,
+  0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
+    0x1e5ff206, 0x1e59d770,
+  0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
+    0x1e2f1b4a, 0x1e29001e,
+  0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
+    0x1dfe3fe6, 0x1df82426,
+  0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
+    0x1dcd5fe2, 0x1dc7438e,
+  0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
+    0x1d9c7b45, 0x1d965e5f,
+  0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
+    0x1d6b9217, 0x1d6574a0,
+  0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
+    0x1d3aa460, 0x1d348658,
+  0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
+    0x1d09b227, 0x1d03938f,
+  0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
+    0x1cd8bb74, 0x1cd29c4d,
+  0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
+    0x1ca7c04d, 0x1ca1a099,
+  0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
+    0x1c76c0bc, 0x1c70a07b,
+  0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
+    0x1c45bcc7, 0x1c3f9bf9,
+  0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
+    0x1c14b475, 0x1c0e931d,
+  0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
+    0x1be3a7cf, 0x1bdd85ed,
+  0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
+    0x1bb296dc, 0x1bac7471,
+  0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
+    0x1b8181a4, 0x1b7b5eb0,
+  0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
+    0x1b50682e, 0x1b4a44b3,
+  0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
+    0x1b1f4a81, 0x1b192680,
+  0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
+    0x1aee28a6, 0x1ae8041f,
+  0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
+    0x1abd02a3, 0x1ab6dd98,
+  0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
+    0x1a8bd881, 0x1a85b2f3,
+  0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
+    0x1a5aaa47, 0x1a548436,
+  0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
+    0x1a2977fc, 0x1a23516a,
+  0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
+    0x19f841a9, 0x19f21a96,
+  0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
+    0x19c70754, 0x19c0dfc2,
+  0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
+    0x1995c906, 0x198fa0f5,
+  0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
+    0x196486c6, 0x195e5e37,
+  0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
+    0x1933409b, 0x192d178f,
+  0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
+    0x1901f68d, 0x18fbcd06,
+  0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
+    0x18d0a8a4, 0x18ca7ea2,
+  0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
+    0x189f56e8, 0x18992c6b,
+  0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
+    0x186e015f, 0x1867d66a,
+  0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
+    0x183ca812, 0x18367ca5,
+  0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
+    0x180b4b08, 0x18051f24,
+  0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
+    0x17d9ea49, 0x17d3bdee,
+  0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
+    0x17a885dc, 0x17a2590d,
+  0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
+    0x17771dc9, 0x1770f086,
+  0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
+    0x1745b218, 0x173f8461,
+  0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
+    0x171442d0, 0x170e14a7,
+  0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
+    0x16e2cff9, 0x16dca15f,
+  0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
+    0x16b1599b, 0x16ab2a90,
+  0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
+    0x167fdfbc, 0x1679b042,
+  0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
+    0x164e6266, 0x1648327d,
+  0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
+    0x161ce19e, 0x1616b148,
+  0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
+    0x15eb5d6e, 0x15e52cab,
+  0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
+    0x15b9d5dd, 0x15b3a4ae,
+  0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
+    0x15884af1, 0x15821958,
+  0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
+    0x1556bcb4, 0x15508ab1,
+  0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
+    0x15252b2c, 0x151ef8c0,
+  0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
+    0x14f39662, 0x14ed638e,
+  0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
+    0x14c1fe5c, 0x14bbcb22,
+  0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
+    0x14906323, 0x148a2f82,
+  0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
+    0x145ec4be, 0x145890b9,
+  0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
+    0x142d2335, 0x1426eecb,
+  0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
+    0x13fb7e8f, 0x13f549c3,
+  0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
+    0x13c9d6d4, 0x13c3a1a6,
+  0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
+    0x13982c0d, 0x1391f67d,
+  0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
+    0x13667e3f, 0x13604850,
+  0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
+    0x1334cd74, 0x132e9725,
+  0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
+    0x130319b3, 0x12fce305,
+  0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
+    0x12d16303, 0x12cb2bf8,
+  0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
+    0x129fa96c, 0x12997205,
+  0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
+    0x126decf5, 0x1267b533,
+  0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
+    0x123c2da8, 0x1235f58b,
+  0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
+    0x120a6b8a, 0x12043314,
+  0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
+    0x11d8a6a4, 0x11d26dd6,
+  0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
+    0x11a6defe, 0x11a0a5d8,
+  0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
+    0x1175149e, 0x116edb22,
+  0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
+    0x1143478e, 0x113d0dbc,
+  0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
+    0x111177d4, 0x110b3dad,
+  0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
+    0x10dfa578, 0x10d96afe,
+  0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
+    0x10add082, 0x10a795b5,
+  0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
+    0x107bf8fa, 0x1075bddb,
+  0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
+    0x104a1ee7, 0x1043e377,
+  0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
+    0x10184251, 0x10120691,
+  0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
+    0xfe6633f, 0xfe02730,
+  0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
+    0xfae455d,
+  0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
+    0xf7c611f,
+  0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
+    0xf4a7a7d,
+  0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
+    0xf189180,
+  0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
+    0xee6a62f,
+  0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
+    0xeb4b891,
+  0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
+    0xe82c8af,
+  0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
+    0xe50d690,
+  0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
+    0xe1ee23c,
+  0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
+    0xdecebba,
+  0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
+    0xdbaf313,
+  0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
+    0xd88f84d,
+  0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
+    0xd56fb71,
+  0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
+    0xd24fc87,
+  0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
+    0xcf2fb96,
+  0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
+    0xcc0f8a5,
+  0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
+    0xc8ef3bd,
+  0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
+    0xc5cece5,
+  0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
+    0xc2ae425,
+  0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
+    0xbf8d985,
+  0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
+    0xbc6cd0c,
+  0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
+    0xb94bec2,
+  0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
+    0xb62aeaf,
+  0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
+    0xb309cdb,
+  0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
+    0xafe894d,
+  0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
+    0xacc740c,
+  0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
+    0xa9a5d22,
+  0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
+    0xa684495,
+  0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
+    0xa362a6d,
+  0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
+    0xa040eb1,
+  0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
+    0x9d1f16b,
+  0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
+    0x99fd2a0,
+  0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
+    0x96db25a,
+  0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
+    0x93b90a0,
+  0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
+    0x9096d79,
+  0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
+    0x8d748ed,
+  0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
+    0x8a52304,
+  0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
+    0x872fbc6,
+  0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
+    0x840d33b,
+  0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
+    0x80ea969,
+  0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
+    0x7dc7e5a,
+  0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
+    0x7aa5214,
+  0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
+    0x77824a0,
+  0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
+    0x745f604,
+  0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
+    0x713c64a,
+  0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
+    0x6e19578,
+  0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
+    0x6af6396,
+  0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
+    0x67d30ad,
+  0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
+    0x64afcc3,
+  0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
+    0x618c7e1,
+  0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
+    0x5e6920e,
+  0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
+    0x5b45b53,
+  0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
+    0x58223b6,
+  0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
+    0x54feb3f,
+  0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
+    0x51db1f7,
+  0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
+    0x4eb77e5,
+  0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
+    0x4b93d11,
+  0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
+    0x4870182,
+  0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
+    0x454c541,
+  0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
+    0x4228854,
+  0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
+    0x3f04ac4,
+  0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
+    0x3be0c99,
+  0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
+    0x38bcdda,
+  0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
+    0x3598e8f,
+  0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
+    0x3274ec0,
+  0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
+    0x2f50e74,
+  0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
+    0x2c2cdb4,
+  0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
+    0x2908c87,
+  0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
+    0x25e4af4,
+  0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
+    0x22c0904,
+  0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
+    0x1f9c6be,
+  0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
+    0x1c7842a,
+  0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
+    0x1954150,
+  0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
+    0x162fe37,
+  0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
+    0x130bae7,
+  0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
+    0xfe7769,
+  0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
+    0xcc33c3,
+  0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
+    0x99effe,
+  0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
+    0x67ac21,
+  0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
+    0x356835,
+  0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
+
+};
+
+/**    
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.   
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.   
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure   
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure   
+ * @param[in]     N          length of the DCT4.   
+ * @param[in]     Nby2       half of the length of the DCT4.   
+ * @param[in]     normalize  normalizing factor.   
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
+ * \par Normalizing factor:    
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:    
+ * \image html dct4NormalizingQ31Table.gif    
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[4] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 8192u:
+    S->pTwiddle = twiddlePtr[3];
+    S->pCosFactor = pCosFactor[3];
+    break;
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 0000000000..feaa2ae3c0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_q15.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 Q15.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ *     
+ * \par Input an output formats:    
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
+ * Number of bits downscaled, depends on the size of the transform.    
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
+ *    
+ * \image html dct4FormatsQ15Table.gif    
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------    
+  *  Step3: Multiply the FFT output with the weights.    
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------    
+  *  Step3: Multiply the FFT output with the weights.    
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 0000000000..887cfb385d
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,387 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_dct4_q31.c    
+*    
+* Description:	Processing function of DCT4 & IDCT4 Q31.    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @addtogroup DCT4_IDCT4    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 DCT4/IDCT4.   
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.   
+ * @param[in]       *pState        points to state buffer.   
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
+ * @return none.   
+ * \par Input an output formats:    
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,    
+ * as the conversion from DCT2 to DCT4 involves one subtraction.    
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
+ * Number of bits downscaled, depends on the size of the transform.    
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
+ *    
+ * \image html dct4FormatsQ31Table.gif    
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
+   * along with some pre-processing and post-processing.    
+   * Computational procedure is explained as follows:    
+   * (a) Pre-processing involves multiplying input with cos factor,    
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
+   *              where,    
+   *                 r(n) -- output of preprocessing    
+   *                 u(n) -- input to preprocessing(actual Source buffer)    
+   * (b) Calculation of DCT2 using FFT is divided into three steps:    
+   *                  Step1: Re-ordering of even and odd elements of input.    
+   *                  Step2: Calculating FFT of the re-ordered input.    
+   *                  Step3: Taking the real part of the product of FFT output and weights.    
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *                        where,    
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------    
+   * Step1: Re-ordering of even and odd elements as    
+   *             pState[i] =  pInlineBuffer[2*i] and    
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------    
+   *  Step3: Multiply the FFT output with the weights.    
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  i = (S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------    
+   *     Step2: Calculate RFFT for N-point input    
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------    
+   *  Step3: Multiply the FFT output with the weights.    
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.    
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,    
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1u);
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**    
+   * @} end of DCT4_IDCT4 group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 0000000000..2043a4e0df
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,382 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_f32.c    
+*    
+* Description:	RFFT & RIFFT Floating point process function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @defgroup RFFT_RIFFT Real FFT Functions    
+ *    
+ * \par    
+ * Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain.     
+ * Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.    
+ *    
+ * \par    
+ * This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT)    
+ * for Q15, Q31, and floating-point data types.      
+ *    
+ *    
+ * \par Algorithm:    
+ *    
+ * Real Fast Fourier Transform:    
+ * \par    
+ * Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure.    
+ * \par    
+ * \image html RFFT.gif "Real Fast Fourier Transform"    
+ * \par    
+ * The RFFT functions operate on blocks of input and output data and each call to the function processes    
+ * fftLenR samples through the transform.  pSrc  points to input array containing fftLenR values.    
+ * pDst  points to output array containing 2*fftLenR values. \n   
+ * Input for real FFT is in the order of     
+ * 
{real[0], real[1], real[2], real[3], ..}
    
+ * Output for real FFT is complex and are in the order of    
+ * 
{real(0), imag(0), real(1), imag(1), ...}
     
+ *    
+ * Real Inverse Fast Fourier Transform:    
+ * \par    
+ * Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure.    
+ * \par    
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"    
+ * \par    
+ * The RIFFT functions operate on blocks of input and output data and each call to the function processes    
+ * 2*fftLenR samples through the transform.  pSrc  points to input array containing 2*fftLenR values.    
+ * pDst  points to output array containing fftLenR values. \n    
+ * Input for real IFFT is complex and are in the order of   
+ * 
{real(0), imag(0), real(1), imag(1), ...}
   
+ *  Output for real IFFT is real and in the order of     
+ * 
{real[0], real[1], real[2], real[3], ..}
   
+ *    
+ * \par Lengths supported by the transform:   
+ * \par    
+ * Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.    
+ *    
+ * \par Instance Structure    
+ * A separate instance structure must be defined for each Instance but the twiddle factors can be reused.    
+ * There are separate instance structure declarations for each of the 3 supported data types.    
+ *    
+ * \par Initialization Functions    
+ * There is also an associated initialization function for each data type.    
+ * The initialization function performs the following operations:    
+ * - Sets the values of the internal structure fields.    
+ * - Initializes twiddle factor tables.   
+ * - Initializes CFFT data structure fields.     
+ * \par    
+ * Use of the initialization function is optional.    
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.    
+ * Manually initialize the instance structure as follows:    
+ * 
    
+ *arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ * 
    
+ * where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT.     
+ * ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT);    
+ * bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order);     
+ * twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table;    
+ * pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients;    
+ * pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding    
+ * static initialization of cfft structure.    
+ *    
+ * \par Fixed-Point Behavior    
+ * Care must be taken when using the fixed-point versions of the RFFT/RIFFT function.    
+ * Refer to the function specific documentation below for usage guidelines.    
+ */
+
+/*--------------------------------------------------------------------    
+ *		Internal functions prototypes    
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the floating-point RFFT/RIFFT.   
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.   
+ * @param[in]  *pSrc points to the input buffer.   
+ * @param[out] *pDst points to the output buffer.   
+ * @return none.   
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**    
+   * @} end of RFFT_RIFFT group    
+   */
+
+/**    
+ * @brief  Core Real FFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  			length of FFT.    
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+ * @param[out]  *pDst 				points to the output buffer.    
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*    
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**    
+ * @brief  Core Real IFFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.    
+ * @return none.    
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*    
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 0000000000..7a54df6e21
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,8369 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_f32.c    
+*    
+* Description:	RFFT & RIFFT Floating point initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+/**    
+* \par    
+* Generation of realCoefA array:    
+* \par    
+* 	n = 4096    
+* 
for (i = 0; i < n; i++)    
+*  {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } 
    
+*/
+
+
+
+static const float32_t realCoefA[8192] = {
+  0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
+    -0.499999850988388f,
+  0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
+    -0.499998688697815f,
+  0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
+    -0.499996334314346f,
+  0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
+    -0.499992787837982f,
+  0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
+    -0.499988079071045f,
+  0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
+    -0.499982208013535f,
+  0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
+    -0.499975144863129f,
+  0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
+    -0.499966919422150f,
+  0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
+    -0.499957501888275f,
+  0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
+    -0.499946922063828f,
+  0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
+    -0.499935150146484f,
+  0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
+    -0.499922215938568f,
+  0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
+    -0.499908089637756f,
+  0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
+    -0.499892801046371f,
+  0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
+    -0.499876320362091f,
+  0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
+    -0.499858677387238f,
+  0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
+    -0.499839842319489f,
+  0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
+    -0.499819844961166f,
+  0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
+    -0.499798685312271f,
+  0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
+    -0.499776333570480f,
+  0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
+    -0.499752789735794f,
+  0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
+    -0.499728083610535f,
+  0.483129411935806f, -0.499715298414230f, 0.482746154069901f,
+    -0.499702215194702f,
+  0.482362866401672f, -0.499688833951950f, 0.481979638338089f,
+    -0.499675154685974f,
+  0.481596380472183f, -0.499661177396774f, 0.481213152408600f,
+    -0.499646931886673f,
+  0.480829954147339f, -0.499632388353348f, 0.480446726083755f,
+    -0.499617516994476f,
+  0.480063527822495f, -0.499602377414703f, 0.479680359363556f,
+    -0.499586939811707f,
+  0.479297190904617f, -0.499571204185486f, 0.478914022445679f,
+    -0.499555170536041f,
+  0.478530883789063f, -0.499538868665695f, 0.478147745132446f,
+    -0.499522238969803f,
+  0.477764606475830f, -0.499505341053009f, 0.477381497621536f,
+    -0.499488145112991f,
+  0.476998418569565f, -0.499470651149750f, 0.476615339517593f,
+    -0.499452859163284f,
+  0.476232260465622f, -0.499434769153595f, 0.475849211215973f,
+    -0.499416410923004f,
+  0.475466161966324f, -0.499397724866867f, 0.475083142518997f,
+    -0.499378770589828f,
+  0.474700123071671f, -0.499359518289566f, 0.474317133426666f,
+    -0.499339967966080f,
+  0.473934143781662f, -0.499320119619370f, 0.473551183938980f,
+    -0.499299973249435f,
+  0.473168224096298f, -0.499279528856277f, 0.472785294055939f,
+    -0.499258816242218f,
+  0.472402364015579f, -0.499237775802612f, 0.472019463777542f,
+    -0.499216467142105f,
+  0.471636593341827f, -0.499194860458374f, 0.471253722906113f,
+    -0.499172955751419f,
+  0.470870882272720f, -0.499150782823563f, 0.470488041639328f,
+    -0.499128282070160f,
+  0.470105201005936f, -0.499105513095856f, 0.469722419977188f,
+    -0.499082416296005f,
+  0.469339638948441f, -0.499059051275253f, 0.468956857919693f,
+    -0.499035388231277f,
+  0.468574106693268f, -0.499011427164078f, 0.468191385269165f,
+    -0.498987197875977f,
+  0.467808693647385f, -0.498962640762329f, 0.467426002025604f,
+    -0.498937815427780f,
+  0.467043310403824f, -0.498912662267685f, 0.466660678386688f,
+    -0.498887240886688f,
+  0.466278046369553f, -0.498861521482468f, 0.465895414352417f,
+    -0.498835533857346f,
+  0.465512841939926f, -0.498809218406677f, 0.465130269527435f,
+    -0.498782604932785f,
+  0.464747726917267f, -0.498755723237991f, 0.464365184307098f,
+    -0.498728543519974f,
+  0.463982671499252f, -0.498701065778732f, 0.463600188493729f,
+    -0.498673290014267f,
+  0.463217705488205f, -0.498645216226578f, 0.462835282087326f,
+    -0.498616874217987f,
+  0.462452858686447f, -0.498588204383850f, 0.462070435285568f,
+    -0.498559266328812f,
+  0.461688071489334f, -0.498530030250549f, 0.461305707693100f,
+    -0.498500496149063f,
+  0.460923373699188f, -0.498470664024353f, 0.460541069507599f,
+    -0.498440563678741f,
+  0.460158795118332f, -0.498410135507584f, 0.459776520729065f,
+    -0.498379439115524f,
+  0.459394276142120f, -0.498348444700241f, 0.459012061357498f,
+    -0.498317152261734f,
+  0.458629876375198f, -0.498285561800003f, 0.458247691392899f,
+    -0.498253703117371f,
+  0.457865566015244f, -0.498221516609192f, 0.457483440637589f,
+    -0.498189061880112f,
+  0.457101345062256f, -0.498156309127808f, 0.456719279289246f,
+    -0.498123258352280f,
+  0.456337243318558f, -0.498089909553528f, 0.455955207347870f,
+    -0.498056292533875f,
+  0.455573230981827f, -0.498022347688675f, 0.455191254615784f,
+    -0.497988134622574f,
+  0.454809308052063f, -0.497953623533249f, 0.454427421092987f,
+    -0.497918814420700f,
+  0.454045534133911f, -0.497883707284927f, 0.453663676977158f,
+    -0.497848302125931f,
+  0.453281819820404f, -0.497812628746033f, 0.452900022268295f,
+    -0.497776657342911f,
+  0.452518254518509f, -0.497740387916565f, 0.452136516571045f,
+    -0.497703820466995f,
+  0.451754778623581f, -0.497666954994202f, 0.451373100280762f,
+    -0.497629791498184f,
+  0.450991421937943f, -0.497592359781265f, 0.450609803199768f,
+    -0.497554630041122f,
+  0.450228184461594f, -0.497516602277756f, 0.449846625328064f,
+    -0.497478276491165f,
+  0.449465066194534f, -0.497439652681351f, 0.449083566665649f,
+    -0.497400760650635f,
+  0.448702067136765f, -0.497361570596695f, 0.448320597410202f,
+    -0.497322082519531f,
+  0.447939187288284f, -0.497282296419144f, 0.447557777166367f,
+    -0.497242212295532f,
+  0.447176426649094f, -0.497201830148697f, 0.446795076131821f,
+    -0.497161179780960f,
+  0.446413785219193f, -0.497120231389999f, 0.446032524108887f,
+    -0.497078984975815f,
+  0.445651292800903f, -0.497037440538406f, 0.445270061492920f,
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+  0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
+    0.499128282070160f,
+  0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
+    0.499172955751419f,
+  0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
+    0.499216467142105f,
+  0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
+    0.499258816242218f,
+  0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
+    0.499299973249435f,
+  0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
+    0.499339967966080f,
+  0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
+    0.499378770589828f,
+  0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
+    0.499416410923004f,
+  0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
+    0.499452859163284f,
+  0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
+    0.499488145112991f,
+  0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
+    0.499522238969803f,
+  0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
+    0.499555170536041f,
+  0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
+    0.499586939811707f,
+  0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
+    0.499617516994476f,
+  0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
+    0.499646931886673f,
+  0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
+    0.499675154685974f,
+  0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
+    0.499702215194702f,
+  0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
+    0.499728083610535f,
+  0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
+    0.499752789735794f,
+  0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
+    0.499776333570480f,
+  0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
+    0.499798685312271f,
+  0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
+    0.499819844961166f,
+  0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
+    0.499839842319489f,
+  0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
+    0.499858677387238f,
+  0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
+    0.499876320362091f,
+  0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
+    0.499892801046371f,
+  0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
+    0.499908089637756f,
+  0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
+    0.499922215938568f,
+  0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
+    0.499935150146484f,
+  0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
+    0.499946922063828f,
+  0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
+    0.499957501888275f,
+  0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
+    0.499966919422150f,
+  0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
+    0.499975144863129f,
+  0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
+    0.499982208013535f,
+  0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
+    0.499988079071045f,
+  0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
+    0.499992787837982f,
+  0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
+    0.499996334314346f,
+  0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
+    0.499998688697815f,
+  0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
+    0.499999850988388f,
+};
+
+
+/**    
+* \par   
+* Generation of realCoefB array:    
+* \par   
+* n = 4096    
+* 
for (i = 0; i < n; i++)    
+* {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } 
    
+*    
+*/
+static const float32_t realCoefB[8192] = {
+  0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
+    0.499999850988388f,
+  0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
+    0.499998688697815f,
+  0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
+    0.499996334314346f,
+  0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
+    0.499992787837982f,
+  0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
+    0.499988079071045f,
+  0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
+    0.499982208013535f,
+  0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
+    0.499975144863129f,
+  0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
+    0.499966919422150f,
+  0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
+    0.499957501888275f,
+  0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
+    0.499946922063828f,
+  0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
+    0.499935150146484f,
+  0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
+    0.499922215938568f,
+  0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
+    0.499908089637756f,
+  0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
+    0.499892801046371f,
+  0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
+    0.499876320362091f,
+  0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
+    0.499858677387238f,
+  0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
+    0.499839842319489f,
+  0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
+    0.499819844961166f,
+  0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
+    0.499798685312271f,
+  0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
+    0.499776333570480f,
+  0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
+    0.499752789735794f,
+  0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
+    0.499728083610535f,
+  0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
+    0.499702215194702f,
+  0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
+    0.499675154685974f,
+  0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
+    0.499646931886673f,
+  0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
+    0.499617516994476f,
+  0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
+    0.499586939811707f,
+  0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
+    0.499555170536041f,
+  0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
+    0.499522238969803f,
+  0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
+    0.499488145112991f,
+  0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
+    0.499452859163284f,
+  0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
+    0.499416410923004f,
+  0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
+    0.499378770589828f,
+  0.525299847126007f, 0.499359518289566f, 0.525682866573334f,
+    0.499339967966080f,
+  0.526065826416016f, 0.499320119619370f, 0.526448845863342f,
+    0.499299973249435f,
+  0.526831746101379f, 0.499279528856277f, 0.527214705944061f,
+    0.499258816242218f,
+  0.527597606182098f, 0.499237775802612f, 0.527980506420136f,
+    0.499216467142105f,
+  0.528363406658173f, 0.499194860458374f, 0.528746306896210f,
+    0.499172955751419f,
+  0.529129147529602f, 0.499150782823563f, 0.529511988162994f,
+    0.499128282070160f,
+  0.529894769191742f, 0.499105513095856f, 0.530277609825134f,
+    0.499082416296005f,
+  0.530660390853882f, 0.499059051275253f, 0.531043112277985f,
+    0.499035388231277f,
+  0.531425893306732f, 0.499011427164078f, 0.531808614730835f,
+    0.498987197875977f,
+  0.532191336154938f, 0.498962640762329f, 0.532573997974396f,
+    0.498937815427780f,
+  0.532956659793854f, 0.498912662267685f, 0.533339321613312f,
+    0.498887240886688f,
+  0.533721983432770f, 0.498861521482468f, 0.534104585647583f,
+    0.498835533857346f,
+  0.534487187862396f, 0.498809218406677f, 0.534869730472565f,
+    0.498782604932785f,
+  0.535252273082733f, 0.498755723237991f, 0.535634815692902f,
+    0.498728543519974f,
+  0.536017298698425f, 0.498701065778732f, 0.536399841308594f,
+    0.498673290014267f,
+  0.536782264709473f, 0.498645216226578f, 0.537164747714996f,
+    0.498616874217987f,
+  0.537547171115875f, 0.498588204383850f, 0.537929534912109f,
+    0.498559266328812f,
+  0.538311958312988f, 0.498530030250549f, 0.538694262504578f,
+    0.498500496149063f,
+  0.539076626300812f, 0.498470664024353f, 0.539458930492401f,
+    0.498440563678741f,
+  0.539841234683990f, 0.498410135507584f, 0.540223479270935f,
+    0.498379439115524f,
+  0.540605723857880f, 0.498348444700241f, 0.540987968444824f,
+    0.498317152261734f,
+  0.541370153427124f, 0.498285561800003f, 0.541752278804779f,
+    0.498253703117371f,
+  0.542134463787079f, 0.498221516609192f, 0.542516589164734f,
+    0.498189061880112f,
+  0.542898654937744f, 0.498156309127808f, 0.543280720710754f,
+    0.498123258352280f,
+  0.543662786483765f, 0.498089909553528f, 0.544044792652130f,
+    0.498056292533875f,
+  0.544426798820496f, 0.498022347688675f, 0.544808745384216f,
+    0.497988134622574f,
+  0.545190691947937f, 0.497953623533249f, 0.545572578907013f,
+    0.497918814420700f,
+  0.545954465866089f, 0.497883707284927f, 0.546336352825165f,
+    0.497848302125931f,
+  0.546718180179596f, 0.497812628746033f, 0.547099947929382f,
+    0.497776657342911f,
+  0.547481775283813f, 0.497740387916565f, 0.547863483428955f,
+    0.497703820466995f,
+  0.548245191574097f, 0.497666954994202f, 0.548626899719238f,
+    0.497629791498184f,
+  0.549008548259735f, 0.497592359781265f, 0.549390196800232f,
+    0.497554630041122f,
+  0.549771785736084f, 0.497516602277756f, 0.550153374671936f,
+    0.497478276491165f,
+  0.550534904003143f, 0.497439652681351f, 0.550916433334351f,
+    0.497400760650635f,
+  0.551297962665558f, 0.497361570596695f, 0.551679372787476f,
+    0.497322082519531f,
+  0.552060842514038f, 0.497282296419144f, 0.552442193031311f,
+    0.497242212295532f,
+  0.552823603153229f, 0.497201830148697f, 0.553204894065857f,
+    0.497161179780960f,
+  0.553586184978485f, 0.497120231389999f, 0.553967475891113f,
+    0.497078984975815f,
+  0.554348707199097f, 0.497037440538406f, 0.554729938507080f,
+    0.496995598077774f,
+  0.555111110210419f, 0.496953487396240f, 0.555492222309113f,
+    0.496911078691483f,
+  0.555873334407806f, 0.496868371963501f, 0.556254446506500f,
+    0.496825367212296f,
+  0.556635499000549f, 0.496782064437866f, 0.557016491889954f,
+    0.496738493442535f,
+  0.557397484779358f, 0.496694594621658f, 0.557778418064117f,
+    0.496650427579880f,
+  0.558159291744232f, 0.496605962514877f, 0.558540165424347f,
+    0.496561229228973f,
+  0.558921039104462f, 0.496516168117523f, 0.559301853179932f,
+    0.496470838785172f,
+  0.559682607650757f, 0.496425211429596f, 0.560063362121582f,
+    0.496379286050797f,
+  0.560444056987762f, 0.496333062648773f, 0.560824692249298f,
+    0.496286571025848f,
+  0.561205327510834f, 0.496239781379700f, 0.561585903167725f,
+    0.496192663908005f,
+  0.561966478824615f, 0.496145308017731f, 0.562346994876862f,
+    0.496097624301910f,
+  0.562727510929108f, 0.496049642562866f, 0.563107967376709f,
+    0.496001392602921f,
+  0.563488364219666f, 0.495952844619751f, 0.563868701457977f,
+    0.495903998613358f,
+  0.564249038696289f, 0.495854884386063f, 0.564629375934601f,
+    0.495805442333221f,
+  0.565009593963623f, 0.495755732059479f, 0.565389811992645f,
+    0.495705723762512f,
+  0.565770030021667f, 0.495655417442322f, 0.566150128841400f,
+    0.495604842901230f,
+  0.566530287265778f, 0.495553970336914f, 0.566910326480865f,
+    0.495502769947052f,
+  0.567290365695953f, 0.495451331138611f, 0.567670345306396f,
+    0.495399564504623f,
+  0.568050265312195f, 0.495347499847412f, 0.568430185317993f,
+    0.495295166969299f,
+  0.568810045719147f, 0.495242536067963f, 0.569189906120300f,
+    0.495189607143402f,
+  0.569569647312164f, 0.495136409997940f, 0.569949388504028f,
+    0.495082914829254f,
+  0.570329129695892f, 0.495029091835022f, 0.570708811283112f,
+    0.494975030422211f,
+  0.571088373661041f, 0.494920641183853f, 0.571467995643616f,
+    0.494865983724594f,
+  0.571847498416901f, 0.494810998439789f, 0.572227001190186f,
+    0.494755744934082f,
+  0.572606444358826f, 0.494700223207474f, 0.572985887527466f,
+    0.494644373655319f,
+  0.573365211486816f, 0.494588255882263f, 0.573744535446167f,
+    0.494531840085983f,
+  0.574123859405518f, 0.494475126266479f, 0.574503064155579f,
+    0.494418144226074f,
+  0.574882268905640f, 0.494360834360123f, 0.575261414051056f,
+    0.494303256273270f,
+  0.575640499591827f, 0.494245409965515f, 0.576019585132599f,
+    0.494187235832214f,
+  0.576398611068726f, 0.494128793478012f, 0.576777577400208f,
+    0.494070053100586f,
+  0.577156484127045f, 0.494011014699936f, 0.577535390853882f,
+    0.493951678276062f,
+  0.577914178371429f, 0.493892073631287f, 0.578292965888977f,
+    0.493832170963287f,
+  0.578671753406525f, 0.493771970272064f, 0.579050421714783f,
+    0.493711471557617f,
+  0.579429090023041f, 0.493650704622269f, 0.579807698726654f,
+    0.493589639663696f,
+  0.580186247825623f, 0.493528276681900f, 0.580564737319946f,
+    0.493466645479202f,
+  0.580943167209625f, 0.493404686450958f, 0.581321597099304f,
+    0.493342459201813f,
+  0.581699967384338f, 0.493279963731766f, 0.582078278064728f,
+    0.493217140436172f,
+  0.582456588745117f, 0.493154048919678f, 0.582834780216217f,
+    0.493090659379959f,
+  0.583212971687317f, 0.493026971817017f, 0.583591103553772f,
+    0.492963016033173f,
+  0.583969175815582f, 0.492898762226105f, 0.584347188472748f,
+    0.492834210395813f,
+  0.584725141525269f, 0.492769360542297f, 0.585103094577789f,
+    0.492704242467880f,
+  0.585480928421021f, 0.492638826370239f, 0.585858762264252f,
+    0.492573112249374f,
+  0.586236536502838f, 0.492507129907608f, 0.586614251136780f,
+    0.492440819740295f,
+  0.586991965770721f, 0.492374241352081f, 0.587369561195374f,
+    0.492307394742966f,
+  0.587747097015381f, 0.492240220308304f, 0.588124632835388f,
+    0.492172777652740f,
+  0.588502109050751f, 0.492105036973953f, 0.588879525661469f,
+    0.492037028074265f,
+  0.589256882667542f, 0.491968721151352f, 0.589634180068970f,
+    0.491900116205215f,
+  0.590011477470398f, 0.491831213235855f, 0.590388655662537f,
+    0.491762012243271f,
+  0.590765833854675f, 0.491692543029785f, 0.591142892837524f,
+    0.491622805595398f,
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+  0.506902694702148f, -0.499952346086502f, 0.506519258022308f,
+    -0.499957501888275f,
+  0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
+    -0.499966919422150f,
+  0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
+    -0.499975144863129f,
+  0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
+    -0.499982208013535f,
+  0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
+    -0.499988079071045f,
+  0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
+    -0.499992787837982f,
+  0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
+    -0.499996334314346f,
+  0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
+    -0.499998688697815f,
+  0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
+    -0.499999850988388f,
+};
+
+
+
+/**    
+* @brief  Initialization function for the floating-point RFFT/RIFFT.   
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.   
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.   
+* @param[in]     fftLenReal     length of the FFT.   
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
+* \par    
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    
+* This function also initializes Twiddle factor table.     
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 8192u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 2048u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 16u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 64u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**    
+   * @} end of RFFT_RIFFT group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 0000000000..50b9d994d0
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2229 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_q15.c    
+*    
+* Description:	RFFT & RIFFT Q15 initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+
+
+/**    
+* \par    
+* Generation floating point real_CoefA array:    
+* \par    
+* n = 4096    
+* 
for (i = 0; i < n; i++)    
+*  {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } 
    
+* \par    
+* Convert to fixed point Q15 format    
+*       round(pATable[i] * pow(2, 15))    
+*/
+
+
+static const q15_t ALIGN4 realCoefAQ15[8192] = {
+  0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
+  0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
+  0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
+  0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
+  0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
+  0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
+  0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
+  0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
+  0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
+  0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
+  0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
+  0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
+  0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
+  0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
+  0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
+  0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
+  0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
+  0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
+  0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
+  0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
+  0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
+  0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
+  0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
+  0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
+  0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
+  0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
+  0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
+  0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
+  0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
+  0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
+  0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
+  0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
+  0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
+  0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
+  0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
+  0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
+  0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
+  0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
+  0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
+  0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
+  0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
+  0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
+  0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
+  0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
+  0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
+  0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
+  0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
+  0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
+  0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
+  0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
+  0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
+  0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
+  0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
+  0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
+  0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
+  0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
+  0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
+  0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
+  0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
+  0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
+  0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
+  0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
+  0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
+  0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
+  0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
+  0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
+  0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
+  0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
+  0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
+  0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
+  0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
+  0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
+  0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
+  0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
+  0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
+  0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
+  0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
+  0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
+  0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
+  0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
+  0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
+  0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
+  0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
+  0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
+  0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
+  0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
+  0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
+  0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
+  0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
+  0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
+  0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
+  0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
+  0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
+  0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
+  0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
+  0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
+  0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
+  0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
+  0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
+  0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
+  0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
+  0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
+  0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
+  0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
+  0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
+  0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
+  0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
+  0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
+  0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
+  0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
+  0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
+  0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
+  0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
+  0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
+  0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
+  0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
+  0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
+  0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
+  0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
+  0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
+  0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
+  0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
+  0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
+  0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
+  0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
+  0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
+  0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
+  0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
+  0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
+  0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
+  0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
+  0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
+  0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
+  0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
+  0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
+  0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
+  0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
+  0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
+  0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
+  0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
+  0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
+  0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
+  0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
+  0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
+  0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
+  0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
+  0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
+  0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
+  0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
+  0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
+  0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
+  0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
+  0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
+  0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
+  0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
+  0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
+  0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
+  0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
+  0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
+  0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
+  0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
+  0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
+  0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
+  0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
+  0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
+  0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
+  0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
+  0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
+  0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
+  0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
+  0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
+  0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
+  0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
+  0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
+  0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
+  0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
+  0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
+  0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
+  0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
+  0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
+  0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
+  0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
+  0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
+  0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
+  0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
+  0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
+  0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
+  0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
+  0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
+  0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
+  0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
+  0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
+  0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
+  0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
+  0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
+  0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
+  0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
+  0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
+  0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
+  0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
+  0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
+  0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
+  0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
+  0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
+  0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
+  0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
+  0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
+  0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
+  0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
+  0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
+  0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
+  0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
+  0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
+  0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
+  0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
+  0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
+  0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
+  0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
+  0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
+  0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
+  0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
+  0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
+  0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
+  0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
+  0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
+  0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
+  0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
+  0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
+  0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
+  0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
+  0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
+  0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
+  0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
+  0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
+  0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
+  0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
+  0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
+  0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
+  0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
+  0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
+  0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
+  0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
+  0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
+  0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
+  0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
+  0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
+  0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
+  0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
+  0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
+  0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
+  0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
+  0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
+  0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
+  0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
+  0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
+  0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
+  0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
+  0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
+  0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
+  0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
+  0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
+  0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
+  0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
+  0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
+  0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
+  0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
+  0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
+  0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
+  0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
+  0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
+  0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
+  0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
+  0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
+  0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
+  0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
+  0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
+  0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
+  0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
+  0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
+  0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
+  0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
+  0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
+  0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
+  0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
+  0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
+  0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
+  0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
+  0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
+  0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
+  0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
+  0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
+  0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
+  0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
+  0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
+  0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
+  0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
+  0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
+  0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
+  0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
+  0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
+  0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
+  0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
+  0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
+  0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
+  0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
+  0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
+  0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
+  0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
+  0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
+  0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
+  0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
+  0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
+  0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
+  0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
+  0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
+  0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
+  0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
+  0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
+  0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
+  0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
+  0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
+  0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
+  0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
+  0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
+  0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
+  0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
+  0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
+  0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
+  0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
+  0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
+  0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
+  0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
+  0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
+  0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
+  0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
+  0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
+  0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
+  0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
+  0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
+  0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
+  0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
+  0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
+  0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
+  0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
+  0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
+  0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
+  0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
+  0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
+  0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
+  0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
+  0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
+  0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
+  0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
+  0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
+  0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
+  0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
+  0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
+  0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
+  0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
+  0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
+  0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
+  0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
+  0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
+  0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
+  0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
+  0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
+  0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
+  0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
+  0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
+  0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
+  0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
+  0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
+  0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
+  0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
+  0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
+  0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
+  0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
+  0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
+  0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
+  0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
+  0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
+  0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
+  0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
+  0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
+  0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
+  0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
+  0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
+  0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
+  0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
+  0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
+  0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
+  0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
+  0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
+  0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
+  0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
+  0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
+  0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
+  0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
+  0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
+  0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
+  0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
+  0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
+  0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
+  0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
+  0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
+  0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
+  0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
+  0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
+  0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
+  0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
+  0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
+  0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
+  0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
+  0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
+  0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
+  0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
+  0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
+  0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
+  0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
+  0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
+  0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
+  0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
+  0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
+  0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
+  0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
+  0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
+  0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
+  0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
+  0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
+  0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
+  0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
+  0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
+  0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
+  0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
+  0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
+  0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
+  0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
+  0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
+  0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
+  0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
+  0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
+  0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
+  0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
+  0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
+  0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
+  0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
+  0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
+  0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
+  0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
+  0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
+  0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
+  0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
+  0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
+  0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
+  0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
+  0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
+  0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
+  0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
+  0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
+  0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
+  0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
+  0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
+  0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
+  0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
+  0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
+  0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
+  0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
+  0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
+  0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
+  0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
+  0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
+  0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
+  0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
+  0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
+  0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
+  0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
+  0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
+  0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
+  0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
+  0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
+  0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
+  0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
+  0x45, 0xfa1e, 0x44, 0xfa2b, 0x43, 0xfa37, 0x42, 0xfa44,
+  0x41, 0xfa50, 0x40, 0xfa5d, 0x3f, 0xfa69, 0x3d, 0xfa76,
+  0x3c, 0xfa82, 0x3b, 0xfa8f, 0x3a, 0xfa9b, 0x39, 0xfaa8,
+  0x38, 0xfab4, 0x37, 0xfac1, 0x36, 0xfacd, 0x35, 0xfada,
+  0x34, 0xfae6, 0x33, 0xfaf3, 0x32, 0xfb00, 0x31, 0xfb0c,
+  0x30, 0xfb19, 0x2f, 0xfb25, 0x2e, 0xfb32, 0x2d, 0xfb3e,
+  0x2c, 0xfb4b, 0x2b, 0xfb57, 0x2b, 0xfb64, 0x2a, 0xfb70,
+  0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,
+  0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,
+  0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,
+  0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,
+  0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,
+  0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,
+  0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,
+  0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,
+  0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,
+  0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,
+  0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,
+  0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,
+  0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,
+  0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,
+  0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,
+  0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,
+  0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,
+  0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,
+  0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,
+  0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,
+  0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,
+  0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,
+  0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,
+  0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,
+  0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,
+  0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,
+  0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,
+  0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,
+  0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,
+  0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,
+  0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,
+  0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,
+  0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,
+  0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,
+  0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,
+  0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,
+  0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,
+  0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,
+  0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,
+  0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,
+  0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,
+  0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,
+  0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,
+  0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,
+  0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,
+  0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,
+  0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,
+  0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,
+  0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,
+  0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,
+  0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,
+  0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,
+  0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,
+  0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,
+  0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,
+  0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,
+  0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,
+  0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,
+  0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,
+  0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,
+  0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,
+  0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,
+  0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,
+  0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,
+  0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,
+  0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,
+  0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,
+  0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,
+  0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,
+  0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,
+  0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,
+  0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,
+  0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,
+  0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,
+  0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,
+  0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,
+  0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,
+  0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,
+  0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,
+  0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,
+  0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,
+  0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,
+  0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,
+  0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,
+  0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,
+  0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,
+  0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,
+  0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,
+  0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,
+  0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,
+  0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,
+  0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,
+  0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,
+  0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,
+  0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,
+  0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,
+  0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,
+  0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,
+  0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,
+  0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,
+  0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,
+  0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,
+  0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,
+  0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,
+  0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,
+  0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,
+  0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,
+  0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,
+  0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,
+  0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,
+  0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,
+  0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,
+  0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,
+  0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,
+  0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,
+  0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,
+  0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,
+  0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,
+  0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,
+  0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,
+  0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,
+  0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,
+  0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,
+  0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,
+  0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,
+  0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,
+  0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,
+  0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,
+  0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,
+  0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,
+  0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,
+  0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,
+  0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,
+  0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,
+  0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,
+  0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,
+  0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,
+  0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,
+  0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,
+  0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,
+  0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,
+  0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,
+  0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,
+  0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,
+  0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,
+  0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,
+  0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,
+  0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,
+  0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,
+  0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,
+  0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,
+  0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,
+  0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,
+  0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,
+  0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,
+  0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,
+  0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,
+  0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,
+  0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,
+  0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,
+  0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,
+  0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,
+  0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,
+  0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,
+  0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,
+  0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,
+  0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,
+  0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,
+  0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,
+  0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,
+  0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,
+  0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,
+  0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,
+  0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,
+  0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,
+  0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,
+  0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,
+  0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,
+  0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,
+  0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,
+  0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,
+  0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,
+  0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,
+  0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,
+  0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,
+  0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,
+  0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,
+  0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,
+  0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,
+  0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,
+  0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,
+  0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,
+  0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,
+  0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,
+  0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,
+  0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,
+  0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,
+  0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,
+  0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,
+  0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,
+  0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,
+  0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,
+  0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,
+  0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,
+  0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,
+  0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,
+  0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,
+  0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,
+  0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,
+  0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,
+  0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,
+  0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,
+  0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,
+  0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,
+  0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,
+  0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,
+  0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,
+  0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,
+  0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,
+  0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,
+  0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,
+  0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,
+  0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,
+  0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,
+  0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,
+  0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,
+  0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,
+  0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,
+  0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,
+  0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,
+  0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,
+  0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,
+  0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,
+  0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,
+  0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,
+  0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,
+  0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,
+  0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,
+  0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,
+  0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,
+  0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,
+  0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,
+  0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,
+  0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,
+  0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,
+  0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,
+  0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,
+  0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,
+  0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,
+  0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,
+  0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,
+  0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,
+  0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,
+  0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,
+  0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,
+  0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,
+  0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,
+  0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,
+  0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,
+  0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,
+  0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,
+  0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,
+  0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,
+  0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,
+  0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,
+  0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,
+  0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,
+  0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,
+  0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,
+  0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,
+  0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,
+  0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,
+  0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,
+  0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,
+  0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,
+  0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,
+  0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,
+  0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,
+  0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,
+  0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,
+  0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,
+  0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,
+  0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,
+  0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,
+  0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,
+  0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,
+  0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,
+  0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,
+  0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,
+  0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,
+  0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,
+  0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,
+  0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,
+  0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,
+  0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,
+  0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,
+  0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,
+  0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,
+  0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,
+  0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,
+  0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,
+  0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,
+  0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,
+  0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,
+  0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,
+  0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,
+  0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,
+  0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,
+  0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,
+  0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,
+  0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,
+  0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,
+  0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,
+  0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,
+  0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,
+  0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,
+  0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,
+  0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,
+  0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,
+  0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,
+  0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,
+  0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,
+  0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,
+  0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,
+  0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,
+  0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,
+  0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,
+  0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,
+  0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,
+  0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,
+  0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,
+  0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,
+  0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,
+  0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,
+  0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,
+  0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,
+  0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,
+  0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,
+  0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,
+  0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,
+  0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,
+  0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,
+  0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,
+  0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,
+  0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,
+  0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,
+  0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,
+  0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,
+  0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,
+  0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,
+  0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,
+  0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,
+  0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,
+  0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,
+  0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,
+  0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,
+  0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,
+  0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,
+  0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,
+  0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,
+  0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,
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+  0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,
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+  0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,
+  0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,
+  0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,
+  0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,
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+  0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,
+  0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,
+  0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,
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+  0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,
+  0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,
+  0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,
+  0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,
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+  0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,
+  0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,
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+  0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,
+  0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,
+  0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,
+  0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,
+  0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,
+  0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,
+  0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
+  0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
+  0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
+  0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
+  0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
+  0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
+  0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
+  0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
+  0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
+  0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
+  0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
+  0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
+  0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
+  0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
+  0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
+  0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
+  0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
+  0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
+  0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
+  0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
+  0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
+  0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
+  0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
+  0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
+  0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
+  0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
+  0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
+  0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
+  0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
+  0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
+  0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
+  0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
+  0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
+  0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
+  0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
+  0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
+  0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
+  0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
+  0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
+  0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
+  0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
+  0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
+  0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
+  0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
+  0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
+  0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
+  0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
+  0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
+  0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
+  0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
+  0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
+  0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
+  0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
+  0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
+  0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
+  0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
+  0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
+  0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
+  0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
+  0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
+  0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
+  0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
+  0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
+  0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
+  0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
+  0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
+  0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
+  0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
+  0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
+  0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
+  0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
+  0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
+  0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
+  0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
+  0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
+  0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
+  0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
+  0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
+  0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
+  0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
+  0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
+  0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
+  0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
+  0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
+  0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
+  0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
+  0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
+  0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
+  0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
+  0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
+  0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
+  0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
+  0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
+  0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
+  0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
+  0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
+  0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
+  0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
+  0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
+};
+
+/**    
+* \par   
+* Generation of real_CoefB array:    
+* \par    
+* n = 4096    
+* 
for (i = 0; i < n; i++)    
+*  {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+*  } 
   
+* \par    
+* Convert to fixed point Q15 format    
+*       round(pBTable[i] * pow(2, 15))    
+*    
+*/
+
+static const q15_t ALIGN4 realCoefBQ15[8192] = {
+  0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
+  0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
+  0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
+  0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
+  0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
+  0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
+  0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
+  0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
+  0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
+  0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
+  0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
+  0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
+  0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
+  0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
+  0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
+  0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
+  0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
+  0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
+  0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
+  0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
+  0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
+  0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
+  0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
+  0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
+  0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
+  0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
+  0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
+  0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
+  0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
+  0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
+  0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
+  0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
+  0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
+  0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
+  0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
+  0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
+  0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
+  0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
+  0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
+  0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
+  0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
+  0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
+  0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
+  0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
+  0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
+  0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
+  0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
+  0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
+  0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
+  0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
+  0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
+  0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
+  0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
+  0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
+  0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
+  0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
+  0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
+  0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
+  0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
+  0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
+  0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
+  0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
+  0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
+  0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
+  0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
+  0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
+  0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
+  0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
+  0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
+  0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
+  0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
+  0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
+  0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
+  0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
+  0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
+  0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
+  0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
+  0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
+  0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
+  0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
+  0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
+  0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
+  0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
+  0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
+  0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
+  0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
+  0x50b1, 0x3dc9, 0x50bd, 0x3dc6, 0x50c9, 0x3dc2, 0x50d5, 0x3dbf,
+  0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
+  0x5112, 0x3daf, 0x511e, 0x3dab, 0x512a, 0x3da8, 0x5136, 0x3da4,
+  0x5142, 0x3da1, 0x514e, 0x3d9e, 0x515a, 0x3d9a, 0x5167, 0x3d97,
+  0x5173, 0x3d93, 0x517f, 0x3d90, 0x518b, 0x3d8d, 0x5197, 0x3d89,
+  0x51a3, 0x3d86, 0x51af, 0x3d82, 0x51bb, 0x3d7f, 0x51c7, 0x3d7b,
+  0x51d3, 0x3d78, 0x51df, 0x3d74, 0x51eb, 0x3d71, 0x51f7, 0x3d6d,
+  0x5204, 0x3d6a, 0x5210, 0x3d66, 0x521c, 0x3d63, 0x5228, 0x3d5f,
+  0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
+  0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
+  0x5294, 0x3d3f, 0x52a0, 0x3d3b, 0x52ac, 0x3d37, 0x52b8, 0x3d34,
+  0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
+  0x52f4, 0x3d21, 0x5300, 0x3d1d, 0x530c, 0x3d1a, 0x5318, 0x3d16,
+  0x5324, 0x3d12, 0x5330, 0x3d0e, 0x533c, 0x3d0b, 0x5348, 0x3d07,
+  0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
+  0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
+  0x53b4, 0x3ce4, 0x53c0, 0x3ce0, 0x53cc, 0x3cdd, 0x53d8, 0x3cd9,
+  0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
+  0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
+  0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
+  0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
+  0x54a2, 0x3c95, 0x54ae, 0x3c91, 0x54ba, 0x3c8d, 0x54c6, 0x3c89,
+  0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
+  0x5501, 0x3c74, 0x550d, 0x3c70, 0x5519, 0x3c6c, 0x5525, 0x3c68,
+  0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
+  0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
+  0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
+  0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
+  0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
+  0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
+  0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
+  0x567c, 0x3bec, 0x5687, 0x3be7, 0x5693, 0x3be3, 0x569f, 0x3bde,
+  0x56ab, 0x3bda, 0x56b6, 0x3bd6, 0x56c2, 0x3bd1, 0x56ce, 0x3bcd,
+  0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
+  0x5709, 0x3bb6, 0x5714, 0x3bb2, 0x5720, 0x3bad, 0x572c, 0x3ba9,
+  0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
+  0x5766, 0x3b92, 0x5772, 0x3b8d, 0x577e, 0x3b88, 0x5789, 0x3b84,
+  0x5795, 0x3b7f, 0x57a1, 0x3b7b, 0x57ac, 0x3b76, 0x57b8, 0x3b71,
+  0x57c4, 0x3b6d, 0x57cf, 0x3b68, 0x57db, 0x3b63, 0x57e7, 0x3b5f,
+  0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
+  0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
+  0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
+  0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
+  0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
+  0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
+  0x5909, 0x3ae6, 0x5914, 0x3ae2, 0x5920, 0x3add, 0x592c, 0x3ad8,
+  0x5937, 0x3ad3, 0x5943, 0x3ace, 0x594e, 0x3ac9, 0x595a, 0x3ac4,
+  0x5965, 0x3abf, 0x5971, 0x3aba, 0x597c, 0x3ab5, 0x5988, 0x3ab0,
+  0x5993, 0x3aab, 0x599f, 0x3aa6, 0x59aa, 0x3aa1, 0x59b6, 0x3a9c,
+  0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
+  0x59ef, 0x3a82, 0x59fb, 0x3a7d, 0x5a06, 0x3a78, 0x5a12, 0x3a73,
+  0x5a1d, 0x3a6e, 0x5a29, 0x3a69, 0x5a34, 0x3a64, 0x5a40, 0x3a5f,
+  0x5a4b, 0x3a59, 0x5a57, 0x3a54, 0x5a62, 0x3a4f, 0x5a6e, 0x3a4a,
+  0x5a79, 0x3a45, 0x5a84, 0x3a3f, 0x5a90, 0x3a3a, 0x5a9b, 0x3a35,
+  0x5aa7, 0x3a30, 0x5ab2, 0x3a2b, 0x5abe, 0x3a25, 0x5ac9, 0x3a20,
+  0x5ad4, 0x3a1b, 0x5ae0, 0x3a16, 0x5aeb, 0x3a10, 0x5af7, 0x3a0b,
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+  0x7e45, 0xeca, 0x7e48, 0xebd, 0x7e4a, 0xeb1, 0x7e4d, 0xea5,
+  0x7e50, 0xe99, 0x7e53, 0xe8c, 0x7e56, 0xe80, 0x7e59, 0xe74,
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+  0x7e67, 0xe37, 0x7e6a, 0xe2b, 0x7e6c, 0xe1e, 0x7e6f, 0xe12,
+  0x7e72, 0xe06, 0x7e75, 0xdf9, 0x7e77, 0xded, 0x7e7a, 0xde1,
+  0x7e7d, 0xdd5, 0x7e80, 0xdc8, 0x7e82, 0xdbc, 0x7e85, 0xdb0,
+  0x7e88, 0xda4, 0x7e8a, 0xd97, 0x7e8d, 0xd8b, 0x7e90, 0xd7f,
+  0x7e92, 0xd72, 0x7e95, 0xd66, 0x7e98, 0xd5a, 0x7e9a, 0xd4e,
+  0x7e9d, 0xd41, 0x7e9f, 0xd35, 0x7ea2, 0xd29, 0x7ea5, 0xd1c,
+  0x7ea7, 0xd10, 0x7eaa, 0xd04, 0x7eac, 0xcf8, 0x7eaf, 0xceb,
+  0x7eb1, 0xcdf, 0x7eb4, 0xcd3, 0x7eb6, 0xcc6, 0x7eb9, 0xcba,
+  0x7ebb, 0xcae, 0x7ebe, 0xca1, 0x7ec0, 0xc95, 0x7ec3, 0xc89,
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+  0x7ecf, 0xc4b, 0x7ed1, 0xc3f, 0x7ed4, 0xc32, 0x7ed6, 0xc26,
+  0x7ed8, 0xc1a, 0x7edb, 0xc0d, 0x7edd, 0xc01, 0x7ee0, 0xbf5,
+  0x7ee2, 0xbe8, 0x7ee4, 0xbdc, 0x7ee7, 0xbd0, 0x7ee9, 0xbc3,
+  0x7eeb, 0xbb7, 0x7eed, 0xbab, 0x7ef0, 0xb9e, 0x7ef2, 0xb92,
+  0x7ef4, 0xb85, 0x7ef7, 0xb79, 0x7ef9, 0xb6d, 0x7efb, 0xb60,
+  0x7efd, 0xb54, 0x7f00, 0xb48, 0x7f02, 0xb3b, 0x7f04, 0xb2f,
+  0x7f06, 0xb23, 0x7f08, 0xb16, 0x7f0a, 0xb0a, 0x7f0d, 0xafd,
+  0x7f0f, 0xaf1, 0x7f11, 0xae5, 0x7f13, 0xad8, 0x7f15, 0xacc,
+  0x7f17, 0xac0, 0x7f19, 0xab3, 0x7f1c, 0xaa7, 0x7f1e, 0xa9a,
+  0x7f20, 0xa8e, 0x7f22, 0xa82, 0x7f24, 0xa75, 0x7f26, 0xa69,
+  0x7f28, 0xa5c, 0x7f2a, 0xa50, 0x7f2c, 0xa44, 0x7f2e, 0xa37,
+  0x7f30, 0xa2b, 0x7f32, 0xa1e, 0x7f34, 0xa12, 0x7f36, 0xa06,
+  0x7f38, 0x9f9, 0x7f3a, 0x9ed, 0x7f3c, 0x9e0, 0x7f3e, 0x9d4,
+  0x7f40, 0x9c7, 0x7f42, 0x9bb, 0x7f43, 0x9af, 0x7f45, 0x9a2,
+  0x7f47, 0x996, 0x7f49, 0x989, 0x7f4b, 0x97d, 0x7f4d, 0x970,
+  0x7f4f, 0x964, 0x7f51, 0x958, 0x7f52, 0x94b, 0x7f54, 0x93f,
+  0x7f56, 0x932, 0x7f58, 0x926, 0x7f5a, 0x919, 0x7f5b, 0x90d,
+  0x7f5d, 0x901, 0x7f5f, 0x8f4, 0x7f61, 0x8e8, 0x7f62, 0x8db,
+  0x7f64, 0x8cf, 0x7f66, 0x8c2, 0x7f68, 0x8b6, 0x7f69, 0x8a9,
+  0x7f6b, 0x89d, 0x7f6d, 0x891, 0x7f6e, 0x884, 0x7f70, 0x878,
+  0x7f72, 0x86b, 0x7f73, 0x85f, 0x7f75, 0x852, 0x7f77, 0x846,
+  0x7f78, 0x839, 0x7f7a, 0x82d, 0x7f7b, 0x820, 0x7f7d, 0x814,
+  0x7f7f, 0x807, 0x7f80, 0x7fb, 0x7f82, 0x7ef, 0x7f83, 0x7e2,
+  0x7f85, 0x7d6, 0x7f86, 0x7c9, 0x7f88, 0x7bd, 0x7f89, 0x7b0,
+  0x7f8b, 0x7a4, 0x7f8c, 0x797, 0x7f8e, 0x78b, 0x7f8f, 0x77e,
+  0x7f91, 0x772, 0x7f92, 0x765, 0x7f94, 0x759, 0x7f95, 0x74c,
+  0x7f97, 0x740, 0x7f98, 0x733, 0x7f99, 0x727, 0x7f9b, 0x71a,
+  0x7f9c, 0x70e, 0x7f9e, 0x701, 0x7f9f, 0x6f5, 0x7fa0, 0x6e8,
+  0x7fa2, 0x6dc, 0x7fa3, 0x6cf, 0x7fa4, 0x6c3, 0x7fa6, 0x6b6,
+  0x7fa7, 0x6aa, 0x7fa8, 0x69d, 0x7faa, 0x691, 0x7fab, 0x684,
+  0x7fac, 0x678, 0x7fad, 0x66b, 0x7faf, 0x65f, 0x7fb0, 0x652,
+  0x7fb1, 0x646, 0x7fb2, 0x639, 0x7fb4, 0x62d, 0x7fb5, 0x620,
+  0x7fb6, 0x614, 0x7fb7, 0x607, 0x7fb8, 0x5fb, 0x7fb9, 0x5ee,
+  0x7fbb, 0x5e2, 0x7fbc, 0x5d5, 0x7fbd, 0x5c9, 0x7fbe, 0x5bc,
+  0x7fbf, 0x5b0, 0x7fc0, 0x5a3, 0x7fc1, 0x597, 0x7fc3, 0x58a,
+  0x7fc4, 0x57e, 0x7fc5, 0x571, 0x7fc6, 0x565, 0x7fc7, 0x558,
+  0x7fc8, 0x54c, 0x7fc9, 0x53f, 0x7fca, 0x533, 0x7fcb, 0x526,
+  0x7fcc, 0x51a, 0x7fcd, 0x50d, 0x7fce, 0x500, 0x7fcf, 0x4f4,
+  0x7fd0, 0x4e7, 0x7fd1, 0x4db, 0x7fd2, 0x4ce, 0x7fd3, 0x4c2,
+  0x7fd4, 0x4b5, 0x7fd5, 0x4a9, 0x7fd5, 0x49c, 0x7fd6, 0x490,
+  0x7fd7, 0x483, 0x7fd8, 0x477, 0x7fd9, 0x46a, 0x7fda, 0x45e,
+  0x7fdb, 0x451, 0x7fdc, 0x444, 0x7fdc, 0x438, 0x7fdd, 0x42b,
+  0x7fde, 0x41f, 0x7fdf, 0x412, 0x7fe0, 0x406, 0x7fe0, 0x3f9,
+  0x7fe1, 0x3ed, 0x7fe2, 0x3e0, 0x7fe3, 0x3d4, 0x7fe3, 0x3c7,
+  0x7fe4, 0x3bb, 0x7fe5, 0x3ae, 0x7fe6, 0x3a1, 0x7fe6, 0x395,
+  0x7fe7, 0x388, 0x7fe8, 0x37c, 0x7fe8, 0x36f, 0x7fe9, 0x363,
+  0x7fea, 0x356, 0x7fea, 0x34a, 0x7feb, 0x33d, 0x7fec, 0x330,
+  0x7fec, 0x324, 0x7fed, 0x317, 0x7fed, 0x30b, 0x7fee, 0x2fe,
+  0x7fef, 0x2f2, 0x7fef, 0x2e5, 0x7ff0, 0x2d9, 0x7ff0, 0x2cc,
+  0x7ff1, 0x2c0, 0x7ff1, 0x2b3, 0x7ff2, 0x2a6, 0x7ff2, 0x29a,
+  0x7ff3, 0x28d, 0x7ff3, 0x281, 0x7ff4, 0x274, 0x7ff4, 0x268,
+  0x7ff5, 0x25b, 0x7ff5, 0x24e, 0x7ff6, 0x242, 0x7ff6, 0x235,
+  0x7ff7, 0x229, 0x7ff7, 0x21c, 0x7ff7, 0x210, 0x7ff8, 0x203,
+  0x7ff8, 0x1f7, 0x7ff9, 0x1ea, 0x7ff9, 0x1dd, 0x7ff9, 0x1d1,
+  0x7ffa, 0x1c4, 0x7ffa, 0x1b8, 0x7ffa, 0x1ab, 0x7ffb, 0x19f,
+  0x7ffb, 0x192, 0x7ffb, 0x186, 0x7ffc, 0x179, 0x7ffc, 0x16c,
+  0x7ffc, 0x160, 0x7ffc, 0x153, 0x7ffd, 0x147, 0x7ffd, 0x13a,
+  0x7ffd, 0x12e, 0x7ffd, 0x121, 0x7ffe, 0x114, 0x7ffe, 0x108,
+  0x7ffe, 0xfb, 0x7ffe, 0xef, 0x7ffe, 0xe2, 0x7fff, 0xd6,
+  0x7fff, 0xc9, 0x7fff, 0xbc, 0x7fff, 0xb0, 0x7fff, 0xa3,
+  0x7fff, 0x97, 0x7fff, 0x8a, 0x7fff, 0x7e, 0x7fff, 0x71,
+  0x7fff, 0x65, 0x7fff, 0x58, 0x7fff, 0x4b, 0x7fff, 0x3f,
+  0x7fff, 0x32, 0x7fff, 0x26, 0x7fff, 0x19, 0x7fff, 0xd,
+  0x7fff, 0x0, 0x7fff, 0xfff3, 0x7fff, 0xffe7, 0x7fff, 0xffda,
+  0x7fff, 0xffce, 0x7fff, 0xffc1, 0x7fff, 0xffb5, 0x7fff, 0xffa8,
+  0x7fff, 0xff9b, 0x7fff, 0xff8f, 0x7fff, 0xff82, 0x7fff, 0xff76,
+  0x7fff, 0xff69, 0x7fff, 0xff5d, 0x7fff, 0xff50, 0x7fff, 0xff44,
+  0x7fff, 0xff37, 0x7fff, 0xff2a, 0x7ffe, 0xff1e, 0x7ffe, 0xff11,
+  0x7ffe, 0xff05, 0x7ffe, 0xfef8, 0x7ffe, 0xfeec, 0x7ffd, 0xfedf,
+  0x7ffd, 0xfed2, 0x7ffd, 0xfec6, 0x7ffd, 0xfeb9, 0x7ffc, 0xfead,
+  0x7ffc, 0xfea0, 0x7ffc, 0xfe94, 0x7ffc, 0xfe87, 0x7ffb, 0xfe7a,
+  0x7ffb, 0xfe6e, 0x7ffb, 0xfe61, 0x7ffa, 0xfe55, 0x7ffa, 0xfe48,
+  0x7ffa, 0xfe3c, 0x7ff9, 0xfe2f, 0x7ff9, 0xfe23, 0x7ff9, 0xfe16,
+  0x7ff8, 0xfe09, 0x7ff8, 0xfdfd, 0x7ff7, 0xfdf0, 0x7ff7, 0xfde4,
+  0x7ff7, 0xfdd7, 0x7ff6, 0xfdcb, 0x7ff6, 0xfdbe, 0x7ff5, 0xfdb2,
+  0x7ff5, 0xfda5, 0x7ff4, 0xfd98, 0x7ff4, 0xfd8c, 0x7ff3, 0xfd7f,
+  0x7ff3, 0xfd73, 0x7ff2, 0xfd66, 0x7ff2, 0xfd5a, 0x7ff1, 0xfd4d,
+  0x7ff1, 0xfd40, 0x7ff0, 0xfd34, 0x7ff0, 0xfd27, 0x7fef, 0xfd1b,
+  0x7fef, 0xfd0e, 0x7fee, 0xfd02, 0x7fed, 0xfcf5, 0x7fed, 0xfce9,
+  0x7fec, 0xfcdc, 0x7fec, 0xfcd0, 0x7feb, 0xfcc3, 0x7fea, 0xfcb6,
+  0x7fea, 0xfcaa, 0x7fe9, 0xfc9d, 0x7fe8, 0xfc91, 0x7fe8, 0xfc84,
+  0x7fe7, 0xfc78, 0x7fe6, 0xfc6b, 0x7fe6, 0xfc5f, 0x7fe5, 0xfc52,
+  0x7fe4, 0xfc45, 0x7fe3, 0xfc39, 0x7fe3, 0xfc2c, 0x7fe2, 0xfc20,
+  0x7fe1, 0xfc13, 0x7fe0, 0xfc07, 0x7fe0, 0xfbfa, 0x7fdf, 0xfbee,
+  0x7fde, 0xfbe1, 0x7fdd, 0xfbd5, 0x7fdc, 0xfbc8, 0x7fdc, 0xfbbc,
+  0x7fdb, 0xfbaf, 0x7fda, 0xfba2, 0x7fd9, 0xfb96, 0x7fd8, 0xfb89,
+  0x7fd7, 0xfb7d, 0x7fd6, 0xfb70, 0x7fd5, 0xfb64, 0x7fd5, 0xfb57,
+  0x7fd4, 0xfb4b, 0x7fd3, 0xfb3e, 0x7fd2, 0xfb32, 0x7fd1, 0xfb25,
+  0x7fd0, 0xfb19, 0x7fcf, 0xfb0c, 0x7fce, 0xfb00, 0x7fcd, 0xfaf3,
+  0x7fcc, 0xfae6, 0x7fcb, 0xfada, 0x7fca, 0xfacd, 0x7fc9, 0xfac1,
+  0x7fc8, 0xfab4, 0x7fc7, 0xfaa8, 0x7fc6, 0xfa9b, 0x7fc5, 0xfa8f,
+  0x7fc4, 0xfa82, 0x7fc3, 0xfa76, 0x7fc1, 0xfa69, 0x7fc0, 0xfa5d,
+  0x7fbf, 0xfa50, 0x7fbe, 0xfa44, 0x7fbd, 0xfa37, 0x7fbc, 0xfa2b,
+  0x7fbb, 0xfa1e, 0x7fb9, 0xfa12, 0x7fb8, 0xfa05, 0x7fb7, 0xf9f9,
+  0x7fb6, 0xf9ec, 0x7fb5, 0xf9e0, 0x7fb4, 0xf9d3, 0x7fb2, 0xf9c7,
+  0x7fb1, 0xf9ba, 0x7fb0, 0xf9ae, 0x7faf, 0xf9a1, 0x7fad, 0xf995,
+  0x7fac, 0xf988, 0x7fab, 0xf97c, 0x7faa, 0xf96f, 0x7fa8, 0xf963,
+  0x7fa7, 0xf956, 0x7fa6, 0xf94a, 0x7fa4, 0xf93d, 0x7fa3, 0xf931,
+  0x7fa2, 0xf924, 0x7fa0, 0xf918, 0x7f9f, 0xf90b, 0x7f9e, 0xf8ff,
+  0x7f9c, 0xf8f2, 0x7f9b, 0xf8e6, 0x7f99, 0xf8d9, 0x7f98, 0xf8cd,
+  0x7f97, 0xf8c0, 0x7f95, 0xf8b4, 0x7f94, 0xf8a7, 0x7f92, 0xf89b,
+  0x7f91, 0xf88e, 0x7f8f, 0xf882, 0x7f8e, 0xf875, 0x7f8c, 0xf869,
+  0x7f8b, 0xf85c, 0x7f89, 0xf850, 0x7f88, 0xf843, 0x7f86, 0xf837,
+  0x7f85, 0xf82a, 0x7f83, 0xf81e, 0x7f82, 0xf811, 0x7f80, 0xf805,
+  0x7f7f, 0xf7f9, 0x7f7d, 0xf7ec, 0x7f7b, 0xf7e0, 0x7f7a, 0xf7d3,
+  0x7f78, 0xf7c7, 0x7f77, 0xf7ba, 0x7f75, 0xf7ae, 0x7f73, 0xf7a1,
+  0x7f72, 0xf795, 0x7f70, 0xf788, 0x7f6e, 0xf77c, 0x7f6d, 0xf76f,
+  0x7f6b, 0xf763, 0x7f69, 0xf757, 0x7f68, 0xf74a, 0x7f66, 0xf73e,
+  0x7f64, 0xf731, 0x7f62, 0xf725, 0x7f61, 0xf718, 0x7f5f, 0xf70c,
+  0x7f5d, 0xf6ff, 0x7f5b, 0xf6f3, 0x7f5a, 0xf6e7, 0x7f58, 0xf6da,
+  0x7f56, 0xf6ce, 0x7f54, 0xf6c1, 0x7f52, 0xf6b5, 0x7f51, 0xf6a8,
+  0x7f4f, 0xf69c, 0x7f4d, 0xf690, 0x7f4b, 0xf683, 0x7f49, 0xf677,
+  0x7f47, 0xf66a, 0x7f45, 0xf65e, 0x7f43, 0xf651, 0x7f42, 0xf645,
+  0x7f40, 0xf639, 0x7f3e, 0xf62c, 0x7f3c, 0xf620, 0x7f3a, 0xf613,
+  0x7f38, 0xf607, 0x7f36, 0xf5fa, 0x7f34, 0xf5ee, 0x7f32, 0xf5e2,
+  0x7f30, 0xf5d5, 0x7f2e, 0xf5c9, 0x7f2c, 0xf5bc, 0x7f2a, 0xf5b0,
+  0x7f28, 0xf5a4, 0x7f26, 0xf597, 0x7f24, 0xf58b, 0x7f22, 0xf57e,
+  0x7f20, 0xf572, 0x7f1e, 0xf566, 0x7f1c, 0xf559, 0x7f19, 0xf54d,
+  0x7f17, 0xf540, 0x7f15, 0xf534, 0x7f13, 0xf528, 0x7f11, 0xf51b,
+  0x7f0f, 0xf50f, 0x7f0d, 0xf503, 0x7f0a, 0xf4f6, 0x7f08, 0xf4ea,
+  0x7f06, 0xf4dd, 0x7f04, 0xf4d1, 0x7f02, 0xf4c5, 0x7f00, 0xf4b8,
+  0x7efd, 0xf4ac, 0x7efb, 0xf4a0, 0x7ef9, 0xf493, 0x7ef7, 0xf487,
+  0x7ef4, 0xf47b, 0x7ef2, 0xf46e, 0x7ef0, 0xf462, 0x7eed, 0xf455,
+  0x7eeb, 0xf449, 0x7ee9, 0xf43d, 0x7ee7, 0xf430, 0x7ee4, 0xf424,
+  0x7ee2, 0xf418, 0x7ee0, 0xf40b, 0x7edd, 0xf3ff, 0x7edb, 0xf3f3,
+  0x7ed8, 0xf3e6, 0x7ed6, 0xf3da, 0x7ed4, 0xf3ce, 0x7ed1, 0xf3c1,
+  0x7ecf, 0xf3b5, 0x7ecc, 0xf3a9, 0x7eca, 0xf39c, 0x7ec8, 0xf390,
+  0x7ec5, 0xf384, 0x7ec3, 0xf377, 0x7ec0, 0xf36b, 0x7ebe, 0xf35f,
+  0x7ebb, 0xf352, 0x7eb9, 0xf346, 0x7eb6, 0xf33a, 0x7eb4, 0xf32d,
+  0x7eb1, 0xf321, 0x7eaf, 0xf315, 0x7eac, 0xf308, 0x7eaa, 0xf2fc,
+  0x7ea7, 0xf2f0, 0x7ea5, 0xf2e4, 0x7ea2, 0xf2d7, 0x7e9f, 0xf2cb,
+  0x7e9d, 0xf2bf, 0x7e9a, 0xf2b2, 0x7e98, 0xf2a6, 0x7e95, 0xf29a,
+  0x7e92, 0xf28e, 0x7e90, 0xf281, 0x7e8d, 0xf275, 0x7e8a, 0xf269,
+  0x7e88, 0xf25c, 0x7e85, 0xf250, 0x7e82, 0xf244, 0x7e80, 0xf238,
+  0x7e7d, 0xf22b, 0x7e7a, 0xf21f, 0x7e77, 0xf213, 0x7e75, 0xf207,
+  0x7e72, 0xf1fa, 0x7e6f, 0xf1ee, 0x7e6c, 0xf1e2, 0x7e6a, 0xf1d5,
+  0x7e67, 0xf1c9, 0x7e64, 0xf1bd, 0x7e61, 0xf1b1, 0x7e5e, 0xf1a4,
+  0x7e5c, 0xf198, 0x7e59, 0xf18c, 0x7e56, 0xf180, 0x7e53, 0xf174,
+  0x7e50, 0xf167, 0x7e4d, 0xf15b, 0x7e4a, 0xf14f, 0x7e48, 0xf143,
+  0x7e45, 0xf136, 0x7e42, 0xf12a, 0x7e3f, 0xf11e, 0x7e3c, 0xf112,
+  0x7e39, 0xf105, 0x7e36, 0xf0f9, 0x7e33, 0xf0ed, 0x7e30, 0xf0e1,
+  0x7e2d, 0xf0d5, 0x7e2a, 0xf0c8, 0x7e27, 0xf0bc, 0x7e24, 0xf0b0,
+  0x7e21, 0xf0a4, 0x7e1e, 0xf098, 0x7e1b, 0xf08b, 0x7e18, 0xf07f,
+  0x7e15, 0xf073, 0x7e12, 0xf067, 0x7e0f, 0xf05b, 0x7e0c, 0xf04e,
+  0x7e09, 0xf042, 0x7e06, 0xf036, 0x7e03, 0xf02a, 0x7dff, 0xf01e,
+  0x7dfc, 0xf012, 0x7df9, 0xf005, 0x7df6, 0xeff9, 0x7df3, 0xefed,
+  0x7df0, 0xefe1, 0x7ded, 0xefd5, 0x7de9, 0xefc9, 0x7de6, 0xefbc,
+  0x7de3, 0xefb0, 0x7de0, 0xefa4, 0x7ddd, 0xef98, 0x7dd9, 0xef8c,
+  0x7dd6, 0xef80, 0x7dd3, 0xef74, 0x7dd0, 0xef67, 0x7dcc, 0xef5b,
+  0x7dc9, 0xef4f, 0x7dc6, 0xef43, 0x7dc2, 0xef37, 0x7dbf, 0xef2b,
+  0x7dbc, 0xef1f, 0x7db9, 0xef13, 0x7db5, 0xef06, 0x7db2, 0xeefa,
+  0x7daf, 0xeeee, 0x7dab, 0xeee2, 0x7da8, 0xeed6, 0x7da4, 0xeeca,
+  0x7da1, 0xeebe, 0x7d9e, 0xeeb2, 0x7d9a, 0xeea6, 0x7d97, 0xee99,
+  0x7d93, 0xee8d, 0x7d90, 0xee81, 0x7d8d, 0xee75, 0x7d89, 0xee69,
+  0x7d86, 0xee5d, 0x7d82, 0xee51, 0x7d7f, 0xee45, 0x7d7b, 0xee39,
+  0x7d78, 0xee2d, 0x7d74, 0xee21, 0x7d71, 0xee15, 0x7d6d, 0xee09,
+  0x7d6a, 0xedfc, 0x7d66, 0xedf0, 0x7d63, 0xede4, 0x7d5f, 0xedd8,
+  0x7d5b, 0xedcc, 0x7d58, 0xedc0, 0x7d54, 0xedb4, 0x7d51, 0xeda8,
+  0x7d4d, 0xed9c, 0x7d49, 0xed90, 0x7d46, 0xed84, 0x7d42, 0xed78,
+  0x7d3f, 0xed6c, 0x7d3b, 0xed60, 0x7d37, 0xed54, 0x7d34, 0xed48,
+  0x7d30, 0xed3c, 0x7d2c, 0xed30, 0x7d28, 0xed24, 0x7d25, 0xed18,
+  0x7d21, 0xed0c, 0x7d1d, 0xed00, 0x7d1a, 0xecf4, 0x7d16, 0xece8,
+  0x7d12, 0xecdc, 0x7d0e, 0xecd0, 0x7d0b, 0xecc4, 0x7d07, 0xecb8,
+  0x7d03, 0xecac, 0x7cff, 0xeca0, 0x7cfb, 0xec94, 0x7cf8, 0xec88,
+  0x7cf4, 0xec7c, 0x7cf0, 0xec70, 0x7cec, 0xec64, 0x7ce8, 0xec58,
+  0x7ce4, 0xec4c, 0x7ce0, 0xec40, 0x7cdd, 0xec34, 0x7cd9, 0xec28,
+  0x7cd5, 0xec1c, 0x7cd1, 0xec10, 0x7ccd, 0xec05, 0x7cc9, 0xebf9,
+  0x7cc5, 0xebed, 0x7cc1, 0xebe1, 0x7cbd, 0xebd5, 0x7cb9, 0xebc9,
+  0x7cb5, 0xebbd, 0x7cb1, 0xebb1, 0x7cad, 0xeba5, 0x7ca9, 0xeb99,
+  0x7ca5, 0xeb8d, 0x7ca1, 0xeb81, 0x7c9d, 0xeb75, 0x7c99, 0xeb6a,
+  0x7c95, 0xeb5e, 0x7c91, 0xeb52, 0x7c8d, 0xeb46, 0x7c89, 0xeb3a,
+  0x7c85, 0xeb2e, 0x7c81, 0xeb22, 0x7c7d, 0xeb16, 0x7c79, 0xeb0a,
+  0x7c74, 0xeaff, 0x7c70, 0xeaf3, 0x7c6c, 0xeae7, 0x7c68, 0xeadb,
+  0x7c64, 0xeacf, 0x7c60, 0xeac3, 0x7c5b, 0xeab7, 0x7c57, 0xeaac,
+  0x7c53, 0xeaa0, 0x7c4f, 0xea94, 0x7c4b, 0xea88, 0x7c46, 0xea7c,
+  0x7c42, 0xea70, 0x7c3e, 0xea65, 0x7c3a, 0xea59, 0x7c36, 0xea4d,
+  0x7c31, 0xea41, 0x7c2d, 0xea35, 0x7c29, 0xea29, 0x7c24, 0xea1e,
+  0x7c20, 0xea12, 0x7c1c, 0xea06, 0x7c17, 0xe9fa, 0x7c13, 0xe9ee,
+  0x7c0f, 0xe9e3, 0x7c0a, 0xe9d7, 0x7c06, 0xe9cb, 0x7c02, 0xe9bf,
+  0x7bfd, 0xe9b4, 0x7bf9, 0xe9a8, 0x7bf5, 0xe99c, 0x7bf0, 0xe990,
+  0x7bec, 0xe984, 0x7be7, 0xe979, 0x7be3, 0xe96d, 0x7bde, 0xe961,
+  0x7bda, 0xe955, 0x7bd6, 0xe94a, 0x7bd1, 0xe93e, 0x7bcd, 0xe932,
+  0x7bc8, 0xe926, 0x7bc4, 0xe91b, 0x7bbf, 0xe90f, 0x7bbb, 0xe903,
+  0x7bb6, 0xe8f7, 0x7bb2, 0xe8ec, 0x7bad, 0xe8e0, 0x7ba9, 0xe8d4,
+  0x7ba4, 0xe8c9, 0x7b9f, 0xe8bd, 0x7b9b, 0xe8b1, 0x7b96, 0xe8a5,
+  0x7b92, 0xe89a, 0x7b8d, 0xe88e, 0x7b88, 0xe882, 0x7b84, 0xe877,
+  0x7b7f, 0xe86b, 0x7b7b, 0xe85f, 0x7b76, 0xe854, 0x7b71, 0xe848,
+  0x7b6d, 0xe83c, 0x7b68, 0xe831, 0x7b63, 0xe825, 0x7b5f, 0xe819,
+  0x7b5a, 0xe80e, 0x7b55, 0xe802, 0x7b50, 0xe7f6, 0x7b4c, 0xe7eb,
+  0x7b47, 0xe7df, 0x7b42, 0xe7d3, 0x7b3e, 0xe7c8, 0x7b39, 0xe7bc,
+  0x7b34, 0xe7b1, 0x7b2f, 0xe7a5, 0x7b2a, 0xe799, 0x7b26, 0xe78e,
+  0x7b21, 0xe782, 0x7b1c, 0xe777, 0x7b17, 0xe76b, 0x7b12, 0xe75f,
+  0x7b0e, 0xe754, 0x7b09, 0xe748, 0x7b04, 0xe73d, 0x7aff, 0xe731,
+  0x7afa, 0xe725, 0x7af5, 0xe71a, 0x7af0, 0xe70e, 0x7aeb, 0xe703,
+  0x7ae6, 0xe6f7, 0x7ae2, 0xe6ec, 0x7add, 0xe6e0, 0x7ad8, 0xe6d4,
+  0x7ad3, 0xe6c9, 0x7ace, 0xe6bd, 0x7ac9, 0xe6b2, 0x7ac4, 0xe6a6,
+  0x7abf, 0xe69b, 0x7aba, 0xe68f, 0x7ab5, 0xe684, 0x7ab0, 0xe678,
+  0x7aab, 0xe66d, 0x7aa6, 0xe661, 0x7aa1, 0xe656, 0x7a9c, 0xe64a,
+  0x7a97, 0xe63f, 0x7a92, 0xe633, 0x7a8d, 0xe628, 0x7a88, 0xe61c,
+  0x7a82, 0xe611, 0x7a7d, 0xe605, 0x7a78, 0xe5fa, 0x7a73, 0xe5ee,
+  0x7a6e, 0xe5e3, 0x7a69, 0xe5d7, 0x7a64, 0xe5cc, 0x7a5f, 0xe5c0,
+  0x7a59, 0xe5b5, 0x7a54, 0xe5a9, 0x7a4f, 0xe59e, 0x7a4a, 0xe592,
+  0x7a45, 0xe587, 0x7a3f, 0xe57c, 0x7a3a, 0xe570, 0x7a35, 0xe565,
+  0x7a30, 0xe559, 0x7a2b, 0xe54e, 0x7a25, 0xe542, 0x7a20, 0xe537,
+  0x7a1b, 0xe52c, 0x7a16, 0xe520, 0x7a10, 0xe515, 0x7a0b, 0xe509,
+  0x7a06, 0xe4fe, 0x7a00, 0xe4f3, 0x79fb, 0xe4e7, 0x79f6, 0xe4dc,
+  0x79f0, 0xe4d0, 0x79eb, 0xe4c5, 0x79e6, 0xe4ba, 0x79e0, 0xe4ae,
+  0x79db, 0xe4a3, 0x79d6, 0xe498, 0x79d0, 0xe48c, 0x79cb, 0xe481,
+  0x79c5, 0xe476, 0x79c0, 0xe46a, 0x79bb, 0xe45f, 0x79b5, 0xe454,
+  0x79b0, 0xe448, 0x79aa, 0xe43d, 0x79a5, 0xe432, 0x799f, 0xe426,
+  0x799a, 0xe41b, 0x7994, 0xe410, 0x798f, 0xe404, 0x7989, 0xe3f9,
+  0x7984, 0xe3ee, 0x797e, 0xe3e2, 0x7979, 0xe3d7, 0x7973, 0xe3cc,
+  0x796e, 0xe3c1, 0x7968, 0xe3b5, 0x7963, 0xe3aa, 0x795d, 0xe39f,
+  0x7958, 0xe394, 0x7952, 0xe388, 0x794c, 0xe37d, 0x7947, 0xe372,
+  0x7941, 0xe367, 0x793b, 0xe35b, 0x7936, 0xe350, 0x7930, 0xe345,
+  0x792b, 0xe33a, 0x7925, 0xe32e, 0x791f, 0xe323, 0x791a, 0xe318,
+  0x7914, 0xe30d, 0x790e, 0xe301, 0x7909, 0xe2f6, 0x7903, 0xe2eb,
+  0x78fd, 0xe2e0, 0x78f7, 0xe2d5, 0x78f2, 0xe2ca, 0x78ec, 0xe2be,
+  0x78e6, 0xe2b3, 0x78e0, 0xe2a8, 0x78db, 0xe29d, 0x78d5, 0xe292,
+  0x78cf, 0xe287, 0x78c9, 0xe27b, 0x78c3, 0xe270, 0x78be, 0xe265,
+  0x78b8, 0xe25a, 0x78b2, 0xe24f, 0x78ac, 0xe244, 0x78a6, 0xe239,
+  0x78a1, 0xe22d, 0x789b, 0xe222, 0x7895, 0xe217, 0x788f, 0xe20c,
+  0x7889, 0xe201, 0x7883, 0xe1f6, 0x787d, 0xe1eb, 0x7877, 0xe1e0,
+  0x7871, 0xe1d5, 0x786b, 0xe1ca, 0x7866, 0xe1be, 0x7860, 0xe1b3,
+  0x785a, 0xe1a8, 0x7854, 0xe19d, 0x784e, 0xe192, 0x7848, 0xe187,
+  0x7842, 0xe17c, 0x783c, 0xe171, 0x7836, 0xe166, 0x7830, 0xe15b,
+  0x782a, 0xe150, 0x7824, 0xe145, 0x781e, 0xe13a, 0x7818, 0xe12f,
+  0x7812, 0xe124, 0x780b, 0xe119, 0x7805, 0xe10e, 0x77ff, 0xe103,
+  0x77f9, 0xe0f8, 0x77f3, 0xe0ed, 0x77ed, 0xe0e2, 0x77e7, 0xe0d7,
+  0x77e1, 0xe0cc, 0x77db, 0xe0c1, 0x77d5, 0xe0b6, 0x77ce, 0xe0ab,
+  0x77c8, 0xe0a0, 0x77c2, 0xe095, 0x77bc, 0xe08a, 0x77b6, 0xe07f,
+  0x77b0, 0xe074, 0x77a9, 0xe069, 0x77a3, 0xe05e, 0x779d, 0xe054,
+  0x7797, 0xe049, 0x7790, 0xe03e, 0x778a, 0xe033, 0x7784, 0xe028,
+  0x777e, 0xe01d, 0x7777, 0xe012, 0x7771, 0xe007, 0x776b, 0xdffc,
+  0x7765, 0xdff1, 0x775e, 0xdfe7, 0x7758, 0xdfdc, 0x7752, 0xdfd1,
+  0x774b, 0xdfc6, 0x7745, 0xdfbb, 0x773f, 0xdfb0, 0x7738, 0xdfa5,
+  0x7732, 0xdf9b, 0x772c, 0xdf90, 0x7725, 0xdf85, 0x771f, 0xdf7a,
+  0x7718, 0xdf6f, 0x7712, 0xdf65, 0x770c, 0xdf5a, 0x7705, 0xdf4f,
+  0x76ff, 0xdf44, 0x76f8, 0xdf39, 0x76f2, 0xdf2f, 0x76eb, 0xdf24,
+  0x76e5, 0xdf19, 0x76df, 0xdf0e, 0x76d8, 0xdf03, 0x76d2, 0xdef9,
+  0x76cb, 0xdeee, 0x76c5, 0xdee3, 0x76be, 0xded8, 0x76b8, 0xdece,
+  0x76b1, 0xdec3, 0x76ab, 0xdeb8, 0x76a4, 0xdead, 0x769d, 0xdea3,
+  0x7697, 0xde98, 0x7690, 0xde8d, 0x768a, 0xde83, 0x7683, 0xde78,
+  0x767d, 0xde6d, 0x7676, 0xde62, 0x766f, 0xde58, 0x7669, 0xde4d,
+  0x7662, 0xde42, 0x765c, 0xde38, 0x7655, 0xde2d, 0x764e, 0xde22,
+  0x7648, 0xde18, 0x7641, 0xde0d, 0x763a, 0xde02, 0x7634, 0xddf8,
+  0x762d, 0xdded, 0x7626, 0xdde2, 0x7620, 0xddd8, 0x7619, 0xddcd,
+  0x7612, 0xddc3, 0x760b, 0xddb8, 0x7605, 0xddad, 0x75fe, 0xdda3,
+  0x75f7, 0xdd98, 0x75f0, 0xdd8e, 0x75ea, 0xdd83, 0x75e3, 0xdd78,
+  0x75dc, 0xdd6e, 0x75d5, 0xdd63, 0x75ce, 0xdd59, 0x75c8, 0xdd4e,
+  0x75c1, 0xdd44, 0x75ba, 0xdd39, 0x75b3, 0xdd2e, 0x75ac, 0xdd24,
+  0x75a5, 0xdd19, 0x759f, 0xdd0f, 0x7598, 0xdd04, 0x7591, 0xdcfa,
+  0x758a, 0xdcef, 0x7583, 0xdce5, 0x757c, 0xdcda, 0x7575, 0xdcd0,
+  0x756e, 0xdcc5, 0x7567, 0xdcbb, 0x7561, 0xdcb0, 0x755a, 0xdca6,
+  0x7553, 0xdc9b, 0x754c, 0xdc91, 0x7545, 0xdc86, 0x753e, 0xdc7c,
+  0x7537, 0xdc72, 0x7530, 0xdc67, 0x7529, 0xdc5d, 0x7522, 0xdc52,
+  0x751b, 0xdc48, 0x7514, 0xdc3d, 0x750d, 0xdc33, 0x7506, 0xdc29,
+  0x74ff, 0xdc1e, 0x74f8, 0xdc14, 0x74f1, 0xdc09, 0x74ea, 0xdbff,
+  0x74e2, 0xdbf5, 0x74db, 0xdbea, 0x74d4, 0xdbe0, 0x74cd, 0xdbd5,
+  0x74c6, 0xdbcb, 0x74bf, 0xdbc1, 0x74b8, 0xdbb6, 0x74b1, 0xdbac,
+  0x74aa, 0xdba2, 0x74a2, 0xdb97, 0x749b, 0xdb8d, 0x7494, 0xdb83,
+  0x748d, 0xdb78, 0x7486, 0xdb6e, 0x747f, 0xdb64, 0x7477, 0xdb59,
+  0x7470, 0xdb4f, 0x7469, 0xdb45, 0x7462, 0xdb3b, 0x745b, 0xdb30,
+  0x7453, 0xdb26, 0x744c, 0xdb1c, 0x7445, 0xdb11, 0x743e, 0xdb07,
+  0x7436, 0xdafd, 0x742f, 0xdaf3, 0x7428, 0xdae8, 0x7420, 0xdade,
+  0x7419, 0xdad4, 0x7412, 0xdaca, 0x740b, 0xdabf, 0x7403, 0xdab5,
+  0x73fc, 0xdaab, 0x73f5, 0xdaa1, 0x73ed, 0xda97, 0x73e6, 0xda8c,
+  0x73df, 0xda82, 0x73d7, 0xda78, 0x73d0, 0xda6e, 0x73c8, 0xda64,
+  0x73c1, 0xda5a, 0x73ba, 0xda4f, 0x73b2, 0xda45, 0x73ab, 0xda3b,
+  0x73a3, 0xda31, 0x739c, 0xda27, 0x7395, 0xda1d, 0x738d, 0xda13,
+  0x7386, 0xda08, 0x737e, 0xd9fe, 0x7377, 0xd9f4, 0x736f, 0xd9ea,
+  0x7368, 0xd9e0, 0x7360, 0xd9d6, 0x7359, 0xd9cc, 0x7351, 0xd9c2,
+  0x734a, 0xd9b8, 0x7342, 0xd9ae, 0x733b, 0xd9a4, 0x7333, 0xd99a,
+  0x732c, 0xd98f, 0x7324, 0xd985, 0x731d, 0xd97b, 0x7315, 0xd971,
+  0x730d, 0xd967, 0x7306, 0xd95d, 0x72fe, 0xd953, 0x72f7, 0xd949,
+  0x72ef, 0xd93f, 0x72e7, 0xd935, 0x72e0, 0xd92b, 0x72d8, 0xd921,
+  0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
+  0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
+  0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
+  0x7274, 0xd8a0, 0x726d, 0xd896, 0x7265, 0xd88c, 0x725d, 0xd882,
+  0x7255, 0xd878, 0x724e, 0xd86f, 0x7246, 0xd865, 0x723e, 0xd85b,
+  0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
+  0x7217, 0xd82a, 0x720f, 0xd820, 0x7207, 0xd816, 0x71ff, 0xd80c,
+  0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
+  0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
+  0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
+  0x7199, 0xd78d, 0x7191, 0xd783, 0x7189, 0xd77a, 0x7181, 0xd770,
+  0x7179, 0xd766, 0x7171, 0xd75c, 0x7169, 0xd753, 0x7161, 0xd749,
+  0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
+  0x7139, 0xd719, 0x7131, 0xd70f, 0x7129, 0xd705, 0x7121, 0xd6fc,
+  0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
+  0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
+  0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
+  0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
+  0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
+  0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
+  0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
+  0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
+  0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
+  0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
+  0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
+  0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
+  0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
+  0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
+  0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
+  0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
+  0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
+  0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
+  0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
+  0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
+  0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
+  0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
+  0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
+  0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
+  0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
+  0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
+  0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
+  0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
+  0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
+  0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
+  0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
+  0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
+  0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
+  0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
+  0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
+  0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
+  0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
+  0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
+  0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
+  0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
+  0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
+  0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
+  0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
+  0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
+  0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
+  0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
+  0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
+  0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
+  0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
+  0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
+  0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
+  0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
+  0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
+  0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
+  0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
+  0x6981, 0xcf48, 0x6978, 0xcf40, 0x696e, 0xcf38, 0x6965, 0xcf30,
+  0x695b, 0xcf28, 0x6951, 0xcf20, 0x6948, 0xcf18, 0x693e, 0xcf10,
+  0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
+  0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
+  0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
+  0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
+  0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
+  0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
+  0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
+  0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
+  0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
+  0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
+  0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
+  0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
+  0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
+  0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
+  0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
+  0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
+  0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
+  0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
+  0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
+  0x6648, 0xccb6, 0x663e, 0xccaf, 0x6634, 0xcca7, 0x662a, 0xcca0,
+  0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
+  0x65f8, 0xcc7a, 0x65ed, 0xcc73, 0x65e3, 0xcc6b, 0x65d9, 0xcc64,
+  0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
+  0x65a6, 0xcc3f, 0x659c, 0xcc38, 0x6592, 0xcc30, 0x6588, 0xcc29,
+  0x657e, 0xcc21, 0x6574, 0xcc1a, 0x6569, 0xcc13, 0x655f, 0xcc0b,
+  0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
+  0x652c, 0xcbe7, 0x6522, 0xcbe0, 0x6518, 0xcbd8, 0x650d, 0xcbd1,
+  0x6503, 0xcbca, 0x64f9, 0xcbc2, 0x64ef, 0xcbbb, 0x64e4, 0xcbb4,
+  0x64da, 0xcbad, 0x64d0, 0xcba5, 0x64c5, 0xcb9e, 0x64bb, 0xcb97,
+  0x64b1, 0xcb90, 0x64a7, 0xcb89, 0x649c, 0xcb81, 0x6492, 0xcb7a,
+  0x6488, 0xcb73, 0x647d, 0xcb6c, 0x6473, 0xcb65, 0x6469, 0xcb5e,
+  0x645e, 0xcb56, 0x6454, 0xcb4f, 0x644a, 0xcb48, 0x643f, 0xcb41,
+  0x6435, 0xcb3a, 0x642b, 0xcb33, 0x6420, 0xcb2c, 0x6416, 0xcb25,
+  0x640b, 0xcb1e, 0x6401, 0xcb16, 0x63f7, 0xcb0f, 0x63ec, 0xcb08,
+  0x63e2, 0xcb01, 0x63d7, 0xcafa, 0x63cd, 0xcaf3, 0x63c3, 0xcaec,
+  0x63b8, 0xcae5, 0x63ae, 0xcade, 0x63a3, 0xcad7, 0x6399, 0xcad0,
+  0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
+  0x6365, 0xcaad, 0x635a, 0xcaa6, 0x6350, 0xca9f, 0x6345, 0xca99,
+  0x633b, 0xca92, 0x6330, 0xca8b, 0x6326, 0xca84, 0x631b, 0xca7d,
+  0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
+  0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
+  0x62bc, 0xca3f, 0x62b2, 0xca38, 0x62a7, 0xca32, 0x629d, 0xca2b,
+  0x6292, 0xca24, 0x6288, 0xca1d, 0x627d, 0xca16, 0x6272, 0xca10,
+  0x6268, 0xca09, 0x625d, 0xca02, 0x6253, 0xc9fb, 0x6248, 0xc9f5,
+  0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
+  0x6213, 0xc9d3, 0x6208, 0xc9cc, 0x61fe, 0xc9c6, 0x61f3, 0xc9bf,
+  0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
+  0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
+  0x6193, 0xc983, 0x6188, 0xc97d, 0x617d, 0xc976, 0x6173, 0xc970,
+  0x6168, 0xc969, 0x615d, 0xc963, 0x6153, 0xc95c, 0x6148, 0xc955,
+  0x613d, 0xc94f, 0x6132, 0xc948, 0x6128, 0xc942, 0x611d, 0xc93b,
+  0x6112, 0xc935, 0x6107, 0xc92e, 0x60fd, 0xc928, 0x60f2, 0xc921,
+  0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
+  0x60bc, 0xc901, 0x60b1, 0xc8fb, 0x60a6, 0xc8f4, 0x609b, 0xc8ee,
+  0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
+  0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
+  0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
+  0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
+  0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
+  0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
+  0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
+  0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
+  0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
+  0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
+  0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
+  0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
+  0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
+  0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
+  0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
+  0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
+  0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
+  0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
+  0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
+  0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
+  0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
+  0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
+  0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
+  0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
+  0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
+  0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
+  0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
+  0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
+  0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
+  0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
+  0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
+  0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
+  0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
+  0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
+  0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
+  0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
+  0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
+  0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
+  0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
+  0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
+  0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
+  0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
+  0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
+  0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
+  0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
+  0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
+  0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
+  0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
+  0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
+  0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
+  0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
+  0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
+  0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
+  0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
+  0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
+  0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
+  0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
+  0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
+  0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
+  0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
+  0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
+  0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
+  0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
+  0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
+  0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
+  0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
+  0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
+  0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
+  0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
+  0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
+  0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
+  0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
+  0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
+  0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
+  0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
+  0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
+  0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
+  0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
+  0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
+  0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
+  0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
+  0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
+  0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
+  0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
+  0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
+  0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
+  0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
+  0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
+  0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
+  0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
+  0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
+  0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
+  0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
+  0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
+  0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
+  0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
+  0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
+  0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
+  0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
+  0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
+  0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
+  0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
+  0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
+  0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
+  0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
+  0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
+  0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
+  0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
+  0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
+  0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
+  0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
+  0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
+  0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
+  0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
+  0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
+  0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
+  0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
+  0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
+  0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
+  0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
+  0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
+  0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
+  0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
+  0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
+  0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
+  0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
+  0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
+  0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
+  0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
+  0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
+  0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
+  0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
+  0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
+  0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
+  0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
+  0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
+  0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
+  0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
+  0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
+  0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
+  0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
+  0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
+  0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
+  0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
+  0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
+  0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
+  0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
+  0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
+  0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
+  0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
+  0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
+  0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
+  0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
+  0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
+  0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
+  0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
+  0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
+  0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
+  0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
+  0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
+  0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
+  0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
+  0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
+  0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
+  0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
+  0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
+  0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
+  0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
+  0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
+  0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
+  0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
+  0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
+  0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
+  0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
+};
+
+/**    
+* @brief  Initialization function for the Q15 RFFT/RIFFT.   
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.   
+* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.   
+* @param[in]      fftLenReal     length of the FFT.   
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
+* \par    
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    
+* This function also initializes Twiddle factor table.     
+*/
+
+arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 8192:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 2048u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 16u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 64u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**    
+   * @} end of RFFT_RIFFT group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 0000000000..400fe586c3
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4274 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_init_q31.c    
+*    
+* Description:	RFFT & RIFFT Q31 initialisation function    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**    
+ * @ingroup groupTransforms    
+ */
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+/**    
+* \par    
+* Generation floating point realCoefAQ31 array:    
+* \par    
+* n = 4096    
+* 
for (i = 0; i < n; i++)    
+* {    
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+* }
    
+* \par    
+* Convert to fixed point Q31 format    
+*     round(pATable[i] * pow(2, 31))    
+*/
+
+
+static const q31_t realCoefAQ31[8192] = {
+  0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
+  0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
+  0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
+  0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
+  0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
+  0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
+  0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
+  0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
+  0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
+  0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
+  0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
+  0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
+  0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
+  0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
+  0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
+  0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
+  0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
+  0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
+  0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
+  0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
+  0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
+  0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
+  0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
+  0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
+  0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
+  0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
+  0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
+  0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
+  0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
+  0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
+  0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
+  0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
+  0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
+  0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
+  0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
+  0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
+  0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
+  0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
+  0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
+  0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
+  0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
+  0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
+  0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
+  0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
+  0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
+  0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
+  0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
+  0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
+  0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
+  0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
+  0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
+  0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
+  0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
+  0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
+  0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
+  0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
+  0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
+  0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
+  0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
+  0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
+  0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
+  0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
+  0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
+  0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
+  0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
+  0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
+  0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
+  0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
+  0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
+  0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
+  0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
+  0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
+  0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
+  0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
+  0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
+  0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
+  0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
+  0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
+  0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
+  0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
+  0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
+  0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
+  0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
+  0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
+  0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
+  0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
+  0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
+  0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
+  0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
+  0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
+  0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
+  0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
+  0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
+  0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
+  0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
+  0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
+  0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
+  0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
+  0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
+  0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
+  0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
+  0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
+  0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
+  0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
+  0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
+  0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
+  0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
+  0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
+  0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
+  0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
+  0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
+  0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
+  0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
+  0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
+  0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
+  0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
+  0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
+  0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
+  0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
+  0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
+  0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
+  0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
+  0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
+  0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
+  0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
+  0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
+  0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
+  0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
+  0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
+  0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
+  0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
+  0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
+  0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
+  0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
+  0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
+  0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
+  0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
+  0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
+  0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
+  0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
+  0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
+  0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
+  0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
+  0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
+  0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
+  0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
+  0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
+  0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
+  0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
+  0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
+  0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
+  0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
+  0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
+  0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
+  0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
+  0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
+  0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
+  0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
+  0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
+  0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
+  0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
+  0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
+  0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
+  0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
+  0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
+  0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
+  0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
+  0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
+  0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
+  0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
+  0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
+  0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
+  0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
+  0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
+  0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
+  0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
+  0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
+  0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
+  0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
+  0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
+  0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
+  0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
+  0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
+  0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
+  0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
+  0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
+  0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
+  0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
+  0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
+  0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
+  0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
+  0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
+  0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
+  0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
+  0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
+  0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
+  0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
+  0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
+  0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
+  0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
+  0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
+  0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
+  0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
+  0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
+  0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
+  0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
+  0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
+  0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
+  0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
+  0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
+  0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
+  0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
+  0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
+  0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
+  0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
+  0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
+  0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
+  0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
+  0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
+  0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
+  0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
+  0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
+  0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
+  0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
+  0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
+  0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
+  0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
+  0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
+  0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
+  0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
+  0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
+  0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
+  0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
+  0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
+  0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
+  0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
+  0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
+  0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
+  0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
+  0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
+  0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
+  0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
+  0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
+  0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
+  0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
+  0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
+  0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
+  0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
+  0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
+  0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
+  0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
+  0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
+  0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
+  0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
+  0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
+  0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
+  0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
+  0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
+  0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
+  0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
+  0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
+  0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
+  0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
+  0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
+  0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
+  0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
+  0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
+  0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
+  0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
+  0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
+  0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
+  0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
+  0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
+  0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
+  0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
+  0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
+  0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
+  0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
+  0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
+  0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
+  0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
+  0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
+  0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
+  0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
+  0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
+  0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
+  0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
+  0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
+  0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
+  0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
+  0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
+  0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
+  0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
+  0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
+  0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
+  0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
+  0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
+  0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
+  0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
+  0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
+  0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
+  0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
+  0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
+  0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
+  0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
+  0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
+  0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
+  0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
+  0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
+  0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
+  0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
+  0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
+  0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
+  0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
+  0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
+  0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
+  0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
+  0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
+  0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
+  0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
+  0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
+  0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
+  0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
+  0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
+  0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
+  0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
+  0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
+  0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
+  0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
+  0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
+  0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
+  0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
+  0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
+  0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
+  0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
+  0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
+  0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
+  0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
+  0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
+  0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
+  0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
+  0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
+  0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
+  0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
+  0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
+  0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
+  0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
+  0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
+  0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
+  0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
+  0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
+  0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
+  0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
+  0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
+  0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
+  0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
+  0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
+  0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
+  0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
+  0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
+  0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
+  0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
+  0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
+  0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
+  0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
+  0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
+  0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
+  0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
+  0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
+  0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
+  0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
+  0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
+  0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
+  0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
+  0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
+  0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
+  0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
+  0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
+  0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
+  0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
+  0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
+  0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
+  0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
+  0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
+  0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
+  0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
+  0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
+  0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
+  0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
+  0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
+  0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
+  0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
+  0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
+  0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
+  0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
+  0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
+  0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
+  0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
+  0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
+  0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
+  0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
+  0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
+  0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
+  0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
+  0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
+  0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
+  0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
+  0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
+  0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
+  0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
+  0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
+  0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
+  0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
+  0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
+  0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
+  0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
+  0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
+  0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
+  0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
+  0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
+  0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
+  0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
+  0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
+  0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
+  0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
+  0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
+  0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
+  0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
+  0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
+  0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
+  0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
+  0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
+  0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
+  0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
+  0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
+  0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
+  0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
+  0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
+  0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
+  0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
+  0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
+  0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
+  0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
+  0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
+  0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
+  0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
+  0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
+  0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
+  0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
+  0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
+  0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
+  0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
+  0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
+  0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
+  0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
+  0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
+  0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
+  0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
+  0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
+  0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
+  0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
+  0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
+  0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
+  0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
+  0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
+  0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
+  0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
+  0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
+  0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
+  0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
+  0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
+  0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
+  0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
+  0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
+  0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
+  0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
+  0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
+  0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
+  0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
+  0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
+  0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
+  0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
+  0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
+  0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
+  0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
+  0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
+  0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
+  0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
+  0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
+  0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
+  0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
+  0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
+  0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
+  0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
+  0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
+  0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
+  0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
+  0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
+  0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
+  0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
+  0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
+  0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
+  0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
+  0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
+  0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
+  0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
+  0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
+  0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
+  0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
+  0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
+  0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
+  0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
+  0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
+  0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
+  0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
+  0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
+  0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
+  0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
+  0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
+  0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
+  0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
+  0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
+  0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
+  0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
+  0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
+  0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
+  0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
+  0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
+  0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
+  0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
+  0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
+  0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
+  0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
+  0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
+  0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
+  0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
+  0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
+  0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
+  0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
+  0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
+  0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
+  0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
+  0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
+  0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
+  0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
+  0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
+  0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
+  0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
+  0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
+  0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
+  0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
+  0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
+  0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
+  0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
+  0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
+  0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
+  0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
+  0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
+  0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
+  0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
+  0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
+  0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
+  0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
+  0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
+  0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
+  0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
+  0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
+  0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
+  0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
+  0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
+  0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
+  0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
+  0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
+  0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
+  0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
+  0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
+  0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
+  0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
+  0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
+  0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
+  0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
+  0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
+  0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
+  0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
+  0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
+  0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
+  0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
+  0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
+  0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
+  0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
+  0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
+  0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
+  0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
+  0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
+  0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
+  0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
+  0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
+  0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
+  0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
+  0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
+  0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
+  0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
+  0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
+  0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
+  0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
+  0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
+  0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
+  0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
+  0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
+  0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
+  0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
+  0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
+  0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
+  0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
+  0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
+  0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
+  0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
+  0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
+  0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
+  0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
+  0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
+  0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
+  0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
+  0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
+  0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
+  0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
+  0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
+  0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
+  0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
+  0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
+  0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
+  0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
+  0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
+  0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
+  0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
+  0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
+  0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
+  0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
+  0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
+  0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
+  0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
+  0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
+  0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
+  0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
+  0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
+  0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
+  0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
+  0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
+  0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
+  0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
+  0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
+  0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
+  0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
+  0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
+  0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
+  0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
+  0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
+  0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
+  0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
+  0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
+  0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
+  0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
+  0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
+  0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
+  0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
+  0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
+  0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
+  0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
+  0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
+  0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
+  0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
+  0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
+  0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
+  0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
+  0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
+  0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
+  0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
+  0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
+  0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
+  0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
+  0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
+  0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
+  0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
+  0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
+  0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
+  0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
+  0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
+  0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
+  0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
+  0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
+  0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
+  0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
+  0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
+  0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
+  0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
+  0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
+  0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
+  0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
+  0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
+  0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
+  0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
+  0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
+  0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
+  0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
+  0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
+  0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
+  0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
+  0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
+  0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
+  0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
+  0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
+  0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
+  0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
+  0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
+  0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
+  0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
+  0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
+  0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
+  0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
+  0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
+  0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
+  0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
+  0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
+  0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
+  0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
+  0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
+  0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
+  0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
+  0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
+  0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
+  0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
+  0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
+  0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
+  0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
+  0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
+  0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
+  0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
+  0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
+  0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
+  0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
+  0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
+  0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
+  0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
+  0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
+  0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
+  0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
+  0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
+  0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
+  0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
+  0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
+  0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
+  0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
+  0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
+  0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
+  0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
+  0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
+  0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
+  0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
+  0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
+  0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
+  0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
+  0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
+  0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
+  0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
+  0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
+  0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
+  0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
+  0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
+  0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
+  0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
+  0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
+  0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
+  0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
+  0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
+  0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
+  0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
+  0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
+  0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
+  0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
+  0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
+  0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
+  0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
+  0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
+  0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
+  0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
+  0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
+  0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
+  0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
+  0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
+  0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
+  0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
+  0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
+  0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
+  0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
+  0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
+  0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
+  0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
+  0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
+  0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
+  0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
+  0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
+  0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
+  0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
+  0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
+  0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
+  0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
+  0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
+  0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
+  0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
+  0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
+  0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
+  0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
+  0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
+  0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
+  0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
+  0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
+  0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
+  0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
+  0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
+  0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
+  0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
+  0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
+  0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
+  0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
+  0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
+  0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
+  0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
+  0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
+  0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
+  0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
+  0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
+  0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
+  0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
+  0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
+  0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
+  0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
+  0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
+  0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
+  0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
+  0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
+  0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
+  0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
+  0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
+  0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
+  0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
+  0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
+  0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
+  0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
+  0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
+  0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
+  0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
+  0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
+  0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
+  0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
+  0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
+  0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
+  0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
+  0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
+  0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
+  0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
+  0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
+  0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
+  0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
+  0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
+  0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
+  0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
+  0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
+  0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
+  0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
+  0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
+  0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
+  0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
+  0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
+  0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
+  0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
+  0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
+  0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
+  0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
+  0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
+  0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
+  0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
+  0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
+  0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
+  0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
+  0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
+  0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
+  0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
+  0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
+  0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
+  0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
+  0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
+  0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
+  0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
+  0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
+  0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
+  0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
+  0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
+  0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
+  0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
+  0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
+  0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
+  0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
+  0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
+  0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
+  0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
+  0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
+  0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
+  0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
+  0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
+  0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
+  0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
+  0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
+  0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
+  0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
+  0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
+  0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
+  0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
+  0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
+  0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
+  0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
+  0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
+  0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
+  0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
+  0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
+  0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
+  0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
+  0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
+  0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
+  0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
+  0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
+  0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
+  0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
+  0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
+  0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
+  0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
+  0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
+  0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
+  0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
+  0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
+  0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
+  0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
+  0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
+  0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
+  0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
+  0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
+  0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
+  0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
+  0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
+  0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
+  0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
+  0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
+  0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
+  0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
+  0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
+  0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
+  0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
+  0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
+  0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
+  0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
+  0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
+  0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
+  0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
+  0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
+  0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
+  0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
+  0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
+  0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
+  0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
+  0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
+  0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
+  0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
+  0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
+  0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
+  0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
+  0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
+  0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
+  0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
+  0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
+  0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
+  0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
+  0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
+  0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
+  0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
+  0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
+  0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
+  0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
+  0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
+  0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
+  0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
+  0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
+  0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
+  0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
+  0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
+  0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
+  0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
+  0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
+  0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
+  0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
+  0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
+  0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
+  0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
+  0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
+  0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
+  0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
+  0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
+  0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
+  0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
+  0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
+  0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
+  0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
+  0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
+  0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
+  0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
+  0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
+  0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
+  0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
+  0x13bd3, 0xff36f170, 0x11594, 0xff438234,
+  0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
+  0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
+  0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
+  0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
+  0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
+  0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
+  0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
+  0x0, 0x0, 0x13c, 0xc90fe,
+  0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
+  0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
+  0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
+  0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
+  0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
+  0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
+  0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
+  0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
+  0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
+  0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
+  0x25519, 0x1147271, 0x28c9c, 0x12102f4,
+  0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
+  0x341f4, 0x146b438, 0x38356, 0x153448c,
+  0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
+  0x45648, 0x178f536, 0x4a188, 0x1858552,
+  0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
+  0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
+  0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
+  0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
+  0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
+  0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
+  0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
+  0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
+  0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
+  0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
+  0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
+  0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
+  0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
+  0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
+  0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
+  0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
+  0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
+  0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
+  0x164757, 0x3562038, 0x16f047, 0x362acc5,
+  0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
+  0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
+  0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
+  0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
+  0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
+  0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
+  0x2064ab, 0x405c361, 0x213018, 0x4124dee,
+  0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
+  0x23a124, 0x437eca4, 0x24766a, 0x444768d,
+  0x254e27, 0x451004d, 0x262859, 0x45d89e2,
+  0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
+  0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
+  0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
+  0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
+  0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
+  0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
+  0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
+  0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
+  0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
+  0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
+  0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
+  0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
+  0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
+  0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
+  0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
+  0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
+  0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
+  0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
+  0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
+  0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
+  0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
+  0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
+  0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
+  0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
+  0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
+  0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
+  0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
+  0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
+  0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
+  0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
+  0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
+  0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
+  0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
+  0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
+  0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
+  0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
+  0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
+  0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
+  0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
+  0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
+  0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
+  0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
+  0x91b01d, 0x884104b, 0x935d64, 0x8908483,
+  0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
+  0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
+  0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
+  0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
+  0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
+  0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
+  0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
+  0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
+  0xb15502, 0x9640837, 0xb32e42, 0x9707635,
+  0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
+  0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
+  0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
+  0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
+  0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
+  0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
+  0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
+  0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
+  0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
+  0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
+  0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
+  0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
+  0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
+  0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
+  0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
+  0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
+  0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
+  0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
+  0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
+  0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
+  0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
+  0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
+  0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
+  0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
+  0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
+  0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
+  0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
+  0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
+  0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
+  0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
+  0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
+  0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
+  0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
+  0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
+  0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
+  0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
+  0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
+  0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
+  0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
+  0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
+  0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
+  0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
+  0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
+  0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
+  0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
+  0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
+  0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
+  0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
+  0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
+  0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
+  0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
+  0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
+  0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
+  0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
+  0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
+  0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
+  0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
+  0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
+  0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
+  0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
+  0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
+  0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
+  0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
+  0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
+  0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
+  0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
+  0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
+  0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
+  0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
+  0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
+  0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
+  0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
+  0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
+  0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
+  0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
+  0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
+  0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
+  0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
+  0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
+  0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
+  0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
+  0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
+  0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
+  0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
+  0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
+  0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
+  0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
+  0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
+  0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
+  0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
+  0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
+  0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
+  0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
+  0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
+  0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
+  0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
+  0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
+  0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
+  0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
+  0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
+  0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
+  0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
+  0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
+  0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
+  0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
+  0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
+  0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
+  0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
+  0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
+  0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
+  0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
+  0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
+  0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
+  0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
+  0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
+  0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
+  0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
+  0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
+  0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
+  0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
+  0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
+  0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
+  0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
+  0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
+  0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
+  0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
+  0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
+  0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
+  0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
+  0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
+  0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
+  0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
+  0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
+  0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
+  0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
+  0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
+  0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
+  0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
+  0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
+  0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
+  0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
+  0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
+  0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
+  0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
+  0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
+  0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
+  0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
+  0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
+  0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
+  0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
+  0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
+  0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
+  0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
+  0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
+  0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
+  0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
+  0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
+  0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
+  0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
+  0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
+  0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
+  0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
+  0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
+  0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
+  0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
+  0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
+  0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
+  0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
+  0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
+  0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
+  0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
+  0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
+  0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
+  0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
+  0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
+  0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
+  0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
+  0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
+  0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
+  0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
+  0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
+  0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
+  0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
+  0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
+  0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
+  0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
+  0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
+  0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
+  0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
+  0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
+  0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
+  0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
+  0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
+  0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
+  0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
+  0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
+  0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
+  0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
+  0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
+  0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
+  0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
+  0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
+  0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
+  0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
+  0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
+  0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
+  0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
+  0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
+  0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
+  0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
+  0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
+  0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
+  0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
+  0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
+  0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
+  0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
+  0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
+  0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
+  0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
+  0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
+  0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
+  0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
+  0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
+  0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
+  0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
+  0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
+  0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
+  0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
+  0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
+  0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
+  0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
+  0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
+  0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
+  0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
+  0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
+  0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
+  0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
+  0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
+  0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
+  0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
+  0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
+  0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
+  0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
+  0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
+  0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
+  0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
+  0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
+  0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
+  0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
+  0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
+  0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
+  0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
+  0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
+  0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
+  0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
+  0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
+  0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
+  0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
+  0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
+  0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
+  0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
+  0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
+  0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
+  0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
+  0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
+  0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
+  0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
+  0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
+  0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
+  0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
+  0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
+  0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
+  0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
+  0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
+  0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
+  0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
+  0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
+  0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
+  0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
+  0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
+  0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
+  0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
+  0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
+  0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
+  0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
+  0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
+  0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
+  0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
+  0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
+  0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
+  0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
+  0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
+  0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
+  0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
+  0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
+  0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
+  0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
+  0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
+  0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
+  0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
+  0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
+  0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
+  0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
+  0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
+  0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
+  0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
+  0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
+  0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
+  0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
+  0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
+  0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
+  0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
+  0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
+  0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
+  0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
+  0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
+  0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
+  0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
+  0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
+  0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
+  0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
+  0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
+  0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
+  0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
+  0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
+  0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
+  0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
+  0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
+  0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
+  0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
+  0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
+  0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
+  0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
+  0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
+  0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
+  0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
+  0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
+  0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
+  0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
+  0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
+  0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
+  0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
+  0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
+  0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
+  0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
+  0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
+  0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
+  0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
+  0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
+  0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
+  0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
+  0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
+  0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
+  0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
+  0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
+  0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
+  0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
+  0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
+  0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
+  0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
+  0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
+  0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
+  0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
+  0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
+  0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
+  0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
+  0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
+  0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
+  0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
+  0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
+  0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
+  0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
+  0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
+  0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
+  0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
+  0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
+  0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
+  0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
+  0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
+  0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
+  0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
+  0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
+  0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
+  0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
+  0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
+  0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
+  0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
+  0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
+  0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
+  0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
+  0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
+  0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
+  0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
+  0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
+  0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
+  0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
+  0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
+  0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
+  0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
+  0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
+  0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
+  0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
+  0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
+  0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
+  0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
+  0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
+  0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
+  0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
+  0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
+  0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
+  0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
+  0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
+  0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
+  0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
+  0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
+  0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
+  0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
+  0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
+  0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
+  0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
+  0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
+  0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
+  0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
+  0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
+  0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
+  0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
+  0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
+  0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
+  0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
+  0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
+  0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
+  0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
+  0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
+  0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
+  0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
+  0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
+  0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
+  0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
+  0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
+  0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
+  0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
+  0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
+  0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
+  0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
+  0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
+  0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
+  0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
+  0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
+  0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
+  0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
+  0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
+  0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
+  0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
+  0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
+  0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
+  0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
+  0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
+  0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
+  0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
+  0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
+  0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
+  0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
+  0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
+  0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
+  0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
+  0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
+  0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
+  0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
+  0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
+  0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
+  0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
+  0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
+  0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
+  0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
+  0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
+  0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
+  0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
+  0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
+  0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
+  0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
+  0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
+  0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
+  0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
+  0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
+  0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
+  0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
+  0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
+  0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
+  0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
+  0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
+  0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
+  0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
+  0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
+  0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
+  0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
+  0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
+  0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
+  0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
+  0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
+  0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
+  0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
+  0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
+  0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
+  0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
+  0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
+  0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
+  0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
+  0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
+  0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
+  0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
+  0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
+  0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
+  0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
+  0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
+  0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
+  0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
+  0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
+  0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
+  0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
+  0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
+  0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
+  0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
+  0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
+  0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
+  0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
+  0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
+  0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
+  0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
+  0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
+  0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
+  0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
+  0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
+  0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
+  0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
+  0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
+  0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
+  0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
+  0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
+  0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
+  0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
+  0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
+  0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
+  0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
+  0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
+  0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
+  0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
+  0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
+  0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
+  0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
+  0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
+  0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
+  0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
+  0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
+  0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
+  0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
+  0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
+  0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
+  0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
+  0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
+  0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
+  0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
+  0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
+  0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
+  0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
+  0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
+  0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
+  0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
+  0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
+  0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
+  0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
+  0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
+  0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
+  0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
+  0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
+  0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
+  0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
+  0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
+  0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
+  0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
+  0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
+  0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
+  0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
+  0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
+  0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
+  0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
+  0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
+  0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
+  0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
+  0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
+  0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
+  0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
+  0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
+  0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
+  0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
+  0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
+  0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
+  0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
+  0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
+  0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
+  0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
+  0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
+  0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
+  0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
+  0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
+  0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
+  0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
+  0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
+  0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
+  0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
+  0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
+  0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
+  0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
+  0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
+  0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
+  0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
+  0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
+  0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
+  0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
+  0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
+  0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
+  0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
+  0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
+  0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
+  0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
+  0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
+  0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
+  0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
+  0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
+  0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
+  0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
+  0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
+  0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
+  0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
+  0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
+  0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
+  0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
+  0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
+  0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
+  0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
+  0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
+  0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
+  0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
+  0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
+  0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
+  0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
+  0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
+  0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
+  0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
+  0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
+  0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
+  0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
+  0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
+  0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
+  0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
+  0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
+  0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
+  0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
+  0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
+  0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
+  0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
+  0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
+  0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
+  0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
+  0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
+  0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
+  0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
+  0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
+  0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
+  0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
+  0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
+  0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
+  0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
+  0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
+  0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
+  0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
+  0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
+  0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
+  0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
+  0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
+  0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
+  0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
+  0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
+  0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
+  0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
+  0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
+  0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
+  0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
+  0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
+  0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
+  0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
+  0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
+  0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
+  0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
+  0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
+  0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
+  0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
+  0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
+  0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
+  0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
+  0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
+  0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
+  0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
+  0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
+  0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
+  0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
+  0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
+  0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
+  0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
+  0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
+  0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
+  0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
+  0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
+  0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
+  0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
+  0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
+  0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
+  0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
+  0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
+  0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
+  0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
+  0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
+  0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
+  0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
+  0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
+  0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
+  0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
+  0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
+  0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
+  0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
+  0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
+  0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
+  0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
+  0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
+  0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
+  0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
+  0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
+  0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
+  0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
+  0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
+  0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
+  0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
+  0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
+  0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
+  0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
+  0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
+  0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
+  0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
+  0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
+  0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
+  0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
+  0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
+  0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
+  0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
+  0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
+  0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
+  0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
+  0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
+  0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
+  0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
+  0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
+  0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
+  0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
+  0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
+  0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
+  0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
+  0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
+  0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
+  0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
+  0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
+  0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
+  0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
+  0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
+  0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
+  0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
+  0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
+  0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
+  0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
+  0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
+  0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
+  0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
+  0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
+  0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
+  0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
+  0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
+  0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
+  0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
+  0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
+  0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
+  0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
+  0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
+  0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
+  0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
+  0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
+  0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
+  0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
+  0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
+  0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
+  0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
+  0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
+  0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
+  0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
+  0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
+  0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
+  0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
+  0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
+  0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
+  0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
+  0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
+  0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
+  0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
+  0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
+  0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
+  0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
+  0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
+  0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
+  0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
+  0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
+  0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
+  0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
+  0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
+  0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
+  0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
+  0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
+  0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
+  0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
+  0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
+  0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
+  0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
+  0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
+  0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
+  0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
+  0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
+  0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
+  0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
+  0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
+  0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
+  0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
+  0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
+  0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
+  0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
+  0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
+  0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
+  0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
+  0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
+  0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
+  0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
+  0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
+  0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
+  0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
+  0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
+  0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
+  0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
+  0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
+  0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
+  0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
+  0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
+  0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
+  0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
+  0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
+  0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
+  0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
+  0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
+  0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
+  0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
+  0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
+  0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
+  0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
+  0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
+  0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
+  0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
+  0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
+  0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
+  0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
+  0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
+  0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
+  0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
+  0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
+  0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
+  0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
+  0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
+  0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
+  0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
+  0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
+  0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
+  0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
+  0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
+  0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
+  0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
+  0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
+  0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
+  0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
+  0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
+  0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
+  0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
+  0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
+  0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
+  0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
+  0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
+  0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
+  0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
+  0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
+  0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
+  0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
+  0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
+  0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
+  0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
+  0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
+  0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
+  0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
+  0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
+  0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
+  0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
+  0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
+  0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
+  0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
+  0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
+  0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
+  0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
+  0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
+  0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
+  0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
+  0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
+  0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
+  0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
+  0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
+  0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
+  0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
+};
+
+
+/**    
+* \par   
+* Generation of realCoefBQ31 array:    
+* \par    
+*  n = 4096        
+* 
for (i = 0; i < n; i++)    
+* {    
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+* } 
    
+* \par    
+* Convert to fixed point Q31 format    
+*     round(pBTable[i] * pow(2, 31))    
+*    
+*/
+
+static const q31_t realCoefBQ31[8192] = {
+  0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
+  0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
+  0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
+  0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
+  0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
+  0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
+  0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
+  0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
+  0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
+  0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
+  0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
+  0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
+  0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
+  0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
+  0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
+  0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
+  0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
+  0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
+  0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
+  0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
+  0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
+  0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
+  0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
+  0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
+  0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
+  0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
+  0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
+  0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
+  0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
+  0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
+  0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
+  0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
+  0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
+  0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
+  0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
+  0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
+  0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
+  0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
+  0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
+  0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
+  0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
+  0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
+  0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
+  0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
+  0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
+  0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
+  0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
+  0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
+  0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
+  0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
+  0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
+  0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
+  0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
+  0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
+  0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
+  0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
+  0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
+  0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
+  0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
+  0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
+  0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
+  0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
+  0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
+  0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
+  0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
+  0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
+  0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
+  0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
+  0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
+  0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
+  0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
+  0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
+  0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
+  0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
+  0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
+  0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
+  0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
+  0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
+  0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
+  0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
+  0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
+  0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
+  0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
+  0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
+  0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
+  0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
+  0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
+  0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
+  0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
+  0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
+  0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
+  0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
+  0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
+  0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
+  0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
+  0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
+  0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
+  0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
+  0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
+  0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
+  0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
+  0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
+  0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
+  0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
+  0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
+  0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
+  0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
+  0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
+  0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
+  0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
+  0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
+  0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
+  0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
+  0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
+  0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
+  0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
+  0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
+  0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
+  0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
+  0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
+  0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
+  0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
+  0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
+  0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
+  0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
+  0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
+  0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
+  0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
+  0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
+  0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
+  0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
+  0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
+  0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
+  0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
+  0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
+  0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
+  0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
+  0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
+  0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
+  0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
+  0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
+  0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
+  0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
+  0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
+  0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
+  0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
+  0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
+  0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
+  0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
+  0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
+  0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
+  0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
+  0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
+  0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
+  0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
+  0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
+  0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
+  0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
+  0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
+  0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
+  0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
+  0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
+  0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
+  0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
+  0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
+  0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
+  0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
+  0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
+  0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
+  0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
+  0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
+  0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
+  0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
+  0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
+  0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
+  0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
+  0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
+  0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
+  0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
+  0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
+  0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
+  0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
+  0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
+  0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
+  0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
+  0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
+  0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
+  0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
+  0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
+  0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
+  0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
+  0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
+  0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
+  0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
+  0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
+  0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
+  0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
+  0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
+  0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
+  0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
+  0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
+  0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
+  0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
+  0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
+  0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
+  0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
+  0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
+  0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
+  0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
+  0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
+  0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
+  0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
+  0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
+  0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
+  0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
+  0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
+  0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
+  0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
+  0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
+  0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
+  0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
+  0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
+  0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
+  0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
+  0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
+  0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
+  0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
+  0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
+  0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
+  0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
+  0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
+  0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
+  0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
+  0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
+  0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
+  0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
+  0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
+  0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
+  0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
+  0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
+  0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
+  0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
+  0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
+  0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
+  0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
+  0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
+  0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
+  0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
+  0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
+  0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
+  0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
+  0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
+  0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
+  0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
+  0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
+  0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
+  0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
+  0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
+  0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
+  0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
+  0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
+  0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
+  0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
+  0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
+  0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
+  0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
+  0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
+  0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
+  0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
+  0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
+  0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
+  0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
+  0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
+  0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
+  0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
+  0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
+  0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
+  0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
+  0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
+  0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
+  0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
+  0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
+  0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
+  0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
+  0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
+  0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
+  0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
+  0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
+  0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
+  0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
+  0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
+  0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
+  0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
+  0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
+  0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
+  0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
+  0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
+  0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
+  0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
+  0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
+  0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
+  0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
+  0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
+  0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
+  0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
+  0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
+  0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
+  0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
+  0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
+  0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
+  0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
+  0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
+  0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
+  0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
+  0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
+  0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
+  0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
+  0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
+  0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
+  0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
+  0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
+  0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
+  0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
+  0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
+  0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
+  0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
+  0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
+  0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
+  0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
+  0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
+  0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
+  0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
+  0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
+  0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
+  0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
+  0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
+  0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
+  0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
+  0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
+  0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
+  0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
+  0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
+  0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
+  0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
+  0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
+  0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
+  0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
+  0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
+  0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
+  0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
+  0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
+  0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
+  0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
+  0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
+  0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
+  0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
+  0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
+  0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
+  0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
+  0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
+  0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
+  0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
+  0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
+  0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
+  0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
+  0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
+  0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
+  0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
+  0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
+  0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
+  0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
+  0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
+  0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
+  0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
+  0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
+  0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
+  0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
+  0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
+  0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
+  0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
+  0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
+  0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
+  0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
+  0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
+  0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
+  0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
+  0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
+  0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
+  0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
+  0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
+  0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
+  0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
+  0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
+  0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
+  0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
+  0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
+  0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
+  0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
+  0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
+  0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
+  0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
+  0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
+  0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
+  0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
+  0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
+  0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
+  0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
+  0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
+  0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
+  0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
+  0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
+  0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
+  0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
+  0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
+  0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
+  0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
+  0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
+  0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
+  0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
+  0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
+  0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
+  0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
+  0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
+  0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
+  0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
+  0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
+  0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
+  0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
+  0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
+  0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
+  0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
+  0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
+  0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
+  0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
+  0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
+  0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
+  0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
+  0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
+  0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
+  0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
+  0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
+  0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
+  0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
+  0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
+  0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
+  0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
+  0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
+  0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
+  0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
+  0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
+  0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
+  0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
+  0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
+  0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
+  0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
+  0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
+  0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
+  0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
+  0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
+  0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
+  0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
+  0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
+  0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
+  0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
+  0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
+  0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
+  0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
+  0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
+  0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
+  0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
+  0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
+  0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
+  0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
+  0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
+  0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
+  0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
+  0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
+  0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
+  0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
+  0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
+  0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
+  0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
+  0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
+  0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
+  0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
+  0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
+  0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
+  0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
+  0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
+  0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
+  0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
+  0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
+  0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
+  0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
+  0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
+  0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
+  0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
+  0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
+  0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
+  0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
+  0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
+  0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
+  0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
+  0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
+  0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
+  0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
+  0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
+  0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
+  0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
+  0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
+  0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
+  0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
+  0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
+  0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
+  0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
+  0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
+  0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
+  0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
+  0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
+  0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
+  0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
+  0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
+  0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
+  0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
+  0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
+  0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
+  0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
+  0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
+  0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
+  0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
+  0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
+  0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
+  0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
+  0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
+  0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
+  0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
+  0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
+  0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
+  0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
+  0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
+  0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
+  0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
+  0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
+  0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
+  0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
+  0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
+  0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
+  0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
+  0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
+  0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
+  0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
+  0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
+  0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
+  0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
+  0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
+  0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
+  0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
+  0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
+  0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
+  0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
+  0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
+  0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
+  0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
+  0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
+  0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
+  0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
+  0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
+  0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
+  0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
+  0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
+  0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
+  0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
+  0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
+  0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
+  0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
+  0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
+  0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
+  0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
+  0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
+  0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
+  0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
+  0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
+  0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
+  0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
+  0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
+  0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
+  0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
+  0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
+  0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
+  0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
+  0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
+  0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
+  0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
+  0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
+  0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
+  0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
+  0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
+  0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
+  0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
+  0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
+  0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
+  0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
+  0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
+  0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
+  0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
+  0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
+  0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
+  0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
+  0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
+  0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
+  0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
+  0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
+  0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
+  0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
+  0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
+  0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
+  0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
+  0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
+  0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
+  0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
+  0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
+  0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
+  0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
+  0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
+  0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
+  0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
+  0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
+  0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
+  0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
+  0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
+  0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
+  0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
+  0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
+  0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
+  0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
+  0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
+  0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
+  0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
+  0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
+  0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
+  0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
+  0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
+  0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
+  0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
+  0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
+  0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
+  0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
+  0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
+  0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
+  0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
+  0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
+  0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
+  0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
+  0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
+  0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
+  0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
+  0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
+  0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
+  0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
+  0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
+  0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
+  0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
+  0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
+  0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
+  0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
+  0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
+  0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
+  0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
+  0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
+  0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
+  0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
+  0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
+  0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
+  0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
+  0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
+  0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
+  0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
+  0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
+  0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
+  0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
+  0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
+  0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
+  0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
+  0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
+  0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
+  0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
+  0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
+  0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
+  0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
+  0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
+  0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
+  0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
+  0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
+  0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
+  0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
+  0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
+  0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
+  0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
+  0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
+  0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
+  0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
+  0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
+  0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
+  0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
+  0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
+  0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
+  0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
+  0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
+  0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
+  0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
+  0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
+  0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
+  0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
+  0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
+  0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
+  0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
+  0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
+  0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
+  0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
+  0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
+  0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
+  0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
+  0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
+  0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
+  0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
+  0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
+  0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
+  0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
+  0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
+  0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
+  0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
+  0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
+  0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
+  0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
+  0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
+  0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
+  0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
+  0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
+  0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
+  0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
+  0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
+  0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
+  0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
+  0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
+  0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
+  0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
+  0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
+  0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
+  0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
+  0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
+  0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
+  0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
+  0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
+  0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
+  0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
+  0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
+  0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
+  0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
+  0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
+  0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
+  0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
+  0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
+  0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
+  0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
+  0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
+  0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
+  0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
+  0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
+  0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
+  0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
+  0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
+  0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
+  0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
+  0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
+  0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
+  0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
+  0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
+  0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
+  0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
+  0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
+  0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
+  0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
+  0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
+  0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
+  0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
+  0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
+  0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
+  0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
+  0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
+  0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
+  0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
+  0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
+  0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
+  0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
+  0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
+  0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
+  0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
+  0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
+  0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
+  0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
+  0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
+  0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
+  0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
+  0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
+  0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
+  0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
+  0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
+  0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
+  0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
+  0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
+  0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
+  0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
+  0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
+  0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
+  0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
+  0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
+  0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
+  0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
+  0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
+  0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
+  0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
+  0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
+  0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
+  0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
+  0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
+  0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
+  0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
+  0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
+  0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
+  0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
+  0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
+  0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
+  0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
+  0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
+  0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
+  0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
+  0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
+  0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
+  0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
+  0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
+  0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
+  0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
+  0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
+  0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
+  0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
+  0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
+  0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
+  0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
+  0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
+  0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
+  0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
+  0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
+  0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
+  0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
+  0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
+  0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
+  0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
+  0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
+  0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
+  0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
+  0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
+  0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
+  0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
+  0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
+  0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
+  0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
+  0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
+  0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
+  0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
+  0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
+  0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
+  0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
+  0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
+  0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
+  0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
+  0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
+  0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
+  0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
+  0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
+  0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
+  0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
+  0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
+  0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
+  0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
+  0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
+  0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
+  0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
+  0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
+  0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
+  0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
+  0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
+  0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
+  0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
+  0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
+  0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
+  0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
+  0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
+  0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
+  0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
+  0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
+  0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
+  0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
+  0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
+  0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
+  0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
+  0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
+  0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
+  0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
+  0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
+  0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
+  0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
+  0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
+  0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
+  0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
+  0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
+  0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
+  0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
+  0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
+  0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
+  0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
+  0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
+  0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
+  0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
+  0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
+  0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
+  0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
+  0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
+  0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
+  0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
+  0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
+  0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
+  0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
+  0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
+  0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
+  0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
+  0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
+  0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
+  0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
+  0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
+  0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
+  0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
+  0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
+  0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
+  0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
+  0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
+  0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
+  0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
+  0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
+  0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
+  0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
+  0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
+  0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
+  0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
+  0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
+  0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
+  0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
+  0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
+  0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
+  0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
+  0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
+  0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
+  0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
+  0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
+  0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
+  0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
+  0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
+  0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
+  0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
+  0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
+  0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
+  0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
+  0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
+  0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
+  0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
+  0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
+  0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
+  0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
+  0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
+  0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
+  0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
+  0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
+  0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
+  0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
+  0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
+  0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
+  0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
+  0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
+  0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
+  0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
+  0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
+  0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
+  0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
+  0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
+  0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
+  0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
+  0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
+  0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
+  0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
+  0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
+  0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
+  0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
+  0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
+  0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
+  0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
+  0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
+  0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
+  0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
+  0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
+  0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
+  0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
+  0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
+  0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
+  0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
+  0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
+  0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
+  0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
+  0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
+  0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
+  0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
+  0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
+  0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
+  0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
+  0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
+  0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
+  0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
+  0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
+  0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
+  0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
+  0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
+  0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
+  0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
+  0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
+  0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
+  0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
+  0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
+  0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
+  0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
+  0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
+  0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
+  0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
+  0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
+  0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
+  0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
+  0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
+  0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
+  0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
+  0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
+  0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
+  0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
+  0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
+  0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
+  0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
+  0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
+  0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
+  0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
+  0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
+  0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
+  0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
+  0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
+  0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
+  0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
+  0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
+  0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
+  0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
+  0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
+  0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
+  0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
+  0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
+  0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
+  0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
+  0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
+  0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
+  0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
+  0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
+  0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
+  0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
+  0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
+  0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
+  0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
+  0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
+  0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
+  0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
+  0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
+  0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
+  0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
+  0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
+  0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
+  0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
+  0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
+  0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
+  0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
+  0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
+  0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
+  0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
+  0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
+  0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
+  0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
+  0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
+  0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
+  0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
+  0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
+  0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
+  0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
+  0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
+  0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
+  0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
+  0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
+  0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
+  0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
+  0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
+  0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
+  0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
+  0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
+  0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
+  0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
+  0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
+  0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
+  0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
+  0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
+  0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
+  0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
+  0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
+  0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
+  0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
+  0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
+  0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
+  0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
+  0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
+  0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
+  0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
+  0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
+  0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
+  0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
+  0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
+  0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
+  0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
+  0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
+  0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
+  0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
+  0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
+  0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
+  0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
+  0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
+  0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
+  0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
+  0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
+  0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
+  0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
+  0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
+  0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
+  0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
+  0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
+  0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
+  0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
+  0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
+  0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
+  0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
+  0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
+  0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
+  0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
+  0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
+  0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
+  0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
+  0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
+  0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
+  0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
+  0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
+  0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
+  0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
+  0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
+  0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
+  0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
+  0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
+  0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
+  0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
+  0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
+  0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
+  0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
+  0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
+  0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
+  0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
+  0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
+  0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
+  0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
+  0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
+  0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
+  0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
+  0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
+  0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
+  0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
+  0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
+  0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
+  0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
+  0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
+  0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
+  0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
+  0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
+  0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
+  0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
+  0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
+  0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
+  0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
+  0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
+  0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
+  0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
+  0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
+  0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
+  0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
+  0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
+  0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
+  0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
+  0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
+  0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
+  0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
+  0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
+  0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
+  0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
+  0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
+  0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
+  0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
+  0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
+  0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
+  0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
+  0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
+  0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
+  0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
+  0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
+  0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
+  0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
+  0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
+  0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
+  0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
+  0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
+  0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
+  0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
+  0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
+  0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
+  0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
+  0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
+  0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
+  0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
+  0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
+  0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
+  0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
+  0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
+  0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
+  0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
+  0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
+  0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
+  0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
+  0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
+  0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
+  0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
+  0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
+  0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
+  0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
+  0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
+  0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
+  0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
+  0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
+  0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
+  0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
+  0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
+  0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
+  0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
+  0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
+  0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
+  0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
+  0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
+  0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
+  0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
+  0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
+  0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
+  0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
+  0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
+  0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
+  0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
+  0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
+  0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
+  0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
+  0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
+  0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
+  0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
+  0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
+  0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
+  0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
+  0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
+  0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
+  0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
+  0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
+  0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
+  0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
+  0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
+  0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
+  0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
+  0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
+  0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
+  0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
+  0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
+  0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
+  0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
+  0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
+  0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
+  0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
+  0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
+  0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
+  0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
+  0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
+  0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
+  0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
+  0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
+  0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
+  0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
+  0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
+  0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
+  0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
+  0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
+  0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
+  0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
+  0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
+  0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
+  0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
+  0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
+  0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
+  0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
+  0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
+  0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
+  0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
+  0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
+  0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
+  0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
+  0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
+  0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
+  0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
+  0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
+  0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
+  0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
+  0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
+  0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
+  0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
+  0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
+  0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
+  0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
+  0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
+  0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
+  0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
+  0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
+  0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
+  0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
+  0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
+  0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
+  0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
+  0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
+  0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
+  0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
+  0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
+  0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
+  0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
+  0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
+  0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
+  0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
+  0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
+  0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
+  0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
+  0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
+  0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
+  0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
+  0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
+  0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
+  0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
+  0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
+  0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
+  0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
+  0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
+  0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
+  0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
+  0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
+  0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
+  0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
+  0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
+  0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
+  0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
+  0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
+  0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
+  0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
+  0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
+  0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
+  0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
+  0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
+  0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
+  0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
+  0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
+  0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
+  0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
+  0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
+  0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
+  0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
+  0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
+  0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
+  0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
+  0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
+  0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
+  0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
+  0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
+  0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
+  0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
+  0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
+  0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
+  0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
+  0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
+  0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
+  0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
+  0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
+  0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
+  0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
+  0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
+  0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
+  0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
+  0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
+  0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
+  0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
+  0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
+  0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
+  0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
+  0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
+  0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
+  0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
+  0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
+  0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
+  0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
+  0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
+  0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
+  0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
+  0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
+  0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
+  0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
+  0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
+  0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
+  0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
+  0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
+  0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
+  0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
+  0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
+  0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
+  0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
+  0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
+  0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
+  0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
+  0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
+  0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
+  0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
+  0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
+  0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
+  0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
+  0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
+  0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
+  0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
+  0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
+  0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
+  0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
+  0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
+  0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
+  0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
+  0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
+  0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
+  0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
+  0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
+  0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
+  0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
+  0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
+  0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
+  0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
+  0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
+  0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
+  0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
+  0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
+  0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
+  0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
+  0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
+  0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
+  0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
+  0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
+  0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
+  0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
+  0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
+  0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
+  0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
+  0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
+  0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
+  0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
+  0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
+  0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
+  0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
+  0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
+  0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
+  0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
+  0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
+  0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
+  0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
+  0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
+  0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
+  0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
+  0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
+  0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
+  0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
+  0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
+  0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
+  0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
+  0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
+  0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
+  0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
+  0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
+  0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
+  0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
+  0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
+  0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
+  0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
+  0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
+  0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
+  0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
+  0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
+  0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
+  0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
+  0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
+  0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
+  0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
+  0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
+  0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
+  0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
+  0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
+  0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
+  0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
+  0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
+  0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
+  0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
+  0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
+  0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
+  0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
+  0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
+  0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
+  0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
+  0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
+  0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
+  0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
+  0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
+  0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
+  0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
+  0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
+  0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
+  0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
+  0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
+  0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
+  0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
+  0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
+  0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
+  0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
+  0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
+  0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
+  0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
+  0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
+  0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
+  0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
+  0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
+  0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
+  0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
+  0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
+  0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
+  0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
+  0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
+  0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
+  0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
+  0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
+  0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
+  0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
+  0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
+  0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
+  0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
+  0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
+  0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
+  0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
+  0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
+  0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
+  0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
+  0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
+  0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
+  0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
+  0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
+  0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
+  0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
+  0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
+  0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
+  0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
+  0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
+  0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
+  0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
+  0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
+  0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
+  0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
+  0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
+  0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
+  0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
+  0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
+  0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
+  0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
+  0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
+  0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
+  0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
+  0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
+  0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
+  0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
+  0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
+  0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
+  0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
+  0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
+  0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
+  0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
+  0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
+  0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
+  0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
+  0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
+  0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
+  0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
+  0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
+  0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
+  0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
+  0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
+  0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
+  0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
+  0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
+  0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
+  0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
+  0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
+  0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
+  0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
+  0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
+  0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
+  0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
+  0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
+  0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
+  0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
+  0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
+  0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
+  0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
+  0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
+  0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
+  0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
+  0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
+  0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
+  0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
+  0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
+  0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
+  0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
+  0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
+  0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
+  0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
+  0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
+  0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
+  0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
+  0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
+  0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
+  0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
+  0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
+  0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
+  0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
+  0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
+  0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
+  0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
+  0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
+  0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
+  0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
+  0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
+  0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
+  0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
+  0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
+  0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
+  0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
+  0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
+  0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
+  0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
+  0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
+  0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
+  0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
+  0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
+  0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
+  0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
+  0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
+  0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
+  0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
+  0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
+  0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
+  0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
+  0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
+  0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
+  0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
+  0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
+  0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
+  0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
+  0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
+  0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
+  0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
+  0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
+  0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
+  0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
+  0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
+  0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
+  0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
+  0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
+  0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
+  0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
+  0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
+  0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
+  0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
+  0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
+  0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
+  0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
+  0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
+  0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
+  0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
+  0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
+  0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
+  0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
+  0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
+  0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
+  0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
+  0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
+  0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
+  0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
+  0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
+  0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
+  0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
+  0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
+  0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
+  0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
+  0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
+  0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
+  0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
+  0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
+  0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
+  0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
+  0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
+  0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
+  0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
+  0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
+  0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
+  0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
+  0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
+  0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
+  0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
+  0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
+  0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
+  0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
+  0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
+  0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
+  0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
+  0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
+  0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
+  0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
+  0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
+  0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
+  0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
+  0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
+  0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
+  0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
+  0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
+  0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
+  0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
+  0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
+  0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
+  0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
+  0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
+  0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
+  0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
+  0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
+  0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
+  0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
+  0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
+  0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
+  0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
+  0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
+  0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
+  0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
+  0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
+  0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
+  0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
+  0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
+  0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
+  0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
+  0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
+  0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
+  0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
+  0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
+  0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
+  0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
+  0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
+  0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
+  0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
+  0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
+  0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
+  0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
+  0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
+  0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
+  0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
+  0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
+  0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
+  0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
+  0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
+  0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
+  0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
+  0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
+  0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
+  0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
+  0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
+  0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
+  0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
+  0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
+  0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
+  0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
+  0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
+  0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
+  0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
+  0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
+  0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
+  0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
+  0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
+  0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
+  0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
+  0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
+  0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
+  0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
+  0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
+  0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
+  0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
+  0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
+  0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
+  0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
+  0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
+  0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
+  0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
+  0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
+  0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
+  0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
+  0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
+  0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
+  0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
+  0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
+  0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
+  0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
+  0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
+  0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
+  0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
+  0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
+  0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
+  0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
+  0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
+  0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
+  0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
+  0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
+  0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
+  0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
+  0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
+  0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
+  0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
+  0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
+  0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
+  0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
+  0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
+  0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
+  0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
+  0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
+  0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
+  0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
+  0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
+  0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
+  0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
+  0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
+  0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
+  0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
+  0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
+  0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
+  0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
+  0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
+  0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
+  0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
+  0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
+  0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
+  0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
+  0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
+  0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
+  0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
+  0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
+  0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
+  0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
+  0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
+  0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
+  0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
+  0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
+  0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
+  0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
+  0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
+  0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
+  0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
+  0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
+  0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
+  0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
+  0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
+  0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
+  0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
+  0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
+  0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
+  0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
+  0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
+  0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
+  0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
+  0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
+  0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
+  0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
+  0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
+  0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
+  0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
+  0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
+  0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
+  0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
+  0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
+  0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
+  0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
+  0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
+  0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
+  0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
+  0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
+  0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
+  0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
+  0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
+  0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
+  0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
+  0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
+  0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
+  0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
+  0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
+  0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
+  0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
+  0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
+  0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
+  0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
+  0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
+  0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
+  0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
+  0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
+  0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
+  0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
+  0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
+  0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
+  0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
+  0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
+  0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
+  0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
+  0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
+  0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
+  0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
+  0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
+  0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
+  0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
+  0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
+  0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
+  0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
+  0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
+  0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
+  0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
+  0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
+  0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
+  0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
+  0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
+  0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
+  0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
+  0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
+  0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
+  0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
+  0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
+  0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
+  0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
+  0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
+  0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
+  0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
+  0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
+  0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
+  0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
+  0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
+  0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
+  0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
+  0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
+  0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
+  0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
+  0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
+  0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
+  0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
+  0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
+  0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
+  0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
+  0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
+  0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
+  0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
+  0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
+  0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
+  0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
+  0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
+  0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
+  0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
+  0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
+  0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
+  0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
+  0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
+  0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
+  0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
+  0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
+  0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
+  0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
+  0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
+  0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
+  0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
+  0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
+  0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
+  0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
+  0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
+  0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
+  0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
+  0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
+  0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
+  0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
+  0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
+  0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
+  0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
+  0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
+  0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
+  0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
+  0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
+  0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
+  0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
+  0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
+  0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
+  0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
+  0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
+  0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
+  0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
+  0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
+  0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
+  0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
+  0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
+  0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
+  0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
+};
+
+/**    
+* @brief  Initialization function for the Q31 RFFT/RIFFT.   
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.   
+* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.   
+* @param[in]      fftLenReal     length of the FFT.   
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
+*    
+* \par Description:   
+* \par   
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
+* \par    
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
+* \par    
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par    
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 8192:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 2048u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 16u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 64u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**    
+   * @} end of RFFT_RIFFT group    
+   */
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 0000000000..c0c201277e
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,460 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_q15.c    
+*    
+* Description:	RFFT & RIFFT Q15 process function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------    
+*		Internal functions prototypes    
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q15 RFFT/RIFFT.   
+ * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.   
+ * @param[in]  *pSrc points to the input buffer.   
+ * @param[out] *pDst points to the output buffer.   
+ * @return none.   
+ *    
+ * \par Input an output formats:   
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.    
+ * Hence the output format is different for different RFFT sizes.    
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
+ * \par    
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"    
+ * \par    
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"    
+ */
+
+void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst)
+{
+  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+  /**    
+   * @} end of RFFT_RIFFT group    
+   */
+
+/**    
+ * @brief  Core Real FFT process    
+ * @param  *pSrc 				points to the input buffer.   
+ * @param  fftLen  				length of FFT.   
+ * @param  *pATable 			points to the A twiddle Coef buffer.    
+ * @param  *pBTable 			points to the B twiddle Coef buffer.   
+ * @param  *pDst 				points to the output buffer.   
+ * @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ * The function implements a Real FFT    
+ */
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+
+
+//  pSrc[2u * fftLen] = pSrc[0]; 
+//  pSrc[(2u * fftLen) + 1u] = pSrc[1]; 
+
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  pSrc1 = &pSrc[2];
+  pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*    
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*    
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    outR = *pSrc1 * *pCoefA;
+    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+    outR = outR + (*pSrc2 * *pCoefB);
+    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+     */
+
+    outI = *pSrc2 * *(pCoefB + 1);
+    outI = outI - (*(pSrc2 + 1) * *pCoefB);
+    outI = outI + (*(pSrc1 + 1) * *pCoefA);
+    outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**    
+ * @brief  Core Real IFFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  		    length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ * The function implements a Real IFFT    
+ */
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+  q15_t *pDst1 = &pDst[0];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  pSrc1 = &pSrc[0];
+  pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*    
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
+
+     */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +  
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+    /*    
+       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+    /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*    
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    outR = *pSrc2 * *pCoefB;
+    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+    outR = outR + (*pSrc1 * *pCoefA);
+    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+    /*   
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+     */
+
+    outI = *(pSrc1 + 1) * *pCoefA;
+    outI = outI - (*pSrc1 * *(pCoefA + 1));
+    outI = outI - (*pSrc2 * *(pCoefB + 1));
+    outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    *pDst1++ = (q15_t) outR;
+    *pDst1++ = (q15_t) (outI >> 15);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 0000000000..afcb470416
--- /dev/null
+++ b/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.    
+*    
+* $Date:        15. February 2012  
+* $Revision: 	V1.1.0  
+*    
+* Project: 	    CMSIS DSP Library    
+* Title:	    arm_rfft_q31.c    
+*    
+* Description:	RFFT & RIFFT Q31 process function    
+*    
+*    
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.1.0 2012/02/15 
+*    Updated with more optimizations, bug fixes and minor API changes.  
+*   
+* Version 1.0.10 2011/7/15  
+*    Big Endian support added and Merged M0 and M3/M4 Source code.   
+*    
+* Version 1.0.3 2010/11/29   
+*    Re-organized the CMSIS folders and updated documentation.    
+*     
+* Version 1.0.2 2010/11/11    
+*    Documentation updated.     
+*    
+* Version 1.0.1 2010/10/05     
+*    Production release and review comments incorporated.    
+*    
+* Version 1.0.0 2010/09/20     
+*    Production release and review comments incorporated.    
+*    
+* Version 0.0.7  2010/06/10     
+*    Misra-C changes done    
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------    
+*		Internal functions prototypes    
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+/**    
+ * @addtogroup RFFT_RIFFT    
+ * @{    
+ */
+
+/**    
+ * @brief Processing function for the Q31 RFFT/RIFFT.   
+ * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.   
+ * @param[in]  *pSrc points to the input buffer.   
+ * @param[out] *pDst points to the output buffer.   
+ * @return none.   
+ *    
+ * \par Input an output formats:   
+ * \par    
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different RFFT sizes.    
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
+ * \par    
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"    
+ *    
+ * \par    
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"    
+ */
+
+void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst)
+{
+  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    /*  Real FFT core process */
+    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+
+  /**    
+   * @} end of RFFT_RIFFT group    
+   */
+
+/**    
+ * @brief  Core Real FFT process    
+ * @param[in]   *pSrc 				points to the input buffer.    
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+ * @param[out]  *pDst 				points to the output buffer.    
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ */
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*    
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+    /* write output */
+    *pOut1++ = (outR << 1u);
+    *pOut1++ = (outI << 1u);
+
+    /* write complex conjugate output */
+    *pOut2-- = -(outI << 1u);
+    *pOut2-- = (outR << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+}
+
+
+/**    
+ * @brief  Core Real IFFT process    
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.    
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.    
+ */
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*    
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
+
+     */
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pIn[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* - pIn[2 * i] * pATable[2 * i + 1] */
+    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+    /* pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+    /* write output */
+    *pDst++ = (outR << 1u);
+    *pDst++ = (outI << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+
+  }
+
+
+}
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--- /dev/null
+++ b/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html
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+
+
+
+
+MISRA-C:2004 Compliance Exceptions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
MISRA-C:2004 Compliance Exceptions 
  

+

+

+
CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .

+
CMSIS-CORE violates the following MISRA-C:2004 rules:

+
    
+
  • Required Rule 8.5, object/function definition in header file.
    
+ Violated since function definitions in header files are used to allow 'inlining'.
    • 
+

+
    
+
  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+ Violated since unions are used for effective representation of core registers.
    • 
+

+
    
+
  • Advisory Rule 19.7, Function-like macro defined.
    
+ Violated since function-like macros are used to allow more efficient code. 
    • 
+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/_reg_map_pg.html b/CMSIS/Documentation/Core/html/_reg_map_pg.html
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--- /dev/null
+++ b/CMSIS/Documentation/Core/html/_reg_map_pg.html
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+
+
+
+
+Register Mapping
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Register Mapping 
  

+

+

+
The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.

+
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+
+
CMSIS Register Name Cortex-M3 and Cortex-M4 Cortex-M0 and Cortex-M0+ Register Name  
Nested Vectored Interrupt Controller (NVIC) Register Access  
NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers  
NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers  
NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers  
NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers  
NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register  
NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register  
NVIC->STIR STIR - Software Triggered Interrupt Register  
System Control Block (SCB) Register Access  
SCB->CPUID CPUID CPUID CPUID Base Register  
SCB->ICSR ICSR ICSR Interrupt Control and State Register  
SCB->VTOR VTOR - Vector Table Offset Register  
SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register  
SCB->SCR SCR SCR System Control Register  
SCB->CCR CCR CCR Configuration and Control Register  
SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers  
SCB->SHCSR SHCSR SHCSR System Handler Control and State Register  
SCB->CFSR CFSR - Configurable Fault Status Registers  
SCB->HFSR HFSR - HardFault Status Register  
SCB->DFSR DFSR - Debug Fault Status Register  
SCB->MMFAR MMFAR - MemManage Fault Address Register  
SCB->BFAR BFAR - BusFault Address Register  
SCB->AFSR AFSR - Auxiliary Fault Status Register  
SCB->PFR[] ID_PFR0..1 - Processor Feature Registers  
SCB->DFR ID_DFR0 - Debug Feature Register  
SCB->ADR ID_AFR0 - Auxiliary Feature Register  
SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers  
SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers  
SCB->CPACR CPACR - Coprocessor Access Control Register  
System Control and ID Registers not in the SCB (SCnSCB) Register Access  
SCnSCB->ICTR ICTR - Interrupt Controller Type Register  
SCnSCB->ACTLR ACTLR - Auxiliary Control Register  
System Timer (SysTick) Control and Status Register Access  
SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register  
SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register  
SysTick->VAL STCVR SYST_CVR SysTick Current Value Register  
SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register  
Data Watchpoint and Trace (DWT) Register Access  
DWT->CTRL DWT_CTRL - Control Register  
DWT->CYCCNT DWT_CYCCNT - Cycle Count Register  
DWT->CPICNT DWT_CPICNT - CPI Count Register  
DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register  
DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register  
DWT->LSUCNT DWT_LSUCNT - LSU Count Register  
DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register  
DWT->PCSR DWT_PCSR - Program Counter Sample Register  
DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3  
DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3  
DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3  
Instrumentation Trace Macrocell (ITM) Register Access  
ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers  
ITM->TER ITM_TER - Trace Enable Register  
ITM->TPR ITM_TPR - ITM Trace Privilege Register  
ITM->TCR ITM_TCR - Trace Control Register  
Trace Port Interface (TPIU) Register Access  
TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register  
TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register  
TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register  
TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register  
TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register  
TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register  
TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register  
TPI->TRIGGER TRIGGER - TRIGGER  
TPI->FIFO0 FIFO data 0 - Integration ETM Data  
TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2  
TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0  
TPI->FIFO1 FIFO data 1 - Integration ITM Data  
TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control  
TPI->CLAIMSET CLAIMSET - Claim tag set  
TPI->CLAIMCLR CLAIMCLR - Claim tag clear  
TPI->DEVID TPIU_DEVID - TPIU_DEVID  
TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE  
Memory Protection Unit (MPU) Register Access  
MPU->TYPE MPU_TYPE - MPU Type Register  
MPU->CTRL MPU_CTRL - MPU Control Register  
MPU->RNR MPU_RNR - MPU Region Number Register  
MPU->RBAR MPU_RBAR - MPU Region Base Address Register  
MPU->RASR MPU_RASR - MPU Region Attribute and Size Register  
MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register  
MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register  
Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]  
FPU->FPCCR FPCCR - FP Context Control Register  
FPU->FPCAR FPCAR - FP Context Address Register  
FPU->FPDSCR FPDSCR - FP Default Status Control Register  
FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/_templates_pg.html b/CMSIS/Documentation/Core/html/_templates_pg.html
new file mode 100644
index 0000000000..fbaf46331f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/_templates_pg.html
@@ -0,0 +1,215 @@
+
+
+
+
+Template Files
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Template Files 
  

+

+

+
ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliancy. These template files include the following:

+
    
+
  • Register names of the Core Peripherals and names of the Core Exception Vectors.
    • 
+
  • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4)
    • 
+
  • Generic startup code and system configuration code.
    • 
+

+
The detailed file structure of the CMSIS-CORE is shown in the following picture.

+

+CMSIS_CORE_Files.png
+

+CMSIS-CORE File Structure

+ 

+Template Files

+
The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:

+
    
+
  • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
    • 
+
  • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
    • 
+
  • Interrupt vectors in the startup file that are device specific.
    • 
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Template File Description  
".\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s" Startup file template for ARM C/C++ Compiler.  
".\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s" Startup file template for GNU GCC ARM Embedded Compiler.  
".\Device\_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s" Startup file template for GNU Sourcery G++ Compiler.  
".\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s" Startup file template for IAR C/C++ Compiler.  
".\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c" Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).  
".\Device\_Template_Vendor\Vendor\Device\Include\Device.h" Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.  
".\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h" Generic system device configuration include file.  

+
In addition ARM provides the following core header files that do not need any modifications.

+
+
+
+
+
+
+
+
+
+
+
+
Core Header Files Description  
core_<cpu>.h Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
    
+
  • core_cm0.h: for the Cortex-M0 processor
    • 
+
  • core_cm0plus.h: for the Cortex-M0+ processor
    • 
+
  • core_cm3.h: for the Cortex-M0 processor
    • 
+
  • core_cm4.h: for the Cortex-M0 processor
    • 
+
  • core_sc000.h: for the SecurCore SC000 processor
    • 
+
  • core_sc300.h: for the SecurCore SC300 processor   
    • 
+

+
core_cmInstr.h Defines intrinsic functions to access special Cortex-M instructions.  
core_cmFunc.h Defines functions to access the Cortex-M core peripherals.  
core_cm4_simd.h Defines intrinsic functions to access the Cortex-M4 SIMD instructions.  

+

+Adaption of Template Files to Devices

+
Copy the complete folder including files and replace:

+
    
+
  • folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
    • 
+
  • folder name 'Device' with the specific device name e.g.: LPC17xx.
    • 
+
  • in the filenames 'Device' with the specific device name e.g.: LPC17xx.
    • 
+

+
Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:

+
+
+
+
+
+
+
+
+
+
+
+
Placeholder Replaced with  
<Device> the specific device name or device family name; i.e. LPC17xx.  
<DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1. 
<DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.  
Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.  

+
The adaption of the template files is described in detail on the following pages:

+
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html b/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
new file mode 100644
index 0000000000..a69504c8e7
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
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+
+
+
+
+Using CMSIS with generic ARM Processors
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Using CMSIS with generic ARM Processors 
  

+

+

+
ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Folder Processor Description  
".\Device\ARM\ARMCM0" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.   
".\Device\ARM\ARMCM0plus" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.   
".\Device\ARM\ARMCM3" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.   
".\Device\ARM\ARMCM4" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.   
".\Device\ARM\ARMSC000" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.   
".\Device\ARM\ARMSC300" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.   

+

+Create generic Libraries with CMSIS

+
The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP  Libraries are an example for such a generic library.

+
To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.

+
Example: 

+
The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define CORTEX_M4, CORTEX_M3, or CORTEX_M0. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4], and Debug Access.

+
#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
+
+#if defined (CORTEX_M4)
+  #include "core_cm4.h"
+#elif defined (CORTEX_M3)
+  #include "core_cm3.h"
+#elif defined (CORTEX_M0)
+  #include "core_cm0.h"
+#elif defined (CORTEX_M0PLUS)
+  #include "core_cm0plus.h"
+#else
+  #error "Processor not specified or unsupported."
+#endif
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/_using_pg.html b/CMSIS/Documentation/Core/html/_using_pg.html
new file mode 100644
index 0000000000..4e6a54b04d
--- /dev/null
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@@ -0,0 +1,216 @@
+
+
+
+
+Using CMSIS in Embedded Applications
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Using CMSIS in Embedded Applications 
  

+

+

+
To use the CMSIS-CORE the following files are added to the embedded application:

+
+
Note:
The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.

+
The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

+
The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

+
The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

+
+

+CMSIS_CORE_Files_user.png
+

+CMSIS-CORE User Files

+
 The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. Using CMSIS with generic ARM Processors explains how to use CMSIS-CORE for ARM processors.

+
For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:

+
+
+
+
+
+
+
+
+
+
+
+
File Description  
".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.  
".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.  
".\ARM\INC\ST\STM32F10x\stm32f10x.h" Device Header File <device.h> for the STM32F10x device families.  
".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" system_Device.h Template File for the STM32F10x device families.  

+
Note:
The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.

+
Thereafter, the functions described under Reference  can be used in the application.

+
A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.

+
#include <stm32f10x.h>                           // File name depends on device used
+
+uint32_t volatile msTicks;                       // Counter for millisecond Interval
+
+void SysTick_Handler (void) {                    // SysTick Interrupt Handler
+  msTicks++;                                     // Increment Counter
+}
+
+void WaitForTick (void)  {
+  uint32_t curTicks;
+
+  curTicks = msTicks;                            // Save Current SysTick Value
+  while (msTicks == curTicks)  {                 // Wait for next SysTick Interrupt
+    __WFE ();                                    // Power-Down until next Event/Interrupt
+  }
+}
+
+void TIM1_UP_IRQHandler (void) {                 // Timer Interrupt Handler
+  ;                                              // Add user code here
+}
+
+void timer1_init(int frequency) {                // Set up Timer (device specific)
+  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
+  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
+}
+
+
+void Device_Initialization (void)  {             // Configure & Initialize MCU
+  if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
+       : // Handle Error 
+  }
+  timer1_init ();                                // setup device-specific timer
+}
+
+
+// The processor clock is initialized by CMSIS startup + system file
+void main (void) {                                   // user application starts here
+  Device_Initialization ();                      // Configure & Initialize MCU
+  while (1)  {                                   // Endless Loop (the Super-Loop)
+    __disable_irq ();                            // Disable all interrupts
+    Get_InputValues ();                          // Read Values
+    __enable_irq ();                             // Enable all interrupts 
+    Calculation_Response ();                     // Calculate Results
+    Output_Response ();                          // Output Results
+    WaitForTick ();                              // Synchronize to SysTick Timer
+  }
+}
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/annotated.html b/CMSIS/Documentation/Core/html/annotated.html
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--- /dev/null
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+
+
+
+
+Data Structures
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Data Structures
  

+

+

+
Here are the data structures with brief descriptions:

+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
APSR_TypeUnion type to access the Application Program Status Register (APSR) 
CONTROL_TypeUnion type to access the Control Registers (CONTROL) 
CoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug) 
DWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT) 
FPU_TypeStructure type to access the Floating Point Unit (FPU) 
IPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR) 
ITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM) 
MPU_TypeStructure type to access the Memory Protection Unit (MPU) 
NVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC) 
SCB_TypeStructure type to access the System Control Block (SCB) 
SCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB 
SysTick_TypeStructure type to access the System Timer (SysTick) 
TPI_TypeStructure type to access the Trace Port Interface Register (TPI) 
xPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR) 

+

+

+  
+
+
+
+
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+
+
+
+
+Data Structure Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Data Structure Index
  

+

+

+
A | C | D | F | I | M | N | S | T | X

+
+
+
+
+
+
+
+
+
+
+
+
  A  

+
  D  

+		ITM_Type   
  S  

+
  X  

+
  M  

+
APSR_Type   DWT_Type   SCB_Type   xPSR_Type   
  C  

+
  F  

+		MPU_Type   SCnSCB_Type   
  N  

+		SysTick_Type   
CONTROL_Type   FPU_Type   
  T  

+
CoreDebug_Type   
  I  

+		NVIC_Type   
TPI_Type   
IPSR_Type   

+
A | C | D | F | I | M | N | S | T | X

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/closed.png b/CMSIS/Documentation/Core/html/closed.png
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diff --git a/CMSIS/Documentation/Core/html/cmsis.css b/CMSIS/Documentation/Core/html/cmsis.css
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index 0000000000..a5c4b8de50
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/CMSIS/Documentation/Core/html/device_h_pg.html b/CMSIS/Documentation/Core/html/device_h_pg.html
new file mode 100644
index 0000000000..463bf6b5ef
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/device_h_pg.html
@@ -0,0 +1,516 @@
+
+
+
+
+Device Header File <device.h>
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Device Header File <device.h> 
  

+

+

+
The Device Header File <device.h> contains the following sections that are device specific:

+
    
+
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • 
+
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • 
+
  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • 
+
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • 
+

+
Reference  describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+
Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

+
    
+
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • 
+
  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
    • 
+

+
Example: 

+
The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      
+  HardFault_IRQn                = -13,      
+  SVCall_IRQn                   = -5,       
+  PendSV_IRQn                   = -2,       
+  SysTick_IRQn                  = -1,       
+/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+  WAKEUP0_IRQn                  = 0,        
+  WAKEUP1_IRQn                  = 1,        
+  WAKEUP2_IRQn                  = 2,
+                 :       :
+                 :       :
+  EINT1_IRQn                    = 30,       
+  EINT0_IRQn                    = 31,       
+} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+
The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+
The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+
core_cm0.h 

+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
core_cm0plus.h 

+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
core_cm3.h 

+
+
+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
core_cm4.h 

+
+
+
+
+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
core_sc000.h 

+
+
+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
core_sc300.h 

+
+
+
+
+
+
+
+
+
+
+
+
#define Value Range Default Description  
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  

+
Example 

+
The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

+
#define __CM4_REV                 0x0001    /* Core revision r0p1                                 */
+#define __MPU_PRESENT             1         /* MPU present or not                                 */
+#define __NVIC_PRIO_BITS          3         /* Number of Bits used for Priority Levels            */
+#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used       */
+#define __FPU_PRESENT             1         /* FPU present or not                                 */
+.
+.
+#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */
+

+CMSIS Version and Processor Information

+
Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+
core_cm0.h 

+
#define __CM0_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION         ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM0_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x00)                                   /* Cortex-M Core                    */
+
core_cm0plus.h 

+
#define __CM0PLUS_CMSIS_VERSION_MAIN   (0x03)                                /* [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB    (0x00)                                /* [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION        ((__CM0P_CMSIS_VERSION_MAIN << 16) | \
+                                     __CM0P_CMSIS_VERSION_SUB          )  /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x00)                                /* Cortex-M Core                    */
+
core_cm3.h 

+
#define __CM3_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION         ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM3_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x03)                                   /* Cortex-M Core                    */
+
core_cm4.h 

+
#define __CM4_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION         ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM4_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x04)                                   /* Cortex-M Core                    */
+
core_sc000.h 

+
#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
+...    
+#define __CORTEX_SC                 (0)                                      /* Cortex secure core             */
+
core_sc300.h 

+
#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
+...    
+#define __CORTEX_SC                 (300)                                    /* Cortex secure core             */
+

+Device Peripheral Access Layer

+
The Device Header File <device.h> contains for each peripheral:

+
    
+
  • Register Layout Typedef
    • 
+
  • Base Address
    • 
+
  • Access Definitions
    • 
+

+
The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+
The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */
+/** @addtogroup <Device>_Definitions <Device> Definitions
+  This file defines all structures and symbols for <Device>:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - Peripheral definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M# Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/******  Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
+  <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device                                                    */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a CORTEX-M0 device
+         __CM3_REV if your device is a CORTEX-M3 device
+         __CM4_REV if your device is a CORTEX-M4 device                                           */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
+#define __FPU_PRESENT             0        /*!< FPU present or not                                */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device                                          */
+#include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name                                                 */
+#include "system_<Device>.h"                /* <Device> System  include file                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup <Device>_Peripherals <Device> Peripherals
+  <Device> Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */               
+  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
+  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
+  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
+       uint32_t RESERVED0[1];
+  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
+  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
+  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
+  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
+       uint32_t RESERVED1[2];
+  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
+} <DeviceAbbreviation>_TMR_TypeDef;
+/*@}*/ /* end of group <Device>_TMR */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses                
+         following is an example for timer                                    */
+/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+/*@}*/ /* end of group <Device>_MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions                
+         following is an example for timer                                    */
+
+/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
+  @{
+*/
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+/*@}*/ /* end of group <Device>_PeripheralDecl */
+
+/*@}*/ /* end of group <Device>_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
 

+

+  
+
+
+
+
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+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- _ -

+
+
+
- a -

+
+
+
- b -

+
+
+
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+
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+
- z -

+

+

+  
+
+
+
+
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+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- _ -

+
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+
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+
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- v -

+
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+
- w -

+
+
+
- z -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/globals.html b/CMSIS/Documentation/Core/html/globals.html
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+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- _ -

+
+
+
- b -

+
+
+
- d -

+
+
+
- h -

+
+
+
- i -

+
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+
+
+
- p -

+
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+
+
+
- u -

+
+
+
- w -

+

+

+  
+
+
+
+
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+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

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+ 
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diff --git a/CMSIS/Documentation/Core/html/globals_eval.html b/CMSIS/Documentation/Core/html/globals_eval.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/Core/html/globals_eval.html
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+Index
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+  
+  
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+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

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+ 
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+  
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diff --git a/CMSIS/Documentation/Core/html/globals_func.html b/CMSIS/Documentation/Core/html/globals_func.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/Core/html/globals_func.html
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+Index
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- _ -

+
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+
- i -

+
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+
- n -

+
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+
- s -

+

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+  
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diff --git a/CMSIS/Documentation/Core/html/globals_vars.html b/CMSIS/Documentation/Core/html/globals_vars.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/Core/html/globals_vars.html
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+
+
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+
+Index
+
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group___core___register__gr.html b/CMSIS/Documentation/Core/html/group___core___register__gr.html
new file mode 100644
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+
+
+
+
+Core Register Access
+
+
+
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+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Core Register Access
  

+

+

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+Functions
uint32_t __get_CONTROL (void)
 Read the CONTROL register.  
void __set_CONTROL (uint32_t control)
 Set the CONTROL Register.  
uint32_t __get_IPSR (void)
 Read the IPSR register.  
uint32_t __get_APSR (void)
 Read the APSR register.  
uint32_t __get_xPSR (void)
 Read the xPSR register.  
uint32_t __get_PSP (void)
 Read the PSP register.  
void __set_PSP (uint32_t topOfProcStack)
 Set the PSP register.  
uint32_t __get_MSP (void)
 Read the MSP register.  
void __set_MSP (uint32_t topOfMainStack)
 Set the MSP register.  
uint32_t __get_PRIMASK (void)
 Read the PRIMASK register bit.  
void __set_PRIMASK (uint32_t priMask)
 Set the Priority Mask bit.  
uint32_t __get_BASEPRI (void)
 Read the BASEPRI register [not for Cortex-M0 variants].  
void __set_BASEPRI (uint32_t basePri)
 Set the BASEPRI register [not for Cortex-M0 variants].  
uint32_t __get_FAULTMASK (void)
 Read the FAULTMASK register [not for Cortex-M0 variants].  
void __set_FAULTMASK (uint32_t faultMask)
 Set the FAULTMASK register [not for Cortex-M0 variants].  
uint32_t __get_FPSCR (void)
 Read the FPSCR register [only for Cortex-M4].  
void __set_FPSCR (uint32_t fpscr)
 Set the FPSC register [only for Cortex-M4].  
void __enable_irq (void)
 Globally enables interrupts and configurable fault handlers.  
void __disable_irq (void)
 Globally disables interrupts and configurable fault handlers.  
void __enable_fault_irq (void)
 Enables interrupts and all fault handlers [not for Cortex-M0 variants].  
void __disable_fault_irq (void)
 Disables interrupts and all fault handlers [not for Cortex-M0 variants].  

+
Description

+
The following functions provide access to Cortex-M core registers. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __disable_fault_irq (void )

+

+

+
The function disables interrupts and all fault handlers by setting the F-bit in the CPSR. The function uses the instruction CPSID f.

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Can be executed in privileged mode only.
    • 
+
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __disable_irq (void )

+

+

+
The function disables interrupts and all configurable fault handlers by setting the I-bit in the CPSR. The function uses the instruction CPSID i.

+
Remarks:
    
+
  • Can be executed in privileged mode only.
    • 
+
  • Basically, it sets PRIMASK.
    • 
+
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __enable_fault_irq (void )

+

+

+
The function enables interrupts and all fault handlers by clearing the F-bit in the CPSR. The function uses the instruction CPSIE f.

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Can be executed in privileged mode only.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __enable_irq (void )

+

+

+
The function enables interrupts and all configurable fault handlers by clearing the I-bit in the CPSR. The function uses the instruction CPSIE i.

+
Remarks:
    
+
  • Can be executed in privileged mode only.
    • 
+
  • Basically, it clears PRIMASK.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_APSR (void )

+

+

+
The function reads the Application Program Status Register (APSR) using the instruction MRS. 

+

+ The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

+
    
+
  • N (APSR[31]) (Negative flag)
      
+
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • 
+
    • =0 The instruction result has a positive value or equal zero. 
      
+
      
+
      • 
+
    
+
    • 
+
  • Z (APSR[30]) (Zero flag)
      
+
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. 
      
+
      
+
      • 
+
    
+
    • 
+
  • C (APSR[29]) (Carry or borrow flag)
      
+
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • 
+
    • =inverse of borrow output status For unsigned subtract operations. 
      
+
      
+
      • 
+
    
+
    • 
+
  • V (APSR[28]) (Overflow flag)
      
+
    • =1 A signed overflow occurred (for signed additions or subtractions). 
      
+
      
+
      • 
+
    
+
    • 
+
  • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
      
+
    • This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
      • 
+
    • =1 When saturation or an overflow occurred. 
      
+
      
+
      • 
+
    
+
    • 
+
  • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
      
+
    • Can be set by the parallel add and subtract instructions.
      • 
+
    • Are used by the SEL instruction to perform byte-based selection from two registers.
      • 
+
    
+
    • 
+

+
Returns:
APSR register value

+
Remarks:
    
+
  • Some instructions update all flags; some instructions update a subset of the flags.
    • 
+
  • If a flag is not updated, the original value is preserved.
    • 
+
  • Conditional instructions that are not executed have no effect on the flags.
    • 
+
  • The CMSIS does not provide a function to update this register.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_BASEPRI (void )

+

+

+
The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS. 

+

+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Returns:
BASEPRI register value

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_CONTROL (void )

+

+

+
The function reads the CONTROL register value using the instruction MRS. 

+

+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: 

+

+
    
+
  • CONTROL[2] [only Cortex-M4]
      
+
    • =0 FPU not active
      • 
+
    • =1 FPU active 
      
+
      
+
      • 
+
    
+
    • 
+
  • CONTROL[1]
      
+
    • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
      • 
+
    • =0 In thread mode - Default stack pointer MSP is used.
      • 
+
    • =1 In thread mode - Alternate stack pointer PSP is used. 
      
+
      
+
      • 
+
    
+
    • 
+
  • CONTROL[0] [not Cortex-M0]
      
+
    • =0 In thread mode and privileged state.
      • 
+
    • =1 In thread mode and user state.
      • 
+
    
+
    • 
+

+
Returns:
CONTROL register value

+
Remarks:
    
+
  • The processor can be in user state or privileged state when running in thread mode.
    • 
+
  • Exception handlers always run in privileged state.
    • 
+
  • On reset, the processor is in thread mode with privileged access rights.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_FAULTMASK (void )

+

+

+
The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS. 

+

+ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

+
Returns:
FAULTMASK register value

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_FPSCR (void )

+

+

+
The function reads the Floating-Point Status Control Register (FPSCR) value. 

+

+ FPSCR provides all necessary User level controls of the floating-point system.

+
Returns:
    
+
  • FPSCR register value, when __FPU_PRESENT=1
    • 
+
  • =0, when __FPU_PRESENT=0
    • 
+

+

+
Remarks:
    
+
  • Only for Cortex-M4.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_IPSR (void )

+

+

+
The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS. 

+

+ The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

+
    
+
  • ISR_NUMBER (IPSR[8:0])
      
+
    • =0 Thread mode
      • 
+
    • =1 Reserved
      • 
+
    • =2 NMI
      • 
+
    • =3 HardFault
      • 
+
    • =4 MemManage
      • 
+
    • =5 BusFault
      • 
+
    • =6 UsageFault
      • 
+
    • =7-10 Reserved
      • 
+
    • =11 SVCall
      • 
+
    • =12 Reserved for Debug
      • 
+
    • =13 Reserved
      • 
+
    • =14 PendSV
      • 
+
    • =15 SysTick
      • 
+
    • =16 IRQ0
      • 
+
    • ...
      • 
+
    • =n+15 IRQ(n-1)
      • 
+
    
+
    • 
+

+
Returns:
ISPR register value

+
Remarks:
    
+
  • This register is read-only.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_MSP (void )

+

+

+
The function reads the Main Status Pointer (MSP) value using the instruction MRS. 

+

+ Physically two different stack pointers (SP) exist:

+
    
+
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • 
+
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • 
+

+
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    
+
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • 
+
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • 
+

+
Returns:
MSP Register value

+
Remarks:
    
+
  • Only one of the two SPs is visible at a time.
    • 
+
  • For many applications, the system can completely rely on the MSP.
    • 
+
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_PRIMASK (void )

+

+

+
The function reads the Priority Mask register (PRIMASK) value using the instruction MRS. 

+

+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Returns:
PRIMASK register value
    
+
  • =0 no effect
    • 
+
  • =1 prevents the activation of all exceptions with configurable priority
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_PSP (void )

+

+

+
The function reads the Program Status Pointer (PSP) value using the instruction MRS. 

+

+ Physically two different stack pointers (SP) exist:

+
    
+
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • 
+
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • 
+

+
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    
+
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • 
+
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • 
+

+
Returns:
PSP register value

+
Remarks:
    
+
  • Only one of the two SPs is visible at a time.
    • 
+
  • For many applications, the system can completely rely on the MSP.
    • 
+
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __get_xPSR (void )

+

+

+
The function reads the combined Program Status Register (xPSR) using the instruction MRS. 

+

+ xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: 

+
    
+
  • Application Program Status Register (APSR) 
    • 
+
  • Interrupt Program Status Register (IPSR) 
    • 
+
  • Execution Program Status Register (EPSR)
    • 
+

+
In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

+
    
+
  • IT (xPSR[26:25]) (If-Then condition instruction)
      
+
    • Contains up to four instructions following an IT instruction.
      • 
+
    • Each instruction in the block is conditional.
      • 
+
    • The conditions for the instructions are either all the same, or some can be the inverse of others. 
      
+
      
+
      • 
+
    
+
    • 
+
  • T (xPSR[24]) (Thumb bit)
      
+
    • =1 Indicates that that the processor is in Thumb state.
      • 
+
    • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
      • 
+
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      • 
+
    
+
    • 
+

+
Returns:
xPSR register value

+
Remarks:
    
+
  • The CMSIS does not provide functions that access EPSR.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_BASEPRI (uint32_t basePri)

+

+

+
The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR. 

+

+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Parameters:

+  
+    
+  
[in]basePriBASEPRI value to set

+  

+

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Cannot be set in user state.
    • 
+
  • Useful for changing the masking level or disabling the masking.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_CONTROL (uint32_t control)

+

+

+
The function sets the CONTROL register value using the instruction MSR. 

+

+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: 

+

+
    
+
  • CONTROL[2] [only Cortex-M4]
      
+
    • =0 FPU not active
      • 
+
    • =1 FPU active 
      
+
      
+
      • 
+
    
+
    • 
+
  • CONTROL[1]
      
+
    • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
      • 
+
    • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
      • 
+
    • =0 In thread mode - Default stack pointer MSP is used.
      • 
+
    • =1 In thread mode - Alternate stack pointer PSP is used. 
      
+
      
+
      • 
+
    
+
    • 
+
  • CONTROL[0] [not writeable for Cortex-M0]
      
+
    • Writeable only when the processor is in privileged state.
      • 
+
    • Can be used to switch the processor to user state (thread mode).
      • 
+
    • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
      • 
+
    • =0 In thread mode and privileged state.
      • 
+
    • =1 In thread mode and user state.
      • 
+
    
+
    • 
+

+
Parameters:

+  
+    
+  
[in]controlCONTROL register value to set

+  

+

+
Remarks:
    
+
  • The processor can be in user state or privileged state when running in thread mode.
    • 
+
  • Exception handlers always run in privileged state.
    • 
+
  • On reset, the processor is in thread mode with privileged access rights.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_FAULTMASK (uint32_t faultMask)

+

+

+
The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR. 

+

+ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

+
    
+
  1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
    2. 
+
  2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
    3. 
+

+
Parameters:

+  
+    
+  
[in]faultMaskFAULTMASK register value to set

+  

+

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • 
+
  • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
    • 
+
  • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
    • 
+
  • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_FPSCR (uint32_t fpscr)

+

+

+
The function sets the Floating-Point Status Control Register (FPSCR) value. 

+

+ FPSCR provides all necessary User level control of the floating-point system. 

+

+
    
+
  • N (FPSC[31]) (Negative flag)
      
+
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • 
+
    • =0 The instruction result has a positive value or equal zero. 
      
+
      
+
      • 
+
    
+
    • 
+
  • Z (FPSC[30]) (Zero flag)
      
+
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. 
      
+
      
+
      • 
+
    
+
    • 
+
  • C (FPSC[29]) (Carry or borrow flag)
      
+
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • 
+
    • =inverse of borrow output status For unsigned subtract operations. 
      
+
      
+
      • 
+
    
+
    • 
+
  • V (FPSC[28]) (Overflow flag)
      
+
    • =1 A signed overflow occurred (for signed additions or subtractions). 
      
+
      
+
      • 
+
    
+
    • 
+
  • AHP (FPSC[26]) (Alternative half-precision flag)
      
+
    • =1 Alternative half-precision format selected.
      • 
+
    • =0 IEEE half-precision format selected. 
      
+
      
+
      • 
+
    
+
    • 
+
  • DN (FPSC[25]) (Default NaN mode control flag)
      
+
    • =1 Any operation involving one or more NaNs returns the Default NaN.
      • 
+
    • =0 NaN operands propagate through to the output of a floating-point operation. 
      
+
      
+
      • 
+
    
+
    • 
+
  • FZ (FPSC[24]) (Flush-to-zero mode control flag)
      
+
    • =1 Flush-to-zero mode enabled.
      • 
+
    • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 
      
+
      
+
      • 
+
    
+
    • 
+
  • RMode (FPSC[23:22]) (Rounding Mode control flags)
      
+
    • =0b00 Round to Nearest (RN) mode.
      • 
+
    • =0b01 Round towards Plus Infinity (RP) mode.
      • 
+
    • =0b10 Round towards Minus Infinity (RM) mode.
      • 
+
    • =0b11 Round towards Zero (RZ) mode.
      • 
+
    • The specified rounding mode is used by almost all floating-point instructions. 
      
+
      
+
      • 
+
    
+
    • 
+
  • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
      
+
    • See Cumulative exception bits (FPSC[4:0]). 
      
+
      
+
      • 
+
    
+
    • 
+
  • IXC (FPSC[4]) (Inexact cumulative exception flag)
      
+
    • =1 Exception occurred.
      • 
+
    • =0 Value has to be set explicitly.
      • 
+
    • Flag is not cleared automatically. 
      
+
      
+
      • 
+
    
+
    • 
+
  • UFC (FPSC[3]) (Underflow cumulative exception flag)
      
+
    • =1 Exception occurred.
      • 
+
    • =0 Value has to be set explicitly.
      • 
+
    • Flag is not cleared automatically. 
      
+
      
+
      • 
+
    
+
    • 
+
  • OFC (FPSC[2]) (Overflow cumulative exception flag)
      
+
    • =1 Exception occurred.
      • 
+
    • =0 Value has to be set explicitly.
      • 
+
    • Flag is not cleared automatically. 
      
+
      
+
      • 
+
    
+
    • 
+
  • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
      
+
    • =1 Exception occurred.
      • 
+
    • =0 Value has to be set explicitly.
      • 
+
    • Flag is not cleared automatically. 
      
+
      
+
      • 
+
    
+
    • 
+
  • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
      
+
    • =1 Exception occurred.
      • 
+
    • =0 Value has to be set explicitly.
      • 
+
    • Flag is not cleared automatically.
      • 
+
    
+
    • 
+

+
Parameters:

+  
+    
+  
[in]fpscrFPSCR value to set

+  

+

+
Remarks:
    
+
  • Only for Cortex-M4.
    • 
+
  • The variable __FPU_PRESENT has to be set to 1.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_MSP (uint32_t topOfMainStack)

+

+

+
The function sets the Main Status Pointer (MSP) value using the instruction MSR. 

+

+ Physically two different stack pointers (SP) exist:

+
    
+
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • 
+
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • 
+

+
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    
+
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • 
+
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • 
+

+
Parameters:

+  
+    
+  
[in]topOfMainStackMSP value to set

+  

+

+
Remarks:
    
+
  • Only one of the two SPs is visible at a time.
    • 
+
  • For many applications, the system can completely rely on the MSP.
    • 
+
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_PRIMASK (uint32_t priMask)

+

+

+
The function sets the Priority Mask register (PRIMASK) value using the instruction MSR. 

+

+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Parameters:

+  
+    
+  
[in]priMaskPriority Mask
    
+
  • =0 no effect
    • 
+
  • =1 prevents the activation of all exceptions with configurable priority
    • 
+

+

+  

+

+
Remarks:
    
+
  • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
    • 
+
  • When set and a fault occurs, the hard fault handler will be executed.
    • 
+
  • Useful for temprorarily disabling all interrupts for timing critical tasks.
    • 
+
  • Does not have the ability to mask BusFault or bypass MPU.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __set_PSP (uint32_t topOfProcStack)

+

+

+
The function sets the Program Status Pointer (PSP) value using the instruction MSR. 

+

+ Physically two different stack pointers (SP) exist:

+
    
+
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • 
+
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • 
+

+
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    
+
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • 
+
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • 
+

+
Parameters:

+  
+    
+  
[in]topOfProcStackPSP value to set

+  

+

+
Remarks:
    
+
  • Only one of the two SPs is visible at a time.
    • 
+
  • For many applications, the system can completely rely on the MSP.
    • 
+
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • 
+

+

+
See also:

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html b/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html
new file mode 100644
index 0000000000..08890ab137
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html
@@ -0,0 +1,278 @@
+
+
+
+
+Debug Access
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
Debug Access
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Variables
volatile int32_t ITM_RxBuffer
 external variable to receive characters  

+Functions
uint32_t ITM_SendChar (uint32_t ch)
 Transmits a character via channel 0.  
int32_t ITM_ReceiveChar (void)
 ITM Receive Character.  
int32_t ITM_CheckChar (void)
 ITM Check Character.  

+
Description

+
CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

+
The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

+
    
+
  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
    • 
+

+
    
+
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
    • 
+

+
Remarks:
    
+
  • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
    • 
+
  • The ITM channel 0 can be enabled for the user task.
    • 
+
  • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
    • 
+

+

+

+ 

+ITM Debug Support in uVision

+
In a debug session, uVision uses the Debug (printf) Viewer window to display data.

+
Direction: Microcontroller --> uVision:

+
    
+
  • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
    • 
+

+
Direction: uVision --> Microcontroller:

+
    
+
  • Check if ITM_RxBuffer variable is available (only performed once).
    • 
+
  • Read the character from the Debug (printf) Viewer window.
    • 
+
  • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
    • 
+

+
Note:
The current solution does not use a buffer mechanism for transmitting the characters.

+

+ 

+Example:

+
Example for the usage of the ITM Channel 31 for RTOS Kernels:

+
// check if debugger connected and ITM channel enabled for tracing
+if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+    (ITM->TCR & ITM_TCR_ITMENA) &&
+    (ITM->TER & (1UL >> 31))) {
+    
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+}
+
 
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
volatile int32_t ITM_RxBuffer

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t ITM_CheckChar (void )

+

+

+
This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.

+
Returns:
    
+
  • =0 - No character available
    • 
+
  • =1 - Character available 
    • 
+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t ITM_ReceiveChar (void )

+

+

+
This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Returns:
    
+
  • Received character
    • 
+
  • =1 - No character received 
    • 
+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t ITM_SendChar (uint32_t ch)

+

+

+
This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Parameters:

+  
+    
+  
[in]chCharacter to transmit

+  

+

+
Returns:
Character to transmit 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html b/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html
new file mode 100644
index 0000000000..6d1c50982a
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html
@@ -0,0 +1,1033 @@
+
+
+
+
+Interrupts and Exceptions (NVIC)
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Enumerations |
+Functions  

+  

+
Interrupts and Exceptions (NVIC)
  

+

+

+
+
Describes programming of interrupts and exception functions.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Enumerations
enum  IRQn_Type { 

+  NonMaskableInt_IRQn =  -14, 
+

+  HardFault_IRQn =  -13, 
+

+  MemoryManagement_IRQn =  -12, 
+

+  BusFault_IRQn =  -11, 
+

+  UsageFault_IRQn =  -10, 
+

+  SVCall_IRQn =  -5, 
+

+  DebugMonitor_IRQn =  -4, 
+

+  PendSV_IRQn =  -2, 
+

+  SysTick_IRQn =  -1, 
+

+  WWDG_STM_IRQn =  0, 
+

+  PVD_STM_IRQn =  1
+

+ }
 Definition of IRQn numbers.  More...

+Functions
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0 variants].  
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0 variants].  
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable an external interrupt.  
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable an external interrupt.  
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending interrupt.  
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set an interrupt to pending.  
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear an interrupt from pending.  
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the interrupt active status [not for Cortex-M0 variants].  
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt.  
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt.  
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0 variants].  
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0 variants].  
void NVIC_SystemReset (void)
 Reset the system.  

+
Description

+
ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

+
The table below describes the core exception names and their availability in various Cortex-M cores.

+
+
+
+
+
+
+
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+
+
+
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+
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+
Core Exception Name IRQn Value M0 M0p M3 M4 SC000 SC300 Description  
NonMaskableInt_IRQn -14 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 		Non Maskable Interrupt  
HardFault_IRQn -13 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 		Hard Fault Interrupt  
MemoryManagement_IRQn -12     

+check.png
+

+ 

+check.png
+

+ 		  

+check.png
+

+ 		Memory Management Interrupt  
BusFault_IRQn -11     

+check.png
+

+ 

+check.png
+

+ 		  

+check.png
+

+ 		Bus Fault Interrupt  
UsageFault_IRQn -10     

+check.png
+

+ 

+check.png
+

+ 		  

+check.png
+

+ 		Usage Fault Interrupt  
SVCall_IRQn -5 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 		SV Call Interrupt   
DebugMonitor_IRQn -4     

+check.png
+

+ 

+check.png
+

+ 		  

+check.png
+

+ 		Debug Monitor Interrupt  
PendSV_IRQn -2 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 		Pend SV Interrupt  
SysTick_IRQn -1 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 

+check.png
+

+ 		System Tick Interrupt  

+

+For Cortex-M0 and Cortex-M0+

+
The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:

+
__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+

+For Cortex-M3

+
The following exception names are fixed and define the start of the vector table for a Cortex-M3:

+
__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+

+Example

+
The following is an examples for device-specific interrupts:

+
; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+
Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

+
Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+
The user application may simply define an interrupt handler function by using the handler name as shown below.

+
void WWDG_IRQHandler(void)
+{
+  ...
+}
+

+Code Example 1

+
The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.

+
#include "LPC17xx.h"
+
+uint32_t priorityGroup;                                     /* Variables to store priority group and priority */
+uint32_t priority;
+uint32_t preemptPriority;
+uint32_t subPriority;
+
+
+int main (void)  {
+
+  NVIC_SetPriorityGrouping(5);                              /* Set priority group to 5:
+                                                               Bit[7..6] preempt priority Bits, 
+                                                               Bit[5..3] subpriority Bits 
+                                                               (valid for five priority bits) */
+     
+  priorityGroup =  NVIC_GetPriorityGrouping();              /* Get used priority grouping */
+
+  priority = NVIC_EncodePriority(priorityGroup, 1, 6);      /* Encode priority with 6 for subpriority and 1 for preempt priority
+                                                               Note: priority depends on the used priority grouping */
+                                                               
+  NVIC_SetPriority(UART0_IRQn, priority);                   /* Set new priority */
+
+  priority =  NVIC_GetPriority(UART0_IRQn);                 /* Retrieve priority again */    
+
+  NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+  while(1);
+}
+

+Code Example 2

+
The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.

+
#include "LPC17xx.h"
+
+uint32_t active;                                            /* Variable to store interrupt active state */
+
+
+void TIMER0_IRQHandler(void)  {                             /* Timer 0 interrupt handler  */
+
+  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occured */ 
+    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occured */
+  }
+  active = NVIC_GetActive(TIMER0_IRQn);                     /* Get interrupt active state of timer 0 */
+}
+
+
+int main (void) {
+                                                            /* Set match channel register MR0 to 1 millisecond */
+  LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1);     /* 1 ms? */
+  
+  LPC_TIM0->MCR = (3 << 0);                                 /* Enable interrupt and reset for match channel MR0 */
+
+  NVIC_EnableIRQ(TIMER0_IRQn);                              /* Enable NVIC interrupt for timer 0 */
+  
+  LPC_TIM0->TCR = (1 << 0);                                 /* Enable timer 0 */
+
+  while(1);
+}
+
 
Enumeration Type Documentation

+
+

+

+      
+        
+          
+        
+      
enum IRQn_Type

+

+

+
The core exception enumeration names for IRQn values are defined in the file device.h.

+
Negative IRQn values represent processor core exceptions (internal interrupts). Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.

+
The table below describes the core exception names and their availability in various Cortex-M cores. 

+
Enumerator: 

+
+
+
+
+
+
+
+
+
+
+
+
NonMaskableInt_IRQn 
+
Exception 2: Non Maskable Interrupt. 

+
HardFault_IRQn 
+
Exception 3: Hard Fault Interrupt. 

+
MemoryManagement_IRQn 
+
Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. 

+
BusFault_IRQn 
+
Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. 

+
UsageFault_IRQn 
+
Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. 

+
SVCall_IRQn 
+
Exception 11: SV Call Interrupt. 

+
DebugMonitor_IRQn 
+
Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. 

+
PendSV_IRQn 
+
Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. 

+
SysTick_IRQn 
+
Exception 15: System Tick Interrupt. 

+
WWDG_STM_IRQn 
+
Device Interrupt 0: Window WatchDog Interrupt. 

+
PVD_STM_IRQn 
+
Device Interrupt 1: PVD through EXTI Line detection Interrupt. 

+

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)

+

+

+
This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Remarks:
    
+
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • 
+
  • An interrupt can have the status pending though it is not active.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void NVIC_DecodePriority (uint32_t Priority, 
uint32_t PriorityGroup, 
uint32_t * pPreemptPriority, 
uint32_t * pSubPriority 
)

+

+

+
This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]PriorityPriority 
[in]PriorityGroupPriority group 
[out]*pPreemptPriorityPreemptive priority value (starting from 0) 
[out]*pSubPrioritySubpriority value (starting from 0)

+  

+

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_DisableIRQ (IRQn_Type IRQn)

+

+

+
This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters:

+  
+    
+  
[in]IRQnNumber of the external interrupt to disable

+  

+

+
Remarks:
    
+
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_EnableIRQ (IRQn_Type IRQn)

+

+

+
This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Remarks:
    
+
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • 
+
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: 
    
+ ICTR[4:0]
      
+
    • =0 - 32 interrupts supported
      • 
+
    • =1 - 64 interrupts supported
      • 
+
    • ...
      • 
+
    
+
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, 
uint32_t PreemptPriority, 
uint32_t SubPriority 
)

+

+

+
This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters:

+  
+    
+    
+    
+  
[in]PriorityGroupPriority group 
[in]PreemptPriorityPreemptive priority value (starting from 0) 
[in]SubPrioritySubpriority value (starting from 0)

+  

+

+
Returns:
Encoded priority for the interrupt

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t NVIC_GetActive (IRQn_Type IRQn)

+

+

+
This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Returns:
    
+
  • =0 Interrupt is not active
    • 
+
  • =1 Interrupt is active, or active and pending
    • 
+

+

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • 
+
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)

+

+

+
This function returns the pending status of the specified interrupt IRQn.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Returns:
    
+
  • =0 Interrupt is not pending
    • 
+
  • =1 Interrupt is pending
    • 
+

+

+
Remarks:
    
+
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t NVIC_GetPriority (IRQn_Type IRQn)

+

+

+
This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.

+
The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Returns:
Interrupt priority

+
Remarks:
    
+
  • Each external interrupt has an associated priority-level register.
    • 
+
  • Unimplemented bits are read as zero.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t NVIC_GetPriorityGrouping (void )

+

+

+
This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

+
Returns:
Priority grouping field

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • By default, priority group setting is zero.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_SetPendingIRQ (IRQn_Type IRQn)

+

+

+
This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.

+
Parameters:

+  
+    
+  
[in]IRQnInterrupt number

+  

+

+
Remarks:
    
+
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void NVIC_SetPriority (IRQn_Type IRQn, 
uint32_t priority 
)

+

+

+
Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

+
The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

+
Parameters:

+  
+    
+    
+  
[in]IRQnInterrupt Number 
[in]priorityPriority to set

+  

+

+
Remarks:
    
+
  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
    • 
+
  • Writes to unimplemented bits are ignored.
    • 
+
  • For Cortex-M0:
      
+
    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
      • 
+
    • Supports 0 to 192 priority levels.
      • 
+
    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
      • 
+
    
+
    • 
+
  • For Cortex-M3 and Cortex-M4:
      
+
    • Dynamic switching of interrupt priority levels is supported.
      • 
+
    • Supports 0 to 255 priority levels.
      • 
+
    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
      • 
+
    
+
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)

+

+

+
The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+
Parameters:

+  
+    
+  
[in]PriorityGroupPriority group

+  

+

+
Remarks:
    
+
  • not for Cortex-M0 variants.
    • 
+
  • By default, priority group setting is zero.
    • 
+

+

+
See also:

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void NVIC_SystemReset (void )

+

+

+
This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

+
Remarks:
    
+
  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
    • 
+

+

+
See also:

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group___sys_tick__gr.html b/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
new file mode 100644
index 0000000000..0c55ae9b4e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
@@ -0,0 +1,196 @@
+
+
+
+
+Systick Timer (SYSTICK)
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Systick Timer (SYSTICK)
  

+

+

+
+
Initialize and start the SysTick timer.  
+More...

+
+
+
+
+

+Functions
uint32_t SysTick_Config (uint32_t ticks)
 System Tick Timer Configuration.  

+
Description

+
The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.

+

+Code Example

+
The code below shows the usage of the function SysTick_Config() with an LPC1700.

+
#include "LPC17xx.h"
+
+uint32_t msTicks = 0;                                       /* Variable to store millisecond ticks */
+
+                                            
+void SysTick_Handler(void)  {                               /* SysTick interrupt Handler.
+  msTicks++;                                                   See startup file startup_LPC17xx.s for SysTick vector */ 
+}
+
+
+int main (void)  {
+  uint32_t returnCode;
+
+  returnCode = SysTick_Config(SystemCoreClock / 1000);      /* Configure SysTick to generate an interrupt every millisecond */
+
+  if (returnCode != 0)  {                                   /* Check return code for errors */
+    // Error Handling 
+  }
+
+  while(1);
+}
+
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t SysTick_Config (uint32_t ticks)

+

+

+
Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.

+
Parameters:

+  
+    
+  
[in]ticksNumber of ticks between two interrupts

+  

+

+
Returns:
0 - success 

+

+1 - failure

+
Note:
When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html
new file mode 100644
index 0000000000..9935034c24
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html
@@ -0,0 +1,766 @@
+
+
+
+
+Intrinsic Functions for CPU Instructions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Intrinsic Functions for CPU Instructions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void __NOP (void)
 No Operation.  
void __WFI (void)
 Wait For Interrupt.  
void __WFE (void)
 Wait For Event.  
void __SEV (void)
 Send Event.  
void __ISB (void)
 Instruction Synchronization Barrier.  
void __DSB (void)
 Data Synchronization Barrier.  
void __DMB (void)
 Data Memory Barrier.  
uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit)  
uint32_t __REV16 (uint32_t value)
 Reverse byte order (16 bit)  
int32_t __REVSH (int32_t value)
 Reverse byte order in signed short value.  
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value [not for Cortex-M0 variants].  
uint32_t __ROR (uint32_t value, uint32_t shift)
 Rotate a value right by a number of bits.  
uint8_t __LDREXB (volatile uint8_t *addr)
 LDR Exclusive (8 bit) [not for Cortex-M0 variants].  
uint16_t __LDREXH (volatile uint16_t *addr)
 LDR Exclusive (16 bit) [not for Cortex-M0 variants].  
uint32_t __LDREXW (volatile uint32_t *addr)
 LDR Exclusive (32 bit) [not for Cortex-M0 variants].  
uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
 STR Exclusive (8 bit) [not for Cortex-M0 variants].  
uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
 STR Exclusive (16 bit) [not for Cortex-M0 variants].  
uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
 STR Exclusive (32 bit) [not for Cortex-M0 variants].  
void __CLREX (void)
 Remove the exclusive lock [not for Cortex-M0 variants].  
uint32_t __SSAT (unint32_t value, uint32_t sat)
 Signed Saturate [not for Cortex-M0 variants].  
uint32_t __USAT (uint32_t value, uint32_t sat)
 Unsigned Saturate [not for Cortex-M0 variants].  
uint8_t __CLZ (uint32_t value)
 Count leading zeros [not for Cortex-M0 variants].  

+
Description

+
The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __CLREX (void )

+

+

+
This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants]. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint8_t __CLZ (uint32_t value)

+

+

+
This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+  
[in]valueValue to count the leading zeros 

+  

+

+
Returns:
number of leading zeros in value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __DMB (void )

+

+

+
This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __DSB (void )

+

+

+
This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __ISB (void )

+

+

+
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint8_t __LDREXB (volatile uint8_t * addr)

+

+

+
This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+  
[in]*addrPointer to data 

+  

+

+
Returns:
value of type uint8_t at (*addr) 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint16_t __LDREXH (volatile uint16_t * addr)

+

+

+
This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+  
[in]*addrPointer to data 

+  

+

+
Returns:
value of type uint16_t at (*addr) 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __LDREXW (volatile uint32_t * addr)

+

+

+
This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+  
[in]*addrPointer to data 

+  

+

+
Returns:
value of type uint32_t at (*addr) 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __NOP (void )

+

+

+
This function does nothing. This instruction can be used for code alignment purposes. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __RBIT (uint32_t value)

+

+

+
This function reverses the bit order of the given value [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+  
[in]valueValue to reverse 

+  

+

+
Returns:
Reversed value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __REV (uint32_t value)

+

+

+
This function reverses the byte order in integer value.

+
Parameters:

+  
+    
+  
[in]valueValue to reverse 

+  

+

+
Returns:
Reversed value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __REV16 (uint32_t value)

+

+

+
This function reverses the byte order in two unsigned short values.

+
Parameters:

+  
+    
+  
[in]valueValue to reverse 

+  

+

+
Returns:
Reversed value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t __REVSH (int32_t value)

+

+

+
This function reverses the byte order in a signed short value with sign extension to integer.

+
Parameters:

+  
+    
+  
[in]valueValue to reverse 

+  

+

+
Returns:
Reversed value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __ROR (uint32_t value, 
uint32_t shift 
)

+

+

+
This function rotates a value right by a specified number of bits.

+
Parameters:

+  
+    
+    
+  
[in]valueValue to be shifted right 
[in]shiftNumber of bits in the range [1..31] 

+  

+

+
Returns:
Rotated value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __SEV (void )

+

+

+
Send Event is a hint instruction. It causes an event to be signaled to the CPU. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SSAT (unint32_t value, 
uint32_t sat 
)

+

+

+
This function saturates a signed value [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+    
+  
[in]valueValue to be saturated 
[in]satBit position to saturate to [1..32] 

+  

+

+
Returns:
Saturated value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __STREXB (uint8_t value, 
volatile uint8_t * addr 
)

+

+

+
This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+    
+  
[in]valueValue to store 
[in]*addrPointer to location 

+  

+

+
Returns:
0 Function succeeded 

+

+1 Function failed 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __STREXH (uint16_t value, 
volatile uint16_t * addr 
)

+

+

+
This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+    
+  
[in]valueValue to store 
[in]*addrPointer to location 

+  

+

+
Returns:
0 Function succeeded 

+

+1 Function failed 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __STREXW (uint32_t value, 
volatile uint32_t * addr 
)

+

+

+
This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+    
+  
[in]valueValue to store 
[in]*addrPointer to location 

+  

+

+
Returns:
0 Function succeeded 

+

+1 Function failed 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USAT (uint32_t value, 
uint32_t sat 
)

+

+

+
This function saturates an unsigned value [not for Cortex-M0 variants].

+
Parameters:

+  
+    
+    
+  
[in]valueValue to be saturated 
[in]satBit position to saturate to [0..31] 

+  

+

+
Returns:
Saturated value 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __WFE (void )

+

+

+
Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: 

+
    
+
  • If the event register is 0, then WFE suspends execution until one of the following events occurs:
      
+
    • An exception, unless masked by the exception mask registers or the current priority level.
      • 
+
    • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
      • 
+
    • A Debug Entry request, if Debug is enabled.
      • 
+
    • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
      • 
+
    
+
    • 
+

+
    
+
  • If the event register is 1, then WFE clears it to 0 and returns immediately. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void __WFI (void )

+

+

+
WFI is a hint instruction that suspends execution until one of the following events occurs:

+
    
+
  • A non-masked interrupt occurs and is taken.
    • 
+
  • An interrupt masked by PRIMASK becomes pending.
    • 
+
  • A Debug Entry request. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html b/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html
new file mode 100644
index 0000000000..dc102cd035
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html
@@ -0,0 +1,3079 @@
+
+
+
+
+Intrinsic Functions for SIMD Instructions [only Cortex-M4]
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Intrinsic Functions for SIMD Instructions [only Cortex-M4]
  

+

+

+
+
Access to dedicated SIMD instructions.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
uint32_t __SADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed addition.  
uint32_t __QADD8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating addition.  
uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed addition with halved results.  
uint32_t __UADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned addition.  
uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating addition.  
uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned addition with halved results.  
uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed subtraction.  
uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating subtract.  
uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed subtraction with halved results.  
uint32_t __USUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned subtract.  
uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating subtraction.  
uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned subtraction with halved results.  
uint32_t __SADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed addition.  
uint32_t __QADD16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating addition.  
uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition with halved results.  
uint32_t __UADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition.  
uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition.  
uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition with halved results.  
uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction.  
uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating subtract.  
uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction with halved results.  
uint32_t __USUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract.  
uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction.  
uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction with halved results.  
uint32_t __SASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit addition and subtraction with exchange.  
uint32_t __QASX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit add and subtract with exchange.  
uint32_t __SHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition and subtraction with halved results.  
uint32_t __UASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition and subtraction with exchange.  
uint32_t __UQASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition and subtraction with exchange.  
uint32_t __UHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition and subtraction with halved results and exchange.  
uint32_t __SSAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction and addition with exchange.  
uint32_t __QSAX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit subtract and add with exchange.  
uint32_t __SHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction and addition with halved results.  
uint32_t __USAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract and add with exchange.  
uint32_t __UQSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction and addition with exchange.  
uint32_t __UHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction and addition with halved results and exchange.  
uint32_t __USAD8 (uint32_t val1, uint32_t val2)
 Unsigned sum of quad 8-bit unsigned absolute difference.  
uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
 Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.  
uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit saturate.  
uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit unsigned saturate.  
uint32_t __UXTB16 (uint32_t val)
 Dual extract 8-bits and zero-extend to 16-bits.  
uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
 Extracted 16-bit to 32-bit unsigned addition.  
uint32_t __SXTB16 (uint32_t val)
 Dual extract 8-bits and sign extend each to 16-bits.  
uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
 Dual extracted 8-bit to 16-bit signed addition.  
uint32_t __SMUAD (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply.  
uint32_t __SMUADX (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply with exchange.  
uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with single 32-bit accumulator.  
uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.  
uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
 Dual 16-bit signed multiply with single 64-bit accumulator.  
unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Dual 16-bit signed multiply with exchange with single 64-bit accumulator.  
uint32_t __SMUSD (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply returning difference.  
uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply with exchange returning difference.  
uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply subtract with 32-bit accumulate.  
uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.  
uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
 Q setting dual 16-bit signed multiply subtract with 64-bit accumulate.  
unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.  
uint32_t __SEL (uint32_t val1, uint32_t val2)
 Select bytes based on GE bits.  
uint32_t __QADD (uint32_t val1, uint32_t val2)
 Q setting saturating add.  
uint32_t __QSUB (uint32_t val1, uint32_t val2)
 Q setting saturating subtract.  
uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3.  
uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3.  

+
Description

+
Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.

+
SIMD Features:

+
    
+
  • Simultaneous computation of 2x16-bit or 4x8-bit operands
    • 
+
  • Fractional arithmetic
    • 
+
  • User definable saturation modes (arbitrary word-width)
    • 
+
  • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
    • 
+
  • Simultaneous 8/16-bit select operations
    • 
+
  • Performance up to 3.2 GOPS at 800MHz
    • 
+
  • Performance is achieved with a "near zero" increase in power consumption on a typical implementation
    • 
+

+
Examples: 

+
Addition: Add two values using SIMD function

+
uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+  return __SADD16(val1, val2);
+}
+
Subtraction: Subtract two values using SIMD function

+
uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+  return __SSUB16(val1, val2);
+}
+
Multiplication: Performing a multiplication using SIMD function

+
uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+  return __SMUAD(val1, val2);
+}
+
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __PKHBT (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands 
val2second 16-bit operands 
val3value for left-shifting val2. Value range [0..31].

+  

+

+
Returns:
the combination of halfwords.

+
Operation:
   res[15:0]  = val1[15:0]
+   res[31:16] = val2[31:16]<<val3 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __PKHTB (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters:

+  
+    
+    
+    
+  
val1second 16-bit operands 
val2first 16-bit operands 
val3value for right-shifting val2. Value range [1..32].

+  

+

+
Returns:
the combination of halfwords.

+
Operation:
   res[15:0]  = val2[15:0]>>val3
+   res[31:16] = val1[31:16] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QADD (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to obtain the saturating add of two integers.

+ The Q bit is set if the operation saturates.

+
Parameters:

+  
+    
+    
+  
val1first summand of the saturating add operation. 
val2second summand of the saturating add operation.

+  

+

+
Returns:
the saturating addition of val1 and val2.

+
Operation:
   res[31:0] = SAT(val1 + SAT(val2 * 2))
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands. 
val2second two 16-bit summands.

+  

+

+
Returns:
    
+
  • the saturated addition of the low halfwords, in the low halfword of the return value. 
    • 
+
  • the saturated addition of the high halfwords, in the high halfword of the return value.
    • 
+

+

+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0]
+   res[31:16] = val1[31:16] + val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1. 

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands. 
val2second four 8-bit summands.

+  

+

+
Returns:
    
+
  • the saturated addition of the first byte of each operand in the first byte of the return value. 
    • 
+
  • the saturated addition of the second byte of each operand in the second byte of the return value. 
    • 
+
  • the saturated addition of the third byte of each operand in the third byte of the return value. 
    • 
+
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value. 
    • 
+

+

+
The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8] 
+   res[23:16] = val1[23:16] + val2[23:16] 
+   res[31:24] = val1[31:24] + val2[31:24]          
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters:

+  
+    
+    
+  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.

+  

+

+
Returns:
    
+
  • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • 
+

+

+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  - val2[31:16]   
+   res[31:16] = val1[31:16] + val2[15:0]  
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QSAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters:

+  
+    
+    
+  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.

+  

+

+
Returns:
    
+
  • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. 
    • 
+
  • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. 
    • 
+

+

+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QSUB (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to obtain the saturating subtraction of two integers.

+ The Q bit is set if the operation saturates.

+
Parameters:

+  
+    
+    
+  
val1minuend of the saturating subtraction operation. 
val2subtrahend of the saturating subtraction operation.

+  

+

+
Returns:
the saturating subtraction of val1 and val2.

+
Operation:
   res[31:0] = SAT(val1 - SAT(val2 * 2))
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QSUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands. 
val2second two 16-bit operands.

+  

+

+
Returns:
    
+
  • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. 
    • 
+
  • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • 
+

+

+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]
+   res[31:16] = val1[31:16] - val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __QSUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands. 
val2second four 8-bit operands.

+  

+

+
Returns:
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0] 
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed integer additions.

+ The GE bits in the APSR are set according to the results of the additions.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands. 
val2second two 16-bit summands.

+  

+

+
Returns:
    
+
  • the addition of the low halfwords in the low halfword of the return value. 
    • 
+
  • the addition of the high halfwords in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0]
+   res[31:16] = val1[31:16] + val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. 

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands. 
val2second four 8-bit summands.

+  

+

+
Returns:
    
+
  • the addition of the first bytes from each operand, in the first byte of the return value. 
    • 
+
  • the addition of the second bytes of each operand, in the second byte of the return value. 
    • 
+
  • the addition of the third bytes of each operand, in the third byte of the return value. 
    • 
+
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value. 
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 
    • 
+
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • 
+
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • 
+
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8] 
+   res[23:16] = val1[23:16] + val2[23:16] 
+   res[31:24] = val1[31:24] + val2[31:24]          
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.

+ The GE bits in the APRS are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.

+  

+

+
Returns:
    
+
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[31:16]   
+   res[31:16] = val1[31:16] + val2[15:0]  
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SEL (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.

+
Parameters:

+  
+    
+    
+  
val1four selectable 8-bit values. 
val2four selectable 8-bit values.

+  

+

+
Returns:
The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria: 
    
+
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] 
    • 
+
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] 
    • 
+
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] 
    • 
+
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] 
    • 
+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two signed 16-bit integer additions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands. 
val2second two 16-bit summands.

+  

+

+
Returns:
    
+
  • the halved addition of the low halfwords, in the low halfword of the return value. 
    • 
+
  • the halved addition of the high halfwords, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0]  >> 1
+   res[31:16] = val1[31:16] + val2[31:16] >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four signed 8-bit integer additions, halving the results. 

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands. 
val2second four 8-bit summands.

+  

+

+
Returns:
    
+
  • the halved addition of the first bytes from each operand, in the first byte of the return value. 
    • 
+
  • the halved addition of the second bytes from each operand, in the second byte of the return value. 
    • 
+
  • the halved addition of the third bytes from each operand, in the third byte of the return value. 
    • 
+
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0]  >> 1
+   res[15:8]  = val1[15:8]  + val2[15:8] >> 1
+   res[23:16] = val1[23:16] + val2[23:16] >> 1
+   res[31:24] = val1[31:24] + val2[31:24] >> 1         
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands. 
val2second 16-bit operands.

+  

+

+
Returns:
    
+
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1  
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHSAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands. 
val2second 16-bit operands.

+  

+

+
Returns:
    
+
  • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • 
+
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHSUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two signed 16-bit integer subtractions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands. 
val2second two 16-bit operands.

+  

+

+
Returns:
    
+
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. 
    • 
+
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
+   res[31:16] = val1[31:16] - val2[31:16]  >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SHSUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four signed 8-bit integer subtractions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands. 
val2second four 8-bit operands.

+  

+

+
Returns:
    
+
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0]   >> 1
+   res[15:8]  = val1[15:8]  - val2[15:8]  >> 1
+   res[23:16] = val1[23:16] - val2[23:16] >> 1
+   res[31:24] = val1[31:24] - val2[31:24] >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMLAD (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.

+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the product of each multiplication added to the accumulate value, as a 32-bit integer.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 + p2 + val3[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMLADX (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.

+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 + p2 + val3[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint64_t __SMLALD (uint32_t val1, 
uint32_t val2, 
uint64_t val3 
)

+

+

+
This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the product of each multiplication added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   sum = p1 + p2 + val3[63:32][31:0]
+   res[63:32] = sum[63:32]
+   res[31:0]  = sum[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
unsigned long long __SMLALDX (uint32_t val1, 
uint32_t val2, 
unsigned long long val3 
)

+

+

+
This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the product of each multiplication added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   sum = p1 + p2 + val3[63:32][31:0]
+   res[63:32] = sum[63:32]
+   res[31:0] = sum[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMLSD (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.

+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the difference of the product of each multiplication, added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 - p2 + val3[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMLSDX (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.

+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the difference of the product of each multiplication, added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 - p2 + val3[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint64_t __SMLSLD (uint32_t val1, 
uint32_t val2, 
uint64_t val3 
)

+

+

+
This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the difference of the product of each multiplication, added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[63:0] = p1 - p2 + val3[63:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
unsigned long long __SMLSLDX (uint32_t val1, 
uint32_t val2, 
unsigned long long val3 
)

+

+

+
This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters:

+  
+    
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.

+  

+

+
Returns:
the difference of the product of each multiplication, added to the accumulate value.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[63:0] = p1 - p2 + val3[63:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMUAD (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed multiplications, adding the products together.

+ The Q bit is set if the addition overflows.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.

+  

+

+
Returns:
the sum of the products of the two 16-bit signed multiplications.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 + p2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMUADX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.

+ The Q bit is set if the addition overflows.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.

+  

+

+
Returns:
the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 + p2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMUSD (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.

+  

+

+
Returns:
the difference of the products of the two 16-bit signed multiplications.

+
Operation:
   p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 - p2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SMUSDX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.

+  

+

+
Returns:
the difference of the products of the two 16-bit signed multiplications.

+
Operation:
   p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 - p2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SSAT16 (uint32_t val1, 
const uint32_t val2 
)

+

+

+
This function enables you to saturate two signed 16-bit values to a selected signed range.

+ The Q bit is set if either operation saturates.

+
Parameters:

+  
+    
+    
+  
val1two signed 16-bit values to be saturated. 
val2bit position for saturation, an integral constant expression in the range 1 to 16.

+  

+

+
Returns:
the sum of the absolute differences of the following bytes, added to the accumulation value: 
    
+
  • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. 
    • 
+
  • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • 
+

+

+
Operation:
   Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SSAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.

+  

+

+
Returns:
    
+
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SSUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit signed integer subtractions.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands of each subtraction. 
val2second two 16-bit operands of each subtraction.

+  

+

+
Returns:
    
+
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If 
    
+
  • res is the return value, then: 
    • 
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]
+   res[31:16] = val1[31:16] - val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SSUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four 8-bit signed integer subtractions.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands of each subtraction. 
val2second four 8-bit operands of each subtraction.

+  

+

+
Returns:
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
the results of the operation.

+
If res is the return value, then: 
    
+
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 
    • 
+
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • 
+
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • 
+
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0] 
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __SXTAB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.

+
Parameters:

+  
+    
+    
+  
val1values added to the zero-extended to 16-bit values. 
val2two 8-bit values to be extracted and zero-extended.

+  

+

+
Returns:
the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.

+
Operation:
   res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
+   res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __SXTB16 (uint32_t val)

+

+

+
This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.

+
Parameters:

+  
+    
+  
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.

+  

+

+
Returns:
the 8-bit values sign-extended to 16-bit values. 
    
+
  • sign-extended value of val[7:0] in the low halfword of the return value. 
    • 
+
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = SignExtended(val[7:0]
+   res[31:16] = SignExtended(val[23:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit unsigned integer additions.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands for each addition. 
val2second two 16-bit summands for each addition.

+  

+

+
Returns:
    
+
  • the addition of the low halfwords in each operand, in the low halfword of the return value. 
    • 
+
  • the addition of the high halfwords in each operand, in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0] 
+   res[31:16] = val1[31:16] + val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands for each addition. 
val2second four 8-bit summands for each addition.

+  

+

+
Returns:
    
+
  • the halved addition of the first bytes from each operand, in the first byte of the return value. 
    • 
+
  • the halved addition of the second bytes from each operand, in the second byte of the return value. 
    • 
+
  • the halved addition of the third bytes from each operand, in the third byte of the return value. 
    • 
+
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.

+
If res is the return value, then: 
    
+
  • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 
    • 
+
  • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 
    • 
+
  • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 
    • 
+
  • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8]
+   res[23:16] = val1[23:16] + val2[23:16]
+   res[31:24] = val1[31:24] + val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.

+  

+

+
Returns:
    
+
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.

+
If res is the return value, then:
    
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[31:16]
+   res[31:16] = val1[31:16] + val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two unsigned 16-bit integer additions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands. 
val2second two 16-bit summands.

+  

+

+
Returns:
    
+
  • the halved addition of the low halfwords in each operand, in the low halfword of the return value. 
    • 
+
  • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0]   >> 1
+   res[31:16] = val1[31:16] + val2[31:16]  >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit integer additions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands. 
val2second four 8-bit summands.

+  

+

+
Returns:
    
+
  • the halved addition of the first bytes in each operand, in the first byte of the return value. 
    • 
+
  • the halved addition of the second bytes in each operand, in the second byte of the return value. 
    • 
+
  • the halved addition of the third bytes in each operand, in the third byte of the return value. 
    • 
+
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0]   >> 1
+   res[15:8]  = val1[15:8]  + val2[15:8]  >> 1
+   res[23:16] = val1[23:16] + val2[23:16] >> 1
+   res[31:24] = val1[31:24] + val2[31:24] >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.

+  

+

+
Returns:
    
+
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. 
    • 
+
  • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
    • 
+

+

+
Operation:
   res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHSAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.

+  

+

+
Returns:
    
+
  • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHSUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands. 
val2second two 16-bit operands.

+  

+

+
Returns:
    
+
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
+   res[31:16] = val1[31:16] - val2[31:16]  >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UHSUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands. 
val2second four 8-bit operands.

+  

+

+
Returns:
    
+
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0]    >> 1
+   res[15:8]  = val1[15:8]  - val2[15:8]   >> 1
+   res[23:16] = val1[23:16] - val2[23:16]  >> 1
+   res[31:24] = val1[31:24] - val2[31:24]  >> 1
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQADD16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit summands. 
val2second two 16-bit summands.

+  

+

+
Returns:
    
+
  • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. 
    • 
+
  • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
    • 
+

+

+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  + val2[15:0] 
+   res[31:16] = val1[31:16] + val2[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQADD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit summands. 
val2second four 8-bit summands.

+  

+

+
Returns:
    
+
  • the halved addition of the first bytes in each operand, in the first byte of the return value. 
    • 
+
  • the halved addition of the second bytes in each operand, in the second byte of the return value. 
    • 
+
  • the halved addition of the third bytes in each operand, in the third byte of the return value. 
    • 
+
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+

+

+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Operation:
   res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8]
+   res[23:16] = val1[23:16] + val2[23:16]
+   res[31:24] = val1[31:24] + val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQASX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands. 
val2second two 16-bit operands.

+  

+

+
Returns:
    
+
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  - val2[31:16]
+   res[31:16] = val1[31:16] + val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQSAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters:

+  
+    
+    
+  
val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. 
val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.

+  

+

+
Returns:
    
+
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • 
+

+

+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQSUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands for each subtraction. 
val2second two 16-bit operands for each subtraction.

+  

+

+
Returns:
    
+
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]   
+   res[31:16] = val1[31:16] - val2[31:16]  
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UQSUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands. 
val2second four 8-bit operands.

+  

+

+
Returns:
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0]
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USAD8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands for the subtractions. 
val2second four 8-bit operands for the subtractions.

+  

+

+
Returns:
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. 
    • 
+

+

+
The sum is returned as a single unsigned integer.

+
Operation:
   absdiff1  = val1[7:0]   - val2[7:0]
+   absdiff2  = val1[15:8]  - val2[15:8]
+   absdiff3  = val1[23:16] - val2[23:16]
+   absdiff4  = val1[31:24] - val2[31:24]
+   res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USADA8 (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)

+

+

+
This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.

+
Parameters:

+  
+    
+    
+    
+  
val1first four 8-bit operands for the subtractions. 
val2second four 8-bit operands for the subtractions. 
val3accumulation value.

+  

+

+
Returns:
the sum of the absolute differences of the following bytes, added to the accumulation value: 
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • 
+

+

+
Operation:
   absdiff1  = val1[7:0]   - val2[7:0]
+   absdiff2  = val1[15:8]  - val2[15:8]
+   absdiff3  = val1[23:16] - val2[23:16]
+   absdiff4  = val1[31:24] - val2[31:24]
+   sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
+   res[31:0] = sum[31:0] + val3[31:0]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USAT16 (uint32_t val1, 
const uint32_t val2 
)

+

+

+
This function enables you to saturate two signed 16-bit values to a selected unsigned range.

+ The Q bit is set if either operation saturates.

+
Parameters:

+  
+    
+    
+  
val1two 16-bit values that are to be saturated. 
val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.

+  

+

+
Returns:
the saturation of the two signed 16-bit values, as non-negative values. 
    
+
  • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. 
    • 
+
  • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • 
+

+

+
Operation:
   Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USAX (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.

+  

+

+
Returns:
    
+
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USUB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform two 16-bit unsigned integer subtractions.

+ The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first two 16-bit operands. 
val2second two 16-bit operands.

+  

+

+
Returns:
    
+
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • 
+
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.

+
If res is the return value, then: 
    
+
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • 
+
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • 
+

+

+
Operation:
   res[15:0]  = val1[15:0]  - val2[15:0]   
+   res[31:16] = val1[31:16] - val2[31:16]  
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __USUB8 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.

+
Parameters:

+  
+    
+    
+  
val1first four 8-bit operands. 
val2second four 8-bit operands.

+  

+

+
Returns:
    
+
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • 
+
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • 
+
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • 
+
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • 
+

+

+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.

+
If res is the return value, then: 
    
+
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 
    • 
+
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • 
+
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • 
+
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • 
+

+

+
Operation:
   res[7:0]   = val1[7:0]   - val2[7:0]
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t __UXTAB16 (uint32_t val1, 
uint32_t val2 
)

+

+

+
This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.

+
Parameters:

+  
+    
+    
+  
val1value added to the zero-extended to 16-bit values. 
val2two 8-bit values to be extracted and zero-extended.

+  

+

+
Returns:
the 8-bit values in val2, zero-extended to 16-bit values and added to val1.

+
Operation:
   res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
+   res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t __UXTB16 (uint32_t val)

+

+

+
This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.

+
Parameters:

+  
+    
+  
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.

+  

+

+
Returns:
the 8-bit values zero-extended to 16-bit values. 
    
+
  • zero-extended value of val[7:0] in the low halfword of the return value. 
    • 
+
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • 
+

+

+
Operation:
   res[15:0]  = ZeroExtended(val[7:0]  )
+   res[31:16] = ZeroExtended(val[23:16])
+
 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group__peripheral__gr.html b/CMSIS/Documentation/Core/html/group__peripheral__gr.html
new file mode 100644
index 0000000000..ffde56f370
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group__peripheral__gr.html
@@ -0,0 +1,231 @@
+
+
+
+
+Peripheral Access
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Peripheral Access
  

+

+

+
+
Describes naming conventions, requirements, and optional features for accessing peripherals.  
+More...

+
Each peripheral provides a data type definition with a name that is composed of a prefix <device abbreviation>_ and the <peripheral name>_, for example LPC_UART for the device LPC and the peripheral UART. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example LPC_UART0, LPC_UART1.

+
    
+
  • The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:
    
+ 
      #define   __I     volatile const       
+  #define   __O     volatile             
+  #define   __IO    volatile             
+
    • 
+

+
    
+
  • The following typedef is an example for a UART. <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels in a device. 
    
+ 
    typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                  /* Offset: 0x000 (R/ )  Receiver Buffer Register            */
+  __O  uint8_t  THR;                  /* Offset: 0x000 ( /W)  Transmit Holding Register           */
+  __IO uint8_t  DLL;                  /* Offset: 0x000 (R/W)  Divisor Latch LSB                   */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                  /* Offset: 0x004 (R/W)  Divisor Latch MSB                   */
+  __IO uint32_t IER;                  /* Offset: 0x004 (R/W)  Interrupt Enable Register           */
+  };
+  union {
+  __I  uint32_t IIR;                  /* Offset: 0x008 (R/ )  Interrupt ID Register               */
+  __O  uint8_t  FCR;                  /* Offset: 0x008 ( /W)  FIFO Control Register               */
+  };
+  __IO uint8_t  LCR;                  /* Offset: 0x00C (R/W)  Line Control Register               */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                  /* Offset: 0x014 (R/ )  Line Status Register                */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                  /* Offset: 0x01C (R/W)  Scratch Pad Register                */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                  /* Offset: 0x020 (R/W)  Autobaud Control Register           */
+  __IO uint8_t  ICR;                  /* Offset: 0x024 (R/W)  IrDA Control Register               */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                  /* Offset: 0x028 (R/W)  Fractional Divider Register         */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                  /* Offset: 0x030 (R/W)  Transmit Enable Register            */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;              /* Offset: 0x058 (R/ )  FIFO Level Register                 */
+} LPC_UART_TypeDef;
+
    • 
+

+
    
+
  • To access the registers of the UART defined above, pointers to a register structure are defined. In this example <device abbreviation>_UART# are two pointers to UARTs defined with above register structure. 
    
+ 
    #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
+
    • 
+

+
    
+
  • The registers in the various UARTs can now be referred in the user code as shown below:
    
+ 
    LPC_UART1->DR   // is the data register of UART1.
+
    • 
+

+

+

+Minimal Requirements

+
To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum: 

+

+

+
    
+
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. 
    
+
    
+ Example: 
    typedef struct
+{
+  __IO uint32_t CTRL;                 /* Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                 /* Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                  /* Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                /* Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
    • 
+

+
    
+
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined). 
    
+
    
+ Example: 
    #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address     */    
+
    • 
+

+
    
+
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2). 
    
+
    
+ Example: 
    #define SysTick ((SysTick_Type *) Systick_BASE)    /* SysTick access definition */
+
    • 
+

+
These definitions allow accessing peripheral registers with simple assignments.

+
Example: 

+ 

+
SysTick->CTRL = 0;    
+

+

+Optional Features

+
Optionally, the file device.h may define:

+
    
+
  • #define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
    • 
+

+
    
+
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_. 
    • 
+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/group__system__init__gr.html b/CMSIS/Documentation/Core/html/group__system__init__gr.html
new file mode 100644
index 0000000000..c2fa9b39a6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/group__system__init__gr.html
@@ -0,0 +1,228 @@
+
+
+
+
+System and Clock Configuration
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
System and Clock Configuration
  

+

+

+
+
+
+
+
+
+
+
+
+

+Variables
uint32_t SystemCoreClock
 Variable to hold the system core clock value.  

+Functions
void SystemInit (void)
 Function to Initialize the system.  
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock.  

+
Description

+
ARM provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

+
    
+
  • A device-specific system configuration function, SystemInit().
    • 
+
  • A global variable that contains the system frequency, SystemCoreClock.
    • 
+

+
The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

+

+Code Example

+
The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.

+
#include "LPC17xx.h"
+
+uint32_t coreClock_1 = 0;                       /* Variables to store core clock values */
+uint32_t coreClock_2 = 0;
+
+
+int main (void)  {
+
+  coreClock_1 = SystemCoreClock;                /* Store value of predefined SystemCoreClock */
+
+  SystemCoreClockUpdate();                      /* Update SystemCoreClock according to register settings */
+
+  coreClock_2 = SystemCoreClock;                /* Store value of calculated SystemCoreClock */
+
+  if (coreClock_2 != coreClock_1)  {            /* Without changing the clock setting both core clock values should be the same */ 
+    // Error Handling
+  }
+
+  while(1);
+}
+
 
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t SystemCoreClock

+

+

+
Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

+
Attention:
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemCoreClockUpdate (void )

+

+

+
Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemInit (void )

+

+

+
Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/index.html b/CMSIS/Documentation/Core/html/index.html
new file mode 100644
index 0000000000..0b4beecf1c
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/index.html
@@ -0,0 +1,205 @@
+
+
+
+
+Overview
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Overview 
  

+

+

+
CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    
+
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • 
+
  • System exception names to interface to system exceptions without having compatibility issues.
    • 
+
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • 
+
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • 
+
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • 
+
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • 
+

+

+
This chapter provides details about the CMSIS-CORE and contains the following sections:

+
+

+

+Cortex-M Reference Manuals

+
The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

+
+

+

+Tested and Verified Toolchains

+
The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

+
    
+
  • ARM: MDK-ARM Version 4.13a (or greater)
    • 
+
  • GNU: GCC ARM Embedded 2011-q4-major (or greater)
    • 
+
  • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51 (or greater)
    • 
+
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater)
    • 
+

+

+
Revision History of CMSIS-CORE

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Version Description  
V3.01 Added support for Cortex-M0+ processor. 

+ Integration of CMSIS DSP Library version 1.1.0 

+   
V3.00 Added support for GNU GCC ARM Embedded Compiler. 

+ Added function __ROR.

+ Added Register Mapping for TPIU, DWT. 

+ Added support for SC000 and SC300 processors.

+ Corrected ITM_SendChar function. 

+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section. 

+ Documentation restructured.   
V2.10 Updated documentation.

+ Updated CMSIS core include files.

+ Changed CMSIS/Device folder structure.

+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.

+ Reworked CMSIS DSP library examples.   
V2.00 Added support for Cortex-M4 processor.  
V1.30 Reworked Startup Concept.

+ Added additional Debug Functionality.

+ Changed folder structure.

+ Added doxygen comments.

+ Added definitions for bit.   
V1.01 Added support for Cortex-M0 processor.  
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX  
V1.00 Initial Release for Cortex-M3 processor.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/installdox b/CMSIS/Documentation/Core/html/installdox
new file mode 100644
index 0000000000..edf5bbfe3e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/installdox
@@ -0,0 +1,112 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet   = 0;
+
+while ( @ARGV ) {
+  $_ = shift @ARGV;
+  if ( s/^-// ) {
+    if ( /^l(.*)/ ) {
+      $v = ($1 eq "") ? shift @ARGV : $1;
+      ($v =~ /\/$/) || ($v .= "/");
+      $_ = $v;
+      if ( /(.+)\@(.+)/ ) {
+        if ( exists $subst{$1} ) {
+          $subst{$1} = $2;
+        } else {
+          print STDERR "Unknown tag file $1 given with option -l\n";
+          &usage();
+        }
+      } else {
+        print STDERR "Argument $_ is invalid for option -l\n";
+        &usage();
+      }
+    }
+    elsif ( /^q/ ) {
+      $quiet = 1;
+    }
+    elsif ( /^\?|^h/ ) {
+      &usage();
+    }
+    else {
+      print STDERR "Illegal option -$_\n";
+      &usage();
+    }
+  }
+  else {
+    push (@files, $_ );
+  }
+}
+
+foreach $sub (keys %subst)
+{
+  if ( $subst{$sub} eq "" ) 
+  {
+    print STDERR "No substitute given for tag file `$sub'\n";
+    &usage();
+  }
+  elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+  {
+    print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; 
+  }
+}
+
+if ( ! @files ) {
+  if (opendir(D,".")) {
+    foreach $file ( readdir(D) ) {
+      $match = ".html";
+      next if ( $file =~ /^\.\.?$/ );
+      ($file =~ /$match/) && (push @files, $file);
+      ($file =~ /\.svg/) && (push @files, $file);
+      ($file =~ "navtree.js") && (push @files, $file);
+    }
+    closedir(D);
+  }
+}
+
+if ( ! @files ) {
+  print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+  if ( ! $quiet ) {
+    print "Editing: $f...\n";
+  }
+  $oldf = $f;
+  $f   .= ".bak";
+  unless (rename $oldf,$f) {
+    print STDERR "Error: cannot rename file $oldf\n";
+    exit 1;
+  }
+  if (open(F,"<$f")) {
+    unless (open(G,">$oldf")) {
+      print STDERR "Error: opening file $oldf for writing\n";
+      exit 1;
+    }
+    if ($oldf ne "tree.js") {
+      while () {
+        s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+    else {
+      while () {
+        s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+  } 
+  else {
+    print STDERR "Warning file $f does not exist\n";
+  }
+  unlink $f;
+}
+
+sub usage {
+  print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+  print STDERR "Options:\n";
+  print STDERR "     -l tagfile\@linkName   tag file + URL or directory \n";
+  print STDERR "     -q                    Quiet mode\n\n";
+  exit 1;
+}
diff --git a/CMSIS/Documentation/Core/html/jquery.js b/CMSIS/Documentation/Core/html/jquery.js
new file mode 100644
index 0000000000..c052173a89
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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+{G[this]=F});return G}o.fn.extend({show:function(J,L){if(J){return this.animate(t("show",3),J,L)}else{for(var H=0,F=this.length;H").appendTo("body");K=I.css("display");if(K==="none"){K="block"}I.remove();m[G]=K}o.data(this[H],"olddisplay",K)}}for(var H=0,F=this.length;H=0;H--){if(G[H].elem==this){if(E){G[H](true)}G.splice(H,1)}}});if(!E){this.dequeue()}return this}});o.each({slideDown:t("show",1),slideUp:t("hide",1),slideToggle:t("toggle",1),fadeIn:{opacity:"show"},fadeOut:{opacity:"hide"}},function(E,F){o.fn[E]=function(G,H){return this.animate(F,G,H)}});o.extend({speed:function(G,H,F){var E=typeof G==="object"?G:{complete:F||!F&&H||o.isFunction(G)&&G,duration:G,easing:F&&H||H&&!o.isFunction(H)&&H};E.duration=o.fx.off?0:typeof E.duration==="number"?E.duration:o.fx.speeds[E.duration]||o.fx.speeds._default;E.old=E.complete;E.complete=function(){if(E.queue!==false){o(this).dequeue()}if(o.isFunction(E.old)){E.old.call(this)}};return E},easing:{linear:function(G,H,E,F){return E+F*G},swing:function(G,H,E,F){return((-Math.cos(G*Math.PI)/2)+0.5)*F+E}},timers:[],fx:function(F,E,G){this.options=E;this.elem=F;this.prop=G;if(!E.orig){E.orig={}}}});o.fx.prototype={update:function(){if(this.options.step){this.options.step.call(this.elem,this.now,this)}(o.fx.step[this.prop]||o.fx.step._default)(this);if((this.prop=="height"||this.prop=="width")&&this.elem.style){this.elem.style.display="block"}},cur:function(F){if(this.elem[this.prop]!=null&&(!this.elem.style||this.elem.style[this.prop]==null)){return this.elem[this.prop]}var E=parseFloat(o.css(this.elem,this.prop,F));return E&&E>-10000?E:parseFloat(o.curCSS(this.elem,this.prop))||0},custom:function(I,H,G){this.startTime=e();this.start=I;this.end=H;this.unit=G||this.unit||"px";this.now=this.start;this.pos=this.state=0;var E=this;function F(J){return E.step(J)}F.elem=this.elem;if(F()&&o.timers.push(F)&&!n){n=setInterval(function(){var K=o.timers;for(var J=0;J=this.options.duration+this.startTime){this.now=this.end;this.pos=this.state=1;this.update();this.options.curAnim[this.prop]=true;var E=true;for(var F in this.options.curAnim){if(this.options.curAnim[F]!==true){E=false}}if(E){if(this.options.display!=null){this.elem.style.overflow=this.options.overflow;this.elem.style.display=this.options.display;if(o.css(this.elem,"display")=="none"){this.elem.style.display="block"}}if(this.options.hide){o(this.elem).hide()}if(this.options.hide||this.options.show){for(var I in this.options.curAnim){o.attr(this.elem.style,I,this.options.orig[I])}}this.options.complete.call(this.elem)}return false}else{var J=G-this.startTime;this.state=J/this.options.duration;this.pos=o.easing[this.options.easing||(o.easing.swing?"swing":"linear")](this.state,J,0,1,this.options.duration);this.now=this.start+((this.end-this.start)*this.pos);this.update()}return true}};o.extend(o.fx,{speeds:{slow:600,fast:200,_default:400},step:{opacity:function(E){o.attr(E.elem.style,"opacity",E.now)},_default:function(E){if(E.elem.style&&E.elem.style[E.prop]!=null){E.elem.style[E.prop]=E.now+E.unit}else{E.elem[E.prop]=E.now}}}});if(document.documentElement.getBoundingClientRect){o.fn.offset=function(){if(!this[0]){return{top:0,left:0}}if(this[0]===this[0].ownerDocument.body){return o.offset.bodyOffset(this[0])}var G=this[0].getBoundingClientRect(),J=this[0].ownerDocument,F=J.body,E=J.documentElement,L=E.clientTop||F.clientTop||0,K=E.clientLeft||F.clientLeft||0,I=G.top+(self.pageYOffset||o.boxModel&&E.scrollTop||F.scrollTop)-L,H=G.left+(self.pageXOffset||o.boxModel&&E.scrollLeft||F.scrollLeft)-K;return{top:I,left:H}}}else{o.fn.offset=function(){if(!this[0]){return{top:0,left:0}}if(this[0]===this[0].ownerDocument.body){return o.offset.bodyOffset(this[0])}o.offset.initialized||o.offset.initialize();var J=this[0],G=J.offsetParent,F=J,O=J.ownerDocument,M,H=O.documentElement,K=O.body,L=O.defaultView,E=L.getComputedStyle(J,null),N=J.offsetTop,I=J.offsetLeft;while((J=J.parentNode)&&J!==K&&J!==H){M=L.getComputedStyle(J,null);N-=J.scrollTop,I-=J.scrollLeft;if(J===G){N+=J.offsetTop,I+=J.offsetLeft;if(o.offset.doesNotAddBorder&&!(o.offset.doesAddBorderForTableAndCells&&/^t(able|d|h)$/i.test(J.tagName))){N+=parseInt(M.borderTopWidth,10)||0,I+=parseInt(M.borderLeftWidth,10)||0}F=G,G=J.offsetParent}if(o.offset.subtractsBorderForOverflowNotVisible&&M.overflow!=="visible"){N+=parseInt(M.borderTopWidth,10)||0,I+=parseInt(M.borderLeftWidth,10)||0}E=M}if(E.position==="relative"||E.position==="static"){N+=K.offsetTop,I+=K.offsetLeft}if(E.position==="fixed"){N+=Math.max(H.scrollTop,K.scrollTop),I+=Math.max(H.scrollLeft,K.scrollLeft)}return{top:N,left:I}}}o.offset={initialize:function(){if(this.initialized){return}var L=document.body,F=document.createElement("div"),H,G,N,I,M,E,J=L.style.marginTop,K='
';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/CMSIS/Documentation/Core/html/modules.html b/CMSIS/Documentation/Core/html/modules.html
new file mode 100644
index 0000000000..62f1bceaad
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/modules.html
@@ -0,0 +1,140 @@
+
+
+
+
+Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Reference
  

+

+

+
Here is a list of all modules:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/nav_f.png b/CMSIS/Documentation/Core/html/nav_f.png
new file mode 100644
index 0000000000..ed8c4935ef
Binary files /dev/null and b/CMSIS/Documentation/Core/html/nav_f.png differ
diff --git a/CMSIS/Documentation/Core/html/nav_h.png b/CMSIS/Documentation/Core/html/nav_h.png
new file mode 100644
index 0000000000..a05d3dbc51
Binary files /dev/null and b/CMSIS/Documentation/Core/html/nav_h.png differ
diff --git a/CMSIS/Documentation/Core/html/navtree.css b/CMSIS/Documentation/Core/html/navtree.css
new file mode 100644
index 0000000000..e46ffcd6e0
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/navtree.css
@@ -0,0 +1,123 @@
+#nav-tree .children_ul {
+  margin:0;
+  padding:4px;
+}
+
+#nav-tree ul {
+  list-style:none outside none;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree li {
+  white-space:nowrap;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .plus {
+  margin:0px;
+}
+
+#nav-tree .selected {
+  background-image: url('tab_a.png');
+  background-repeat:repeat-x;
+  color: #fff;
+  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
+
+#nav-tree img {
+  margin:0px;
+  padding:0px;
+  border:0px;
+  vertical-align: middle;
+}
+
+#nav-tree a {
+  text-decoration:none;
+  padding:0px;
+  margin:0px;
+  outline:none;
+}
+
+#nav-tree .label {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .label a {
+  padding:2px;
+}
+
+#nav-tree .selected a {
+  text-decoration:none;
+  padding:2px;
+  margin:0px;
+  color:#fff;
+}
+
+#nav-tree .children_ul {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree {
+  padding: 0px 0px;
+  background-color: #FAFAFF; 
+  font-size:14px;
+  overflow:auto;
+}
+
+#doc-content {
+  overflow:auto;
+  display:block;
+  padding:0px;
+  margin:0px;
+}
+
+#side-nav {
+  padding:0 6px 0 0;
+  margin: 0px;
+  display:block;
+  position: absolute;
+  left: 0px;
+  width: 300px;
+}
+
+.ui-resizable .ui-resizable-handle {
+  display:block;
+}
+
+.ui-resizable-e {
+  background:url("ftv2splitbar.png") repeat scroll right center transparent;
+  cursor:e-resize;
+  height:100%;
+  right:0;
+  top:0;
+  width:6px;
+}
+
+.ui-resizable-handle {
+  display:none;
+  font-size:0.1px;
+  position:absolute;
+  z-index:1;
+}
+
+#nav-tree-contents {
+  margin: 6px 0px 0px 0px;
+}
+
+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
+
diff --git a/CMSIS/Documentation/Core/html/navtree.js b/CMSIS/Documentation/Core/html/navtree.js
new file mode 100644
index 0000000000..8110357248
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/navtree.js
@@ -0,0 +1,293 @@
+var NAVTREE =
+[
+  [ "CMSIS-CORE", "index.html", [
+    [ "Overview", "index.html", null ],
+    [ "Usage and Description", "pages.html", [
+      [ "Using CMSIS in Embedded Applications", "_using_pg.html", [
+        [ "Using CMSIS with generic ARM Processors", "_using__a_r_m_pg.html", null ]
+      ] ],
+      [ "Template Files", "_templates_pg.html", [
+        [ "Startup File startup_.s", "startup_s_pg.html", null ],
+        [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", null ],
+        [ "Device Header File ", "device_h_pg.html", null ]
+      ] ],
+      [ "MISRA-C:2004 Compliance Exceptions", "_c_o_r_e__m_i_s_r_a__exceptions_pg.html", null ],
+      [ "Register Mapping", "_reg_map_pg.html", null ]
+    ] ],
+    [ "Reference", "modules.html", [
+      [ "Peripheral Access", "group__peripheral__gr.html", null ],
+      [ "System and Clock Configuration", "group__system__init__gr.html", null ],
+      [ "Interrupts and Exceptions (NVIC)", "group___n_v_i_c__gr.html", null ],
+      [ "Core Register Access", "group___core___register__gr.html", null ],
+      [ "Intrinsic Functions for CPU Instructions", "group__intrinsic___c_p_u__gr.html", null ],
+      [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4]", "group__intrinsic___s_i_m_d__gr.html", null ],
+      [ "Systick Timer (SYSTICK)", "group___sys_tick__gr.html", null ],
+      [ "Debug Access", "group___i_t_m___debug__gr.html", null ]
+    ] ],
+    [ "Data Structures", "annotated.html", [
+      [ "APSR_Type", "union_a_p_s_r___type.html", null ],
+      [ "CONTROL_Type", "union_c_o_n_t_r_o_l___type.html", null ],
+      [ "CoreDebug_Type", "struct_core_debug___type.html", null ],
+      [ "DWT_Type", "struct_d_w_t___type.html", null ],
+      [ "FPU_Type", "struct_f_p_u___type.html", null ],
+      [ "IPSR_Type", "union_i_p_s_r___type.html", null ],
+      [ "ITM_Type", "struct_i_t_m___type.html", null ],
+      [ "MPU_Type", "struct_m_p_u___type.html", null ],
+      [ "NVIC_Type", "struct_n_v_i_c___type.html", null ],
+      [ "SCB_Type", "struct_s_c_b___type.html", null ],
+      [ "SCnSCB_Type", "struct_s_cn_s_c_b___type.html", null ],
+      [ "SysTick_Type", "struct_sys_tick___type.html", null ],
+      [ "TPI_Type", "struct_t_p_i___type.html", null ],
+      [ "xPSR_Type", "unionx_p_s_r___type.html", null ]
+    ] ],
+    [ "Data Structure Index", "classes.html", null ],
+    [ "Data Fields", "functions.html", null ],
+    [ "Index", "globals.html", null ]
+  ] ]
+];
+
+function createIndent(o,domNode,node,level)
+{
+  if (node.parentNode && node.parentNode.parentNode)
+  {
+    createIndent(o,domNode,node.parentNode,level+1);
+  }
+  var imgNode = document.createElement("img");
+  if (level==0 && node.childrenData)
+  {
+    node.plus_img = imgNode;
+    node.expandToggle = document.createElement("a");
+    node.expandToggle.href = "javascript:void(0)";
+    node.expandToggle.onclick = function() 
+    {
+      if (node.expanded) 
+      {
+        $(node.getChildrenUL()).slideUp("fast");
+        if (node.isLast)
+        {
+          node.plus_img.src = node.relpath+"ftv2plastnode.png";
+        }
+        else
+        {
+          node.plus_img.src = node.relpath+"ftv2pnode.png";
+        }
+        node.expanded = false;
+      } 
+      else 
+      {
+        expandNode(o, node, false);
+      }
+    }
+    node.expandToggle.appendChild(imgNode);
+    domNode.appendChild(node.expandToggle);
+  }
+  else
+  {
+    domNode.appendChild(imgNode);
+  }
+  if (level==0)
+  {
+    if (node.isLast)
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2plastnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2lastnode.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+    else
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2pnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2node.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+  }
+  else
+  {
+    if (node.isLast)
+    {
+      imgNode.src = node.relpath+"ftv2blank.png";
+    }
+    else
+    {
+      imgNode.src = node.relpath+"ftv2vertline.png";
+    }
+  }
+  imgNode.border = "0";
+}
+
+function newNode(o, po, text, link, childrenData, lastNode)
+{
+  var node = new Object();
+  node.children = Array();
+  node.childrenData = childrenData;
+  node.depth = po.depth + 1;
+  node.relpath = po.relpath;
+  node.isLast = lastNode;
+
+  node.li = document.createElement("li");
+  po.getChildrenUL().appendChild(node.li);
+  node.parentNode = po;
+
+  node.itemDiv = document.createElement("div");
+  node.itemDiv.className = "item";
+
+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
+
+  createIndent(o,node.itemDiv,node,0);
+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
+
+  var a = document.createElement("a");
+  node.labelSpan.appendChild(a);
+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
+    a.href = node.relpath+link;
+  } 
+  else 
+  {
+    if (childrenData != null) 
+    {
+      a.className = "nolink";
+      a.href = "javascript:void(0)";
+      a.onclick = node.expandToggle.onclick;
+      node.expanded = false;
+    }
+  }
+
+  node.childrenUL = null;
+  node.getChildrenUL = function() 
+  {
+    if (!node.childrenUL) 
+    {
+      node.childrenUL = document.createElement("ul");
+      node.childrenUL.className = "children_ul";
+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
+    }
+    return node.childrenUL;
+  };
+
+  return node;
+}
+
+function showRoot()
+{
+  var headerHeight = $("#top").height();
+  var footerHeight = $("#nav-path").height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
+
+function expandNode(o, node, imm)
+{
+  if (node.childrenData && !node.expanded) 
+  {
+    if (!node.childrenVisited) 
+    {
+      getNode(o, node);
+    }
+    if (imm)
+    {
+      $(node.getChildrenUL()).show();
+    } 
+    else 
+    {
+      $(node.getChildrenUL()).slideDown("fast",showRoot);
+    }
+    if (node.isLast)
+    {
+      node.plus_img.src = node.relpath+"ftv2mlastnode.png";
+    }
+    else
+    {
+      node.plus_img.src = node.relpath+"ftv2mnode.png";
+    }
+    node.expanded = true;
+  }
+}
+
+function getNode(o, po)
+{
+  po.childrenVisited = true;
+  var l = po.childrenData.length-1;
+  for (var i in po.childrenData) 
+  {
+    var nodeData = po.childrenData[i];
+    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
+        i==l);
+  }
+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
+      }
+    }
+  }
+  return null;
+}
+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
+  o.node.depth = 0;
+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
+
+  o.breadcrumbs = findNavTreePage(toroot, NAVTREE);
+  if (o.breadcrumbs == null)
+  {
+    o.breadcrumbs = findNavTreePage("index.html",NAVTREE);
+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
+    var p = o.node;
+    for (var i in o.breadcrumbs) 
+    {
+      var j = o.breadcrumbs[i];
+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/CMSIS/Documentation/Core/html/open.png b/CMSIS/Documentation/Core/html/open.png
new file mode 100644
index 0000000000..8ae8db28dd
Binary files /dev/null and b/CMSIS/Documentation/Core/html/open.png differ
diff --git a/CMSIS/Documentation/Core/html/pages.html b/CMSIS/Documentation/Core/html/pages.html
new file mode 100644
index 0000000000..71f05675e2
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/pages.html
@@ -0,0 +1,140 @@
+
+
+
+
+Usage and Description
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Usage and Description
  

+

+

+
Here is a list of all related documentation pages:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/resize.js b/CMSIS/Documentation/Core/html/resize.js
new file mode 100644
index 0000000000..04fa95ce97
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/resize.js
@@ -0,0 +1,81 @@
+var cookie_namespace = 'doxygen'; 
+var sidenav,navtree,content,header;
+
+function readCookie(cookie) 
+{
+  var myCookie = cookie_namespace+"_"+cookie+"=";
+  if (document.cookie) 
+  {
+    var index = document.cookie.indexOf(myCookie);
+    if (index != -1) 
+    {
+      var valStart = index + myCookie.length;
+      var valEnd = document.cookie.indexOf(";", valStart);
+      if (valEnd == -1) 
+      {
+        valEnd = document.cookie.length;
+      }
+      var val = document.cookie.substring(valStart, valEnd);
+      return val;
+    }
+  }
+  return 0;
+}
+
+function writeCookie(cookie, val, expiration) 
+{
+  if (val==undefined) return;
+  if (expiration == null) 
+  {
+    var date = new Date();
+    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week
+    expiration = date.toGMTString();
+  }
+  document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/";
+}
+ 
+function resizeWidth() 
+{
+  var windowWidth = $(window).width() + "px";
+  var sidenavWidth = $(sidenav).width();
+  content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar
+  writeCookie('width',sidenavWidth, null);
+}
+
+function restoreWidth(navWidth)
+{
+  var windowWidth = $(window).width() + "px";
+  content.css({marginLeft:parseInt(navWidth)+6+"px"});
+  sidenav.css({width:navWidth + "px"});
+}
+
+function resizeHeight() 
+{
+  var headerHeight = header.height();
+  var footerHeight = footer.height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  content.css({height:windowHeight + "px"});
+  navtree.css({height:windowHeight + "px"});
+  sidenav.css({height:windowHeight + "px",top: headerHeight+"px"});
+}
+
+function initResizable()
+{
+  header  = $("#top");
+  sidenav = $("#side-nav");
+  content = $("#doc-content");
+  navtree = $("#nav-tree");
+  footer  = $("#nav-path");
+  $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } });
+  $(window).resize(function() { resizeHeight(); });
+  var width = readCookie('width');
+  if (width) { restoreWidth(width); } else { resizeWidth(); }
+  resizeHeight();
+  var url = location.href;
+  var i=url.indexOf("#");
+  if (i>=0) window.location.hash=url.substr(i);
+  var _preventDefault = function(evt) { evt.preventDefault(); };
+  $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault);
+}
+
+
diff --git a/CMSIS/Documentation/Core/html/search.css b/CMSIS/Documentation/Core/html/search.css
new file mode 100644
index 0000000000..1746d13fd6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/CMSIS/Documentation/Core/html/search/all_5f.html b/CMSIS/Documentation/Core/html/search/all_5f.html
new file mode 100644
index 0000000000..0f4f46b7fc
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_5f.html
@@ -0,0 +1,655 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  __CLREX
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __CLZ
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __disable_fault_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __disable_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __DMB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __DSB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __enable_fault_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __enable_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_APSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_BASEPRI
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_CONTROL
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_FAULTMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_FPSCR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_IPSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_MSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_PRIMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_PSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_xPSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __ISB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXW
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __NOP
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __PKHBT
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __PKHTB
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __RBIT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REV
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REV16
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REVSH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __ROR
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SEL
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __set_BASEPRI
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_CONTROL
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_FAULTMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_FPSCR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_MSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_PRIMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_PSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __SEV
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SHADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLAD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLADX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLALD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLALDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSLD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSLDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUAD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUADX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUSD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUSDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSAT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SSAT16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __STREXB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __STREXH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __STREXW
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SXTAB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SXTB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USADA8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __USAT16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UXTAB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UXTB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __WFE
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __WFI
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  _reserved0
+  

+    APSR_Type::_reserved0()
+    IPSR_Type::_reserved0()
+    xPSR_Type::_reserved0()
+    CONTROL_Type::_reserved0()
+  

+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_61.html b/CMSIS/Documentation/Core/html/search/all_61.html
new file mode 100644
index 0000000000..e4f1a97c3d
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_61.html
@@ -0,0 +1,55 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  ACPR
+  TPI_Type
+ 

+

+

+ 

+  ACTLR
+  SCnSCB_Type
+ 

+

+

+ 

+  ADR
+  SCB_Type
+ 

+

+

+ 

+  AFSR
+  SCB_Type
+ 

+

+

+ 

+  AIRCR
+  SCB_Type
+ 

+

+

+ 

+  APSR_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_62.html b/CMSIS/Documentation/Core/html/search/all_62.html
new file mode 100644
index 0000000000..aa9d4dcca0
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_62.html
@@ -0,0 +1,43 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  BFAR
+  SCB_Type
+ 

+

+

+ 

+  BusFault_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_63.html b/CMSIS/Documentation/Core/html/search/all_63.html
new file mode 100644
index 0000000000..d49655a0d2
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_63.html
@@ -0,0 +1,133 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  CALIB
+  SysTick_Type
+ 

+

+

+ 

+  CCR
+  SCB_Type
+ 

+

+

+ 

+  CFSR
+  SCB_Type
+ 

+

+

+ 

+  CLAIMCLR
+  TPI_Type
+ 

+

+

+ 

+  CLAIMSET
+  TPI_Type
+ 

+

+

+ 

+  COMP0
+  DWT_Type
+ 

+

+

+ 

+  COMP1
+  DWT_Type
+ 

+

+

+ 

+  COMP2
+  DWT_Type
+ 

+

+

+ 

+  COMP3
+  DWT_Type
+ 

+

+

+ 

+  CONTROL_Type
+ 

+

+
+

+ 

+  CPACR
+  SCB_Type
+ 

+

+

+ 

+  CPICNT
+  DWT_Type
+ 

+

+

+ 

+  CPUID
+  SCB_Type
+ 

+

+

+ 

+  CSPSR
+  TPI_Type
+ 

+

+
+

+ 

+  CYCCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_64.html b/CMSIS/Documentation/Core/html/search/all_64.html
new file mode 100644
index 0000000000..7f145c738f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_64.html
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  DCRDR
+  CoreDebug_Type
+ 

+

+

+ 

+  DCRSR
+  CoreDebug_Type
+ 

+

+

+ 

+  DebugMonitor_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  DEMCR
+  CoreDebug_Type
+ 

+

+

+ 

+  DEVID
+  TPI_Type
+ 

+

+

+ 

+  DEVTYPE
+  TPI_Type
+ 

+

+

+ 

+  DFR
+  SCB_Type
+ 

+

+

+ 

+  DFSR
+  SCB_Type
+ 

+

+

+ 

+  DHCSR
+  CoreDebug_Type
+ 

+

+

+ 

+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_65.html b/CMSIS/Documentation/Core/html/search/all_65.html
new file mode 100644
index 0000000000..b3db09ddee
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_65.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  EXCCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_66.html b/CMSIS/Documentation/Core/html/search/all_66.html
new file mode 100644
index 0000000000..74554be58f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_66.html
@@ -0,0 +1,109 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  FFCR
+  TPI_Type
+ 

+

+

+ 

+  FFSR
+  TPI_Type
+ 

+

+

+ 

+  FIFO0
+  TPI_Type
+ 

+

+

+ 

+  FIFO1
+  TPI_Type
+ 

+

+

+ 

+  FOLDCNT
+  DWT_Type
+ 

+

+

+ 

+  FPCA
+  CONTROL_Type
+ 

+

+

+ 

+  FPCAR
+  FPU_Type
+ 

+

+

+ 

+  FPCCR
+  FPU_Type
+ 

+

+

+ 

+  FPDSCR
+  FPU_Type
+ 

+

+

+ 

+  FPU_Type
+ 

+

+

+ 

+  FSCR
+  TPI_Type
+ 

+

+

+ 

+  FUNCTION0
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION1
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION2
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION3
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_68.html b/CMSIS/Documentation/Core/html/search/all_68.html
new file mode 100644
index 0000000000..db6d192f3d
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_68.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  HardFault_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  HFSR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_69.html b/CMSIS/Documentation/Core/html/search/all_69.html
new file mode 100644
index 0000000000..704a08c740
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_69.html
@@ -0,0 +1,147 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  IABR
+  NVIC_Type
+ 

+

+

+ 

+  ICER
+  NVIC_Type
+ 

+

+

+ 

+  ICPR
+  NVIC_Type
+ 

+

+

+ 

+  ICSR
+  SCB_Type
+ 

+

+

+ 

+  ICTR
+  SCnSCB_Type
+ 

+

+

+ 

+  IP
+  NVIC_Type
+ 

+

+

+ 

+  IPSR_Type
+ 

+

+

+ 

+  IRQn_Type
+  Ref_NVIC.txt
+ 

+

+

+ 

+  ISAR
+  SCB_Type
+ 

+

+

+ 

+  ISER
+  NVIC_Type
+ 

+

+

+ 

+  ISPR
+  NVIC_Type
+ 

+

+
+

+ 

+  IT
+  xPSR_Type
+ 

+

+

+ 

+  ITATBCTR0
+  TPI_Type
+ 

+

+

+ 

+  ITATBCTR2
+  TPI_Type
+ 

+

+

+ 

+  ITCTRL
+  TPI_Type
+ 

+

+

+ 

+  ITM_CheckChar
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_ReceiveChar
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_RxBuffer
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_SendChar
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_6c.html b/CMSIS/Documentation/Core/html/search/all_6c.html
new file mode 100644
index 0000000000..337c839fce
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_6c.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  LOAD
+  SysTick_Type
+ 

+

+

+ 

+  LSUCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_6d.html b/CMSIS/Documentation/Core/html/search/all_6d.html
new file mode 100644
index 0000000000..540c1dd78e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_6d.html
@@ -0,0 +1,84 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  MASK0
+  DWT_Type
+ 

+

+

+ 

+  MASK1
+  DWT_Type
+ 

+

+

+ 

+  MASK2
+  DWT_Type
+ 

+

+

+ 

+  MASK3
+  DWT_Type
+ 

+

+

+ 

+  MemoryManagement_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  MISRA.txt
+ 

+

+

+ 

+  MMFAR
+  SCB_Type
+ 

+

+

+ 

+  MMFR
+  SCB_Type
+ 

+

+

+ 

+  MPU_Type
+ 

+

+

+ 

+  MVFR0
+  FPU_Type
+ 

+

+

+ 

+  MVFR1
+  FPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_6e.html b/CMSIS/Documentation/Core/html/search/all_6e.html
new file mode 100644
index 0000000000..f534a31c96
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_6e.html
@@ -0,0 +1,124 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  NonMaskableInt_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  nPRIV
+  CONTROL_Type
+ 

+

+

+ 

+  NVIC_ClearPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_DecodePriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_DisableIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_EnableIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_EncodePriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetActive
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPriorityGrouping
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPriorityGrouping
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SystemReset
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_6f.html b/CMSIS/Documentation/Core/html/search/all_6f.html
new file mode 100644
index 0000000000..e8d54e7ff4
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_6f.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Overview.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_70.html b/CMSIS/Documentation/Core/html/search/all_70.html
new file mode 100644
index 0000000000..90cb2f2562
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_70.html
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  PCSR
+  DWT_Type
+ 

+

+

+ 

+  PendSV_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  PFR
+  SCB_Type
+ 

+

+

+ 

+  PORT
+  ITM_Type
+ 

+

+

+ 

+  PVD_STM_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_71.html b/CMSIS/Documentation/Core/html/search/all_71.html
new file mode 100644
index 0000000000..0c1e07b428
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_71.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_72.html b/CMSIS/Documentation/Core/html/search/all_72.html
new file mode 100644
index 0000000000..6bc5db5497
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_72.html
@@ -0,0 +1,198 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  RASR
+  MPU_Type
+ 

+

+

+ 

+  RASR_A1
+  MPU_Type
+ 

+

+

+ 

+  RASR_A2
+  MPU_Type
+ 

+

+

+ 

+  RASR_A3
+  MPU_Type
+ 

+

+

+ 

+  RBAR
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A1
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A2
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A3
+  MPU_Type
+ 

+

+
+
+
+
+

+ 

+  Ref_Debug.txt
+ 

+

+

+ 

+  Ref_NVIC.txt
+ 

+

+
+
+
+
+
+
+
+
+
+
+

+ 

+  RESERVED7
+  TPI_Type
+ 

+

+

+ 

+  RNR
+  MPU_Type
+ 

+

+

+ 

+  RSERVED1
+  NVIC_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_73.html b/CMSIS/Documentation/Core/html/search/all_73.html
new file mode 100644
index 0000000000..2d720ed96d
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_73.html
@@ -0,0 +1,119 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  SCB_Type
+ 

+

+

+ 

+  SCnSCB_Type
+ 

+

+

+ 

+  SCR
+  SCB_Type
+ 

+

+

+ 

+  SHCSR
+  SCB_Type
+ 

+

+

+ 

+  SHP
+  SCB_Type
+ 

+

+

+ 

+  SLEEPCNT
+  DWT_Type
+ 

+

+

+ 

+  SPPR
+  TPI_Type
+ 

+

+

+ 

+  SPSEL
+  CONTROL_Type
+ 

+

+

+ 

+  SSPSR
+  TPI_Type
+ 

+

+

+ 

+  STIR
+  NVIC_Type
+ 

+

+

+ 

+  SVCall_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  SystemCoreClock
+  Ref_SystemAndClock.txt
+ 

+

+

+ 

+  SystemCoreClockUpdate
+  Ref_SystemAndClock.txt
+ 

+

+

+ 

+  SystemInit
+  Ref_SystemAndClock.txt
+ 

+

+

+ 

+  SysTick_Config
+  Ref_Systick.txt
+ 

+

+

+ 

+  SysTick_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  SysTick_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_74.html b/CMSIS/Documentation/Core/html/search/all_74.html
new file mode 100644
index 0000000000..47364a09c4
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_74.html
@@ -0,0 +1,66 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  T
+  xPSR_Type
+ 

+

+

+ 

+  TCR
+  ITM_Type
+ 

+

+

+ 

+  Template.txt
+ 

+

+

+ 

+  TER
+  ITM_Type
+ 

+

+

+ 

+  TPI_Type
+ 

+

+

+ 

+  TPR
+  ITM_Type
+ 

+

+

+ 

+  TRIGGER
+  TPI_Type
+ 

+

+

+ 

+  TYPE
+  MPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_75.html b/CMSIS/Documentation/Core/html/search/all_75.html
new file mode 100644
index 0000000000..67c5a0185f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_75.html
@@ -0,0 +1,49 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  u16
+  ITM_Type
+ 

+

+

+ 

+  u32
+  ITM_Type
+ 

+

+

+ 

+  u8
+  ITM_Type
+ 

+

+

+ 

+  UsageFault_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  Using.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_76.html b/CMSIS/Documentation/Core/html/search/all_76.html
new file mode 100644
index 0000000000..4d6ec2cc80
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_76.html
@@ -0,0 +1,41 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  VAL
+  SysTick_Type
+ 

+

+

+ 

+  VTOR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_77.html b/CMSIS/Documentation/Core/html/search/all_77.html
new file mode 100644
index 0000000000..a52b4fb5ab
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_77.html
@@ -0,0 +1,37 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  WWDG_STM_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_78.html b/CMSIS/Documentation/Core/html/search/all_78.html
new file mode 100644
index 0000000000..b0a07512f3
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_78.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  xPSR_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/all_7a.html b/CMSIS/Documentation/Core/html/search/all_7a.html
new file mode 100644
index 0000000000..1c0da898bf
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/all_7a.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_61.html b/CMSIS/Documentation/Core/html/search/classes_61.html
new file mode 100644
index 0000000000..1f2ce6b6bd
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_61.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  APSR_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_63.html b/CMSIS/Documentation/Core/html/search/classes_63.html
new file mode 100644
index 0000000000..6f3877710b
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_63.html
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  CONTROL_Type
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_64.html b/CMSIS/Documentation/Core/html/search/classes_64.html
new file mode 100644
index 0000000000..f045f1e3ac
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_64.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_66.html b/CMSIS/Documentation/Core/html/search/classes_66.html
new file mode 100644
index 0000000000..b7d460306c
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_66.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  FPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_69.html b/CMSIS/Documentation/Core/html/search/classes_69.html
new file mode 100644
index 0000000000..52ad50f6ff
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_69.html
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  IPSR_Type
+ 

+

+

+ 

+  ITM_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_6d.html b/CMSIS/Documentation/Core/html/search/classes_6d.html
new file mode 100644
index 0000000000..bf46580031
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_6d.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  MPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_6e.html b/CMSIS/Documentation/Core/html/search/classes_6e.html
new file mode 100644
index 0000000000..3065a7a93d
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_6e.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  NVIC_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_73.html b/CMSIS/Documentation/Core/html/search/classes_73.html
new file mode 100644
index 0000000000..39c24f7a07
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_73.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  SCB_Type
+ 

+

+

+ 

+  SCnSCB_Type
+ 

+

+

+ 

+  SysTick_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_74.html b/CMSIS/Documentation/Core/html/search/classes_74.html
new file mode 100644
index 0000000000..e88762bda6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_74.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  TPI_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/classes_78.html b/CMSIS/Documentation/Core/html/search/classes_78.html
new file mode 100644
index 0000000000..b0a07512f3
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/classes_78.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  xPSR_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/close.png b/CMSIS/Documentation/Core/html/search/close.png
new file mode 100644
index 0000000000..9342d3dfee
Binary files /dev/null and b/CMSIS/Documentation/Core/html/search/close.png differ
diff --git a/CMSIS/Documentation/Core/html/search/enums_69.html b/CMSIS/Documentation/Core/html/search/enums_69.html
new file mode 100644
index 0000000000..e7e2f67aa5
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enums_69.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  IRQn_Type
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_62.html b/CMSIS/Documentation/Core/html/search/enumvalues_62.html
new file mode 100644
index 0000000000..356e93684a
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_62.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  BusFault_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_64.html b/CMSIS/Documentation/Core/html/search/enumvalues_64.html
new file mode 100644
index 0000000000..d7c69562e3
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_64.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  DebugMonitor_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_68.html b/CMSIS/Documentation/Core/html/search/enumvalues_68.html
new file mode 100644
index 0000000000..34bd28197b
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_68.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  HardFault_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_6d.html b/CMSIS/Documentation/Core/html/search/enumvalues_6d.html
new file mode 100644
index 0000000000..5332353762
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_6d.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  MemoryManagement_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_6e.html b/CMSIS/Documentation/Core/html/search/enumvalues_6e.html
new file mode 100644
index 0000000000..db14a2d072
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_6e.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  NonMaskableInt_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_70.html b/CMSIS/Documentation/Core/html/search/enumvalues_70.html
new file mode 100644
index 0000000000..77dc5567fb
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_70.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  PendSV_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  PVD_STM_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_73.html b/CMSIS/Documentation/Core/html/search/enumvalues_73.html
new file mode 100644
index 0000000000..08e3fcc7b0
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_73.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  SVCall_IRQn
+  Ref_NVIC.txt
+ 

+

+

+ 

+  SysTick_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_75.html b/CMSIS/Documentation/Core/html/search/enumvalues_75.html
new file mode 100644
index 0000000000..8c4b0e137e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_75.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  UsageFault_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/enumvalues_77.html b/CMSIS/Documentation/Core/html/search/enumvalues_77.html
new file mode 100644
index 0000000000..748b4d81e2
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/enumvalues_77.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  WWDG_STM_IRQn
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/files_6d.html b/CMSIS/Documentation/Core/html/search/files_6d.html
new file mode 100644
index 0000000000..8ecfaa012d
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/files_6d.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  MISRA.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/files_6f.html b/CMSIS/Documentation/Core/html/search/files_6f.html
new file mode 100644
index 0000000000..e8d54e7ff4
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/files_6f.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Overview.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/files_72.html b/CMSIS/Documentation/Core/html/search/files_72.html
new file mode 100644
index 0000000000..96683f6f72
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/files_72.html
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+

+ 

+  Ref_Debug.txt
+ 

+

+

+ 

+  Ref_NVIC.txt
+ 

+

+
+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/files_74.html b/CMSIS/Documentation/Core/html/search/files_74.html
new file mode 100644
index 0000000000..be1c1f1459
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/files_74.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Template.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/files_75.html b/CMSIS/Documentation/Core/html/search/files_75.html
new file mode 100644
index 0000000000..0fcb29d7e6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/files_75.html
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Using.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/functions_5f.html b/CMSIS/Documentation/Core/html/search/functions_5f.html
new file mode 100644
index 0000000000..b4c96cd891
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/functions_5f.html
@@ -0,0 +1,644 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  __CLREX
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __CLZ
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __disable_fault_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __disable_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __DMB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __DSB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __enable_fault_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __enable_irq
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_APSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_BASEPRI
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_CONTROL
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_FAULTMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_FPSCR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_IPSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_MSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_PRIMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_PSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __get_xPSR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __ISB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __LDREXW
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __NOP
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __PKHBT
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __PKHTB
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __QSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __RBIT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REV
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REV16
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __REVSH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __ROR
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SEL
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __set_BASEPRI
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_CONTROL
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_FAULTMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_FPSCR
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_MSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_PRIMASK
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __set_PSP
+  Ref_CoreReg.txt
+ 

+

+

+ 

+  __SEV
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SHADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SHSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLAD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLADX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLALD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLALDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSLD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMLSLDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUAD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUADX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUSD
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SMUSDX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSAT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SSAT16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __STREXB
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __STREXH
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __STREXW
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __SXTAB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __SXTB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UHSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQADD16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQADD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQASX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UQSUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAD8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USADA8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAT
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __USAT16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USAX
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USUB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __USUB8
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UXTAB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __UXTB16
+  Ref_cm4_simd.txt
+ 

+

+

+ 

+  __WFE
+  Ref_cmInstr.txt
+ 

+

+

+ 

+  __WFI
+  Ref_cmInstr.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/functions_69.html b/CMSIS/Documentation/Core/html/search/functions_69.html
new file mode 100644
index 0000000000..073a792344
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/functions_69.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  ITM_CheckChar
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_ReceiveChar
+  Ref_Debug.txt
+ 

+

+

+ 

+  ITM_SendChar
+  Ref_Debug.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/functions_6e.html b/CMSIS/Documentation/Core/html/search/functions_6e.html
new file mode 100644
index 0000000000..f85ddeca30
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/functions_6e.html
@@ -0,0 +1,98 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  NVIC_ClearPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_DecodePriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_DisableIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_EnableIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_EncodePriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetActive
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_GetPriorityGrouping
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPendingIRQ
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPriority
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SetPriorityGrouping
+  Ref_NVIC.txt
+ 

+

+

+ 

+  NVIC_SystemReset
+  Ref_NVIC.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/functions_73.html b/CMSIS/Documentation/Core/html/search/functions_73.html
new file mode 100644
index 0000000000..add7be0ef1
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/functions_73.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  SystemCoreClockUpdate
+  Ref_SystemAndClock.txt
+ 

+

+

+ 

+  SystemInit
+  Ref_SystemAndClock.txt
+ 

+

+

+ 

+  SysTick_Config
+  Ref_Systick.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/mag_sel.png b/CMSIS/Documentation/Core/html/search/mag_sel.png
new file mode 100644
index 0000000000..81f6040a20
Binary files /dev/null and b/CMSIS/Documentation/Core/html/search/mag_sel.png differ
diff --git a/CMSIS/Documentation/Core/html/search/nomatches.html b/CMSIS/Documentation/Core/html/search/nomatches.html
new file mode 100644
index 0000000000..b1ded27e9a
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/nomatches.html
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+

+
No Matches

+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/search.css b/CMSIS/Documentation/Core/html/search/search.css
new file mode 100644
index 0000000000..1746d13fd6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/CMSIS/Documentation/Core/html/search/search.js b/CMSIS/Documentation/Core/html/search/search.js
new file mode 100644
index 0000000000..6b45bd0477
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/search.js
@@ -0,0 +1,738 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "enums",
+  6: "enumvalues"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of .
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/CMSIS/Documentation/Core/html/search/search_l.png b/CMSIS/Documentation/Core/html/search/search_l.png
new file mode 100644
index 0000000000..c872f4da4a
Binary files /dev/null and b/CMSIS/Documentation/Core/html/search/search_l.png differ
diff --git a/CMSIS/Documentation/Core/html/search/search_m.png b/CMSIS/Documentation/Core/html/search/search_m.png
new file mode 100644
index 0000000000..b429a16ba6
Binary files /dev/null and b/CMSIS/Documentation/Core/html/search/search_m.png differ
diff --git a/CMSIS/Documentation/Core/html/search/search_r.png b/CMSIS/Documentation/Core/html/search/search_r.png
new file mode 100644
index 0000000000..97ee8b4396
Binary files /dev/null and b/CMSIS/Documentation/Core/html/search/search_r.png differ
diff --git a/CMSIS/Documentation/Core/html/search/variables_5f.html b/CMSIS/Documentation/Core/html/search/variables_5f.html
new file mode 100644
index 0000000000..804c2d0da5
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_5f.html
@@ -0,0 +1,31 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  _reserved0
+  

+    APSR_Type::_reserved0()
+    IPSR_Type::_reserved0()
+    xPSR_Type::_reserved0()
+    CONTROL_Type::_reserved0()
+  

+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_61.html b/CMSIS/Documentation/Core/html/search/variables_61.html
new file mode 100644
index 0000000000..45a0ac58a1
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_61.html
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  ACPR
+  TPI_Type
+ 

+

+

+ 

+  ACTLR
+  SCnSCB_Type
+ 

+

+

+ 

+  ADR
+  SCB_Type
+ 

+

+

+ 

+  AFSR
+  SCB_Type
+ 

+

+

+ 

+  AIRCR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_62.html b/CMSIS/Documentation/Core/html/search/variables_62.html
new file mode 100644
index 0000000000..5f65963cce
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_62.html
@@ -0,0 +1,37 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  BFAR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_63.html b/CMSIS/Documentation/Core/html/search/variables_63.html
new file mode 100644
index 0000000000..7127f121e0
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_63.html
@@ -0,0 +1,123 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  CALIB
+  SysTick_Type
+ 

+

+

+ 

+  CCR
+  SCB_Type
+ 

+

+

+ 

+  CFSR
+  SCB_Type
+ 

+

+

+ 

+  CLAIMCLR
+  TPI_Type
+ 

+

+

+ 

+  CLAIMSET
+  TPI_Type
+ 

+

+

+ 

+  COMP0
+  DWT_Type
+ 

+

+

+ 

+  COMP1
+  DWT_Type
+ 

+

+

+ 

+  COMP2
+  DWT_Type
+ 

+

+

+ 

+  COMP3
+  DWT_Type
+ 

+

+

+ 

+  CPACR
+  SCB_Type
+ 

+

+

+ 

+  CPICNT
+  DWT_Type
+ 

+

+

+ 

+  CPUID
+  SCB_Type
+ 

+

+

+ 

+  CSPSR
+  TPI_Type
+ 

+

+
+

+ 

+  CYCCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_64.html b/CMSIS/Documentation/Core/html/search/variables_64.html
new file mode 100644
index 0000000000..2a678b6da7
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_64.html
@@ -0,0 +1,68 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  DCRDR
+  CoreDebug_Type
+ 

+

+

+ 

+  DCRSR
+  CoreDebug_Type
+ 

+

+

+ 

+  DEMCR
+  CoreDebug_Type
+ 

+

+

+ 

+  DEVID
+  TPI_Type
+ 

+

+

+ 

+  DEVTYPE
+  TPI_Type
+ 

+

+

+ 

+  DFR
+  SCB_Type
+ 

+

+

+ 

+  DFSR
+  SCB_Type
+ 

+

+

+ 

+  DHCSR
+  CoreDebug_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_65.html b/CMSIS/Documentation/Core/html/search/variables_65.html
new file mode 100644
index 0000000000..b3db09ddee
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_65.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  EXCCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_66.html b/CMSIS/Documentation/Core/html/search/variables_66.html
new file mode 100644
index 0000000000..709a9e9c84
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_66.html
@@ -0,0 +1,104 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  FFCR
+  TPI_Type
+ 

+

+

+ 

+  FFSR
+  TPI_Type
+ 

+

+

+ 

+  FIFO0
+  TPI_Type
+ 

+

+

+ 

+  FIFO1
+  TPI_Type
+ 

+

+

+ 

+  FOLDCNT
+  DWT_Type
+ 

+

+

+ 

+  FPCA
+  CONTROL_Type
+ 

+

+

+ 

+  FPCAR
+  FPU_Type
+ 

+

+

+ 

+  FPCCR
+  FPU_Type
+ 

+

+

+ 

+  FPDSCR
+  FPU_Type
+ 

+

+

+ 

+  FSCR
+  TPI_Type
+ 

+

+

+ 

+  FUNCTION0
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION1
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION2
+  DWT_Type
+ 

+

+

+ 

+  FUNCTION3
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_68.html b/CMSIS/Documentation/Core/html/search/variables_68.html
new file mode 100644
index 0000000000..5b9971c959
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_68.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  HFSR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_69.html b/CMSIS/Documentation/Core/html/search/variables_69.html
new file mode 100644
index 0000000000..75edc19d45
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_69.html
@@ -0,0 +1,113 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  IABR
+  NVIC_Type
+ 

+

+

+ 

+  ICER
+  NVIC_Type
+ 

+

+

+ 

+  ICPR
+  NVIC_Type
+ 

+

+

+ 

+  ICSR
+  SCB_Type
+ 

+

+

+ 

+  ICTR
+  SCnSCB_Type
+ 

+

+

+ 

+  IP
+  NVIC_Type
+ 

+

+

+ 

+  ISAR
+  SCB_Type
+ 

+

+

+ 

+  ISER
+  NVIC_Type
+ 

+

+

+ 

+  ISPR
+  NVIC_Type
+ 

+

+
+

+ 

+  IT
+  xPSR_Type
+ 

+

+

+ 

+  ITATBCTR0
+  TPI_Type
+ 

+

+

+ 

+  ITATBCTR2
+  TPI_Type
+ 

+

+

+ 

+  ITCTRL
+  TPI_Type
+ 

+

+

+ 

+  ITM_RxBuffer
+  Ref_Debug.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_6c.html b/CMSIS/Documentation/Core/html/search/variables_6c.html
new file mode 100644
index 0000000000..337c839fce
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_6c.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  LOAD
+  SysTick_Type
+ 

+

+

+ 

+  LSUCNT
+  DWT_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_6d.html b/CMSIS/Documentation/Core/html/search/variables_6d.html
new file mode 100644
index 0000000000..2f3ed3d53c
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_6d.html
@@ -0,0 +1,68 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  MASK0
+  DWT_Type
+ 

+

+

+ 

+  MASK1
+  DWT_Type
+ 

+

+

+ 

+  MASK2
+  DWT_Type
+ 

+

+

+ 

+  MASK3
+  DWT_Type
+ 

+

+

+ 

+  MMFAR
+  SCB_Type
+ 

+

+

+ 

+  MMFR
+  SCB_Type
+ 

+

+

+ 

+  MVFR0
+  FPU_Type
+ 

+

+

+ 

+  MVFR1
+  FPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_6e.html b/CMSIS/Documentation/Core/html/search/variables_6e.html
new file mode 100644
index 0000000000..a802996b98
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_6e.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  nPRIV
+  CONTROL_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_70.html b/CMSIS/Documentation/Core/html/search/variables_70.html
new file mode 100644
index 0000000000..a017e22b15
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_70.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  PCSR
+  DWT_Type
+ 

+

+

+ 

+  PFR
+  SCB_Type
+ 

+

+

+ 

+  PORT
+  ITM_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_71.html b/CMSIS/Documentation/Core/html/search/variables_71.html
new file mode 100644
index 0000000000..0c1e07b428
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_71.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_72.html b/CMSIS/Documentation/Core/html/search/variables_72.html
new file mode 100644
index 0000000000..ea9fc465e2
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_72.html
@@ -0,0 +1,148 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  RASR
+  MPU_Type
+ 

+

+

+ 

+  RASR_A1
+  MPU_Type
+ 

+

+

+ 

+  RASR_A2
+  MPU_Type
+ 

+

+

+ 

+  RASR_A3
+  MPU_Type
+ 

+

+

+ 

+  RBAR
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A1
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A2
+  MPU_Type
+ 

+

+

+ 

+  RBAR_A3
+  MPU_Type
+ 

+

+
+
+
+
+
+
+

+ 

+  RESERVED7
+  TPI_Type
+ 

+

+

+ 

+  RNR
+  MPU_Type
+ 

+

+

+ 

+  RSERVED1
+  NVIC_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_73.html b/CMSIS/Documentation/Core/html/search/variables_73.html
new file mode 100644
index 0000000000..d4b45aebc6
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_73.html
@@ -0,0 +1,74 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  SCR
+  SCB_Type
+ 

+

+

+ 

+  SHCSR
+  SCB_Type
+ 

+

+

+ 

+  SHP
+  SCB_Type
+ 

+

+

+ 

+  SLEEPCNT
+  DWT_Type
+ 

+

+

+ 

+  SPPR
+  TPI_Type
+ 

+

+

+ 

+  SPSEL
+  CONTROL_Type
+ 

+

+

+ 

+  SSPSR
+  TPI_Type
+ 

+

+

+ 

+  STIR
+  NVIC_Type
+ 

+

+

+ 

+  SystemCoreClock
+  Ref_SystemAndClock.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_74.html b/CMSIS/Documentation/Core/html/search/variables_74.html
new file mode 100644
index 0000000000..66d0dbb7bf
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_74.html
@@ -0,0 +1,56 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  T
+  xPSR_Type
+ 

+

+

+ 

+  TCR
+  ITM_Type
+ 

+

+

+ 

+  TER
+  ITM_Type
+ 

+

+

+ 

+  TPR
+  ITM_Type
+ 

+

+

+ 

+  TRIGGER
+  TPI_Type
+ 

+

+

+ 

+  TYPE
+  MPU_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_75.html b/CMSIS/Documentation/Core/html/search/variables_75.html
new file mode 100644
index 0000000000..dded075176
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_75.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  u16
+  ITM_Type
+ 

+

+

+ 

+  u32
+  ITM_Type
+ 

+

+

+ 

+  u8
+  ITM_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_76.html b/CMSIS/Documentation/Core/html/search/variables_76.html
new file mode 100644
index 0000000000..4d6ec2cc80
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_76.html
@@ -0,0 +1,41 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  VAL
+  SysTick_Type
+ 

+

+

+ 

+  VTOR
+  SCB_Type
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_77.html b/CMSIS/Documentation/Core/html/search/variables_77.html
new file mode 100644
index 0000000000..fdc60a2f2e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_77.html
@@ -0,0 +1,31 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/search/variables_7a.html b/CMSIS/Documentation/Core/html/search/variables_7a.html
new file mode 100644
index 0000000000..1c0da898bf
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/search/variables_7a.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/Core/html/startup_s_pg.html b/CMSIS/Documentation/Core/html/startup_s_pg.html
new file mode 100644
index 0000000000..e16b33c1f2
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/startup_s_pg.html
@@ -0,0 +1,359 @@
+
+
+
+
+Startup File startup_<device>.s
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Startup File startup_<device>.s 
  

+

+

+
The Startup File startup_<device>.s contains:

+
    
+
  • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
    • 
+
  • The setup values for the Main Stack Pointer (MSP).
    • 
+
  • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
    • 
+
  • Interrupt vectors that are device specific with weak functions that implement default routines.
    • 
+

+
The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

+
To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.

+
Example: 

+
The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
                ; External Interrupts
+                DCD     WAKEUP0_IRQHandler       ; 16+ 0: Wakeup PIO0.0
+                DCD     WAKEUP1_IRQHandler       ; 16+ 1: Wakeup PIO0.1
+                DCD     WAKEUP2_IRQHandler       ; 16+ 2: Wakeup PIO0.2
+                 :       :
+                 :       :
+                DCD     EINT1_IRQHandler         ; 16+30: PIO INT1
+                DCD     EINT0_IRQHandler         ; 16+31: PIO INT0
+         :  
+         :
+                EXPORT  WAKEUP0_IRQHandler       [WEAK]
+                EXPORT  WAKEUP1_IRQHandler       [WEAK]
+                EXPORT  WAKEUP2_IRQHandler       [WEAK]
+                 :       :
+                 :       :                                               
+                EXPORT  EINT1_IRQHandler         [WEAK]
+                EXPORT  EINT0_IRQHandler         [WEAK]
+
+WAKEUP0_IRQHandler
+WAKEUP1_IRQHandler
+WAKEUP1_IRQHandler
+      :
+      :
+EINT1_IRQHandler
+EINT0_IRQHandler
+                B       .
+

+startup_Device.s Template File

+
The startup_Device.s Template File for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

+
;/**************************************************************************//**
+; * @file     startup_<Device>.s
+; * @brief    CMSIS Cortex-M# Core Device Startup File for
+; *           Device <Device>
+; * @version  V3.01
+; * @date     06. March 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     <DeviceInterrupt>_IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT  <DeviceInterrupt>_IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+<DeviceInterrupt>_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_core_debug___type.html b/CMSIS/Documentation/Core/html/struct_core_debug___type.html
new file mode 100644
index 0000000000..2d8c7d6e1c
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_core_debug___type.html
@@ -0,0 +1,207 @@
+
+
+
+
+CoreDebug_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
CoreDebug_Type Struct Reference
  

+

+

+
+
Structure type to access the Core Debug Register (CoreDebug).  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__IO uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register.  
__O uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register.  
__IO uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register.  
__IO uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t CoreDebug_Type::DCRDR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__O uint32_t CoreDebug_Type::DCRSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t CoreDebug_Type::DEMCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t CoreDebug_Type::DHCSR

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_d_w_t___type.html b/CMSIS/Documentation/Core/html/struct_d_w_t___type.html
new file mode 100644
index 0000000000..eb5fb16005
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_d_w_t___type.html
@@ -0,0 +1,492 @@
+
+
+
+
+DWT_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
DWT_Type Struct Reference
  

+

+

+
+
Structure type to access the Data Watchpoint and Trace Register (DWT).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__IO uint32_t CTRL
 Offset: 0x000 (R/W) Control Register.  
__IO uint32_t CYCCNT
 Offset: 0x004 (R/W) Cycle Count Register.  
__IO uint32_t CPICNT
 Offset: 0x008 (R/W) CPI Count Register.  
__IO uint32_t EXCCNT
 Offset: 0x00C (R/W) Exception Overhead Count Register.  
__IO uint32_t SLEEPCNT
 Offset: 0x010 (R/W) Sleep Count Register.  
__IO uint32_t LSUCNT
 Offset: 0x014 (R/W) LSU Count Register.  
__IO uint32_t FOLDCNT
 Offset: 0x018 (R/W) Folded-instruction Count Register.  
__I uint32_t PCSR
 Offset: 0x01C (R/ ) Program Counter Sample Register.  
__IO uint32_t COMP0
 Offset: 0x020 (R/W) Comparator Register 0.  
__IO uint32_t MASK0
 Offset: 0x024 (R/W) Mask Register 0.  
__IO uint32_t FUNCTION0
 Offset: 0x028 (R/W) Function Register 0.  
uint32_t RESERVED0 [1]
 Reserved.  
__IO uint32_t COMP1
 Offset: 0x030 (R/W) Comparator Register 1.  
__IO uint32_t MASK1
 Offset: 0x034 (R/W) Mask Register 1.  
__IO uint32_t FUNCTION1
 Offset: 0x038 (R/W) Function Register 1.  
uint32_t RESERVED1 [1]
 Reserved.  
__IO uint32_t COMP2
 Offset: 0x040 (R/W) Comparator Register 2.  
__IO uint32_t MASK2
 Offset: 0x044 (R/W) Mask Register 2.  
__IO uint32_t FUNCTION2
 Offset: 0x048 (R/W) Function Register 2.  
uint32_t RESERVED2 [1]
 Reserved.  
__IO uint32_t COMP3
 Offset: 0x050 (R/W) Comparator Register 3.  
__IO uint32_t MASK3
 Offset: 0x054 (R/W) Mask Register 3.  
__IO uint32_t FUNCTION3
 Offset: 0x058 (R/W) Function Register 3.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::COMP0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::COMP1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::COMP2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::COMP3

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::CPICNT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::CTRL

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::CYCCNT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::EXCCNT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::FOLDCNT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::FUNCTION0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::FUNCTION1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::FUNCTION2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::FUNCTION3

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::LSUCNT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::MASK0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::MASK1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::MASK2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::MASK3

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t DWT_Type::PCSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t DWT_Type::RESERVED0[1]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t DWT_Type::RESERVED1[1]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t DWT_Type::RESERVED2[1]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t DWT_Type::SLEEPCNT

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_f_p_u___type.html b/CMSIS/Documentation/Core/html/struct_f_p_u___type.html
new file mode 100644
index 0000000000..5ac444b4a7
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_f_p_u___type.html
@@ -0,0 +1,237 @@
+
+
+
+
+FPU_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
FPU_Type Struct Reference
  

+

+

+
+
Structure type to access the Floating Point Unit (FPU).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t RESERVED0 [1]
 Reserved.  
__IO uint32_t FPCCR
 Offset: 0x004 (R/W) Floating-Point Context Control Register.  
__IO uint32_t FPCAR
 Offset: 0x008 (R/W) Floating-Point Context Address Register.  
__IO uint32_t FPDSCR
 Offset: 0x00C (R/W) Floating-Point Default Status Control Register.  
__I uint32_t MVFR0
 Offset: 0x010 (R/ ) Media and FP Feature Register 0.  
__I uint32_t MVFR1
 Offset: 0x014 (R/ ) Media and FP Feature Register 1.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t FPU_Type::FPCAR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t FPU_Type::FPCCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t FPU_Type::FPDSCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t FPU_Type::MVFR0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t FPU_Type::MVFR1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t FPU_Type::RESERVED0[1]

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_i_t_m___type.html b/CMSIS/Documentation/Core/html/struct_i_t_m___type.html
new file mode 100644
index 0000000000..807428e10f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_i_t_m___type.html
@@ -0,0 +1,298 @@
+
+
+
+
+ITM_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
ITM_Type Struct Reference
  

+

+

+
+
Structure type to access the Instrumentation Trace Macrocell Register (ITM).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
union {
   __O uint8_t   u8
 Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.  
   __O uint16_t   u16
 Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.  
   __O uint32_t   u32
 Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.  
} PORT [32]
 Offset: 0x000 ( /W) ITM Stimulus Port Registers.  
uint32_t RESERVED0 [864]
 Reserved.  
__IO uint32_t TER
 Offset: 0xE00 (R/W) ITM Trace Enable Register.  
uint32_t RESERVED1 [15]
 Reserved.  
__IO uint32_t TPR
 Offset: 0xE40 (R/W) ITM Trace Privilege Register.  
uint32_t RESERVED2 [15]
 Reserved.  
__IO uint32_t TCR
 Offset: 0xE80 (R/W) ITM Trace Control Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__O { ... }    ITM_Type::PORT[32]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ITM_Type::RESERVED0[864]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ITM_Type::RESERVED1[15]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ITM_Type::RESERVED2[15]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t ITM_Type::TCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t ITM_Type::TER

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t ITM_Type::TPR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__O uint16_t ITM_Type::u16

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__O uint32_t ITM_Type::u32

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__O uint8_t ITM_Type::u8

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_m_p_u___type.html b/CMSIS/Documentation/Core/html/struct_m_p_u___type.html
new file mode 100644
index 0000000000..6abb25b03e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_m_p_u___type.html
@@ -0,0 +1,312 @@
+
+
+
+
+MPU_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
MPU_Type Struct Reference
  

+

+

+
+
Structure type to access the Memory Protection Unit (MPU).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__I uint32_t TYPE
 Offset: 0x000 (R/ ) MPU Type Register.  
__IO uint32_t CTRL
 Offset: 0x004 (R/W) MPU Control Register.  
__IO uint32_t RNR
 Offset: 0x008 (R/W) MPU Region RNRber Register.  
__IO uint32_t RBAR
 Offset: 0x00C (R/W) MPU Region Base Address Register.  
__IO uint32_t RASR
 Offset: 0x010 (R/W) MPU Region Attribute and Size Register.  
__IO uint32_t RBAR_A1
 Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.  
__IO uint32_t RASR_A1
 Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.  
__IO uint32_t RBAR_A2
 Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.  
__IO uint32_t RASR_A2
 Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.  
__IO uint32_t RBAR_A3
 Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.  
__IO uint32_t RASR_A3
 Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::CTRL

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RASR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RASR_A1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RASR_A2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RASR_A3

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RBAR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RBAR_A1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RBAR_A2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RBAR_A3

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t MPU_Type::RNR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t MPU_Type::TYPE

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html b/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html
new file mode 100644
index 0000000000..63b78ca890
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html
@@ -0,0 +1,342 @@
+
+
+
+
+NVIC_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
NVIC_Type Struct Reference
  

+

+

+
+
Structure type to access the Nested Vectored Interrupt Controller (NVIC).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__IO uint32_t ISER [8]
 Offset: 0x000 (R/W) Interrupt Set Enable Register.  
uint32_t RESERVED0 [24]
 Reserved.  
__IO uint32_t ICER [8]
 Offset: 0x080 (R/W) Interrupt Clear Enable Register.  
uint32_t RSERVED1 [24]
 Reserved.  
__IO uint32_t ISPR [8]
 Offset: 0x100 (R/W) Interrupt Set Pending Register.  
uint32_t RESERVED2 [24]
 Reserved.  
__IO uint32_t ICPR [8]
 Offset: 0x180 (R/W) Interrupt Clear Pending Register.  
uint32_t RESERVED3 [24]
 Reserved.  
__IO uint32_t IABR [8]
 Offset: 0x200 (R/W) Interrupt Active bit Register.  
uint32_t RESERVED4 [56]
 Reserved.  
__IO uint8_t IP [240]
 Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)  
uint32_t RESERVED5 [644]
 Reserved.  
__O uint32_t STIR
 Offset: 0xE00 ( /W) Software Trigger Interrupt Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t NVIC_Type::IABR[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t NVIC_Type::ICER[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t NVIC_Type::ICPR[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint8_t NVIC_Type::IP[240]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t NVIC_Type::ISER[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t NVIC_Type::ISPR[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RESERVED0[24]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RESERVED2[24]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RESERVED3[24]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RESERVED4[56]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RESERVED5[644]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t NVIC_Type::RSERVED1[24]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__O uint32_t NVIC_Type::STIR

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_s_c_b___type.html b/CMSIS/Documentation/Core/html/struct_s_c_b___type.html
new file mode 100644
index 0000000000..de2783ad1f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_s_c_b___type.html
@@ -0,0 +1,462 @@
+
+
+
+
+SCB_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
SCB_Type Struct Reference
  

+

+

+
+
Structure type to access the System Control Block (SCB).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__I uint32_t CPUID
 Offset: 0x000 (R/ ) CPUID Base Register.  
__IO uint32_t ICSR
 Offset: 0x004 (R/W) Interrupt Control and State Register.  
__IO uint32_t VTOR
 Offset: 0x008 (R/W) Vector Table Offset Register.  
__IO uint32_t AIRCR
 Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.  
__IO uint32_t SCR
 Offset: 0x010 (R/W) System Control Register.  
__IO uint32_t CCR
 Offset: 0x014 (R/W) Configuration Control Register.  
__IO uint8_t SHP [12]
 Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)  
__IO uint32_t SHCSR
 Offset: 0x024 (R/W) System Handler Control and State Register.  
__IO uint32_t CFSR
 Offset: 0x028 (R/W) Configurable Fault Status Register.  
__IO uint32_t HFSR
 Offset: 0x02C (R/W) HardFault Status Register.  
__IO uint32_t DFSR
 Offset: 0x030 (R/W) Debug Fault Status Register.  
__IO uint32_t MMFAR
 Offset: 0x034 (R/W) MemManage Fault Address Register.  
__IO uint32_t BFAR
 Offset: 0x038 (R/W) BusFault Address Register.  
__IO uint32_t AFSR
 Offset: 0x03C (R/W) Auxiliary Fault Status Register.  
__I uint32_t PFR [2]
 Offset: 0x040 (R/ ) Processor Feature Register.  
__I uint32_t DFR
 Offset: 0x048 (R/ ) Debug Feature Register.  
__I uint32_t ADR
 Offset: 0x04C (R/ ) Auxiliary Feature Register.  
__I uint32_t MMFR [4]
 Offset: 0x050 (R/ ) Memory Model Feature Register.  
__I uint32_t ISAR [5]
 Offset: 0x060 (R/ ) Instruction Set Attributes Register.  
uint32_t RESERVED0 [5]
 Reserved.  
__IO uint32_t CPACR
 Offset: 0x088 (R/W) Coprocessor Access Control Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::ADR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::AFSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::AIRCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::BFAR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::CCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::CFSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::CPACR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::CPUID

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::DFR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::DFSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::HFSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::ICSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::ISAR[5]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::MMFAR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::MMFR[4]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCB_Type::PFR[2]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t SCB_Type::RESERVED0[5]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::SCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::SHCSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint8_t SCB_Type::SHP[12]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCB_Type::VTOR

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html b/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html
new file mode 100644
index 0000000000..4c307fe41e
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html
@@ -0,0 +1,192 @@
+
+
+
+
+SCnSCB_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
SCnSCB_Type Struct Reference
  

+

+

+
+
Structure type to access the System Control and ID Register not in the SCB.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t RESERVED0 [1]
 Reserved.  
__I uint32_t ICTR
 Offset: 0x004 (R/ ) Interrupt Controller Type Register.  
__IO uint32_t ACTLR
 Offset: 0x008 (R/W) Auxiliary Control Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SCnSCB_Type::ACTLR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SCnSCB_Type::ICTR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t SCnSCB_Type::RESERVED0[1]

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_sys_tick___type.html b/CMSIS/Documentation/Core/html/struct_sys_tick___type.html
new file mode 100644
index 0000000000..81f2d6f272
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_sys_tick___type.html
@@ -0,0 +1,207 @@
+
+
+
+
+SysTick_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
SysTick_Type Struct Reference
  

+

+

+
+
Structure type to access the System Timer (SysTick).  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__IO uint32_t CTRL
 Offset: 0x000 (R/W) SysTick Control and Status Register.  
__IO uint32_t LOAD
 Offset: 0x004 (R/W) SysTick Reload Value Register.  
__IO uint32_t VAL
 Offset: 0x008 (R/W) SysTick Current Value Register.  
__I uint32_t CALIB
 Offset: 0x00C (R/ ) SysTick Calibration Register.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__I uint32_t SysTick_Type::CALIB

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SysTick_Type::CTRL

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SysTick_Type::LOAD

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t SysTick_Type::VAL

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/struct_t_p_i___type.html b/CMSIS/Documentation/Core/html/struct_t_p_i___type.html
new file mode 100644
index 0000000000..cadd4e0301
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/struct_t_p_i___type.html
@@ -0,0 +1,507 @@
+
+
+
+
+TPI_Type Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
TPI_Type Struct Reference
  

+

+

+
+
Structure type to access the Trace Port Interface Register (TPI).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
__IO uint32_t SSPSR
 Offset: 0x000 (R/ ) Supported Parallel Port Size Register.  
__IO uint32_t CSPSR
 Offset: 0x004 (R/W) Current Parallel Port Size Register.  
uint32_t RESERVED0 [2]
 Reserved.  
__IO uint32_t ACPR
 Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.  
uint32_t RESERVED1 [55]
 Reserved.  
__IO uint32_t SPPR
 Offset: 0x0F0 (R/W) Selected Pin Protocol Register.  
uint32_t RESERVED2 [131]
 Reserved.  
__I uint32_t FFSR
 Offset: 0x300 (R/ ) Formatter and Flush Status Register.  
__IO uint32_t FFCR
 Offset: 0x304 (R/W) Formatter and Flush Control Register.  
__I uint32_t FSCR
 Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.  
uint32_t RESERVED3 [759]
 Reserved.  
__I uint32_t TRIGGER
 Offset: 0xEE8 (R/ ) TRIGGER.  
__I uint32_t FIFO0
 Offset: 0xEEC (R/ ) Integration ETM Data.  
__I uint32_t ITATBCTR2
 Offset: 0xEF0 (R/ ) ITATBCTR2.  
uint32_t RESERVED4 [1]
 Reserved.  
__I uint32_t ITATBCTR0
 Offset: 0xEF8 (R/ ) ITATBCTR0.  
__I uint32_t FIFO1
 Offset: 0xEFC (R/ ) Integration ITM Data.  
__IO uint32_t ITCTRL
 Offset: 0xF00 (R/W) Integration Mode Control.  
uint32_t RESERVED5 [39]
 Reserved.  
__IO uint32_t CLAIMSET
 Offset: 0xFA0 (R/W) Claim tag set.  
__IO uint32_t CLAIMCLR
 Offset: 0xFA4 (R/W) Claim tag clear.  
uint32_t RESERVED7 [8]
 Reserved.  
__I uint32_t DEVID
 Offset: 0xFC8 (R/ ) TPIU_DEVID.  
__I uint32_t DEVTYPE
 Offset: 0xFCC (R/ ) TPIU_DEVTYPE.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::ACPR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::CLAIMCLR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::CLAIMSET

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::CSPSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::DEVID

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::DEVTYPE

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::FFCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::FFSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::FIFO0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::FIFO1

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::FSCR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::ITATBCTR0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::ITATBCTR2

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::ITCTRL

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED0[2]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED1[55]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED2[131]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED3[759]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED4[1]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED5[39]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t TPI_Type::RESERVED7[8]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::SPPR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__IO uint32_t TPI_Type::SSPSR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
__I uint32_t TPI_Type::TRIGGER

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/system_c_pg.html b/CMSIS/Documentation/Core/html/system_c_pg.html
new file mode 100644
index 0000000000..04920b01e7
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/system_c_pg.html
@@ -0,0 +1,286 @@
+
+
+
+
+System Configuration Files system_<device>.c and system_<device>.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
System Configuration Files system_<device>.c and system_<device>.h 
  

+

+

+
The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

+
For devices with external memory BUS the system_<device>.c also configures the BUS system.

+
The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

+

+system_Device.c Template File

+
The system_Device.c Template File for the Cortex-M3 is shown below.

+
/**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "<Device>.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization     
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+

+system_Device.h Template File

+
The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

+
/**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/tab_a.png b/CMSIS/Documentation/Core/html/tab_a.png
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diff --git a/CMSIS/Documentation/Core/html/tab_b.png b/CMSIS/Documentation/Core/html/tab_b.png
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diff --git a/CMSIS/Documentation/Core/html/tab_h.png b/CMSIS/Documentation/Core/html/tab_h.png
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diff --git a/CMSIS/Documentation/Core/html/tab_s.png b/CMSIS/Documentation/Core/html/tab_s.png
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diff --git a/CMSIS/Documentation/Core/html/tab_topnav.png b/CMSIS/Documentation/Core/html/tab_topnav.png
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index 0000000000..b257b7780f
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diff --git a/CMSIS/Documentation/Core/html/tabs.css b/CMSIS/Documentation/Core/html/tabs.css
new file mode 100644
index 0000000000..ffbab509d7
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/tabs.css
@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
+    font-size: 12px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
+}
+
+.tabs1 .tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_topnav.png');
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html b/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html
new file mode 100644
index 0000000000..9bcc52feea
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html
@@ -0,0 +1,268 @@
+
+
+
+
+APSR_Type Union Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
APSR_Type Union Reference
  

+

+

+
+
Union type to access the Application Program Status Register (APSR).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
struct {
   uint32_t   _reserved0:27
 bit: 0..26 Reserved  
   uint32_t   Q:1
 bit: 27 Saturation condition flag  
   uint32_t   V:1
 bit: 28 Overflow condition code flag  
   uint32_t   C:1
 bit: 29 Carry condition code flag  
   uint32_t   Z:1
 bit: 30 Zero condition code flag  
   uint32_t   N:1
 bit: 31 Negative condition code flag  
} b
 Structure used for bit access.  
uint32_t w
 Type used for word access.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::_reserved0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
struct { ... }   APSR_Type::b

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::C

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::N

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::Q

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::V

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::w

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t APSR_Type::Z

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html b/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html
new file mode 100644
index 0000000000..b943e1283f
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html
@@ -0,0 +1,238 @@
+
+
+
+
+CONTROL_Type Union Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
CONTROL_Type Union Reference
  

+

+

+
+
Union type to access the Control Registers (CONTROL).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
struct {
   uint32_t   nPRIV:1
 bit: 0 Execution privilege in Thread mode  
   uint32_t   SPSEL:1
 bit: 1 Stack to be used  
   uint32_t   FPCA:1
 bit: 2 FP extension active flag  
   uint32_t   _reserved0:29
 bit: 3..31 Reserved  
} b
 Structure used for bit access.  
uint32_t w
 Type used for word access.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t CONTROL_Type::_reserved0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
struct { ... }   CONTROL_Type::b

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t CONTROL_Type::FPCA

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t CONTROL_Type::nPRIV

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t CONTROL_Type::SPSEL

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t CONTROL_Type::w

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html b/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html
new file mode 100644
index 0000000000..f2cd1c0b05
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html
@@ -0,0 +1,208 @@
+
+
+
+
+IPSR_Type Union Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
IPSR_Type Union Reference
  

+

+

+
+
Union type to access the Interrupt Program Status Register (IPSR).  
+

+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number  
   uint32_t   _reserved0:23
 bit: 9..31 Reserved  
} b
 Structure used for bit access.  
uint32_t w
 Type used for word access.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t IPSR_Type::_reserved0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
struct { ... }   IPSR_Type::b

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t IPSR_Type::ISR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t IPSR_Type::w

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html b/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html
new file mode 100644
index 0000000000..1816f20879
--- /dev/null
+++ b/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html
@@ -0,0 +1,313 @@
+
+
+
+
+xPSR_Type Union Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-CORE
+    Version 3.01
+   

+   
CMSIS-CORE support for Cortex-M processor-based devices

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
xPSR_Type Union Reference
  

+

+

+
+
Union type to access the Special-Purpose Program Status Registers (xPSR).  
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Data Fields
struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number  
   uint32_t   _reserved0:15
 bit: 9..23 Reserved  
   uint32_t   T:1
 bit: 24 Thumb bit (read 0)  
   uint32_t   IT:2
 bit: 25..26 saved IT state (read 0)  
   uint32_t   Q:1
 bit: 27 Saturation condition flag  
   uint32_t   V:1
 bit: 28 Overflow condition code flag  
   uint32_t   C:1
 bit: 29 Carry condition code flag  
   uint32_t   Z:1
 bit: 30 Zero condition code flag  
   uint32_t   N:1
 bit: 31 Negative condition code flag  
} b
 Structure used for bit access.  
uint32_t w
 Type used for word access.  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::_reserved0

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
struct { ... }   xPSR_Type::b

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::C

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::ISR

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::IT

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::N

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::Q

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::T

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::V

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::w

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t xPSR_Type::Z

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/Biquad.gif b/CMSIS/Documentation/DSP/html/Biquad.gif
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index 0000000000..7a3b46abe1
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index 0000000000..356152babd
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diff --git a/CMSIS/Documentation/DSP/html/LMS.gif b/CMSIS/Documentation/DSP/html/LMS.gif
new file mode 100644
index 0000000000..15eddafbd7
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index 0000000000..fb8e5bd1fc
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index 0000000000..47095d0216
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index 0000000000..219220e4b9
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diff --git a/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_b_e_8txt.html b/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_b_e_8txt.html
new file mode 100644
index 0000000000..c20c5ccd44
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_b_e_8txt.html
@@ -0,0 +1,484 @@
+
+
+
+
+DSP_Lib CM0 BE.txt File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
DSP_Lib CM0 BE.txt File Reference
  

+

+

+
+
+
+

+Functions
Rebuild target DSP_Lib CM0 BE 

+compiling arm_abs_f32 c 

+compiling arm_abs_q7 c 

+compiling arm_abs_q15 c 

+compiling arm_abs_q31 c 

+compiling arm_add_f32 c 

+compiling arm_add_q7 c 

+compiling arm_add_q15 c 

+compiling arm_add_q31 c 

+compiling arm_dot_prod_f32 c 

+compiling arm_dot_prod_q7 c 

+compiling arm_dot_prod_q15 c 

+compiling arm_dot_prod_q31 c 

+compiling arm_mult_f32 c 

+compiling arm_mult_q7 c 

+compiling arm_mult_q15 c 

+compiling arm_mult_q31 c 

+compiling arm_negate_f32 c 

+compiling arm_negate_q7 c 

+compiling arm_negate_q15 c 

+compiling arm_negate_q31 c 

+compiling arm_offset_f32 c 

+compiling arm_offset_q7 c 

+compiling arm_offset_q15 c 

+compiling arm_offset_q31 c 

+compiling arm_scale_f32 c 

+compiling arm_scale_q7 c 

+compiling arm_scale_q15 c 

+compiling arm_scale_q31 c 

+compiling arm_shift_q7 c 

+compiling arm_shift_q15 c 

+compiling arm_shift_q31 c 

+compiling arm_sub_f32 c 

+compiling arm_sub_q7 c 

+compiling arm_sub_q15 c 

+compiling arm_sub_q31 c 

+compiling arm_cos_f32 c 

+compiling arm_cos_q15 c 

+compiling arm_cos_q31 c 

+compiling arm_sin_f32 c 

+compiling arm_sin_q15 c 

+compiling arm_sin_q31 c 

+compiling arm_sqrt_q15 c 

+compiling arm_sqrt_q31 c 

+compiling arm_cmplx_conj_f32 c 

+compiling arm_cmplx_conj_q15 c 

+compiling arm_cmplx_conj_q31 c 

+compiling 

+arm_cmplx_dot_prod_f32 c 

+compiling 

+arm_cmplx_dot_prod_q15 c 

+compiling 

+arm_cmplx_dot_prod_q31 c 

+compiling arm_cmplx_mag_f32 c 

+compiling arm_cmplx_mag_q15 c 

+compiling arm_cmplx_mag_q31 c 

+compiling 

+arm_cmplx_mag_squared_f32 c 

+compiling 

+arm_cmplx_mag_squared_q15 c 

+compiling 

+arm_cmplx_mag_squared_q31 c 

+compiling 

+arm_cmplx_mult_cmplx_f32 c 

+compiling 

+arm_cmplx_mult_cmplx_q15 c 

+compiling 

+arm_cmplx_mult_cmplx_q31 c 

+compiling 

+arm_cmplx_mult_real_f32 c 

+compiling 

+arm_cmplx_mult_real_q15 c 

+compiling 

+arm_cmplx_mult_real_q31 c 

+compiling 

+arm_biquad_cascade_df1_32x64_init_q31 

+c compiling 

+arm_biquad_cascade_df1_32x64_q31 

+c compiling 

+arm_biquad_cascade_df1_f32 c 

+compiling 

+arm_biquad_cascade_df1_fast_q15 

+c compiling 

+arm_biquad_cascade_df1_fast_q31 

+c compiling 

+arm_biquad_cascade_df1_init_f32 

+c compiling 

+arm_biquad_cascade_df1_init_q15 

+c compiling 

+arm_biquad_cascade_df1_init_q31 

+c compiling 

+arm_biquad_cascade_df1_q15 c 

+compiling 

+arm_biquad_cascade_df1_q31 c 

+compiling 

+arm_biquad_cascade_df2T_f32 c 

+compiling 

+arm_biquad_cascade_df2T_init_f32 

+c compiling arm_conv_f32 c 

+compiling arm_conv_fast_q15 c 

+compiling 

+arm_conv_fast_opt_q15 c 

+compiling arm_conv_fast_q31 c 

+compiling arm_conv_partial_f32 

+c compiling 

+arm_conv_partial_fast_q15 c 

+compiling 

+arm_conv_partial_fast_opt_q15 

+c compiling 

+arm_conv_partial_fast_q31 c 

+compiling arm_conv_partial_q7 

+c compiling 

+arm_conv_partial_opt_q7 c 

+compiling arm_conv_partial_q15 

+c compiling 

+arm_conv_partial_opt_q15 c 

+compiling arm_conv_partial_q31 

+c compiling arm_conv_q7 c 

+compiling arm_conv_opt_q7 c 

+compiling arm_conv_q15 c 

+compiling arm_conv_opt_q15 c 

+compiling arm_conv_q31 c 

+compiling arm_correlate_f32 c 

+compiling 

+arm_correlate_fast_q15 c 

+compiling 

+arm_correlate_fast_opt_q15 c 

+compiling 

+arm_correlate_fast_q31 c 

+compiling arm_correlate_q7 c 

+compiling arm_correlate_opt_q7 

+c compiling arm_correlate_q15 

+c compiling 

+arm_correlate_opt_q15 c 

+compiling arm_correlate_q31 c 

+compiling arm_fir_decimate_f32 

+c compiling 

+arm_fir_decimate_fast_q15 c 

+compiling 

+arm_fir_decimate_fast_q31 c 

+compiling 

+arm_fir_decimate_init_f32 c 

+compiling 

+arm_fir_decimate_init_q15 c 

+compiling 

+arm_fir_decimate_init_q31 c 

+compiling arm_fir_decimate_q15 

+c compiling 

+arm_fir_decimate_q31 c 

+compiling arm_fir_f32 c 

+compiling arm_fir_fast_q15 c 

+compiling arm_fir_fast_q31 c 

+compiling arm_fir_init_f32 c 

+compiling arm_fir_init_q7 c 

+compiling arm_fir_init_q15 c 

+compiling arm_fir_init_q31 c 

+compiling 

+arm_fir_interpolate_f32 c 

+compiling 

+arm_fir_interpolate_init_f32 c 

+compiling 

+arm_fir_interpolate_init_q15 c 

+compiling 

+arm_fir_interpolate_init_q31 c 

+compiling 

+arm_fir_interpolate_q15 c 

+compiling 

+arm_fir_interpolate_q31 c 

+compiling arm_fir_lattice_f32 

+c compiling 

+arm_fir_lattice_init_f32 c 

+compiling 

+arm_fir_lattice_init_q15 c 

+compiling 

+arm_fir_lattice_init_q31 c 

+compiling arm_fir_lattice_q15 

+c compiling 

+arm_fir_lattice_q31 c 

+compiling arm_fir_q7 c 

+compiling arm_fir_q15 c 

+compiling arm_fir_q31 c 

+compiling arm_fir_sparse_f32 c 

+compiling 

+arm_fir_sparse_init_f32 c 

+compiling 

+arm_fir_sparse_init_q7 c 

+compiling 

+arm_fir_sparse_init_q15 c 

+compiling 

+arm_fir_sparse_init_q31 c 

+compiling arm_fir_sparse_q7 c 

+compiling arm_fir_sparse_q15 c 

+compiling arm_fir_sparse_q31 c 

+compiling arm_iir_lattice_f32 

+c compiling 

+arm_iir_lattice_init_f32 c 

+compiling 

+arm_iir_lattice_init_q15 c 

+compiling 

+arm_iir_lattice_init_q31 c 

+compiling arm_iir_lattice_q15 

+c compiling 

+arm_iir_lattice_q31 c 

+compiling arm_lms_f32 c 

+compiling arm_lms_init_f32 c 

+compiling arm_lms_init_q15 c 

+compiling arm_lms_init_q31 c 

+compiling arm_lms_norm_f32 c 

+compiling 

+arm_lms_norm_init_f32 c 

+compiling 

+arm_lms_norm_init_q15 c 

+compiling 

+arm_lms_norm_init_q31 c 

+compiling arm_lms_norm_q15 c 

+compiling arm_lms_norm_q31 c 

+compiling arm_lms_q15 c 

+compiling arm_lms_q31 c 

+compiling arm_mat_add_f32 c 

+compiling arm_mat_add_q15 c 

+compiling arm_mat_add_q31 c 

+compiling arm_mat_init_f32 c 

+compiling arm_mat_init_q15 c 

+compiling arm_mat_init_q31 c 

+compiling arm_mat_inverse_f32 

+c compiling arm_mat_mult_f32 c 

+compiling 

+arm_mat_mult_fast_q15 c 

+compiling 

+arm_mat_mult_fast_q31 c 

+compiling arm_mat_mult_q15 c 

+compiling arm_mat_mult_q31 c 

+compiling arm_mat_scale_f32 c 

+compiling arm_mat_scale_q15 c 

+compiling arm_mat_scale_q31 c 

+compiling arm_mat_sub_f32 c 

+compiling arm_mat_sub_q15 c 

+compiling arm_mat_sub_q31 c 

+compiling arm_mat_trans_f32 c 

+compiling arm_mat_trans_q15 c 

+compiling arm_mat_trans_q31 c 

+compiling arm_bitreversal c 

+compiling arm_cfft_radix2_f32 

+c compiling 

+arm_cfft_radix2_init_f32 c 

+compiling 

+arm_cfft_radix2_init_q15 c 

+compiling 

+arm_cfft_radix2_init_q31 c 

+compiling arm_cfft_radix2_q15 

+c compiling 

+arm_cfft_radix2_q31 c 

+compiling arm_cfft_radix4_f32 

+c compiling 

+arm_cfft_radix4_init_f32 c 

+compiling 

+arm_cfft_radix4_init_q15 c 

+compiling 

+arm_cfft_radix4_init_q31 c 

+compiling arm_cfft_radix4_q15 

+c compiling 

+arm_cfft_radix4_q31 c 

+compiling arm_dct4_f32 c 

+compiling arm_dct4_init_f32 c 

+compiling arm_dct4_init_q15 c 

+compiling arm_dct4_init_q31 c 

+compiling arm_dct4_q15 c 

+compiling arm_dct4_q31 c 

+compiling arm_rfft_f32 c 

+compiling arm_rfft_init_f32 c 

+compiling arm_rfft_init_q15 c 

+compiling arm_rfft_init_q31 c 

+compiling arm_rfft_q15 c 

+compiling arm_rfft_q31 c 

+compiling arm_pid_init_f32 c 

+compiling arm_pid_init_q15 c 

+compiling arm_pid_init_q31 c 

+compiling arm_pid_reset_f32 c 

+compiling arm_pid_reset_q15 c 

+compiling arm_pid_reset_q31 c 

+compiling arm_sin_cos_f32 c 

+compiling arm_sin_cos_q31 c 

+compiling arm_max_f32 c 

+compiling arm_max_q7 c 

+compiling arm_max_q15 c 

+compiling arm_max_q31 c 

+compiling arm_mean_f32 c 

+compiling arm_mean_q7 c 

+compiling arm_mean_q15 c 

+compiling arm_mean_q31 c 

+compiling arm_min_f32 c 

+compiling arm_min_q7 c 

+compiling arm_min_q15 c 

+compiling arm_min_q31 c 

+compiling arm_power_f32 c 

+compiling arm_power_q7 c 

+compiling arm_power_q15 c 

+compiling arm_power_q31 c 

+compiling arm_rms_f32 c 

+compiling arm_rms_q15 c 

+compiling arm_rms_q31 c 

+compiling arm_std_f32 c 

+compiling arm_std_q15 c 

+compiling arm_std_q31 c 

+compiling arm_var_f32 c 

+compiling arm_var_q15 c 

+compiling arm_var_q31 c 

+compiling arm_copy_f32 c 

+compiling arm_copy_q7 c 

+compiling arm_copy_q15 c 

+compiling arm_copy_q31 c 

+compiling arm_fill_f32 c 

+compiling arm_fill_q7 c 

+compiling arm_fill_q15 c 

+compiling arm_fill_q31 c 

+compiling arm_float_to_q7 c 

+compiling arm_float_to_q15 c 

+compiling arm_float_to_q31 c 

+compiling arm_q7_to_float c 

+compiling arm_q7_to_q15 c 

+compiling arm_q7_to_q31 c 

+compiling arm_q15_to_float c 

+compiling arm_q15_to_q7 c 

+compiling arm_q15_to_q31 c 

+compiling arm_q31_to_float c 

+compiling arm_q31_to_q7 c 

+compiling arm_q31_to_q15 c 

+compiling arm_common_tables c 

+creating Library User command 		file (s) copied.".\intermediateFiles\arm_cortexM0b_math.lib"-0 Error(s)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
Rebuild target DSP_Lib CM0 BE compiling arm_abs_f32 c compiling arm_abs_q7 c compiling arm_abs_q15 c compiling arm_abs_q31 c compiling arm_add_f32 c compiling arm_add_q7 c compiling arm_add_q15 c compiling arm_add_q31 c compiling arm_dot_prod_f32 c compiling arm_dot_prod_q7 c compiling arm_dot_prod_q15 c compiling arm_dot_prod_q31 c compiling arm_mult_f32 c compiling arm_mult_q7 c compiling arm_mult_q15 c compiling arm_mult_q31 c compiling arm_negate_f32 c compiling arm_negate_q7 c compiling arm_negate_q15 c compiling arm_negate_q31 c compiling arm_offset_f32 c compiling arm_offset_q7 c compiling arm_offset_q15 c compiling arm_offset_q31 c compiling arm_scale_f32 c compiling arm_scale_q7 c compiling arm_scale_q15 c compiling arm_scale_q31 c compiling arm_shift_q7 c compiling arm_shift_q15 c compiling arm_shift_q31 c compiling arm_sub_f32 c compiling arm_sub_q7 c compiling arm_sub_q15 c compiling arm_sub_q31 c compiling arm_cos_f32 c compiling arm_cos_q15 c compiling arm_cos_q31 c compiling arm_sin_f32 c compiling arm_sin_q15 c compiling arm_sin_q31 c compiling arm_sqrt_q15 c compiling arm_sqrt_q31 c compiling arm_cmplx_conj_f32 c compiling arm_cmplx_conj_q15 c compiling arm_cmplx_conj_q31 c compiling arm_cmplx_dot_prod_f32 c compiling arm_cmplx_dot_prod_q15 c compiling arm_cmplx_dot_prod_q31 c compiling arm_cmplx_mag_f32 c compiling arm_cmplx_mag_q15 c compiling arm_cmplx_mag_q31 c compiling arm_cmplx_mag_squared_f32 c compiling arm_cmplx_mag_squared_q15 c compiling arm_cmplx_mag_squared_q31 c compiling arm_cmplx_mult_cmplx_f32 c compiling arm_cmplx_mult_cmplx_q15 c compiling arm_cmplx_mult_cmplx_q31 c compiling arm_cmplx_mult_real_f32 c compiling arm_cmplx_mult_real_q15 c compiling arm_cmplx_mult_real_q31 c compiling arm_biquad_cascade_df1_32x64_init_q31 c compiling arm_biquad_cascade_df1_32x64_q31 c compiling arm_biquad_cascade_df1_f32 c compiling arm_biquad_cascade_df1_fast_q15 c compiling arm_biquad_cascade_df1_fast_q31 c compiling arm_biquad_cascade_df1_init_f32 c compiling arm_biquad_cascade_df1_init_q15 c compiling arm_biquad_cascade_df1_init_q31 c compiling arm_biquad_cascade_df1_q15 c compiling arm_biquad_cascade_df1_q31 c compiling arm_biquad_cascade_df2T_f32 c compiling arm_biquad_cascade_df2T_init_f32 c compiling arm_conv_f32 c compiling arm_conv_fast_q15 c compiling arm_conv_fast_opt_q15 c compiling arm_conv_fast_q31 c compiling arm_conv_partial_f32 c compiling arm_conv_partial_fast_q15 c compiling arm_conv_partial_fast_opt_q15 c compiling arm_conv_partial_fast_q31 c compiling arm_conv_partial_q7 c compiling arm_conv_partial_opt_q7 c compiling arm_conv_partial_q15 c compiling arm_conv_partial_opt_q15 c compiling arm_conv_partial_q31 c compiling arm_conv_q7 c compiling arm_conv_opt_q7 c compiling arm_conv_q15 c compiling arm_conv_opt_q15 c compiling arm_conv_q31 c compiling arm_correlate_f32 c compiling arm_correlate_fast_q15 c compiling arm_correlate_fast_opt_q15 c compiling arm_correlate_fast_q31 c compiling arm_correlate_q7 c compiling arm_correlate_opt_q7 c compiling arm_correlate_q15 c compiling arm_correlate_opt_q15 c compiling arm_correlate_q31 c compiling arm_fir_decimate_f32 c compiling arm_fir_decimate_fast_q15 c compiling arm_fir_decimate_fast_q31 c compiling arm_fir_decimate_init_f32 c compiling arm_fir_decimate_init_q15 c compiling arm_fir_decimate_init_q31 c compiling arm_fir_decimate_q15 c compiling arm_fir_decimate_q31 c compiling arm_fir_f32 c compiling arm_fir_fast_q15 c compiling arm_fir_fast_q31 c compiling arm_fir_init_f32 c compiling arm_fir_init_q7 c compiling arm_fir_init_q15 c compiling arm_fir_init_q31 c compiling arm_fir_interpolate_f32 c compiling arm_fir_interpolate_init_f32 c compiling arm_fir_interpolate_init_q15 c compiling arm_fir_interpolate_init_q31 c compiling arm_fir_interpolate_q15 c compiling arm_fir_interpolate_q31 c compiling arm_fir_lattice_f32 c compiling arm_fir_lattice_init_f32 c compiling arm_fir_lattice_init_q15 c compiling arm_fir_lattice_init_q31 c compiling arm_fir_lattice_q15 c compiling arm_fir_lattice_q31 c compiling arm_fir_q7 c compiling arm_fir_q15 c compiling arm_fir_q31 c compiling arm_fir_sparse_f32 c compiling arm_fir_sparse_init_f32 c compiling arm_fir_sparse_init_q7 c compiling arm_fir_sparse_init_q15 c compiling arm_fir_sparse_init_q31 c compiling arm_fir_sparse_q7 c compiling arm_fir_sparse_q15 c compiling arm_fir_sparse_q31 c compiling arm_iir_lattice_f32 c compiling arm_iir_lattice_init_f32 c compiling arm_iir_lattice_init_q15 c compiling arm_iir_lattice_init_q31 c compiling arm_iir_lattice_q15 c compiling arm_iir_lattice_q31 c compiling arm_lms_f32 c compiling arm_lms_init_f32 c compiling arm_lms_init_q15 c compiling arm_lms_init_q31 c compiling arm_lms_norm_f32 c compiling arm_lms_norm_init_f32 c compiling arm_lms_norm_init_q15 c compiling arm_lms_norm_init_q31 c compiling arm_lms_norm_q15 c compiling arm_lms_norm_q31 c compiling arm_lms_q15 c compiling arm_lms_q31 c compiling arm_mat_add_f32 c compiling arm_mat_add_q15 c compiling arm_mat_add_q31 c compiling arm_mat_init_f32 c compiling arm_mat_init_q15 c compiling arm_mat_init_q31 c compiling arm_mat_inverse_f32 c compiling arm_mat_mult_f32 c compiling arm_mat_mult_fast_q15 c compiling arm_mat_mult_fast_q31 c compiling arm_mat_mult_q15 c compiling arm_mat_mult_q31 c compiling arm_mat_scale_f32 c compiling arm_mat_scale_q15 c compiling arm_mat_scale_q31 c compiling arm_mat_sub_f32 c compiling arm_mat_sub_q15 c compiling arm_mat_sub_q31 c compiling arm_mat_trans_f32 c compiling arm_mat_trans_q15 c compiling arm_mat_trans_q31 c compiling arm_bitreversal c compiling arm_cfft_radix2_f32 c compiling arm_cfft_radix2_init_f32 c compiling arm_cfft_radix2_init_q15 c compiling arm_cfft_radix2_init_q31 c compiling arm_cfft_radix2_q15 c compiling arm_cfft_radix2_q31 c compiling arm_cfft_radix4_f32 c compiling arm_cfft_radix4_init_f32 c compiling arm_cfft_radix4_init_q15 c compiling arm_cfft_radix4_init_q31 c compiling arm_cfft_radix4_q15 c compiling arm_cfft_radix4_q31 c compiling arm_dct4_f32 c compiling arm_dct4_init_f32 c compiling arm_dct4_init_q15 c compiling arm_dct4_init_q31 c compiling arm_dct4_q15 c compiling arm_dct4_q31 c compiling arm_rfft_f32 c compiling arm_rfft_init_f32 c compiling arm_rfft_init_q15 c compiling arm_rfft_init_q31 c compiling arm_rfft_q15 c compiling arm_rfft_q31 c compiling arm_pid_init_f32 c compiling arm_pid_init_q15 c compiling arm_pid_init_q31 c compiling arm_pid_reset_f32 c compiling arm_pid_reset_q15 c compiling arm_pid_reset_q31 c compiling arm_sin_cos_f32 c compiling arm_sin_cos_q31 c compiling arm_max_f32 c compiling arm_max_q7 c compiling arm_max_q15 c compiling arm_max_q31 c compiling arm_mean_f32 c compiling arm_mean_q7 c compiling arm_mean_q15 c compiling arm_mean_q31 c compiling arm_min_f32 c compiling arm_min_q7 c compiling arm_min_q15 c compiling arm_min_q31 c compiling arm_power_f32 c compiling arm_power_q7 c compiling arm_power_q15 c compiling arm_power_q31 c compiling arm_rms_f32 c compiling arm_rms_q15 c compiling arm_rms_q31 c compiling arm_std_f32 c compiling arm_std_q15 c compiling arm_std_q31 c compiling arm_var_f32 c compiling arm_var_q15 c compiling arm_var_q31 c compiling arm_copy_f32 c compiling arm_copy_q7 c compiling arm_copy_q15 c compiling arm_copy_q31 c compiling arm_fill_f32 c compiling arm_fill_q7 c compiling arm_fill_q15 c compiling arm_fill_q31 c compiling arm_float_to_q7 c compiling arm_float_to_q15 c compiling arm_float_to_q31 c compiling arm_q7_to_float c compiling arm_q7_to_q15 c compiling arm_q7_to_q31 c compiling arm_q15_to_float c compiling arm_q15_to_q7 c compiling arm_q15_to_q31 c compiling arm_q31_to_float c compiling arm_q31_to_q7 c compiling arm_q31_to_q15 c compiling arm_common_tables c creating Library User command file (s )

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_l_e_8txt.html b/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_l_e_8txt.html
new file mode 100644
index 0000000000..b0eb534be9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m0_01_l_e_8txt.html
@@ -0,0 +1,484 @@
+
+
+
+
+DSP_Lib CM0 LE.txt File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
DSP_Lib CM0 LE.txt File Reference
  

+

+

+
+
+
+

+Functions
Rebuild target DSP_Lib CM0 LE 

+compiling arm_abs_f32 c 

+compiling arm_abs_q7 c 

+compiling arm_abs_q15 c 

+compiling arm_abs_q31 c 

+compiling arm_add_f32 c 

+compiling arm_add_q7 c 

+compiling arm_add_q15 c 

+compiling arm_add_q31 c 

+compiling arm_dot_prod_f32 c 

+compiling arm_dot_prod_q7 c 

+compiling arm_dot_prod_q15 c 

+compiling arm_dot_prod_q31 c 

+compiling arm_mult_f32 c 

+compiling arm_mult_q7 c 

+compiling arm_mult_q15 c 

+compiling arm_mult_q31 c 

+compiling arm_negate_f32 c 

+compiling arm_negate_q7 c 

+compiling arm_negate_q15 c 

+compiling arm_negate_q31 c 

+compiling arm_offset_f32 c 

+compiling arm_offset_q7 c 

+compiling arm_offset_q15 c 

+compiling arm_offset_q31 c 

+compiling arm_scale_f32 c 

+compiling arm_scale_q7 c 

+compiling arm_scale_q15 c 

+compiling arm_scale_q31 c 

+compiling arm_shift_q7 c 

+compiling arm_shift_q15 c 

+compiling arm_shift_q31 c 

+compiling arm_sub_f32 c 

+compiling arm_sub_q7 c 

+compiling arm_sub_q15 c 

+compiling arm_sub_q31 c 

+compiling arm_cos_f32 c 

+compiling arm_cos_q15 c 

+compiling arm_cos_q31 c 

+compiling arm_sin_f32 c 

+compiling arm_sin_q15 c 

+compiling arm_sin_q31 c 

+compiling arm_sqrt_q15 c 

+compiling arm_sqrt_q31 c 

+compiling arm_cmplx_conj_f32 c 

+compiling arm_cmplx_conj_q15 c 

+compiling arm_cmplx_conj_q31 c 

+compiling 

+arm_cmplx_dot_prod_f32 c 

+compiling 

+arm_cmplx_dot_prod_q15 c 

+compiling 

+arm_cmplx_dot_prod_q31 c 

+compiling arm_cmplx_mag_f32 c 

+compiling arm_cmplx_mag_q15 c 

+compiling arm_cmplx_mag_q31 c 

+compiling 

+arm_cmplx_mag_squared_f32 c 

+compiling 

+arm_cmplx_mag_squared_q15 c 

+compiling 

+arm_cmplx_mag_squared_q31 c 

+compiling 

+arm_cmplx_mult_cmplx_f32 c 

+compiling 

+arm_cmplx_mult_cmplx_q15 c 

+compiling 

+arm_cmplx_mult_cmplx_q31 c 

+compiling 

+arm_cmplx_mult_real_f32 c 

+compiling 

+arm_cmplx_mult_real_q15 c 

+compiling 

+arm_cmplx_mult_real_q31 c 

+compiling 

+arm_biquad_cascade_df1_32x64_init_q31 

+c compiling 

+arm_biquad_cascade_df1_32x64_q31 

+c compiling 

+arm_biquad_cascade_df1_f32 c 

+compiling 

+arm_biquad_cascade_df1_fast_q15 

+c compiling 

+arm_biquad_cascade_df1_fast_q31 

+c compiling 

+arm_biquad_cascade_df1_init_f32 

+c compiling 

+arm_biquad_cascade_df1_init_q15 

+c compiling 

+arm_biquad_cascade_df1_init_q31 

+c compiling 

+arm_biquad_cascade_df1_q15 c 

+compiling 

+arm_biquad_cascade_df1_q31 c 

+compiling 

+arm_biquad_cascade_df2T_f32 c 

+compiling 

+arm_biquad_cascade_df2T_init_f32 

+c compiling arm_conv_f32 c 

+compiling arm_conv_fast_q15 c 

+compiling 

+arm_conv_fast_opt_q15 c 

+compiling arm_conv_fast_q31 c 

+compiling arm_conv_partial_f32 

+c compiling 

+arm_conv_partial_fast_q15 c 

+compiling 

+arm_conv_partial_fast_opt_q15 

+c compiling 

+arm_conv_partial_fast_q31 c 

+compiling arm_conv_partial_q7 

+c compiling 

+arm_conv_partial_opt_q7 c 

+compiling arm_conv_partial_q15 

+c compiling 

+arm_conv_partial_opt_q15 c 

+compiling arm_conv_partial_q31 

+c compiling arm_conv_q7 c 

+compiling arm_conv_opt_q7 c 

+compiling arm_conv_q15 c 

+compiling arm_conv_opt_q15 c 

+compiling arm_conv_q31 c 

+compiling arm_correlate_f32 c 

+compiling 

+arm_correlate_fast_q15 c 

+compiling 

+arm_correlate_fast_opt_q15 c 

+compiling 

+arm_correlate_fast_q31 c 

+compiling arm_correlate_q7 c 

+compiling arm_correlate_opt_q7 

+c compiling arm_correlate_q15 

+c compiling 

+arm_correlate_opt_q15 c 

+compiling arm_correlate_q31 c 

+compiling arm_fir_decimate_f32 

+c compiling 

+arm_fir_decimate_fast_q15 c 

+compiling 

+arm_fir_decimate_fast_q31 c 

+compiling 

+arm_fir_decimate_init_f32 c 

+compiling 

+arm_fir_decimate_init_q15 c 

+compiling 

+arm_fir_decimate_init_q31 c 

+compiling arm_fir_decimate_q15 

+c compiling 

+arm_fir_decimate_q31 c 

+compiling arm_fir_f32 c 

+compiling arm_fir_fast_q15 c 

+compiling arm_fir_fast_q31 c 

+compiling arm_fir_init_f32 c 

+compiling arm_fir_init_q7 c 

+compiling arm_fir_init_q15 c 

+compiling arm_fir_init_q31 c 

+compiling 

+arm_fir_interpolate_f32 c 

+compiling 

+arm_fir_interpolate_init_f32 c 

+compiling 

+arm_fir_interpolate_init_q15 c 

+compiling 

+arm_fir_interpolate_init_q31 c 

+compiling 

+arm_fir_interpolate_q15 c 

+compiling 

+arm_fir_interpolate_q31 c 

+compiling arm_fir_lattice_f32 

+c compiling 

+arm_fir_lattice_init_f32 c 

+compiling 

+arm_fir_lattice_init_q15 c 

+compiling 

+arm_fir_lattice_init_q31 c 

+compiling arm_fir_lattice_q15 

+c compiling 

+arm_fir_lattice_q31 c 

+compiling arm_fir_q7 c 

+compiling arm_fir_q15 c 

+compiling arm_fir_q31 c 

+compiling arm_fir_sparse_f32 c 

+compiling 

+arm_fir_sparse_init_f32 c 

+compiling 

+arm_fir_sparse_init_q7 c 

+compiling 

+arm_fir_sparse_init_q15 c 

+compiling 

+arm_fir_sparse_init_q31 c 

+compiling arm_fir_sparse_q7 c 

+compiling arm_fir_sparse_q15 c 

+compiling arm_fir_sparse_q31 c 

+compiling arm_iir_lattice_f32 

+c compiling 

+arm_iir_lattice_init_f32 c 

+compiling 

+arm_iir_lattice_init_q15 c 

+compiling 

+arm_iir_lattice_init_q31 c 

+compiling arm_iir_lattice_q15 

+c compiling 

+arm_iir_lattice_q31 c 

+compiling arm_lms_f32 c 

+compiling arm_lms_init_f32 c 

+compiling arm_lms_init_q15 c 

+compiling arm_lms_init_q31 c 

+compiling arm_lms_norm_f32 c 

+compiling 

+arm_lms_norm_init_f32 c 

+compiling 

+arm_lms_norm_init_q15 c 

+compiling 

+arm_lms_norm_init_q31 c 

+compiling arm_lms_norm_q15 c 

+compiling arm_lms_norm_q31 c 

+compiling arm_lms_q15 c 

+compiling arm_lms_q31 c 

+compiling arm_mat_add_f32 c 

+compiling arm_mat_add_q15 c 

+compiling arm_mat_add_q31 c 

+compiling arm_mat_init_f32 c 

+compiling arm_mat_init_q15 c 

+compiling arm_mat_init_q31 c 

+compiling arm_mat_inverse_f32 

+c compiling arm_mat_mult_f32 c 

+compiling 

+arm_mat_mult_fast_q15 c 

+compiling 

+arm_mat_mult_fast_q31 c 

+compiling arm_mat_mult_q15 c 

+compiling arm_mat_mult_q31 c 

+compiling arm_mat_scale_f32 c 

+compiling arm_mat_scale_q15 c 

+compiling arm_mat_scale_q31 c 

+compiling arm_mat_sub_f32 c 

+compiling arm_mat_sub_q15 c 

+compiling arm_mat_sub_q31 c 

+compiling arm_mat_trans_f32 c 

+compiling arm_mat_trans_q15 c 

+compiling arm_mat_trans_q31 c 

+compiling arm_bitreversal c 

+compiling arm_cfft_radix2_f32 

+c compiling 

+arm_cfft_radix2_init_f32 c 

+compiling 

+arm_cfft_radix2_init_q15 c 

+compiling 

+arm_cfft_radix2_init_q31 c 

+compiling arm_cfft_radix2_q15 

+c compiling 

+arm_cfft_radix2_q31 c 

+compiling arm_cfft_radix4_f32 

+c compiling 

+arm_cfft_radix4_init_f32 c 

+compiling 

+arm_cfft_radix4_init_q15 c 

+compiling 

+arm_cfft_radix4_init_q31 c 

+compiling arm_cfft_radix4_q15 

+c compiling 

+arm_cfft_radix4_q31 c 

+compiling arm_dct4_f32 c 

+compiling arm_dct4_init_f32 c 

+compiling arm_dct4_init_q15 c 

+compiling arm_dct4_init_q31 c 

+compiling arm_dct4_q15 c 

+compiling arm_dct4_q31 c 

+compiling arm_rfft_f32 c 

+compiling arm_rfft_init_f32 c 

+compiling arm_rfft_init_q15 c 

+compiling arm_rfft_init_q31 c 

+compiling arm_rfft_q15 c 

+compiling arm_rfft_q31 c 

+compiling arm_pid_init_f32 c 

+compiling arm_pid_init_q15 c 

+compiling arm_pid_init_q31 c 

+compiling arm_pid_reset_f32 c 

+compiling arm_pid_reset_q15 c 

+compiling arm_pid_reset_q31 c 

+compiling arm_sin_cos_f32 c 

+compiling arm_sin_cos_q31 c 

+compiling arm_max_f32 c 

+compiling arm_max_q7 c 

+compiling arm_max_q15 c 

+compiling arm_max_q31 c 

+compiling arm_mean_f32 c 

+compiling arm_mean_q7 c 

+compiling arm_mean_q15 c 

+compiling arm_mean_q31 c 

+compiling arm_min_f32 c 

+compiling arm_min_q7 c 

+compiling arm_min_q15 c 

+compiling arm_min_q31 c 

+compiling arm_power_f32 c 

+compiling arm_power_q7 c 

+compiling arm_power_q15 c 

+compiling arm_power_q31 c 

+compiling arm_rms_f32 c 

+compiling arm_rms_q15 c 

+compiling arm_rms_q31 c 

+compiling arm_std_f32 c 

+compiling arm_std_q15 c 

+compiling arm_std_q31 c 

+compiling arm_var_f32 c 

+compiling arm_var_q15 c 

+compiling arm_var_q31 c 

+compiling arm_copy_f32 c 

+compiling arm_copy_q7 c 

+compiling arm_copy_q15 c 

+compiling arm_copy_q31 c 

+compiling arm_fill_f32 c 

+compiling arm_fill_q7 c 

+compiling arm_fill_q15 c 

+compiling arm_fill_q31 c 

+compiling arm_float_to_q7 c 

+compiling arm_float_to_q15 c 

+compiling arm_float_to_q31 c 

+compiling arm_q7_to_float c 

+compiling arm_q7_to_q15 c 

+compiling arm_q7_to_q31 c 

+compiling arm_q15_to_float c 

+compiling arm_q15_to_q7 c 

+compiling arm_q15_to_q31 c 

+compiling arm_q31_to_float c 

+compiling arm_q31_to_q7 c 

+compiling arm_q31_to_q15 c 

+compiling arm_common_tables c 

+creating Library User command 		file (s) copied.".\intermediateFiles\arm_cortexM0l_math.lib"-0 Error(s)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
Rebuild target DSP_Lib CM0 LE compiling arm_abs_f32 c compiling arm_abs_q7 c compiling arm_abs_q15 c compiling arm_abs_q31 c compiling arm_add_f32 c compiling arm_add_q7 c compiling arm_add_q15 c compiling arm_add_q31 c compiling arm_dot_prod_f32 c compiling arm_dot_prod_q7 c compiling arm_dot_prod_q15 c compiling arm_dot_prod_q31 c compiling arm_mult_f32 c compiling arm_mult_q7 c compiling arm_mult_q15 c compiling arm_mult_q31 c compiling arm_negate_f32 c compiling arm_negate_q7 c compiling arm_negate_q15 c compiling arm_negate_q31 c compiling arm_offset_f32 c compiling arm_offset_q7 c compiling arm_offset_q15 c compiling arm_offset_q31 c compiling arm_scale_f32 c compiling arm_scale_q7 c compiling arm_scale_q15 c compiling arm_scale_q31 c compiling arm_shift_q7 c compiling arm_shift_q15 c compiling arm_shift_q31 c compiling arm_sub_f32 c compiling arm_sub_q7 c compiling arm_sub_q15 c compiling arm_sub_q31 c compiling arm_cos_f32 c compiling arm_cos_q15 c compiling arm_cos_q31 c compiling arm_sin_f32 c compiling arm_sin_q15 c compiling arm_sin_q31 c compiling arm_sqrt_q15 c compiling arm_sqrt_q31 c compiling arm_cmplx_conj_f32 c compiling arm_cmplx_conj_q15 c compiling arm_cmplx_conj_q31 c compiling arm_cmplx_dot_prod_f32 c compiling arm_cmplx_dot_prod_q15 c compiling arm_cmplx_dot_prod_q31 c compiling arm_cmplx_mag_f32 c compiling arm_cmplx_mag_q15 c compiling arm_cmplx_mag_q31 c compiling arm_cmplx_mag_squared_f32 c compiling arm_cmplx_mag_squared_q15 c compiling arm_cmplx_mag_squared_q31 c compiling arm_cmplx_mult_cmplx_f32 c compiling arm_cmplx_mult_cmplx_q15 c compiling arm_cmplx_mult_cmplx_q31 c compiling arm_cmplx_mult_real_f32 c compiling arm_cmplx_mult_real_q15 c compiling arm_cmplx_mult_real_q31 c compiling arm_biquad_cascade_df1_32x64_init_q31 c compiling arm_biquad_cascade_df1_32x64_q31 c compiling arm_biquad_cascade_df1_f32 c compiling arm_biquad_cascade_df1_fast_q15 c compiling arm_biquad_cascade_df1_fast_q31 c compiling arm_biquad_cascade_df1_init_f32 c compiling arm_biquad_cascade_df1_init_q15 c compiling arm_biquad_cascade_df1_init_q31 c compiling arm_biquad_cascade_df1_q15 c compiling arm_biquad_cascade_df1_q31 c compiling arm_biquad_cascade_df2T_f32 c compiling arm_biquad_cascade_df2T_init_f32 c compiling arm_conv_f32 c compiling arm_conv_fast_q15 c compiling arm_conv_fast_opt_q15 c compiling arm_conv_fast_q31 c compiling arm_conv_partial_f32 c compiling arm_conv_partial_fast_q15 c compiling arm_conv_partial_fast_opt_q15 c compiling arm_conv_partial_fast_q31 c compiling arm_conv_partial_q7 c compiling arm_conv_partial_opt_q7 c compiling arm_conv_partial_q15 c compiling arm_conv_partial_opt_q15 c compiling arm_conv_partial_q31 c compiling arm_conv_q7 c compiling arm_conv_opt_q7 c compiling arm_conv_q15 c compiling arm_conv_opt_q15 c compiling arm_conv_q31 c compiling arm_correlate_f32 c compiling arm_correlate_fast_q15 c compiling arm_correlate_fast_opt_q15 c compiling arm_correlate_fast_q31 c compiling arm_correlate_q7 c compiling arm_correlate_opt_q7 c compiling arm_correlate_q15 c compiling arm_correlate_opt_q15 c compiling arm_correlate_q31 c compiling arm_fir_decimate_f32 c compiling arm_fir_decimate_fast_q15 c compiling arm_fir_decimate_fast_q31 c compiling arm_fir_decimate_init_f32 c compiling arm_fir_decimate_init_q15 c compiling arm_fir_decimate_init_q31 c compiling arm_fir_decimate_q15 c compiling arm_fir_decimate_q31 c compiling arm_fir_f32 c compiling arm_fir_fast_q15 c compiling arm_fir_fast_q31 c compiling arm_fir_init_f32 c compiling arm_fir_init_q7 c compiling arm_fir_init_q15 c compiling arm_fir_init_q31 c compiling arm_fir_interpolate_f32 c compiling arm_fir_interpolate_init_f32 c compiling arm_fir_interpolate_init_q15 c compiling arm_fir_interpolate_init_q31 c compiling arm_fir_interpolate_q15 c compiling arm_fir_interpolate_q31 c compiling arm_fir_lattice_f32 c compiling arm_fir_lattice_init_f32 c compiling arm_fir_lattice_init_q15 c compiling arm_fir_lattice_init_q31 c compiling arm_fir_lattice_q15 c compiling arm_fir_lattice_q31 c compiling arm_fir_q7 c compiling arm_fir_q15 c compiling arm_fir_q31 c compiling arm_fir_sparse_f32 c compiling arm_fir_sparse_init_f32 c compiling arm_fir_sparse_init_q7 c compiling arm_fir_sparse_init_q15 c compiling arm_fir_sparse_init_q31 c compiling arm_fir_sparse_q7 c compiling arm_fir_sparse_q15 c compiling arm_fir_sparse_q31 c compiling arm_iir_lattice_f32 c compiling arm_iir_lattice_init_f32 c compiling arm_iir_lattice_init_q15 c compiling arm_iir_lattice_init_q31 c compiling arm_iir_lattice_q15 c compiling arm_iir_lattice_q31 c compiling arm_lms_f32 c compiling arm_lms_init_f32 c compiling arm_lms_init_q15 c compiling arm_lms_init_q31 c compiling arm_lms_norm_f32 c compiling arm_lms_norm_init_f32 c compiling arm_lms_norm_init_q15 c compiling arm_lms_norm_init_q31 c compiling arm_lms_norm_q15 c compiling arm_lms_norm_q31 c compiling arm_lms_q15 c compiling arm_lms_q31 c compiling arm_mat_add_f32 c compiling arm_mat_add_q15 c compiling arm_mat_add_q31 c compiling arm_mat_init_f32 c compiling arm_mat_init_q15 c compiling arm_mat_init_q31 c compiling arm_mat_inverse_f32 c compiling arm_mat_mult_f32 c compiling arm_mat_mult_fast_q15 c compiling arm_mat_mult_fast_q31 c compiling arm_mat_mult_q15 c compiling arm_mat_mult_q31 c compiling arm_mat_scale_f32 c compiling arm_mat_scale_q15 c compiling arm_mat_scale_q31 c compiling arm_mat_sub_f32 c compiling arm_mat_sub_q15 c compiling arm_mat_sub_q31 c compiling arm_mat_trans_f32 c compiling arm_mat_trans_q15 c compiling arm_mat_trans_q31 c compiling arm_bitreversal c compiling arm_cfft_radix2_f32 c compiling arm_cfft_radix2_init_f32 c compiling arm_cfft_radix2_init_q15 c compiling arm_cfft_radix2_init_q31 c compiling arm_cfft_radix2_q15 c compiling arm_cfft_radix2_q31 c compiling arm_cfft_radix4_f32 c compiling arm_cfft_radix4_init_f32 c compiling arm_cfft_radix4_init_q15 c compiling arm_cfft_radix4_init_q31 c compiling arm_cfft_radix4_q15 c compiling arm_cfft_radix4_q31 c compiling arm_dct4_f32 c compiling arm_dct4_init_f32 c compiling arm_dct4_init_q15 c compiling arm_dct4_init_q31 c compiling arm_dct4_q15 c compiling arm_dct4_q31 c compiling arm_rfft_f32 c compiling arm_rfft_init_f32 c compiling arm_rfft_init_q15 c compiling arm_rfft_init_q31 c compiling arm_rfft_q15 c compiling arm_rfft_q31 c compiling arm_pid_init_f32 c compiling arm_pid_init_q15 c compiling arm_pid_init_q31 c compiling arm_pid_reset_f32 c compiling arm_pid_reset_q15 c compiling arm_pid_reset_q31 c compiling arm_sin_cos_f32 c compiling arm_sin_cos_q31 c compiling arm_max_f32 c compiling arm_max_q7 c compiling arm_max_q15 c compiling arm_max_q31 c compiling arm_mean_f32 c compiling arm_mean_q7 c compiling arm_mean_q15 c compiling arm_mean_q31 c compiling arm_min_f32 c compiling arm_min_q7 c compiling arm_min_q15 c compiling arm_min_q31 c compiling arm_power_f32 c compiling arm_power_q7 c compiling arm_power_q15 c compiling arm_power_q31 c compiling arm_rms_f32 c compiling arm_rms_q15 c compiling arm_rms_q31 c compiling arm_std_f32 c compiling arm_std_q15 c compiling arm_std_q31 c compiling arm_var_f32 c compiling arm_var_q15 c compiling arm_var_q31 c compiling arm_copy_f32 c compiling arm_copy_q7 c compiling arm_copy_q15 c compiling arm_copy_q31 c compiling arm_fill_f32 c compiling arm_fill_q7 c compiling arm_fill_q15 c compiling arm_fill_q31 c compiling arm_float_to_q7 c compiling arm_float_to_q15 c compiling arm_float_to_q31 c compiling arm_q7_to_float c compiling arm_q7_to_q15 c compiling arm_q7_to_q31 c compiling arm_q15_to_float c compiling arm_q15_to_q7 c compiling arm_q15_to_q31 c compiling arm_q31_to_float c compiling arm_q31_to_q7 c compiling arm_q31_to_q15 c compiling arm_common_tables c creating Library User command file (s )

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diff --git a/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m3_01_l_e_8txt.html b/CMSIS/Documentation/DSP/html/_d_s_p___lib_01_c_m3_01_l_e_8txt.html
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+DSP_Lib CM3 LE.txt File Reference
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CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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DSP_Lib CM3 LE.txt File Reference
  

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diff --git a/CMSIS/Documentation/DSP/html/annotated.html b/CMSIS/Documentation/DSP/html/annotated.html
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+Data Structures
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+  
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

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+

+    
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Data Structures
  

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+
Here are the data structures with brief descriptions:

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arm_bilinear_interp_instance_f32Instance structure for the floating-point bilinear interpolation function 
arm_bilinear_interp_instance_q15Instance structure for the Q15 bilinear interpolation function 
arm_bilinear_interp_instance_q31Instance structure for the Q31 bilinear interpolation function 
arm_bilinear_interp_instance_q7Instance structure for the Q15 bilinear interpolation function 
arm_biquad_cas_df1_32x64_ins_q31Instance structure for the high precision Q31 Biquad cascade filter 
arm_biquad_cascade_df2T_instance_f32Instance structure for the floating-point transposed direct form II Biquad cascade filter 
arm_biquad_casd_df1_inst_f32Instance structure for the floating-point Biquad cascade filter 
arm_biquad_casd_df1_inst_q15Instance structure for the Q15 Biquad cascade filter 
arm_biquad_casd_df1_inst_q31Instance structure for the Q31 Biquad cascade filter 
arm_cfft_radix2_instance_f32Instance structure for the floating-point CFFT/CIFFT function 
arm_cfft_radix2_instance_q15Instance structure for the Q15 CFFT/CIFFT function 
arm_cfft_radix2_instance_q31Instance structure for the Radix-2 Q31 CFFT/CIFFT function 
arm_cfft_radix4_instance_f32Instance structure for the floating-point CFFT/CIFFT function 
arm_cfft_radix4_instance_q15Instance structure for the Q15 CFFT/CIFFT function 
arm_cfft_radix4_instance_q31Instance structure for the Q31 CFFT/CIFFT function 
arm_dct4_instance_f32Instance structure for the floating-point DCT4/IDCT4 function 
arm_dct4_instance_q15Instance structure for the Q15 DCT4/IDCT4 function 
arm_dct4_instance_q31Instance structure for the Q31 DCT4/IDCT4 function 
arm_fir_decimate_instance_f32Instance structure for the floating-point FIR decimator 
arm_fir_decimate_instance_q15Instance structure for the Q15 FIR decimator 
arm_fir_decimate_instance_q31Instance structure for the Q31 FIR decimator 
arm_fir_instance_f32Instance structure for the floating-point FIR filter 
arm_fir_instance_q15Instance structure for the Q15 FIR filter 
arm_fir_instance_q31Instance structure for the Q31 FIR filter 
arm_fir_instance_q7Instance structure for the Q7 FIR filter 
arm_fir_interpolate_instance_f32Instance structure for the floating-point FIR interpolator 
arm_fir_interpolate_instance_q15Instance structure for the Q15 FIR interpolator 
arm_fir_interpolate_instance_q31Instance structure for the Q31 FIR interpolator 
arm_fir_lattice_instance_f32Instance structure for the floating-point FIR lattice filter 
arm_fir_lattice_instance_q15Instance structure for the Q15 FIR lattice filter 
arm_fir_lattice_instance_q31Instance structure for the Q31 FIR lattice filter 
arm_fir_sparse_instance_f32Instance structure for the floating-point sparse FIR filter 
arm_fir_sparse_instance_q15Instance structure for the Q15 sparse FIR filter 
arm_fir_sparse_instance_q31Instance structure for the Q31 sparse FIR filter 
arm_fir_sparse_instance_q7Instance structure for the Q7 sparse FIR filter 
arm_iir_lattice_instance_f32Instance structure for the floating-point IIR lattice filter 
arm_iir_lattice_instance_q15Instance structure for the Q15 IIR lattice filter 
arm_iir_lattice_instance_q31Instance structure for the Q31 IIR lattice filter 
arm_linear_interp_instance_f32Instance structure for the floating-point Linear Interpolate function 
arm_lms_instance_f32Instance structure for the floating-point LMS filter 
arm_lms_instance_q15Instance structure for the Q15 LMS filter 
arm_lms_instance_q31Instance structure for the Q31 LMS filter 
arm_lms_norm_instance_f32Instance structure for the floating-point normalized LMS filter 
arm_lms_norm_instance_q15Instance structure for the Q15 normalized LMS filter 
arm_lms_norm_instance_q31Instance structure for the Q31 normalized LMS filter 
arm_matrix_instance_f32Instance structure for the floating-point matrix structure 
arm_matrix_instance_q15Instance structure for the Q15 matrix structure 
arm_matrix_instance_q31Instance structure for the Q31 matrix structure 
arm_pid_instance_f32Instance structure for the floating-point PID Control 
arm_pid_instance_q15Instance structure for the Q15 PID Control 
arm_pid_instance_q31Instance structure for the Q31 PID Control 
arm_rfft_instance_f32Instance structure for the floating-point RFFT/RIFFT function 
arm_rfft_instance_q15Instance structure for the Q15 RFFT/RIFFT function 
arm_rfft_instance_q31Instance structure for the Q31 RFFT/RIFFT function 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__abs__f32_8c.html
new file mode 100644
index 0000000000..88ba4d22d2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_abs_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_abs_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__abs__f32_8d.html
new file mode 100644
index 0000000000..2ba92a2c13
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_abs_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_abs_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__abs__q15_8c.html
new file mode 100644
index 0000000000..9000b7f487
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_abs_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_abs_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__abs__q15_8d.html
new file mode 100644
index 0000000000..7fbd576cac
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_abs_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_abs_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__abs__q31_8c.html
new file mode 100644
index 0000000000..4ba471afe6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_abs_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_abs_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__abs__q31_8d.html
new file mode 100644
index 0000000000..1abde3f05a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_abs_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_abs_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__abs__q7_8c.html
new file mode 100644
index 0000000000..43285f1ce6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_abs_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_abs_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__abs__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__abs__q7_8d.html
new file mode 100644
index 0000000000..31a12560ac
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__abs__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_abs_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_abs_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__add__f32_8c.html
new file mode 100644
index 0000000000..f54c8de6d0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_add_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_add_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__add__f32_8d.html
new file mode 100644
index 0000000000..b4fbfebf75
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_add_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_add_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__add__q15_8c.html
new file mode 100644
index 0000000000..83c5614f04
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_add_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__add__q15_8d.html
new file mode 100644
index 0000000000..c26b174bac
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_add_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_add_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__add__q31_8c.html
new file mode 100644
index 0000000000..5c7cd891c5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_add_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__add__q31_8d.html
new file mode 100644
index 0000000000..2327a7b4e5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_add_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_add_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__add__q7_8c.html
new file mode 100644
index 0000000000..151754dc4a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_add_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_add_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__add__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__add__q7_8d.html
new file mode 100644
index 0000000000..224e6e24fa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__add__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_add_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_add_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
new file mode 100644
index 0000000000..6615914b1b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
@@ -0,0 +1,138 @@
+
+
+
+
+arm_biquad_cascade_df1_32x64_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_init_q31.c File Reference
  

+

+

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8d.html
new file mode 100644
index 0000000000..3d0958f8e5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_32x64_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_32x64_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8c.html
new file mode 100644
index 0000000000..4e2420adba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8c.html
@@ -0,0 +1,138 @@
+
+
+
+
+arm_biquad_cascade_df1_32x64_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_q31.c File Reference
  

+

+

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8d.html
new file mode 100644
index 0000000000..af6b80e694
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__32x64__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_32x64_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_32x64_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8c.html
new file mode 100644
index 0000000000..7ebf22ae2c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8d.html
new file mode 100644
index 0000000000..fd166ec286
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8c.html
new file mode 100644
index 0000000000..6de8035f20
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8d.html
new file mode 100644
index 0000000000..99c8c29780
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8c.html
new file mode 100644
index 0000000000..658c5eaea4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8d.html
new file mode 100644
index 0000000000..562fbcbd22
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8c.html
new file mode 100644
index 0000000000..b566369bd4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8d.html
new file mode 100644
index 0000000000..f79128a749
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8c.html
new file mode 100644
index 0000000000..d2a15ff5c8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8d.html
new file mode 100644
index 0000000000..a610e8a942
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8c.html
new file mode 100644
index 0000000000..63fcf99525
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8d.html
new file mode 100644
index 0000000000..b90ce95370
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8c.html
new file mode 100644
index 0000000000..cad6556485
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8d.html
new file mode 100644
index 0000000000..bb23e6b8da
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8c.html
new file mode 100644
index 0000000000..f96fd04eb7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df1_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8d.html
new file mode 100644
index 0000000000..534f50dcb5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df1__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df1_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df1_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__f32_8c.html
new file mode 100644
index 0000000000..c8e57c7286
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df2T_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__init__f32_8c.html
new file mode 100644
index 0000000000..10b9320619
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2_t__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_biquad_cascade_df2T_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__f32_8d.html
new file mode 100644
index 0000000000..d5128c457a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df2t_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df2t_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__init__f32_8d.html
new file mode 100644
index 0000000000..b52640c6c3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__biquad__cascade__df2t__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_biquad_cascade_df2t_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_biquad_cascade_df2t_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__bitreversal_8c.html b/CMSIS/Documentation/DSP/html/arm__bitreversal_8c.html
new file mode 100644
index 0000000000..47c7d28ce9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__bitreversal_8c.html
@@ -0,0 +1,297 @@
+
+
+
+
+arm_bitreversal.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_bitreversal.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 In-place bit reversal function.  
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTable)
 In-place bit reversal function.  
void arm_bitreversal_q15 (q15_t *pSrc16, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 In-place bit reversal function.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
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+          
+          
+          
+        
+      
void arm_bitreversal_f32 (float32_t * pSrc, 
uint16_t fftSize, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_f32(), arm_cfft_radix4_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+          
+        
+      
void arm_bitreversal_q15 (q15_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
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+        
+      
void arm_bitreversal_q31 (q31_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__bitreversal_8d.html b/CMSIS/Documentation/DSP/html/arm__bitreversal_8d.html
new file mode 100644
index 0000000000..cb1ecbc0ef
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__bitreversal_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_bitreversal.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_bitreversal.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8c.html
new file mode 100644
index 0000000000..120a7a7fb6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8c.html
@@ -0,0 +1,244 @@
+
+
+
+
+arm_cfft_radix2_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-2 CFFT/CIFFT.  
void arm_radix2_butterfly_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 Core function for the f32 FFT butterfly process.  
void arm_radix2_butterfly_inverse_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 Core function for the f32 IFFT butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
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+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
end of Radix2_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix2_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+        
+        
+          
+          
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+          
+        
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+          
+          
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+        
+      
void arm_radix2_butterfly_inverse_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of f32 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLen1/fftLenfth 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8d.html
new file mode 100644
index 0000000000..99fc8f56dc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8c.html
new file mode 100644
index 0000000000..854382cdfd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix2_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8d.html
new file mode 100644
index 0000000000..75f8944088
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8c.html
new file mode 100644
index 0000000000..55215ec305
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix2_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8d.html
new file mode 100644
index 0000000000..61a14d3b0d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_init_q15.d File Reference
+
+
+
+
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+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8c.html
new file mode 100644
index 0000000000..9f048826c2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix2_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8d.html
new file mode 100644
index 0000000000..850a327221
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8c.html
new file mode 100644
index 0000000000..4cdc50ab43
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8c.html
@@ -0,0 +1,241 @@
+
+
+
+
+arm_cfft_radix2_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_q15.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  
void arm_radix2_butterfly_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q15 CFFT butterfly process.  
void arm_radix2_butterfly_inverse_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q15 CFFT Inverse butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_inverse_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
end of Radix2_CFFT_CIFFT group 

+
+
References _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix2_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8d.html
new file mode 100644
index 0000000000..fb1899fd5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8c.html
new file mode 100644
index 0000000000..632fbaab6e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8c.html
@@ -0,0 +1,237 @@
+
+
+
+
+arm_cfft_radix2_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix2_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  
void arm_radix2_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q31 CFFT butterfly process.  
void arm_radix2_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q31 CFFT Inverse butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
end of Radix2_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix2_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8d.html
new file mode 100644
index 0000000000..9f3ac05d43
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix2__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix2_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix2_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8c.html
new file mode 100644
index 0000000000..3b8574e6fe
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8c.html
@@ -0,0 +1,244 @@
+
+
+
+
+arm_cfft_radix4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-4 CFFT/CIFFT.  
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 Core function for the floating-point CFFT butterfly process.  
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 Core function for the floating-point CIFFT butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
end of Radix4_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8d.html
new file mode 100644
index 0000000000..6f15908f8f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8c.html
new file mode 100644
index 0000000000..f4570669f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8d.html
new file mode 100644
index 0000000000..c1a291a3a8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8c.html
new file mode 100644
index 0000000000..bcc7f4e863
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8d.html
new file mode 100644
index 0000000000..95d0c6aaca
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cfft_radix4_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8d.html
new file mode 100644
index 0000000000..9acc9c9c68
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8c.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8c.html
@@ -0,0 +1,251 @@
+
+
+
+
+arm_cfft_radix4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_q15.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CFFT butterfly process.  
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CIFFT butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)

+

+

+
end of Radix4_CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8d.html
new file mode 100644
index 0000000000..efc1d3dc14
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8c.html
new file mode 100644
index 0000000000..d1a8442ee1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8c.html
@@ -0,0 +1,251 @@
+
+
+
+
+arm_cfft_radix4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cfft_radix4_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CFFT butterfly process.  
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CIFFT butterfly process.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD64.

+
+
Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)

+

+

+
end of Radix4_CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD64.

+
+
Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8d.html
new file mode 100644
index 0000000000..637ed03d9d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cfft_radix4_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cfft_radix4_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__class__marks__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__class__marks__example__f32_8c.html
new file mode 100644
index 0000000000..cdfcf4ca37
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__class__marks__example__f32_8c.html
@@ -0,0 +1,417 @@
+
+
+
+
+arm_class_marks_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_class_marks_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define USE_STATIC_INIT
#define TEST_LENGTH_SAMPLES
#define NUMSTUDENTS
#define NUMSUBJECTS

+Variables
const float32_t testMarks_f32 [TEST_LENGTH_SAMPLES]
const float32_t testUnity_f32 [4]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
uint32_t numStudents
uint32_t numSubjects
float32_t max_marks
float32_t min_marks
float32_t mean
float32_t std
float32_t var
uint32_t student_num

+Functions
int32_t main ()

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define NUMSTUDENTS

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSUBJECTS

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_linear_interp_example_f32.c, and arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
#define USE_STATIC_INIT

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t max_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t mean

+

+

+
Examples: 
arm_class_marks_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by arm_std_f32(), arm_std_q15(), arm_std_q31(), arm_var_f32(), arm_var_q15(), arm_var_q31(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t min_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numStudents

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numSubjects

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t std

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t student_num

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testUnity_f32[4]

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t var

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Referenced by arm_std_f32(), and main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
References arm_mat_init_f32(), arm_mat_mult_f32(), arm_max_f32(), arm_mean_f32(), arm_min_f32(), arm_std_f32(), arm_var_f32(), max_marks, mean, min_marks, NUMSTUDENTS, numStudents, NUMSUBJECTS, numSubjects, std, student_num, testMarks_f32, testOutput, testUnity_f32, and var.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8c.html
new file mode 100644
index 0000000000..c37644f284
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_conj_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_conj_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8d.html
new file mode 100644
index 0000000000..b02b5c0aae
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_conj_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_conj_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8c.html
new file mode 100644
index 0000000000..136fe8b88f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_conj_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_conj_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8d.html
new file mode 100644
index 0000000000..9fc9f3a196
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_conj_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_conj_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8c.html
new file mode 100644
index 0000000000..6710e6180f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_conj_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_conj_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8d.html
new file mode 100644
index 0000000000..0141a6fa33
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__conj__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_conj_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_conj_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8c.html
new file mode 100644
index 0000000000..f1ad9cffed
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8d.html
new file mode 100644
index 0000000000..89550a18c5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_dot_prod_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_dot_prod_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8c.html
new file mode 100644
index 0000000000..2c6b8a3b75
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8d.html
new file mode 100644
index 0000000000..533129680b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_dot_prod_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_dot_prod_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8c.html
new file mode 100644
index 0000000000..78a13bd6df
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8d.html
new file mode 100644
index 0000000000..795c6df7e4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_dot_prod_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_dot_prod_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8c.html
new file mode 100644
index 0000000000..55ca2732f8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8d.html
new file mode 100644
index 0000000000..9373df13ef
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8c.html
new file mode 100644
index 0000000000..e67aa684ef
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8d.html
new file mode 100644
index 0000000000..89091e4d09
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8c.html
new file mode 100644
index 0000000000..946a34139e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8d.html
new file mode 100644
index 0000000000..ffd0c8ed40
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8c.html
new file mode 100644
index 0000000000..ec728d8bed
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_squared_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8d.html
new file mode 100644
index 0000000000..d62543dd90
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_squared_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_squared_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8c.html
new file mode 100644
index 0000000000..058fccf1ff
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_squared_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8d.html
new file mode 100644
index 0000000000..1b7dcb2c49
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_squared_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_squared_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8c.html
new file mode 100644
index 0000000000..2b8e0c7247
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mag_squared_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8d.html
new file mode 100644
index 0000000000..8f9c0c00ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mag__squared__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mag_squared_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mag_squared_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8c.html
new file mode 100644
index 0000000000..4e02029441
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_cmplx_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8d.html
new file mode 100644
index 0000000000..2e99c2ff4d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_cmplx_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_cmplx_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8c.html
new file mode 100644
index 0000000000..e834c9c8b9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_cmplx_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8d.html
new file mode 100644
index 0000000000..b676b258cc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_cmplx_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_cmplx_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8c.html
new file mode 100644
index 0000000000..fa06c34572
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_cmplx_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8d.html
new file mode 100644
index 0000000000..e22ec3f2cd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__cmplx__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_cmplx_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_cmplx_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8c.html
new file mode 100644
index 0000000000..379d324339
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_real_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_real_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8d.html
new file mode 100644
index 0000000000..75059fe98f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_real_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_real_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8c.html
new file mode 100644
index 0000000000..5f596d56a7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_real_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8d.html
new file mode 100644
index 0000000000..45ddc3df60
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_real_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_real_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8c.html
new file mode 100644
index 0000000000..53a6f46127
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_cmplx_mult_real_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8d.html
new file mode 100644
index 0000000000..1b113dd1e0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cmplx__mult__real__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cmplx_mult_real_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cmplx_mult_real_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__common__tables_8c.html b/CMSIS/Documentation/DSP/html/arm__common__tables_8c.html
new file mode 100644
index 0000000000..feaf94d50e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__common__tables_8c.html
@@ -0,0 +1,175 @@
+
+
+
+
+arm_common_tables.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_common_tables.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Variables
const uint16_t armBitRevTable [1024]
const float32_t twiddleCoef [6144]
const q31_t twiddleCoefQ31 [6144]
const q15_t ALIGN4 twiddleCoefQ15 [6144]
const q15_t ALIGN4 armRecipTableQ15 [64]
const q31_t armRecipTableQ31 [64]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 armRecipTableQ15[64]

+

+

+
end of CFFT_CIFFT group 

+
+
Referenced by arm_lms_norm_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t armRecipTableQ31[64]

+

+

+
+
Referenced by arm_lms_norm_init_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__common__tables_8d.html b/CMSIS/Documentation/DSP/html/arm__common__tables_8d.html
new file mode 100644
index 0000000000..1595c1b1d6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__common__tables_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_common_tables.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_common_tables.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__common__tables_8h.html b/CMSIS/Documentation/DSP/html/arm__common__tables_8h.html
new file mode 100644
index 0000000000..1dad8381a9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__common__tables_8h.html
@@ -0,0 +1,203 @@
+
+
+
+
+arm_common_tables.h File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_common_tables.h File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Variables
const uint16_t armBitRevTable [1024]
const q15_t armRecipTableQ15 [64]
const q31_t armRecipTableQ31 [64]
const q31_t realCoefAQ31 [1024]
const q31_t realCoefBQ31 [1024]
const float32_t twiddleCoef [6144]
const q31_t twiddleCoefQ31 [6144]
const q15_t twiddleCoefQ15 [6144]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const q15_t armRecipTableQ15[64]

+

+

+
end of CFFT_CIFFT group 

+
+
Referenced by arm_lms_norm_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t armRecipTableQ31[64]

+

+

+
+
Referenced by arm_lms_norm_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefAQ31[1024]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefBQ31[1024]

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__f32_8c.html
new file mode 100644
index 0000000000..4f26785684
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__f32_8d.html
new file mode 100644
index 0000000000..8f38382d47
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8c.html
new file mode 100644
index 0000000000..170f3f6e9e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_fast_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_fast_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8d.html
new file mode 100644
index 0000000000..160e90b153
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_fast_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_fast_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8c.html
new file mode 100644
index 0000000000..fdac95b8ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8d.html
new file mode 100644
index 0000000000..d6f88fd47d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8c.html
new file mode 100644
index 0000000000..2cf0e603f0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8d.html
new file mode 100644
index 0000000000..4cf9a824d0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8c.html
new file mode 100644
index 0000000000..3705a59c8f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8d.html
new file mode 100644
index 0000000000..dca115e61a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8c.html
new file mode 100644
index 0000000000..665c031606
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_opt_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_opt_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8d.html
new file mode 100644
index 0000000000..08ac3df360
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_opt_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_opt_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8c.html
new file mode 100644
index 0000000000..ed8736e42f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8d.html
new file mode 100644
index 0000000000..58a2f379b2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8c.html
new file mode 100644
index 0000000000..6d998847fb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_fast_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_fast_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8d.html
new file mode 100644
index 0000000000..b64fcad15c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_fast_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_fast_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8c.html
new file mode 100644
index 0000000000..e52d8203af
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8d.html
new file mode 100644
index 0000000000..3380574c7e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8c.html
new file mode 100644
index 0000000000..8c068f37d4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8d.html
new file mode 100644
index 0000000000..29b1d06c21
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8c.html
new file mode 100644
index 0000000000..823c837454
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8d.html
new file mode 100644
index 0000000000..645fd1647c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8c.html
new file mode 100644
index 0000000000..a717e3d5eb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_opt_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_opt_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8d.html
new file mode 100644
index 0000000000..2ba5f8d1f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_opt_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_opt_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8c.html
new file mode 100644
index 0000000000..0b327b6005
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8d.html
new file mode 100644
index 0000000000..b357df482a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8c.html
new file mode 100644
index 0000000000..359e6e6fae
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8d.html
new file mode 100644
index 0000000000..d8b7287518
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8c.html
new file mode 100644
index 0000000000..56313db71c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_partial_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_partial_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8d.html
new file mode 100644
index 0000000000..8c6349221a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_partial_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_partial_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__q15_8c.html
new file mode 100644
index 0000000000..0d2a091a00
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__q15_8d.html
new file mode 100644
index 0000000000..04d99d9a53
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__q31_8c.html
new file mode 100644
index 0000000000..9589413bf5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__q31_8d.html
new file mode 100644
index 0000000000..9b4b8d8897
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__conv__q7_8c.html
new file mode 100644
index 0000000000..f87b92513b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_conv_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_conv_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__conv__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__conv__q7_8d.html
new file mode 100644
index 0000000000..2e98d6f95e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__conv__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_conv_q7.d File Reference
+
+
+
+
+
+
+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_conv_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__convolution__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__convolution__example__f32_8c.html
new file mode 100644
index 0000000000..658fb5ecf7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__convolution__example__f32_8c.html
@@ -0,0 +1,385 @@
+
+
+
+
+arm_convolution_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_convolution_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE
#define DELTA
#define SNR_THRESHOLD

+Variables
float32_t Ak [MAX_BLOCKSIZE]
float32_t Bk [MAX_BLOCKSIZE]
float32_t AxB [MAX_BLOCKSIZE *2]
float32_t testInputA_f32 [64]
float32_t testInputB_f32 [64]
const float testRefOutput_f32 [126]
uint32_t srcALen
uint32_t srcBLen
uint32_t outLen
float32_t snr

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define DELTA

+

+

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD

+

+

+
Examples: 
arm_convolution_example_f32.c, and arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t Ak[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AxB[MAX_BLOCKSIZE *2]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t Bk[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t outLen

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcALen

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by arm_conv_f32(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_fast_q31(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_conv_q15(), arm_conv_q31(), arm_conv_q7(), arm_correlate_f32(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_fast_q31(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_correlate_q31(), arm_correlate_q7(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcBLen

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by arm_conv_f32(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_fast_q31(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_conv_q15(), arm_conv_q31(), arm_conv_q7(), arm_correlate_f32(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_fast_q31(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_correlate_q31(), arm_correlate_q7(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputA_f32[64]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputB_f32[64]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float testRefOutput_f32[126]

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References Ak, arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), arm_cmplx_mult_cmplx_f32(), arm_copy_f32(), arm_fill_f32(), ARM_MATH_SUCCESS, arm_snr_f32(), AxB, Bk, MAX_BLOCKSIZE, outLen, snr, SNR_THRESHOLD, srcALen, srcBLen, status, testInputA_f32, testInputB_f32, and testRefOutput_f32.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__copy__f32_8c.html
new file mode 100644
index 0000000000..14e25cd8f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_copy_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_copy_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__copy__f32_8d.html
new file mode 100644
index 0000000000..c9f4daf6a6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_copy_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_copy_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__copy__q15_8c.html
new file mode 100644
index 0000000000..c099a8f924
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_copy_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_copy_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__copy__q15_8d.html
new file mode 100644
index 0000000000..d21a06658d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_copy_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_copy_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__copy__q31_8c.html
new file mode 100644
index 0000000000..d08f9e7811
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_copy_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_copy_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__copy__q31_8d.html
new file mode 100644
index 0000000000..80eda19df8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_copy_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_copy_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__copy__q7_8c.html
new file mode 100644
index 0000000000..c681bf70ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_copy_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_copy_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__copy__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__copy__q7_8d.html
new file mode 100644
index 0000000000..7fd338da26
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__copy__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_copy_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_copy_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__f32_8c.html
new file mode 100644
index 0000000000..64d5009102
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__f32_8d.html
new file mode 100644
index 0000000000..1a4895b9d0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8c.html
new file mode 100644
index 0000000000..2626471087
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_fast_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_fast_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8d.html
new file mode 100644
index 0000000000..72e779c11d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_fast_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_fast_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8c.html
new file mode 100644
index 0000000000..56bcce21d1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8d.html
new file mode 100644
index 0000000000..c15133c1a2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8c.html
new file mode 100644
index 0000000000..8aea01520f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8d.html
new file mode 100644
index 0000000000..8ba54e0362
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8c.html
new file mode 100644
index 0000000000..230878d18e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_opt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_opt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8d.html
new file mode 100644
index 0000000000..8e1854e62d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_opt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_opt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8c.html
new file mode 100644
index 0000000000..6a19f80f48
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_opt_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_opt_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8d.html
new file mode 100644
index 0000000000..374dc3af5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__opt__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_opt_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_opt_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__q15_8c.html
new file mode 100644
index 0000000000..81b0f2915c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__q15_8d.html
new file mode 100644
index 0000000000..36228ba8ca
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__q31_8c.html
new file mode 100644
index 0000000000..43dbb62351
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__q31_8d.html
new file mode 100644
index 0000000000..ef749de501
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__correlate__q7_8c.html
new file mode 100644
index 0000000000..68d31d8bc5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_correlate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_correlate_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__correlate__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__correlate__q7_8d.html
new file mode 100644
index 0000000000..7a8a6af42d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__correlate__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_correlate_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_correlate_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__cos__f32_8c.html
new file mode 100644
index 0000000000..26735afe3a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__f32_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_cos_f32.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const float32_t cosTable [260]

+Functions
float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__cos__f32_8d.html
new file mode 100644
index 0000000000..ed59c1b524
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cos_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cos_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__cos__q15_8c.html
new file mode 100644
index 0000000000..a406f59e3a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__q15_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_cos_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_cos_q15.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const q15_t cosTableQ15 [259]

+Functions
q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__cos__q15_8d.html
new file mode 100644
index 0000000000..9d2d28834f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cos_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cos_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__cos__q31_8c.html
new file mode 100644
index 0000000000..cb8f14a649
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__q31_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_cos_q31.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const q31_t cosTableQ31 [259]

+Functions
q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__cos__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__cos__q31_8d.html
new file mode 100644
index 0000000000..7f2c808aa9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__cos__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_cos_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_cos_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__f32_8c.html
new file mode 100644
index 0000000000..223adb0ad4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dct4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dct4_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__f32_8d.html
new file mode 100644
index 0000000000..c5feda6a6a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8c.html
new file mode 100644
index 0000000000..bb1a199bda
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8c.html
@@ -0,0 +1,150 @@
+
+
+
+
+arm_dct4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_dct4_init_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t Weights_8192 [16384]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]
static const float32_t cos_factors_8192 [8192]

+Functions
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8d.html
new file mode 100644
index 0000000000..c6f158d2d6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8c.html
new file mode 100644
index 0000000000..cf1cc35828
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8c.html
@@ -0,0 +1,150 @@
+
+
+
+
+arm_dct4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_dct4_init_q15.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const q15_t ALIGN4 WeightsQ15_128 [256]
static const q15_t ALIGN4 WeightsQ15_512 [1024]
static const q15_t ALIGN4 WeightsQ15_2048 [4096]
static const q15_t ALIGN4 WeightsQ15_8192 [16384]
static const q15_t ALIGN4 cos_factorsQ15_128 [128]
static const q15_t ALIGN4 cos_factorsQ15_512 [512]
static const q15_t ALIGN4 cos_factorsQ15_2048 [2048]
static const q15_t ALIGN4 cos_factorsQ15_8192 [8192]

+Functions
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8d.html
new file mode 100644
index 0000000000..33d8a9a984
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8c.html
new file mode 100644
index 0000000000..31ea8de614
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8c.html
@@ -0,0 +1,150 @@
+
+
+
+
+arm_dct4_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_dct4_init_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t WeightsQ31_8192 [16384]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]
static const q31_t cos_factorsQ31_8192 [8192]

+Functions
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8d.html
new file mode 100644
index 0000000000..f337aca211
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__q15_8c.html
new file mode 100644
index 0000000000..7a5a649678
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dct4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dct4_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__q15_8d.html
new file mode 100644
index 0000000000..96541676a3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__dct4__q31_8c.html
new file mode 100644
index 0000000000..38238785e6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dct4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dct4_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dct4__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__dct4__q31_8d.html
new file mode 100644
index 0000000000..212461b612
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dct4__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dct4_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dct4_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8c.html
new file mode 100644
index 0000000000..78d90f8aeb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dot_prod_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8d.html
new file mode 100644
index 0000000000..92bcaeac24
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dot_prod_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dot_prod_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8c.html
new file mode 100644
index 0000000000..4d74fdbd96
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dot_prod_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8d.html
new file mode 100644
index 0000000000..ac376482bb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dot_prod_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dot_prod_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8c.html
new file mode 100644
index 0000000000..397d8a4a39
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dot_prod_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8d.html
new file mode 100644
index 0000000000..b95408aa81
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dot_prod_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dot_prod_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8c.html
new file mode 100644
index 0000000000..bf0456e0f9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_dot_prod_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_dot_prod_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8d.html
new file mode 100644
index 0000000000..ea48c05abb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dot__prod__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_dot_prod_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dot_prod_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__dotproduct__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__dotproduct__example__f32_8c.html
new file mode 100644
index 0000000000..46d725a4dc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__dotproduct__example__f32_8c.html
@@ -0,0 +1,297 @@
+
+
+
+
+arm_dotproduct_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_dotproduct_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE
#define DELTA

+Variables
float32_t srcA_buf_f32 [MAX_BLOCKSIZE]
float32_t srcB_buf_f32 [MAX_BLOCKSIZE]
float32_t refDotProdOut
float32_t multOutput [MAX_BLOCKSIZE]
float32_t testOutput
arm_status status

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define DELTA

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE

+

+

+
+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t multOutput[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refDotProdOut

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t srcA_buf_f32[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t srcB_buf_f32[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), arm_cfft_radix4_init_q31(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_dct4_init_f32(), arm_dct4_init_q15(), arm_dct4_init_q31(), arm_fir_decimate_init_f32(), arm_fir_decimate_init_q15(), arm_fir_decimate_init_q31(), arm_fir_init_q15(), arm_fir_interpolate_init_f32(), arm_fir_interpolate_init_q15(), arm_fir_interpolate_init_q31(), arm_mat_add_f32(), arm_mat_add_q15(), arm_mat_add_q31(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_mult_fast_q15(), arm_mat_mult_fast_q31(), arm_mat_mult_q15(), arm_mat_mult_q31(), arm_mat_scale_f32(), arm_mat_scale_q15(), arm_mat_scale_q31(), arm_mat_sub_f32(), arm_mat_sub_q15(), arm_mat_sub_q31(), arm_mat_trans_f32(), arm_mat_trans_q15(), arm_mat_trans_q31(), arm_rfft_init_f32(), arm_rfft_init_q15(), arm_rfft_init_q31(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_add_f32(), ARM_MATH_TEST_FAILURE, arm_mult_f32(), DELTA, MAX_BLOCKSIZE, multOutput, refDotProdOut, srcA_buf_f32, srcB_buf_f32, status, and testOutput.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fft__bin__data_8c.html b/CMSIS/Documentation/DSP/html/arm__fft__bin__data_8c.html
new file mode 100644
index 0000000000..1211336966
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fft__bin__data_8c.html
@@ -0,0 +1,155 @@
+
+
+
+
+arm_fft_bin_data.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_fft_bin_data.c File Reference
  

+

+

+
+
+
+

+Variables
float32_t testInput_f32_10khz [2048]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_10khz[2048]

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fft__bin__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fft__bin__example__f32_8c.html
new file mode 100644
index 0000000000..4360507463
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fft__bin__example__f32_8c.html
@@ -0,0 +1,295 @@
+
+
+
+
+arm_fft_bin_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_fft_bin_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES

+Variables
float32_t testInput_f32_10khz [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES/2]
uint32_t fftSize
uint32_t ifftFlag
uint32_t doBitReverse
uint32_t refIndex
uint32_t testIndex

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t doBitReverse

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t fftSize

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ifftFlag

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), arm_cfft_radix4_init_q31(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t refIndex

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t testIndex

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES/2] [static]

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), arm_cmplx_mag_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_max_f32(), doBitReverse, fftSize, ifftFlag, refIndex, status, testIndex, testInput_f32_10khz, and testOutput.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fill__f32_8c.html
new file mode 100644
index 0000000000..17eedcdd5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fill_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fill_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fill__f32_8d.html
new file mode 100644
index 0000000000..4e4e652099
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fill_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fill_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fill__q15_8c.html
new file mode 100644
index 0000000000..eae3a5c966
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fill_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fill_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fill__q15_8d.html
new file mode 100644
index 0000000000..e1ad0a62da
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fill_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fill_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fill__q31_8c.html
new file mode 100644
index 0000000000..fd333bab09
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fill_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fill_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fill__q31_8d.html
new file mode 100644
index 0000000000..c00a78969d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fill_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fill_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__fill__q7_8c.html
new file mode 100644
index 0000000000..dc93dfc696
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fill_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fill_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fill__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__fill__q7_8d.html
new file mode 100644
index 0000000000..ca3a3188cd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fill__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fill_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fill_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__data_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__data_8c.html
new file mode 100644
index 0000000000..0490e784d7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__data_8c.html
@@ -0,0 +1,172 @@
+
+
+
+
+arm_fir_data.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_fir_data.c File Reference
  

+

+

+
+
+
+
+

+Variables
float32_t testInput_f32_1kHz_15kHz [320]
float32_t refOutput [320]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t refOutput[320]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_1kHz_15kHz[320]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8c.html
new file mode 100644
index 0000000000..1ebfe31e54
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8d.html
new file mode 100644
index 0000000000..ab94a137d7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8c.html
new file mode 100644
index 0000000000..c44f5a6d5f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8d.html
new file mode 100644
index 0000000000..bfd43d1287
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8c.html
new file mode 100644
index 0000000000..e092a14538
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8d.html
new file mode 100644
index 0000000000..1a98bef8f0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8c.html
new file mode 100644
index 0000000000..74c80859ea
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8d.html
new file mode 100644
index 0000000000..1b5c02836c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8c.html
new file mode 100644
index 0000000000..e94b3790e8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8d.html
new file mode 100644
index 0000000000..f32fe8ca42
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q31_8c.html
new file mode 100644
index 0000000000..b8812abe3f
--- /dev/null
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+
+
+
+
+arm_fir_decimate_init_q31.c File Reference
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__q31_8d.html
new file mode 100644
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@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_init_q31.d File Reference
+
+
+
+
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+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_decimate_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8c.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_q15.c File Reference
+
+
+
+
+
+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8d.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_decimate_q15.d File Reference
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+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
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+

+  

+
arm_fir_decimate_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_decimate_q31.c File Reference
+
+
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+
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+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_decimate_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8d.html
new file mode 100644
index 0000000000..2123d1b881
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__decimate__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
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+arm_fir_decimate_q31.d File Reference
+
+
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+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

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+
arm_fir_decimate_q31.d File Reference
  

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+  
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+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__example__f32_8c.html
new file mode 100644
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+
+
+
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+arm_fir_example_f32.c File Reference
+
+
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+

+
+

+
+ 
+ 
+  
+  
+  
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+  
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+ 
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
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+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_fir_example_f32.c File Reference
  

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+
+

+Defines
#define TEST_LENGTH_SAMPLES
#define SNR_THRESHOLD_F32
#define BLOCK_SIZE
#define NUM_TAPS

+Variables
float32_t testInput_f32_1kHz_15kHz [TEST_LENGTH_SAMPLES]
float32_t refOutput [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
static float32_t firStateF32 [BLOCK_SIZE+NUM_TAPS-1]
const float32_t firCoeffs32 [NUM_TAPS]
uint32_t blockSize
uint32_t numBlocks
float32_t snr

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define BLOCK_SIZE

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
#define NUM_TAPS

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD_F32

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES

+

+

+
+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize

+

+

+
Examples: 
arm_fir_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by arm_abs_f32(), arm_abs_q15(), arm_abs_q31(), arm_abs_q7(), arm_add_f32(), arm_add_q15(), arm_add_q31(), arm_add_q7(), arm_biquad_cas_df1_32x64_q31(), arm_biquad_cascade_df1_f32(), arm_biquad_cascade_df1_q31(), arm_biquad_cascade_df2T_f32(), arm_circularRead_f32(), arm_circularRead_q15(), arm_circularRead_q7(), arm_circularWrite_f32(), arm_circularWrite_q15(), arm_circularWrite_q7(), arm_copy_f32(), arm_copy_q15(), arm_copy_q31(), arm_copy_q7(), arm_dot_prod_f32(), arm_dot_prod_q15(), arm_dot_prod_q31(), arm_dot_prod_q7(), arm_fill_f32(), arm_fill_q15(), arm_fill_q31(), arm_fill_q7(), arm_fir_lattice_f32(), arm_fir_lattice_q15(), arm_fir_q31(), arm_fir_q7(), arm_fir_sparse_f32(), arm_fir_sparse_q15(), arm_fir_sparse_q31(), arm_fir_sparse_q7(), arm_float_to_q15(), arm_float_to_q31(), arm_float_to_q7(), arm_iir_lattice_f32(), arm_iir_lattice_q15(), arm_iir_lattice_q31(), arm_lms_f32(), arm_lms_norm_f32(), arm_lms_norm_q15(), arm_lms_norm_q31(), arm_lms_q15(), arm_lms_q31(), arm_mean_f32(), arm_mean_q15(), arm_mean_q31(), arm_mean_q7(), arm_mult_f32(), arm_mult_q15(), arm_mult_q31(), arm_mult_q7(), arm_negate_f32(), arm_negate_q15(), arm_negate_q31(), arm_negate_q7(), arm_offset_f32(), arm_offset_q15(), arm_offset_q31(), arm_offset_q7(), arm_power_f32(), arm_power_q15(), arm_power_q31(), arm_power_q7(), arm_provide_guard_bits_q15(), arm_provide_guard_bits_q31(), arm_provide_guard_bits_q7(), arm_q15_to_float(), arm_q15_to_q31(), arm_q15_to_q7(), arm_q31_to_float(), arm_q31_to_q15(), arm_q31_to_q7(), arm_q7_to_float(), arm_q7_to_q15(), arm_q7_to_q31(), arm_rms_f32(), arm_rms_q15(), arm_rms_q31(), arm_scale_f32(), arm_scale_q15(), arm_scale_q31(), arm_scale_q7(), arm_shift_q15(), arm_shift_q31(), arm_shift_q7(), arm_std_f32(), arm_std_q15(), arm_std_q31(), arm_sub_f32(), arm_sub_q15(), arm_sub_q31(), arm_sub_q7(), arm_var_f32(), arm_var_q15(), arm_var_q31(), and main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t firCoeffs32[NUM_TAPS]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[BLOCK_SIZE+NUM_TAPS-1] [static]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numBlocks

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refOutput[TEST_LENGTH_SAMPLES]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_fir_f32(), arm_fir_init_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_snr_f32(), blockSize, firCoeffs32, firStateF32, NUM_TAPS, numBlocks, refOutput, snr, SNR_THRESHOLD_F32, status, TEST_LENGTH_SAMPLES, testInput_f32_1kHz_15kHz, and testOutput.

+
+

+

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+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__f32_8c.html
new file mode 100644
index 0000000000..71ef5528a9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__f32_8d.html
new file mode 100644
index 0000000000..359e246f32
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_f32.d File Reference
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
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+

+  

+
arm_fir_f32.d File Reference
  

+

+

+

+

+  
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+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8c.html
new file mode 100644
index 0000000000..54e150499b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8d.html
new file mode 100644
index 0000000000..026bae2e03
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_fast_q15.d File Reference
+
+
+
+
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+
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+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8c.html
new file mode 100644
index 0000000000..4605abe288
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8d.html
new file mode 100644
index 0000000000..2fb5f7ed6a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_fast_q31.d File Reference
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+
+
+
+
+
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+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_fast_q31.d File Reference
  

+

+

+

+

+  
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+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8c.html
new file mode 100644
index 0000000000..5c90dcbf6c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8d.html
new file mode 100644
index 0000000000..4ba7b718f7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8c.html
new file mode 100644
index 0000000000..2ee8b7f037
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8d.html
new file mode 100644
index 0000000000..1cd0f87368
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8c.html
new file mode 100644
index 0000000000..3c278d6a06
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8d.html
new file mode 100644
index 0000000000..2d0a40d88d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8c.html
new file mode 100644
index 0000000000..2e3ab3b029
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_init_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8d.html
new file mode 100644
index 0000000000..ca2a8f4ab2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__init__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_init_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_init_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8c.html
new file mode 100644
index 0000000000..e57b866b08
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8d.html
new file mode 100644
index 0000000000..1f904f8066
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8c.html
new file mode 100644
index 0000000000..94e8e9f721
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8d.html
new file mode 100644
index 0000000000..f71d5ae1de
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8c.html
new file mode 100644
index 0000000000..3785a26b0e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8d.html
new file mode 100644
index 0000000000..a5e696a253
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8c.html
new file mode 100644
index 0000000000..ad02d1b21c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8d.html
new file mode 100644
index 0000000000..819c904514
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8c.html
new file mode 100644
index 0000000000..6b754d51c1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8d.html
new file mode 100644
index 0000000000..9e84021877
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8c.html
new file mode 100644
index 0000000000..49e426fa2a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_interpolate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_interpolate_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8d.html
new file mode 100644
index 0000000000..ebdd40e3aa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__interpolate__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_interpolate_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_interpolate_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8c.html
new file mode 100644
index 0000000000..4bc799759f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8d.html
new file mode 100644
index 0000000000..faf84b8e19
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8c.html
new file mode 100644
index 0000000000..5f14809c59
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8d.html
new file mode 100644
index 0000000000..6f518a3168
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8c.html
new file mode 100644
index 0000000000..fdc2bc0573
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8d.html
new file mode 100644
index 0000000000..d6ff02f60c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8c.html
new file mode 100644
index 0000000000..e902c81188
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8d.html
new file mode 100644
index 0000000000..c7f4ce04e3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8c.html
new file mode 100644
index 0000000000..e9116f03f9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8d.html
new file mode 100644
index 0000000000..595b7acf08
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8c.html
new file mode 100644
index 0000000000..7220fbda8d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_lattice_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8d.html
new file mode 100644
index 0000000000..99794f74fd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__lattice__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_lattice_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_lattice_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__q15_8c.html
new file mode 100644
index 0000000000..1b491cede6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__q15_8d.html
new file mode 100644
index 0000000000..eabfec890d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__q31_8c.html
new file mode 100644
index 0000000000..391494cb2d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__q31_8d.html
new file mode 100644
index 0000000000..632b6bb640
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__q7_8c.html
new file mode 100644
index 0000000000..0473f994a5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__q7_8d.html
new file mode 100644
index 0000000000..1057eeaa52
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8c.html
new file mode 100644
index 0000000000..7c2c64ee73
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8d.html
new file mode 100644
index 0000000000..0c76c7523f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8c.html
new file mode 100644
index 0000000000..e6dc47f159
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8d.html
new file mode 100644
index 0000000000..8981590de2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8c.html
new file mode 100644
index 0000000000..73b52eb56d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8d.html
new file mode 100644
index 0000000000..7e7ece9889
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8c.html
new file mode 100644
index 0000000000..2ba45b657a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8d.html
new file mode 100644
index 0000000000..a90e14ba07
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8c.html
new file mode 100644
index 0000000000..4e72cef91f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_init_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8d.html
new file mode 100644
index 0000000000..ef4f3e3fb4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__init__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_init_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_init_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8c.html
new file mode 100644
index 0000000000..9e645a5359
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8d.html
new file mode 100644
index 0000000000..3f3bd0b79b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8c.html
new file mode 100644
index 0000000000..70121a2e69
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8d.html
new file mode 100644
index 0000000000..31e4ea6f98
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8c.html
new file mode 100644
index 0000000000..8683ae20df
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_fir_sparse_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_fir_sparse_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8d.html
new file mode 100644
index 0000000000..4df97ce538
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__fir__sparse__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_fir_sparse_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_sparse_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__float__to__q15_8c.html
new file mode 100644
index 0000000000..c86f4a9e73
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_float_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_float_to_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__float__to__q15_8d.html
new file mode 100644
index 0000000000..b2a442c4ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_float_to_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_float_to_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__float__to__q31_8c.html
new file mode 100644
index 0000000000..3719972940
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_float_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_float_to_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__float__to__q31_8d.html
new file mode 100644
index 0000000000..1848df535b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_float_to_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_float_to_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__float__to__q7_8c.html
new file mode 100644
index 0000000000..30a870354b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_float_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_float_to_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__float__to__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__float__to__q7_8d.html
new file mode 100644
index 0000000000..d020e4a917
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__float__to__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_float_to_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_float_to_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__data_8c.html b/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__data_8c.html
new file mode 100644
index 0000000000..c74d7fa856
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__data_8c.html
@@ -0,0 +1,169 @@
+
+
+
+
+arm_graphic_equalizer_data.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_graphic_equalizer_data.c File Reference
  

+

+

+
+
+
+
+

+Variables
float32_t testRefOutput_f32 [320]
float32_t testInput_f32 [320]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[320]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefOutput_f32[320]

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__example__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__example__q31_8c.html
new file mode 100644
index 0000000000..987d3f638b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__graphic__equalizer__example__q31_8c.html
@@ -0,0 +1,461 @@
+
+
+
+
+arm_graphic_equalizer_example_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_graphic_equalizer_example_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TESTLENGTH
#define BLOCKSIZE
#define NUMBLOCKS
#define NUMSTAGES
#define SNR_THRESHOLD_F32

+Variables
float32_t testInput_f32 [TESTLENGTH]
static float32_t testOutput [TESTLENGTH]
float32_t testRefOutput_f32 [TESTLENGTH]
static q63_t biquadStateBand1Q31 [4 *2]
static q63_t biquadStateBand2Q31 [4 *2]
static q31_t biquadStateBand3Q31 [4 *2]
static q31_t biquadStateBand4Q31 [4 *2]
static q31_t biquadStateBand5Q31 [4 *2]
q31_t inputQ31 [BLOCKSIZE]
q31_t outputQ31 [BLOCKSIZE]
const q31_t coeffTable [950]
int gainDB [5]
float32_t snr

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define BLOCKSIZE

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMBLOCKS

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSTAGES

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD_F32

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TESTLENGTH

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
q63_t biquadStateBand1Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t biquadStateBand2Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand3Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand4Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand5Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t coeffTable[950]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int gainDB[5]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t inputQ31[BLOCKSIZE]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t outputQ31[BLOCKSIZE]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TESTLENGTH]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TESTLENGTH] [static]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefOutput_f32[TESTLENGTH]

+

+

+
+
Referenced by main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_biquad_cas_df1_32x64_init_q31(), arm_biquad_cas_df1_32x64_q31(), arm_biquad_cascade_df1_init_q31(), arm_biquad_cascade_df1_q31(), arm_float_to_q31(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_q31_to_float(), arm_scale_f32(), arm_scale_q31(), arm_snr_f32(), biquadStateBand1Q31, biquadStateBand2Q31, biquadStateBand3Q31, biquadStateBand4Q31, biquadStateBand5Q31, BLOCKSIZE, coeffTable, gainDB, inputQ31, NUMBLOCKS, NUMSTAGES, outputQ31, snr, SNR_THRESHOLD_F32, status, testInput_f32, TESTLENGTH, testOutput, and testRefOutput_f32.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8c.html
new file mode 100644
index 0000000000..992c9894db
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8d.html
new file mode 100644
index 0000000000..15432f227c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8c.html
new file mode 100644
index 0000000000..3c7b01a9e8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8d.html
new file mode 100644
index 0000000000..280a1e5d49
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8c.html
new file mode 100644
index 0000000000..4ef13e9850
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8d.html
new file mode 100644
index 0000000000..aa33036ca5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8c.html
new file mode 100644
index 0000000000..1b56f1dadd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8d.html
new file mode 100644
index 0000000000..bdeca4e576
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8c.html
new file mode 100644
index 0000000000..2659f53496
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8d.html
new file mode 100644
index 0000000000..abf0d28dc9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8c.html
new file mode 100644
index 0000000000..b550b41c08
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_iir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_iir_lattice_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8d.html
new file mode 100644
index 0000000000..9c0555cba2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__iir__lattice__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_iir_lattice_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_iir_lattice_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__linear__interp__data_8c.html b/CMSIS/Documentation/DSP/html/arm__linear__interp__data_8c.html
new file mode 100644
index 0000000000..7f63da1db3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__linear__interp__data_8c.html
@@ -0,0 +1,155 @@
+
+
+
+
+arm_linear_interp_data.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_linear_interp_data.c File Reference
  

+

+

+
+
+
+

+Variables
const float arm_linear_interep_table [188495]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float arm_linear_interep_table[188495]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__linear__interp__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__linear__interp__example__f32_8c.html
new file mode 100644
index 0000000000..8e83e8da79
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__linear__interp__example__f32_8c.html
@@ -0,0 +1,328 @@
+
+
+
+
+arm_linear_interp_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_linear_interp_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define SNR_THRESHOLD
#define TEST_LENGTH_SAMPLES
#define XSPACING

+Variables
float32_t testInputSin_f32 [TEST_LENGTH_SAMPLES]
float32_t testRefSinOutput32_f32 [TEST_LENGTH_SAMPLES]
float32_t testOutput [TEST_LENGTH_SAMPLES]
float32_t testLinIntOutput [TEST_LENGTH_SAMPLES]
const float arm_linear_interep_table [188495]
float32_t snr1
float32_t snr2

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define XSPACING

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float arm_linear_interep_table[188495]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr1

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr2

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputSin_f32[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_linear_interep_table, arm_linear_interp_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_sin_f32(), arm_snr_f32(), snr1, snr2, status, TEST_LENGTH_SAMPLES, testInputSin_f32, testLinIntOutput, testOutput, testRefSinOutput32_f32, and XSPACING.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__f32_8c.html
new file mode 100644
index 0000000000..fcd450cacb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__f32_8d.html
new file mode 100644
index 0000000000..1e79d87b04
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8c.html
new file mode 100644
index 0000000000..422739eed2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8d.html
new file mode 100644
index 0000000000..640ee0564d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8c.html
new file mode 100644
index 0000000000..b506d14d8e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8d.html
new file mode 100644
index 0000000000..09b50b14cd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8c.html
new file mode 100644
index 0000000000..cb562ccff5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8d.html
new file mode 100644
index 0000000000..9e6fa97fa1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8c.html
new file mode 100644
index 0000000000..07b3bf773c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8d.html
new file mode 100644
index 0000000000..6db69f08eb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8c.html
new file mode 100644
index 0000000000..e68c18cc5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8d.html
new file mode 100644
index 0000000000..415294c5f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8c.html
new file mode 100644
index 0000000000..e79cb552d0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8d.html
new file mode 100644
index 0000000000..e28b4aa0de
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8c.html
new file mode 100644
index 0000000000..4e6d5a2c57
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8d.html
new file mode 100644
index 0000000000..eaf1dff842
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8c.html
new file mode 100644
index 0000000000..842b326f53
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8d.html
new file mode 100644
index 0000000000..9f0ce27288
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8c.html
new file mode 100644
index 0000000000..0860a062db
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_norm_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_norm_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8d.html
new file mode 100644
index 0000000000..497d633a5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__norm__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_norm_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_norm_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__q15_8c.html
new file mode 100644
index 0000000000..547889353e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__q15_8d.html
new file mode 100644
index 0000000000..b0dec0cc0e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__lms__q31_8c.html
new file mode 100644
index 0000000000..08fc4a3fb1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_lms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_lms_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__lms__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__lms__q31_8d.html
new file mode 100644
index 0000000000..21e0f3e417
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__lms__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_lms_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_lms_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8c.html
new file mode 100644
index 0000000000..f2e27d7426
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_add_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_add_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8d.html
new file mode 100644
index 0000000000..9aa07f181c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_add_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_add_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8c.html
new file mode 100644
index 0000000000..f862eab16c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_add_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8d.html
new file mode 100644
index 0000000000..fca1972a71
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_add_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_add_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8c.html
new file mode 100644
index 0000000000..ce8a92d9ee
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_add_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8d.html
new file mode 100644
index 0000000000..a510c00ac4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_add_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_add_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8c.html
new file mode 100644
index 0000000000..63defd1d3d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8d.html
new file mode 100644
index 0000000000..1939b125d3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8c.html
new file mode 100644
index 0000000000..2ab4031d23
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8d.html
new file mode 100644
index 0000000000..4994f128b1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8c.html
new file mode 100644
index 0000000000..148bb52209
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8d.html
new file mode 100644
index 0000000000..fcb0b383ae
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8c.html
new file mode 100644
index 0000000000..daa3cf5231
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_inverse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_inverse_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix inverse.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8d.html
new file mode 100644
index 0000000000..f6b62ab6e7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_inverse_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_inverse_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8c.html
new file mode 100644
index 0000000000..c36f0de1fb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_mult_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8d.html
new file mode 100644
index 0000000000..e24a64675d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_mult_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_mult_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8c.html
new file mode 100644
index 0000000000..08eee6f597
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_mult_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_mult_fast_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8d.html
new file mode 100644
index 0000000000..d21e21dfc1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_mult_fast_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_mult_fast_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8c.html
new file mode 100644
index 0000000000..b273c06bc4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_mult_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_mult_fast_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8d.html
new file mode 100644
index 0000000000..e8a7c94678
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_mult_fast_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_mult_fast_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8c.html
new file mode 100644
index 0000000000..10d0fe67af
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_mult_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8d.html
new file mode 100644
index 0000000000..3fa7e51a31
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_mult_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_mult_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8c.html
new file mode 100644
index 0000000000..8a6afab7b7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_mult_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8d.html
new file mode 100644
index 0000000000..a821e43c39
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_mult_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_mult_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8c.html
new file mode 100644
index 0000000000..1119ac8417
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_scale_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8d.html
new file mode 100644
index 0000000000..56180cf23e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_scale_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_scale_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8c.html
new file mode 100644
index 0000000000..c7c53a4d99
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_scale_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8d.html
new file mode 100644
index 0000000000..1d694813d4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_scale_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_scale_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8c.html
new file mode 100644
index 0000000000..17fe23db3c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_scale_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8d.html
new file mode 100644
index 0000000000..36bd16220c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_scale_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_scale_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8c.html
new file mode 100644
index 0000000000..f3fa8e00c7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_sub_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8d.html
new file mode 100644
index 0000000000..9bd7e520da
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_sub_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_sub_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8c.html
new file mode 100644
index 0000000000..32546ead06
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_sub_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_sub_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8d.html
new file mode 100644
index 0000000000..9660ded453
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_sub_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mat_sub_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8c.html
new file mode 100644
index 0000000000..78ac8aa036
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mat_sub_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_sub_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8d.html
new file mode 100644
index 0000000000..76dcdfcfc7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mat__sub__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mat_sub_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
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+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

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+

+  

+
arm_mat_sub_q31.d File Reference
  

+

+

+

+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__f32_8c.html
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+arm_mat_trans_f32.c File Reference
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
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+

+    
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+  
+

+

+  
+  

+  

+

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+

+

+  

+Functions  

+  

+
arm_mat_trans_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__f32_8d.html
new file mode 100644
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+arm_mat_trans_f32.d File Reference
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+  
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+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
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+  
+

+

+  
+  

+  

+

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+
arm_mat_trans_f32.d File Reference
  

+

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+  
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diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__q15_8c.html
new file mode 100644
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+arm_mat_trans_q15.c File Reference
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

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+    
+

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+  
+

+

+  
+  

+  

+

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+

+  

+Functions  

+  

+
arm_mat_trans_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__q15_8d.html
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+arm_mat_trans_q15.d File Reference
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
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+  
+

+

+  
+  

+  

+

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arm_mat_trans_q15.d File Reference
  

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diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__q31_8c.html
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+arm_mat_trans_q31.c File Reference
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mat_trans_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mat__trans__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mat__trans__q31_8d.html
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+arm_mat_trans_q31.d File Reference
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
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+  
+

+

+  
+  

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arm_mat_trans_q31.d File Reference
  

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diff --git a/CMSIS/Documentation/DSP/html/arm__math_8h.html b/CMSIS/Documentation/DSP/html/arm__math_8h.html
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+arm_math.h File Reference
+
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+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Structures |
+Defines |
+Typedefs |
+Enumerations |
+Functions  

+  

+
arm_math.h File Reference
  

+

+

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+Data Structures
struct  arm_fir_instance_q7
 Instance structure for the Q7 FIR filter.  More...
struct  arm_fir_instance_q15
 Instance structure for the Q15 FIR filter.  More...
struct  arm_fir_instance_q31
 Instance structure for the Q31 FIR filter.  More...
struct  arm_fir_instance_f32
 Instance structure for the floating-point FIR filter.  More...
struct  arm_biquad_casd_df1_inst_q15
 Instance structure for the Q15 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_q31
 Instance structure for the Q31 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_f32
 Instance structure for the floating-point Biquad cascade filter.  More...
struct  arm_matrix_instance_f32
 Instance structure for the floating-point matrix structure.  More...
struct  arm_matrix_instance_q15
 Instance structure for the Q15 matrix structure.  More...
struct  arm_matrix_instance_q31
 Instance structure for the Q31 matrix structure.  More...
struct  arm_pid_instance_q15
 Instance structure for the Q15 PID Control.  More...
struct  arm_pid_instance_q31
 Instance structure for the Q31 PID Control.  More...
struct  arm_pid_instance_f32
 Instance structure for the floating-point PID Control.  More...
struct  arm_linear_interp_instance_f32
 Instance structure for the floating-point Linear Interpolate function.  More...
struct  arm_bilinear_interp_instance_f32
 Instance structure for the floating-point bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q31
 Instance structure for the Q31 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q15
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q7
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_cfft_radix4_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_q31
 Instance structure for the Q31 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
struct  arm_cfft_radix2_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
struct  arm_cfft_radix2_instance_q31
 Instance structure for the Radix-2 Q31 CFFT/CIFFT function.  More...
struct  arm_cfft_radix2_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
struct  arm_rfft_instance_q15
 Instance structure for the Q15 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_q31
 Instance structure for the Q31 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_f32
 Instance structure for the floating-point RFFT/RIFFT function.  More...
struct  arm_dct4_instance_f32
 Instance structure for the floating-point DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q31
 Instance structure for the Q31 DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q15
 Instance structure for the Q15 DCT4/IDCT4 function.  More...
struct  arm_fir_decimate_instance_q15
 Instance structure for the Q15 FIR decimator.  More...
struct  arm_fir_decimate_instance_q31
 Instance structure for the Q31 FIR decimator.  More...
struct  arm_fir_decimate_instance_f32
 Instance structure for the floating-point FIR decimator.  More...
struct  arm_fir_interpolate_instance_q15
 Instance structure for the Q15 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_q31
 Instance structure for the Q31 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_f32
 Instance structure for the floating-point FIR interpolator.  More...
struct  arm_biquad_cas_df1_32x64_ins_q31
 Instance structure for the high precision Q31 Biquad cascade filter.  More...
struct  arm_biquad_cascade_df2T_instance_f32
 Instance structure for the floating-point transposed direct form II Biquad cascade filter.  More...
struct  arm_fir_lattice_instance_q15
 Instance structure for the Q15 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_q31
 Instance structure for the Q31 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_f32
 Instance structure for the floating-point FIR lattice filter.  More...
struct  arm_iir_lattice_instance_q15
 Instance structure for the Q15 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_q31
 Instance structure for the Q31 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_f32
 Instance structure for the floating-point IIR lattice filter.  More...
struct  arm_lms_instance_f32
 Instance structure for the floating-point LMS filter.  More...
struct  arm_lms_instance_q15
 Instance structure for the Q15 LMS filter.  More...
struct  arm_lms_instance_q31
 Instance structure for the Q31 LMS filter.  More...
struct  arm_lms_norm_instance_f32
 Instance structure for the floating-point normalized LMS filter.  More...
struct  arm_lms_norm_instance_q31
 Instance structure for the Q31 normalized LMS filter.  More...
struct  arm_lms_norm_instance_q15
 Instance structure for the Q15 normalized LMS filter.  More...
struct  arm_fir_sparse_instance_f32
 Instance structure for the floating-point sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q31
 Instance structure for the Q31 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q15
 Instance structure for the Q15 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q7
 Instance structure for the Q7 sparse FIR filter.  More...

+Defines
#define __CMSIS_GENERIC
#define DELTA_Q31
 Macros required for reciprocal calculation in Normalized LMS.  
#define DELTA_Q15
#define INDEX_MASK
#define PI
#define TABLE_SIZE
 Macros required for SINE and COSINE Fast math approximations.  
#define TABLE_SPACING_Q31
#define TABLE_SPACING_Q15
#define INPUT_SPACING
 Macros required for SINE and COSINE Controller functions.  
#define ALIGN4
 Macro for Unaligned Support.  
#define __SIMD32(addr)
 definition to read/write two 16 bit values.  
#define _SIMD32_OFFSET(addr)
#define __SIMD64(addr)
#define __PACKq7(v0, v1, v2, v3)
 definition to pack four 8 bit values.  

+Typedefs
typedef int8_t q7_t
 8-bit fractional data type in 1.7 format.  
typedef int16_t q15_t
 16-bit fractional data type in 1.15 format.  
typedef int32_t q31_t
 32-bit fractional data type in 1.31 format.  
typedef int64_t q63_t
 64-bit fractional data type in 1.63 format.  
typedef float float32_t
 32-bit floating-point type definition.  
typedef double float64_t
 64-bit floating-point type definition.  

+Enumerations
enum  arm_status 
 Error status returned by some functions in the library.  More...

+Functions
__STATIC_INLINE q31_t clip_q63_to_q31 (q63_t x)
 Clips Q63 to Q31 values.  
__STATIC_INLINE q15_t clip_q63_to_q15 (q63_t x)
 Clips Q63 to Q15 values.  
__STATIC_INLINE q7_t clip_q31_to_q7 (q31_t x)
 Clips Q31 to Q7 values.  
__STATIC_INLINE q15_t clip_q31_to_q15 (q31_t x)
 Clips Q31 to Q15 values.  
__STATIC_INLINE q63_t mult32x64 (q63_t x, q31_t y)
 Multiplies 32 X 64 and returns 32 bit result in 2.30 format.  
__STATIC_INLINE uint32_t arm_recip_q31 (q31_t in, q31_t *dst, q31_t *pRecipTable)
 Function to Calculates 1/in(reciprocal) value of Q31 Data type.  
__STATIC_INLINE uint32_t arm_recip_q15 (q15_t in, q15_t *dst, q15_t *pRecipTable)
 Function to Calculates 1/in(reciprocal) value of Q15 Data type.  
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication.  
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the Radix-2 Q31 CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Radix-2 Q31 CFFT/CIFFT.  
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 Core function for the floating-point CFFT butterfly process.  
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 Core function for the floating-point CIFFT butterfly process.  
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 In-place bit reversal function.  
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CFFT butterfly process.  
void arm_radix2_butterfly_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 Core function for the f32 FFT butterfly process.  
void arm_radix2_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q31 CFFT butterfly process.  
void arm_radix2_butterfly_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q15 CFFT butterfly process.  
void arm_radix2_butterfly_inverse_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q15 CFFT Inverse butterfly process.  
void arm_radix2_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 Core function for the Radix-2 Q31 CFFT Inverse butterfly process.  
void arm_radix2_butterfly_inverse_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 Core function for the f32 IFFT butterfly process.  
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CIFFT butterfly process.  
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 In-place bit reversal function.  
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CFFT butterfly process.  
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CIFFT butterfly process.  
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 In-place bit reversal function.  
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  
arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  
void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCcosVal)
 Floating-point sin_cos function.  
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  
__STATIC_INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
 Process function for the floating-point PID Control.  
__STATIC_INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
 Process function for the Q31 PID Control.  
__STATIC_INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
 Process function for the Q15 PID Control.  
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst)
 Floating-point matrix inverse.  
__STATIC_INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
 Floating-point Clarke transform.  
__STATIC_INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
 Clarke transform for Q31 version.  
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  
__STATIC_INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
 Floating-point Inverse Clarke transform.  
__STATIC_INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
 Inverse Clarke transform for Q31 version.  
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  
__STATIC_INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
 Floating-point Park transform.  
__STATIC_INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
 Park transform for Q31 version.  
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  
__STATIC_INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
 Floating-point Inverse Park transform.  
__STATIC_INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
 Inverse Park transform for Q31 version.  
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  
__STATIC_INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
 Process function for the floating-point Linear Interpolation Function.  
__STATIC_INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q31 Linear Interpolation Function.  
__STATIC_INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q15 Linear Interpolation Function.  
__STATIC_INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q7 Linear Interpolation Function.  
float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  
q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  
q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  
float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  
q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  
q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  
__STATIC_INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
 Floating-point square root function.  
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  
__STATIC_INLINE void arm_circularWrite_f32 (int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize)
 floating-point Circular write function.  
__STATIC_INLINE void arm_circularRead_f32 (int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 floating-point Circular Read function.  
__STATIC_INLINE void arm_circularWrite_q15 (q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize)
 Q15 Circular write function.  
__STATIC_INLINE void arm_circularRead_q15 (q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 Q15 Circular Read function.  
__STATIC_INLINE void arm_circularWrite_q7 (q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize)
 Q7 Circular write function.  
__STATIC_INLINE void arm_circularRead_q7 (q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 Q7 Circular Read function.  
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Mean value of a Q31 vector.  
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index)
 Minimum value of a Q7 vector.  
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  
__STATIC_INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
 Floating-point bilinear interpolation.  
__STATIC_INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
 Q31 bilinear interpolation.  
__STATIC_INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
 Q15 bilinear interpolation.  
__STATIC_INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)
 Q7 bilinear interpolation.  

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Define Documentation

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#define __CMSIS_GENERIC

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#define __PACKq7( v0, 
 v1, 
 v2, 
 v3 
)

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Referenced by arm_conv_opt_q7(), arm_conv_partial_opt_q7(), arm_fill_q7(), arm_fir_sparse_q7(), arm_mult_q7(), arm_offset_q7(), arm_q31_to_q7(), arm_scale_q7(), and arm_shift_q7().

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#define __SIMD32( addr)

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Referenced by arm_abs_q15(), arm_add_q15(), arm_add_q7(), arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_q15(), arm_cmplx_conj_q15(), arm_cmplx_mag_q15(), arm_cmplx_mag_squared_q15(), arm_cmplx_mult_real_q15(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_q15(), arm_copy_q15(), arm_copy_q7(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_dot_prod_q15(), arm_dot_prod_q7(), arm_fill_q15(), arm_fill_q7(), arm_fir_decimate_fast_q15(), arm_fir_decimate_q15(), arm_fir_fast_q15(), arm_fir_interpolate_q15(), arm_fir_lattice_q15(), arm_fir_q15(), arm_fir_sparse_q15(), arm_fir_sparse_q7(), arm_iir_lattice_q15(), arm_lms_norm_q15(), arm_lms_q15(), arm_mat_add_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_sub_q15(), arm_mat_trans_q15(), arm_mean_q15(), arm_mean_q7(), arm_mult_q15(), arm_mult_q7(), arm_negate_q7(), arm_offset_q15(), arm_offset_q7(), arm_pid_q15(), arm_power_q15(), arm_power_q7(), arm_q15_to_q31(), arm_q15_to_q7(), arm_q31_to_q15(), arm_q31_to_q7(), arm_q7_to_q15(), arm_q7_to_q31(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_rms_q15(), arm_scale_q15(), arm_scale_q7(), arm_shift_q15(), arm_shift_q7(), arm_split_rfft_q15(), arm_split_rifft_q15(), arm_std_q15(), arm_sub_q15(), arm_sub_q7(), and arm_var_q15().

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#define __SIMD64( addr)

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#define _SIMD32_OFFSET( addr)

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Referenced by arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_q15(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_fir_fast_q15(), arm_fir_q15(), arm_mat_scale_q15(), arm_negate_q15(), arm_radix2_butterfly_inverse_q15(), arm_radix2_butterfly_q15(), arm_radix4_butterfly_inverse_q15(), and arm_radix4_butterfly_q15().

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#define ALIGN4

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#define DELTA_Q15

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Referenced by arm_lms_norm_q15().

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#define DELTA_Q31

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Referenced by arm_lms_norm_q31().

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#define INDEX_MASK

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#define INPUT_SPACING

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#define PI

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#define TABLE_SIZE

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#define TABLE_SPACING_Q15

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#define TABLE_SPACING_Q31

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Referenced by arm_cos_q31(), and arm_sin_q31().

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Typedef Documentation

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typedef float float32_t

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typedef double float64_t

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typedef int16_t q15_t

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typedef int32_t q31_t

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typedef int64_t q63_t

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typedef int8_t q7_t

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Enumeration Type Documentation

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enum arm_status

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Enumerator: 

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ARM_MATH_SUCCESS 
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No error 

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ARM_MATH_ARGUMENT_ERROR 
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One or more arguments are incorrect 

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ARM_MATH_LENGTH_ERROR 
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Length of data buffer is incorrect 

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ARM_MATH_SIZE_MISMATCH 
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Size of matrices is not compatible with the operation. 

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ARM_MATH_NANINF 
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Not-a-number (NaN) or infinity is generated 

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ARM_MATH_SINGULAR 
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Generated by matrix inversion if the input matrix is singular and cannot be inverted. 

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ARM_MATH_TEST_FAILURE 
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Test Failed 

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Function Documentation

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void arm_bitreversal_f32 (float32_t * pSrc, 
uint16_t fftSize, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
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Parameters:

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[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

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Returns:
none. 

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Referenced by arm_cfft_radix2_f32(), arm_cfft_radix4_f32(), and arm_rfft_f32().

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void arm_bitreversal_q15 (q15_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
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[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

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Returns:
none. 

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Referenced by arm_cfft_radix2_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

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void arm_bitreversal_q31 (q31_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
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[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

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Returns:
none. 

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Referenced by arm_cfft_radix2_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

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__STATIC_INLINE void arm_circularRead_f32 (int32_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
int32_t * dst, 
int32_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)

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References blockSize.

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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_q31().

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+      
__STATIC_INLINE void arm_circularRead_q15 (q15_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
q15_t * dst, 
q15_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)

+

+

+
+
References blockSize.

+
+
Referenced by arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_circularRead_q7 (q7_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
q7_t * dst, 
q7_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)

+

+

+
+
References blockSize.

+
+
Referenced by arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_circularWrite_f32 (int32_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const int32_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)

+

+

+
end of SQRT group 

+
+
References blockSize.

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_circularWrite_q15 (q15_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const q15_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)

+

+

+
+
References blockSize.

+
+
Referenced by arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_circularWrite_q7 (q7_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const q7_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)

+

+

+
+
References blockSize.

+
+
Referenced by arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of f32 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix2_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix2_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_inverse_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of f32 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLen1/fftLenfth 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_inverse_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix2_CFFT_CIFFT group 

+
+
References _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix2_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix2_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to the twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix4_CFFT_CIFFT group 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD64.

+
+
Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix4_CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and _SIMD32_OFFSET.

+
+
Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to Twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of Radix4_CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
References __SIMD64.

+
+
Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE uint32_t arm_recip_q15 (q15_t in, 
q15_t * dst, 
q15_t * pRecipTable 
)

+

+

+
+
References INDEX_MASK.

+
+
Referenced by arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE uint32_t arm_recip_q31 (q31_t in, 
q31_t * dst, 
q31_t * pRecipTable 
)

+

+

+
+
References clip_q63_to_q31(), and INDEX_MASK.

+
+
Referenced by arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
__STATIC_INLINE q15_t clip_q31_to_q15 (q31_t x)

+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
__STATIC_INLINE q7_t clip_q31_to_q7 (q31_t x)

+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
__STATIC_INLINE q15_t clip_q63_to_q15 (q63_t x)

+

+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
__STATIC_INLINE q31_t clip_q63_to_q31 (q63_t x)

+

+

+
+
Referenced by arm_add_q31(), arm_cmplx_mult_real_q31(), arm_float_to_q31(), arm_iir_lattice_q31(), arm_lms_norm_q31(), arm_lms_q31(), arm_mult_q31(), arm_offset_q31(), arm_pid_init_q31(), arm_recip_q31(), arm_shift_q31(), and arm_sub_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE q63_t mult32x64 (q63_t x, 
q31_t y 
)

+

+

+
+
Referenced by arm_biquad_cas_df1_32x64_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__matrix__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__matrix__example__f32_8c.html
new file mode 100644
index 0000000000..f761d626d4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__matrix__example__f32_8c.html
@@ -0,0 +1,315 @@
+
+
+
+
+arm_matrix_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_matrix_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define SNR_THRESHOLD

+Variables
const float32_t B_f32 [4]
const float32_t A_f32 [16]
float32_t AT_f32 [16]
float32_t ATMA_f32 [16]
float32_t ATMAI_f32 [16]
float32_t X_f32 [4]
const float32_t xRef_f32 [4]
float32_t snr

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD

+

+

+
+
Referenced by main().

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t A_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AT_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMA_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMAI_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t B_f32[4]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t X_f32[4]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t xRef_f32[4]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References A_f32, arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_trans_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_snr_f32(), AT_f32, ATMA_f32, ATMAI_f32, B_f32, snr, SNR_THRESHOLD, status, X_f32, and xRef_f32.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__max__f32_8c.html
new file mode 100644
index 0000000000..175239fd0d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_max_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_max_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__max__f32_8d.html
new file mode 100644
index 0000000000..0d248f6fe8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_max_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_max_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__max__q15_8c.html
new file mode 100644
index 0000000000..c5476ad58b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_max_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_max_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__max__q15_8d.html
new file mode 100644
index 0000000000..d3beac7ac0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_max_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_max_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__max__q31_8c.html
new file mode 100644
index 0000000000..e0f5d21014
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_max_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_max_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__max__q31_8d.html
new file mode 100644
index 0000000000..e4ca717f83
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_max_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_max_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__max__q7_8c.html
new file mode 100644
index 0000000000..3d0a5cf171
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_max_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_max_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__max__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__max__q7_8d.html
new file mode 100644
index 0000000000..34e62c4a4b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__max__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_max_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_max_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mean__f32_8c.html
new file mode 100644
index 0000000000..972641f3be
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mean_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mean_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mean__f32_8d.html
new file mode 100644
index 0000000000..bc2a281bba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mean_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mean_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mean__q15_8c.html
new file mode 100644
index 0000000000..5a3a71d129
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mean_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mean_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mean__q15_8d.html
new file mode 100644
index 0000000000..e372dc36c0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mean_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mean_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mean__q31_8c.html
new file mode 100644
index 0000000000..baefcb3637
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mean_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mean_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Mean value of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mean__q31_8d.html
new file mode 100644
index 0000000000..ddb1823875
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mean_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mean_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__mean__q7_8c.html
new file mode 100644
index 0000000000..00ec2f4c4e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mean_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mean_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mean__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__mean__q7_8d.html
new file mode 100644
index 0000000000..fa3f52cd1c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mean__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mean_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mean_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__min__f32_8c.html
new file mode 100644
index 0000000000..dd9a7771f5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_min_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_min_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__min__f32_8d.html
new file mode 100644
index 0000000000..2526dd6cb5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_min_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_min_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__min__q15_8c.html
new file mode 100644
index 0000000000..74266185d2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_min_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_min_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__min__q15_8d.html
new file mode 100644
index 0000000000..603fe347f2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_min_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_min_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__min__q31_8c.html
new file mode 100644
index 0000000000..12c5f307a7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_min_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_min_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__min__q31_8d.html
new file mode 100644
index 0000000000..a7b77221a4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_min_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_min_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__min__q7_8c.html
new file mode 100644
index 0000000000..cf67b8d87e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_min_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_min_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Minimum value of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__min__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__min__q7_8d.html
new file mode 100644
index 0000000000..cfe463e185
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__min__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_min_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_min_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__mult__f32_8c.html
new file mode 100644
index 0000000000..e074ca0d69
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mult_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__mult__f32_8d.html
new file mode 100644
index 0000000000..7c17c61a26
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mult_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mult_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__mult__q15_8c.html
new file mode 100644
index 0000000000..4d499affaa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mult_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__mult__q15_8d.html
new file mode 100644
index 0000000000..d589b2d8b5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mult_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mult_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__mult__q31_8c.html
new file mode 100644
index 0000000000..74f80113f3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mult_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__mult__q31_8d.html
new file mode 100644
index 0000000000..26569c49d2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mult_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mult_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__mult__q7_8c.html
new file mode 100644
index 0000000000..e875600b58
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_mult_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_mult_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__mult__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__mult__q7_8d.html
new file mode 100644
index 0000000000..ee7e5f4cfd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__mult__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_mult_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_mult_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__negate__f32_8c.html
new file mode 100644
index 0000000000..7880994bd8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_negate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_negate_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__negate__f32_8d.html
new file mode 100644
index 0000000000..f6c61359e3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_negate_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_negate_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__negate__q15_8c.html
new file mode 100644
index 0000000000..ff0b422244
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_negate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_negate_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__negate__q15_8d.html
new file mode 100644
index 0000000000..0cc431be51
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_negate_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_negate_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__negate__q31_8c.html
new file mode 100644
index 0000000000..13f2149b1c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_negate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_negate_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__negate__q31_8d.html
new file mode 100644
index 0000000000..b4699cf570
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_negate_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_negate_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__negate__q7_8c.html
new file mode 100644
index 0000000000..437a4d5f11
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_negate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_negate_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__negate__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__negate__q7_8d.html
new file mode 100644
index 0000000000..b9ba23b4f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__negate__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_negate_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_negate_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__offset__f32_8c.html
new file mode 100644
index 0000000000..29f6d790f5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_offset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_offset_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__offset__f32_8d.html
new file mode 100644
index 0000000000..7d8adff2ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_offset_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_offset_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__offset__q15_8c.html
new file mode 100644
index 0000000000..9ff4c3ffe9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_offset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_offset_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__offset__q15_8d.html
new file mode 100644
index 0000000000..f77dc301f4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_offset_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_offset_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__offset__q31_8c.html
new file mode 100644
index 0000000000..7c5ad5c313
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_offset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_offset_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__offset__q31_8d.html
new file mode 100644
index 0000000000..635e7bde17
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_offset_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_offset_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__offset__q7_8c.html
new file mode 100644
index 0000000000..2c5b0c9b9c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_offset_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_offset_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__offset__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__offset__q7_8d.html
new file mode 100644
index 0000000000..91c75ff17b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__offset__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_offset_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_offset_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8c.html
new file mode 100644
index 0000000000..e871abda2c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_init_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8d.html
new file mode 100644
index 0000000000..9832138914
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8c.html
new file mode 100644
index 0000000000..b4e8ba53a8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_init_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8d.html
new file mode 100644
index 0000000000..fa6ba276a6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8c.html
new file mode 100644
index 0000000000..94deca7bb0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_init_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8d.html
new file mode 100644
index 0000000000..59c9b7e93d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8c.html
new file mode 100644
index 0000000000..2fb27c39aa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_reset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_reset_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8d.html
new file mode 100644
index 0000000000..cbf2f39afc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_reset_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_reset_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8c.html
new file mode 100644
index 0000000000..932bb82ee4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_reset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_reset_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8d.html
new file mode 100644
index 0000000000..f5bc9fe19c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_reset_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_reset_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8c.html
new file mode 100644
index 0000000000..4d8786024f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_pid_reset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_pid_reset_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8d.html
new file mode 100644
index 0000000000..f7ce37835d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_pid_reset_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_pid_reset_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__power__f32_8c.html
new file mode 100644
index 0000000000..b89eec69f8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_power_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_power_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__power__f32_8d.html
new file mode 100644
index 0000000000..3a05d7bd88
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_power_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_power_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__power__q15_8c.html
new file mode 100644
index 0000000000..b97083ec34
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_power_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_power_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__power__q15_8d.html
new file mode 100644
index 0000000000..986d153206
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_power_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_power_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__power__q31_8c.html
new file mode 100644
index 0000000000..48c39bfeda
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_power_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_power_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__power__q31_8d.html
new file mode 100644
index 0000000000..ad8c0c0a0c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_power_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_power_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__power__q7_8c.html
new file mode 100644
index 0000000000..ba05023c4f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_power_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_power_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__power__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__power__q7_8d.html
new file mode 100644
index 0000000000..7b2e5760c1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__power__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_power_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_power_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__float_8c.html b/CMSIS/Documentation/DSP/html/arm__q15__to__float_8c.html
new file mode 100644
index 0000000000..89c0961bc6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__float_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q15_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q15_to_float.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__float_8d.html b/CMSIS/Documentation/DSP/html/arm__q15__to__float_8d.html
new file mode 100644
index 0000000000..78329a35f6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__float_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q15_to_float.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q15_to_float.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8c.html
new file mode 100644
index 0000000000..8c1570a159
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q15_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q15_to_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8d.html
new file mode 100644
index 0000000000..70caf20336
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q15_to_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q15_to_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8c.html
new file mode 100644
index 0000000000..00b348cfe2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q15_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q15_to_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8d.html
new file mode 100644
index 0000000000..bf839fc36e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q15__to__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q15_to_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q15_to_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__float_8c.html b/CMSIS/Documentation/DSP/html/arm__q31__to__float_8c.html
new file mode 100644
index 0000000000..cf29e64216
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__float_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q31_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q31_to_float.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__float_8d.html b/CMSIS/Documentation/DSP/html/arm__q31__to__float_8d.html
new file mode 100644
index 0000000000..2d07063f01
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__float_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q31_to_float.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q31_to_float.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8c.html
new file mode 100644
index 0000000000..ee57feb4ba
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q31_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q31_to_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8d.html
new file mode 100644
index 0000000000..5ebfe2bbfb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q31_to_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q31_to_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8c.html
new file mode 100644
index 0000000000..2ebb610415
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q31_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q31_to_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8d.html
new file mode 100644
index 0000000000..6fbea5f403
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q31__to__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q31_to_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q31_to_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__float_8c.html b/CMSIS/Documentation/DSP/html/arm__q7__to__float_8c.html
new file mode 100644
index 0000000000..b5fe4eb5b7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__float_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q7_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q7_to_float.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__float_8d.html b/CMSIS/Documentation/DSP/html/arm__q7__to__float_8d.html
new file mode 100644
index 0000000000..92b41aa750
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__float_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q7_to_float.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q7_to_float.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8c.html
new file mode 100644
index 0000000000..81f10c7bb1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q7_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q7_to_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8d.html
new file mode 100644
index 0000000000..02b99aa114
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q7_to_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q7_to_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8c.html
new file mode 100644
index 0000000000..ba3cdf4372
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_q7_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_q7_to_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8d.html
new file mode 100644
index 0000000000..50a5a4b7c9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__q7__to__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_q7_to_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_q7_to_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__f32_8c.html
new file mode 100644
index 0000000000..b8832c94bc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__f32_8c.html
@@ -0,0 +1,275 @@
+
+
+
+
+arm_rfft_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rfft_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_split_rfft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
 Core Real FFT process.  
void arm_split_rifft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
 Core Real IFFT process.  
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pATable, 
float32_t * pBTable, 
float32_t * pDst, 
uint32_t modifier 
)

+

+

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pATable, 
float32_t * pBTable, 
float32_t * pDst, 
uint32_t modifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_rfft_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__f32_8d.html
new file mode 100644
index 0000000000..815b5db68a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8c.html
new file mode 100644
index 0000000000..bcd8817106
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8c.html
@@ -0,0 +1,144 @@
+
+
+
+
+arm_rfft_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_rfft_init_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+

+Variables
static const float32_t realCoefA [8192]
static const float32_t realCoefB [8192]

+Functions
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8d.html
new file mode 100644
index 0000000000..adfa2e087b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_init_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_init_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8c.html
new file mode 100644
index 0000000000..6cf18ffdb8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8c.html
@@ -0,0 +1,144 @@
+
+
+
+
+arm_rfft_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_rfft_init_q15.c File Reference
  

+

+

+
+
+
+
+
+
+
+

+Variables
static const q15_t ALIGN4 realCoefAQ15 [8192]
static const q15_t ALIGN4 realCoefBQ15 [8192]

+Functions
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8d.html
new file mode 100644
index 0000000000..7c2f6ff0cb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_init_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_init_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8c.html
new file mode 100644
index 0000000000..9a9f861c93
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8c.html
@@ -0,0 +1,144 @@
+
+
+
+
+arm_rfft_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_rfft_init_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+

+Variables
static const q31_t realCoefAQ31 [8192]
static const q31_t realCoefBQ31 [8192]

+Functions
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8d.html
new file mode 100644
index 0000000000..b9d4276826
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_init_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_init_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__q15_8c.html
new file mode 100644
index 0000000000..72eeae4e45
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__q15_8c.html
@@ -0,0 +1,279 @@
+
+
+
+
+arm_rfft_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rfft_q15.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_split_rfft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
 Core Real FFT process.  
void arm_split_rifft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
 Core Real IFFT process.  
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pATable, 
q15_t * pBTable, 
q15_t * pDst, 
uint32_t modifier 
)

+

+

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
*pSrcpoints to the input buffer. 
fftLenlength of FFT. 
*pATablepoints to the A twiddle Coef buffer. 
*pBTablepoints to the B twiddle Coef buffer. 
*pDstpoints to the output buffer. 
modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real FFT 

+
+
References __SIMD32.

+
+
Referenced by arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pATable, 
q15_t * pBTable, 
q15_t * pDst, 
uint32_t modifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real IFFT 

+
+
References __SIMD32.

+
+
Referenced by arm_rfft_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__q15_8d.html
new file mode 100644
index 0000000000..dc62931c02
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__rfft__q31_8c.html
new file mode 100644
index 0000000000..9bc99f02c3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__q31_8c.html
@@ -0,0 +1,275 @@
+
+
+
+
+arm_rfft_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rfft_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_split_rfft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
 Core Real FFT process.  
void arm_split_rifft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
 Core Real IFFT process.  
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pATable, 
q31_t * pBTable, 
q31_t * pDst, 
uint32_t modifier 
)

+

+

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pATable, 
q31_t * pBTable, 
q31_t * pDst, 
uint32_t modifier 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Referenced by arm_rfft_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rfft__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__rfft__q31_8d.html
new file mode 100644
index 0000000000..fafee11018
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rfft__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rfft_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rfft_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__rms__f32_8c.html
new file mode 100644
index 0000000000..84646a8f15
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_rms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rms_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__rms__f32_8d.html
new file mode 100644
index 0000000000..a2fde5aeda
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rms_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rms_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__rms__q15_8c.html
new file mode 100644
index 0000000000..6ab5ba8234
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_rms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rms_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__rms__q15_8d.html
new file mode 100644
index 0000000000..147accf95d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rms_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rms_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__rms__q31_8c.html
new file mode 100644
index 0000000000..3e78a049c3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_rms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_rms_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__rms__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__rms__q31_8d.html
new file mode 100644
index 0000000000..02ca722a8c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__rms__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_rms_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_rms_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__scale__f32_8c.html
new file mode 100644
index 0000000000..b40d92c3e9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_scale_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__scale__f32_8d.html
new file mode 100644
index 0000000000..71d0b115af
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_scale_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_scale_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__scale__q15_8c.html
new file mode 100644
index 0000000000..4f104b059b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_scale_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__scale__q15_8d.html
new file mode 100644
index 0000000000..cda051451e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_scale_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_scale_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__scale__q31_8c.html
new file mode 100644
index 0000000000..8dcb327231
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_scale_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__scale__q31_8d.html
new file mode 100644
index 0000000000..3ef08e311a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_scale_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_scale_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__scale__q7_8c.html
new file mode 100644
index 0000000000..02b82e5f9f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_scale_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_scale_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__scale__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__scale__q7_8d.html
new file mode 100644
index 0000000000..e51bd68093
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__scale__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_scale_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_scale_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__shift__q15_8c.html
new file mode 100644
index 0000000000..0771cbf6a7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_shift_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_shift_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__shift__q15_8d.html
new file mode 100644
index 0000000000..1e1c42c02f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_shift_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_shift_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__shift__q31_8c.html
new file mode 100644
index 0000000000..2434c3d87a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_shift_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_shift_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__shift__q31_8d.html
new file mode 100644
index 0000000000..8219971f6d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_shift_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_shift_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__shift__q7_8c.html
new file mode 100644
index 0000000000..746025426a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_shift_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_shift_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__shift__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__shift__q7_8d.html
new file mode 100644
index 0000000000..bb93eec4ff
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__shift__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_shift_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_shift_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__signal__converge__data_8c.html b/CMSIS/Documentation/DSP/html/arm__signal__converge__data_8c.html
new file mode 100644
index 0000000000..1e160e09e1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__signal__converge__data_8c.html
@@ -0,0 +1,186 @@
+
+
+
+
+arm_signal_converge_data.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
arm_signal_converge_data.c File Reference
  

+

+

+
+
+
+
+
+

+Variables
float32_t testInput_f32 [1536]
float32_t lmsNormCoeff_f32 [32]
const float32_t FIRCoeff_f32 [32]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t FIRCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsNormCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[1536]

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__signal__converge__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__signal__converge__example__f32_8c.html
new file mode 100644
index 0000000000..60b511b895
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__signal__converge__example__f32_8c.html
@@ -0,0 +1,559 @@
+
+
+
+
+arm_signal_converge_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_signal_converge_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES
#define NUMTAPS
#define BLOCKSIZE
#define DELTA_ERROR
#define DELTA_COEFF
#define MU
#define NUMFRAMES

+Variables
float32_t firStateF32 [NUMTAPS+BLOCKSIZE]
arm_fir_instance_f32 LPF_instance
float32_t lmsStateF32 [NUMTAPS+BLOCKSIZE]
float32_t errOutput [TEST_LENGTH_SAMPLES]
arm_lms_norm_instance_f32 lmsNorm_instance
float32_t testInput_f32 [TEST_LENGTH_SAMPLES]
float32_t lmsNormCoeff_f32 [32]
const float32_t FIRCoeff_f32 [32]
float32_t wire1 [BLOCKSIZE]
float32_t wire2 [BLOCKSIZE]
float32_t wire3 [BLOCKSIZE]
float32_t err_signal [BLOCKSIZE]

+Functions
arm_status test_signal_converge_example (void)
arm_status test_signal_converge (float32_t *err_signal, uint32_t blockSize)
void getinput (float32_t *input, uint32_t fr_cnt, uint32_t blockSize)
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define BLOCKSIZE

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_COEFF

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_ERROR

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MU

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMFRAMES

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMTAPS

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t err_signal[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t errOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t FIRCoeff_f32[32]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_lms_norm_instance_f32 lmsNorm_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsNormCoeff_f32[32]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_fir_instance_f32 LPF_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TEST_LENGTH_SAMPLES]

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void getinput (float32_t * input, 
uint32_t fr_cnt, 
uint32_t blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_abs_f32(), arm_copy_f32(), arm_fir_f32(), arm_fir_init_f32(), arm_lms_norm_f32(), arm_lms_norm_init_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_min_f32(), arm_scale_f32(), arm_sub_f32(), BLOCKSIZE, DELTA_COEFF, DELTA_ERROR, err_signal, FIRCoeff_f32, firStateF32, lmsNormCoeff_f32, lmsStateF32, MU, NUMFRAMES, NUMTAPS, status, testInput_f32, wire1, wire2, and wire3.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status test_signal_converge (float32_t * err_signal, 
uint32_t blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
arm_status test_signal_converge_example (void )

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__cos__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__cos__example__f32_8c.html
new file mode 100644
index 0000000000..d8e8352607
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__cos__example__f32_8c.html
@@ -0,0 +1,334 @@
+
+
+
+
+arm_sin_cos_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_sin_cos_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE
#define DELTA

+Variables
const float32_t testInput_f32 [MAX_BLOCKSIZE]
const float32_t testRefOutput_f32
uint32_t blockSize
float32_t testOutput
float32_t cosOutput
float32_t sinOutput
float32_t cosSquareOutput
float32_t sinSquareOutput
arm_status status

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define DELTA

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testInput_f32[MAX_BLOCKSIZE]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testRefOutput_f32

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_add_f32(), arm_cos_f32(), ARM_MATH_TEST_FAILURE, arm_mult_f32(), arm_sin_f32(), blockSize, cosOutput, cosSquareOutput, DELTA, sinOutput, sinSquareOutput, status, testInput_f32, testOutput, and testRefOutput_f32.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8c.html
new file mode 100644
index 0000000000..dcd5243efb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8c.html
@@ -0,0 +1,144 @@
+
+
+
+
+arm_sin_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_sin_cos_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
 Floating-point sin_cos function.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8d.html
new file mode 100644
index 0000000000..cdc5d79916
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sin_cos_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_cos_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8c.html
new file mode 100644
index 0000000000..beeae4e8df
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8c.html
@@ -0,0 +1,144 @@
+
+
+
+
+arm_sin_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_sin_cos_q31.c File Reference
  

+

+

+
+
+
+
+
+
+
+

+Variables
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+Functions
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8d.html
new file mode 100644
index 0000000000..6b683df747
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sin_cos_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_cos_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__f32_8c.html
new file mode 100644
index 0000000000..32879d1082
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__f32_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_sin_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_sin_f32.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const float32_t sinTable [259]

+Functions
float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__sin__f32_8d.html
new file mode 100644
index 0000000000..d3a536c6a5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sin_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__q15_8c.html
new file mode 100644
index 0000000000..29902f7791
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__q15_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_sin_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_sin_q15.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const q15_t sinTableQ15 [259]

+Functions
q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__sin__q15_8d.html
new file mode 100644
index 0000000000..7b22c43fc3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sin_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__sin__q31_8c.html
new file mode 100644
index 0000000000..76f0e82178
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__q31_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+arm_sin_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
arm_sin_q31.c File Reference
  

+

+

+
+
+
+
+
+
+

+Variables
static const q31_t sinTableQ31 [259]

+Functions
q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sin__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__sin__q31_8d.html
new file mode 100644
index 0000000000..aa5df5e7e3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sin__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sin_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8c.html
new file mode 100644
index 0000000000..b2e0e2544f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sqrt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sqrt_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8d.html
new file mode 100644
index 0000000000..e1b83d3969
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sqrt_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sqrt_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8c.html
new file mode 100644
index 0000000000..6b993c49a0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sqrt_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sqrt_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8d.html
new file mode 100644
index 0000000000..198d421a60
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sqrt__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sqrt_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sqrt_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__std__f32_8c.html
new file mode 100644
index 0000000000..25761b269e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_std_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_std_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__std__f32_8d.html
new file mode 100644
index 0000000000..31defbbedb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_std_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_std_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__std__q15_8c.html
new file mode 100644
index 0000000000..c227f9ea7d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_std_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_std_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__std__q15_8d.html
new file mode 100644
index 0000000000..1f13bb66cd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_std_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_std_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__std__q31_8c.html
new file mode 100644
index 0000000000..a65c77dadd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_std_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_std_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__std__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__std__q31_8d.html
new file mode 100644
index 0000000000..9abfb6b001
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__std__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_std_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_std_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__sub__f32_8c.html
new file mode 100644
index 0000000000..46c9c37d2f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sub_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__sub__f32_8d.html
new file mode 100644
index 0000000000..2e6d2ad0a9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sub_f32.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sub_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__sub__q15_8c.html
new file mode 100644
index 0000000000..73c53d2bc0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sub_q15.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sub_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__sub__q15_8d.html
new file mode 100644
index 0000000000..4536f12460
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q15_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sub_q15.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sub_q15.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__sub__q31_8c.html
new file mode 100644
index 0000000000..f93df485e3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sub_q31.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sub_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__sub__q31_8d.html
new file mode 100644
index 0000000000..19531b0e9c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sub_q31.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sub_q31.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q7_8c.html b/CMSIS/Documentation/DSP/html/arm__sub__q7_8c.html
new file mode 100644
index 0000000000..c73c6fb7d4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q7_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_sub_q7.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_sub_q7.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__sub__q7_8d.html b/CMSIS/Documentation/DSP/html/arm__sub__q7_8d.html
new file mode 100644
index 0000000000..fe39fcbf97
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__sub__q7_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_sub_q7.d File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sub_q7.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__var__f32_8c.html
new file mode 100644
index 0000000000..cf5a5a679b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__f32_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_var_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_var_f32.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__f32_8d.html b/CMSIS/Documentation/DSP/html/arm__var__f32_8d.html
new file mode 100644
index 0000000000..25035b641f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__f32_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_var_f32.d File Reference
+
+
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_var_f32.d File Reference
  

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__q15_8c.html b/CMSIS/Documentation/DSP/html/arm__var__q15_8c.html
new file mode 100644
index 0000000000..b2817d1f49
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__q15_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_var_q15.c File Reference
+
+
+
+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_var_q15.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__q15_8d.html b/CMSIS/Documentation/DSP/html/arm__var__q15_8d.html
new file mode 100644
index 0000000000..42e1c6eb83
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__q15_8d.html
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+
+
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+
+arm_var_q15.d File Reference
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_var_q15.d File Reference
  

+

+

+

+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__q31_8c.html b/CMSIS/Documentation/DSP/html/arm__var__q31_8c.html
new file mode 100644
index 0000000000..be4efcef3b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__q31_8c.html
@@ -0,0 +1,139 @@
+
+
+
+
+arm_var_q31.c File Reference
+
+
+
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+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
arm_var_q31.c File Reference
  

+

+

+
+
+
+
+

+Functions
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm__var__q31_8d.html b/CMSIS/Documentation/DSP/html/arm__var__q31_8d.html
new file mode 100644
index 0000000000..e12a1cd9c6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__var__q31_8d.html
@@ -0,0 +1,131 @@
+
+
+
+
+arm_var_q31.d File Reference
+
+
+
+
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+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_var_q31.d File Reference
  

+

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+  
+
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+
diff --git a/CMSIS/Documentation/DSP/html/arm__variance__example__f32_8c.html b/CMSIS/Documentation/DSP/html/arm__variance__example__f32_8c.html
new file mode 100644
index 0000000000..737b94e9e2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm__variance__example__f32_8c.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_variance_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
arm_variance_example_f32.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE
#define DELTA

+Variables
float32_t wire1 [MAX_BLOCKSIZE]
float32_t wire2 [MAX_BLOCKSIZE]
float32_t wire3 [MAX_BLOCKSIZE]
float32_t testInput_f32 [32]
uint32_t blockSize
float32_t refVarianceOut

+Functions
int32_t main (void)

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define DELTA

+

+

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refVarianceOut

+

+

+
Examples: 
arm_variance_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[32]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[MAX_BLOCKSIZE]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[MAX_BLOCKSIZE]

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[MAX_BLOCKSIZE]

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void )

+

+

+
+
References arm_copy_f32(), arm_dot_prod_f32(), arm_fill_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_mult_f32(), arm_sub_f32(), blockSize, DELTA, mean, refVarianceOut, status, testInput_f32, wire1, wire2, and wire3.

+
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+

+

+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_class_marks_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_class_marks_example_f32_8c-example.html
new file mode 100644
index 0000000000..5ffb7065c8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_class_marks_example_f32_8c-example.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_class_marks_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_class_marks_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:          CMSIS DSP Library  
+* Title:        arm_class_marks_example_f32.c             
+*  
+* Description:  Example code to calculate Minimum, Maximum 
+*               Mean, std and variance of marks obtained in a class 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+*  
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define USE_STATIC_INIT 
+ 
+ /* ---------------------------------------------------------------------- 
+** Global defines  
+** ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES     (20*4) 
+ 
+/* ---------------------------------------------------------------------- 
+** List of Marks scored by 20 students for 4 subjects 
+** ------------------------------------------------------------------- */  
+const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =  
+{    
+        42.000000,      37.000000,      81.000000,      28.000000,       
+        83.000000,      72.000000,      36.000000,      38.000000,       
+        32.000000,      51.000000,      63.000000,      64.000000,       
+        97.000000,      82.000000,      95.000000,      90.000000,       
+        66.000000,      51.000000,      54.000000,      42.000000,       
+        67.000000,      56.000000,      45.000000,      57.000000,       
+        67.000000,      69.000000,      35.000000,      52.000000,       
+        29.000000,      81.000000,      58.000000,      47.000000,       
+        38.000000,      76.000000,      100.000000,     29.000000,       
+        33.000000,      47.000000,      29.000000,      50.000000,       
+        34.000000,      41.000000,      61.000000,      46.000000,       
+        52.000000,      50.000000,      48.000000,      36.000000,       
+        47.000000,      55.000000,      44.000000,      40.000000,       
+        100.000000,     94.000000,      84.000000,      37.000000,       
+        32.000000,      71.000000,      47.000000,      77.000000,       
+        31.000000,      50.000000,      49.000000,      35.000000,       
+        63.000000,      67.000000,      40.000000,      31.000000,       
+        29.000000,      68.000000,      61.000000,      38.000000,       
+        31.000000,      28.000000,      28.000000,      76.000000,       
+        55.000000,      33.000000,      29.000000,      39.000000 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Number of subjects X 1  
+* ------------------------------------------------------------------- */  
+const float32_t testUnity_f32[4] =  
+{    
+        1.000,  1.000,  1.000,  1.000 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+** f32 Output buffer 
+** ------------------------------------------------------------------- */  
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+ 
+/* ------------------------------------------------------------------ 
+* Global defines  
+*------------------------------------------------------------------- */ 
+#define         NUMSTUDENTS  20 
+#define     NUMSUBJECTS  4 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables  
+*------------------------------------------------------------------- */ 
+ 
+uint32_t        numStudents = 20; 
+uint32_t        numSubjects = 4;  
+float32_t       max_marks, min_marks, mean, std, var; 
+uint32_t        student_num;    
+ 
+/* ---------------------------------------------------------------------------------- 
+* Main f32 test function.  It returns maximum marks secured and student number 
+* ------------------------------------------------------------------------------- */ 
+ 
+int32_t main() 
+{ 
+ 
+#ifndef  USE_STATIC_INIT 
+ 
+        arm_matrix_instance_f32 srcA; 
+        arm_matrix_instance_f32 srcB; 
+        arm_matrix_instance_f32 dstC;  
+ 
+        /* Input and output matrices initializations */  
+        arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);  
+        arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);  
+        arm_mat_init_f32(&dstC, numStudents, 1, testOutput);  
+ 
+#else 
+ 
+        /* Static Initializations of Input and output matrix sizes and array */ 
+        arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; 
+        arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; 
+        arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; 
+ 
+#endif 
+ 
+         
+        /* ---------------------------------------------------------------------- 
+        *Call the Matrix multiplication process function   
+        * ------------------------------------------------------------------- */ 
+        arm_mat_mult_f32(&srcA, &srcB, &dstC); 
+         
+        /* ---------------------------------------------------------------------- 
+        ** Call the Max function to calculate max marks among numStudents 
+        ** ------------------------------------------------------------------- */ 
+        arm_max_f32(testOutput, numStudents, &max_marks, &student_num);  
+ 
+        /* ---------------------------------------------------------------------- 
+        ** Call the Min function to calculate min marks among numStudents 
+        ** ------------------------------------------------------------------- */ 
+        arm_min_f32(testOutput, numStudents, &min_marks, &student_num);  
+ 
+        /* ---------------------------------------------------------------------- 
+        ** Call the Mean function to calculate mean 
+        ** ------------------------------------------------------------------- */ 
+        arm_mean_f32(testOutput, numStudents, &mean); 
+ 
+        /* ---------------------------------------------------------------------- 
+        ** Call the std function to calculate standard deviation 
+        ** ------------------------------------------------------------------- */ 
+        arm_std_f32(testOutput, numStudents, &std); 
+ 
+        /* ---------------------------------------------------------------------- 
+        ** Call the var function to calculate variance 
+        ** ------------------------------------------------------------------- */ 
+        arm_var_f32(testOutput, numStudents, &var); 
+ 
+    while(1);                             /* main function does not return */
+} 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_convolution_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_convolution_example_f32_8c-example.html
new file mode 100644
index 0000000000..e368eb600e
--- /dev/null
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@@ -0,0 +1,297 @@
+
+
+
+
+arm_convolution_example_f32.c
+
+
+
+
+
+
+
+
+
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+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_convolution_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_convolution_example_f32.c                 
+*  
+* Description:  Example code demonstrating Convolution of two input signals using fft. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"                                 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   128 
+#define DELTA           (0.000001f) 
+#define SNR_THRESHOLD   90 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+float32_t Ak[MAX_BLOCKSIZE];            /* Input A */ 
+float32_t Bk[MAX_BLOCKSIZE];            /* Input B */ 
+float32_t AxB[MAX_BLOCKSIZE * 2];       /* Output */ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Convolution example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+float32_t testInputA_f32[64] =  
+{  
+-0.808920,      1.357369,       1.180861,       -0.504544,      1.762637,       -0.703285,       
+1.696966,       0.620571,       -0.151093,      -0.100235,      -0.872382,      -0.403579,       
+-0.860749,      -0.382648,      -1.052338,      0.128113,       -0.646269,      1.093377,        
+-2.209198,      0.471706,       0.408901,       1.266242,       0.598252,       1.176827,        
+-0.203421,      0.213596,       -0.851964,      -0.466958,      0.021841,       -0.698938,       
+-0.604107,      0.461778,       -0.318219,      0.942520,       0.577585,       0.417619,        
+0.614665,       0.563679,       -1.295073,      -0.764437,      0.952194,       -0.859222,       
+-0.618554,      -2.268542,      -1.210592,      1.655853,       -2.627219,      -0.994249,       
+-1.374704,      0.343799,       0.025619,       1.227481,       -0.708031,      0.069355,        
+-1.845228,      -1.570886,      1.010668,       -1.802084,      1.630088,       1.286090,        
+-0.161050,      -0.940794,      0.367961,       0.291907 
+                 
+};  
+  
+float32_t testInputB_f32[64] =  
+{  
+0.933724,       0.046881,       1.316470,       0.438345,       0.332682,       2.094885,        
+0.512081,       0.035546,       0.050894,       -2.320371,      0.168711,       -1.830493,       
+-0.444834,      -1.003242,      -0.531494,      -1.365600,      -0.155420,      -0.757692,       
+-0.431880,      -0.380021,      0.096243,       -0.695835,      0.558850,       -1.648962,       
+0.020369,       -0.363630,      0.887146,       0.845503,       -0.252864,      -0.330397,       
+1.269131,       -1.109295,      -1.027876,      0.135940,       0.116721,       -0.293399,       
+-1.349799,      0.166078,       -0.802201,      0.369367,       -0.964568,      -2.266011,       
+0.465178,       0.651222,       -0.325426,      0.320245,       -0.784178,      -0.579456,       
+0.093374,       0.604778,       -0.048225,      0.376297,       -0.394412,      0.578182,        
+-1.218141,      -1.387326,      0.692462,       -0.631297,      0.153137,       -0.638952,       
+0.635474,       -0.970468,      1.334057,       -0.111370 
+};  
+  
+const float testRefOutput_f32[126] =   
+{  
+-0.818943,      1.229484,       -0.533664,      1.016604,       0.341875,       -1.963656,       
+5.171476,       3.478033,       7.616361,       6.648384,       0.479069,       1.792012,        
+-1.295591,      -7.447818,      0.315830,       -10.657445,     -2.483469,      -6.524236,       
+-7.380591,      -3.739005,      -8.388957,      0.184147,       -1.554888,      3.786508,        
+-1.684421,      5.400610,       -1.578126,      7.403361,       8.315999,       2.080267,        
+11.077776,      2.749673,       7.138962,       2.748762,       0.660363,       0.981552,        
+1.442275,       0.552721,       -2.576892,      4.703989,       0.989156,       8.759344,        
+-0.564825,      -3.994680,      0.954710,       -5.014144,      6.592329,       1.599488,        
+-13.979146,     -0.391891,      -4.453369,      -2.311242,      -2.948764,      1.761415,        
+-0.138322,      10.433007,      -2.309103,      4.297153,       8.535523,       3.209462,        
+8.695819,       5.569919,       2.514304,       5.582029,       2.060199,       0.642280,        
+7.024616,       1.686615,       -6.481756,      1.343084,       -3.526451,      1.099073,        
+-2.965764,      -0.173723,      -4.111484,      6.528384,       -6.965658,      1.726291,        
+1.535172,       11.023435,      2.338401,       -4.690188,      1.298210,       3.943885,        
+8.407885,       5.168365,       0.684131,       1.559181,       1.859998,       2.852417,        
+8.574070,       -6.369078,      6.023458,       11.837963,      -6.027632,      4.469678,        
+-6.799093,      -2.674048,      6.250367,       -6.809971,      -3.459360,      9.112410,        
+-2.711621,      -1.336678,      1.564249,       -1.564297,      -1.296760,      8.904013,        
+-3.230109,      6.878013,       -7.819823,      3.369909,       -1.657410,      -2.007358,       
+-4.112825,      1.370685,       -3.420525,      -6.276605,      3.244873,       -3.352638,       
+1.545372,       0.902211,       0.197489,       -1.408732,      0.523390,       0.348440 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t srcALen = 64;   /* Length of Input A */ 
+uint32_t srcBLen = 64;   /* Length of Input B */ 
+uint32_t outLen;                 /* Length of convolution output */ 
+float32_t snr;                   /* output SNR */ 
+ 
+int32_t main(void) 
+{ 
+        arm_status status;         /* Status of the example */ 
+        arm_cfft_radix4_instance_f32 cfft_instance;     /* CFFT Structure instance */ 
+ 
+        /* CFFT Structure instance pointer */ 
+    arm_cfft_radix4_instance_f32 *cfft_instance_ptr =  
+                        (arm_cfft_radix4_instance_f32*) &cfft_instance; 
+ 
+        /* output length of convolution */ 
+        outLen = srcALen + srcBLen - 1; 
+ 
+        /* Initialise the fft input buffers with all zeros */ 
+        arm_fill_f32(0.0,  Ak, MAX_BLOCKSIZE); 
+        arm_fill_f32(0.0,  Bk, MAX_BLOCKSIZE); 
+ 
+        /* Copy the input values to the fft input buffers */ 
+        arm_copy_f32(testInputA_f32,  Ak, MAX_BLOCKSIZE/2); 
+        arm_copy_f32(testInputB_f32,  Bk, MAX_BLOCKSIZE/2); 
+         
+        /* Initialize the CFFT function to compute 64 point fft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); 
+ 
+        /* Transform input a[n] from time domain to frequency domain A[k] */ 
+        arm_cfft_radix4_f32(cfft_instance_ptr, Ak); 
+        /* Transform input b[n] from time domain to frequency domain B[k] */ 
+        arm_cfft_radix4_f32(cfft_instance_ptr, Bk); 
+         
+        /* Complex Multiplication of the two input buffers in frequency domain */ 
+        arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);  
+ 
+    /* Initialize the CIFFT function to compute 64 point ifft */  
+        status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); 
+ 
+        /* Transform the multiplication output from frequency domain to time domain, 
+           that gives the convolved output  */ 
+        arm_cfft_radix4_f32(cfft_instance_ptr, AxB); 
+ 
+        /* SNR Calculation */ 
+        snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); 
+         
+        /* Compare the SNR with threshold to test whether the  
+           computed output is matched with the reference output values. */ 
+        if( snr > SNR_THRESHOLD) 
+        { 
+                status = ARM_MATH_SUCCESS; 
+        } 
+                 
+        if( status != ARM_MATH_SUCCESS) 
+        { 
+          while(1); 
+        } 
+
+    while(1);                             /* main function does not return */
+} 
+                                                                  
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_dotproduct_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_dotproduct_example_f32_8c-example.html
new file mode 100644
index 0000000000..85701e870a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_dotproduct_example_f32_8c-example.html
@@ -0,0 +1,247 @@
+
+
+
+
+arm_dotproduct_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_dotproduct_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_dotproduct_example_f32.c                  
+*  
+* Description:  Example code computing dot product of two vectors. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Dot Product example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */  
+/* ----------------------------------------------------------------------  
+** Test input data of srcA for blockSize 32   
+** ------------------------------------------------------------------- */  
+float32_t srcA_buf_f32[MAX_BLOCKSIZE] =   
+{   
+-0.4325648115282207,    -1.6655843782380970,    0.1253323064748307,      
+ 0.2876764203585489,    -1.1464713506814637,    1.1909154656429988,      
+ 1.1891642016521031,    -0.0376332765933176,    0.3272923614086541,      
+ 0.1746391428209245,    -0.1867085776814394,    0.7257905482933027,      
+-0.5883165430141887,     2.1831858181971011,   -0.1363958830865957,      
+ 0.1139313135208096,     1.0667682113591888,    0.0592814605236053,      
+-0.0956484054836690,    -0.8323494636500225,    0.2944108163926404,      
+-1.3361818579378040,     0.7143245518189522,    1.6235620644462707,      
+-0.6917757017022868,     0.8579966728282626,    1.2540014216025324,      
+-1.5937295764474768,    -1.4409644319010200,    0.5711476236581780,      
+-0.3998855777153632,     0.6899973754643451 
+};   
+  
+/* ----------------------------------------------------------------------  
+** Test input data of srcB for blockSize 32   
+** ------------------------------------------------------------------- */   
+float32_t srcB_buf_f32[MAX_BLOCKSIZE] =   
+{   
+ 1.7491401329284098,    0.1325982188803279,      0.3252281811989881,     
+-0.7938091410349637,    0.3149236145048914,     -0.5272704888029532,     
+ 0.9322666565031119,    1.1646643544607362,     -2.0456694357357357,     
+-0.6443728590041911,    1.7410657940825480,      0.4867684246821860,     
+ 1.0488288293660140,    1.4885752747099299,      1.2705014969484090,     
+-1.8561241921210170,    2.1343209047321410,  1.4358467535865909,         
+-0.9173023332875400,   -1.1060770780029008,      0.8105708062681296,     
+ 0.6985430696369063,   -0.4015827425012831,      1.2687512030669628,     
+-0.7836083053674872,    0.2132664971465569,      0.7878984786088954,     
+ 0.8966819356782295,   -0.1869172943544062,      1.0131816724341454,     
+ 0.2484350696132857,    0.0596083377937976 
+};   
+ 
+/* Reference dot product output */ 
+float32_t  refDotProdOut = 5.9273644806352142;   
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+float32_t multOutput[MAX_BLOCKSIZE];  /* Intermediate output */ 
+float32_t testOutput;  /* Final ouput */ 
+ 
+arm_status status;       /* Status of the example */ 
+
+int32_t main(void) 
+{ 
+        uint32_t i;                      /* Loop counter */ 
+        float32_t diff;          /* Difference between reference and test outputs */ 
+ 
+        /* Multiplication of two input buffers */ 
+        arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); 
+         
+        /* Accumulate the multiplication output values to  
+           get the dot product of the two inputs */ 
+        for(i=0; i< MAX_BLOCKSIZE; i++) 
+    {          
+                arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);        
+    } 
+ 
+        /* absolute value of difference between ref and test */ 
+        diff = fabsf(refDotProdOut - testOutput); 
+         
+        /* Comparison of dot product value with reference */ 
+        if(diff > DELTA) 
+        { 
+                status = ARM_MATH_TEST_FAILURE; 
+        } 
+                 
+        if( status == ARM_MATH_TEST_FAILURE) 
+        { 
+          while(1); 
+        } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_fft_bin_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_fft_bin_example_f32_8c-example.html
new file mode 100644
index 0000000000..4b2f2f8e9b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_fft_bin_example_f32_8c-example.html
@@ -0,0 +1,223 @@
+
+
+
+
+arm_fft_bin_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fft_bin_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3  
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_fft_bin_example_f32.c             
+*  
+* Description:  Example code demonstrating calculation of Max energy bin of  
+*                               frequency domain of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define TEST_LENGTH_SAMPLES 2048 
+ 
+/* ------------------------------------------------------------------- 
+* External Input and Output buffer Declarations for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; 
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+uint32_t fftSize = 1024; 
+uint32_t ifftFlag = 0; 
+uint32_t doBitReverse = 1; 
+ 
+/* Reference index at which max energy of bin ocuurs */ 
+uint32_t refIndex = 213, testIndex = 0; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+   
+        arm_status status; 
+        arm_cfft_radix4_instance_f32 S; 
+        float32_t maxValue; 
+         
+        status = ARM_MATH_SUCCESS; 
+         
+        /* Initialize the CFFT/CIFFT module */  
+        status = arm_cfft_radix4_init_f32(&S, fftSize,  
+                                                                        ifftFlag, doBitReverse); 
+         
+        /* Process the data through the CFFT/CIFFT module */ 
+        arm_cfft_radix4_f32(&S, testInput_f32_10khz); 
+         
+         
+        /* Process the data through the Complex Magnitude Module for  
+        calculating the magnitude at each bin */ 
+        arm_cmplx_mag_f32(testInput_f32_10khz, testOutput,  
+                                        fftSize);  
+         
+        /* Calculates maxValue and returns corresponding BIN value */ 
+        arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); 
+         
+        if(testIndex !=  refIndex) 
+        { 
+                status = ARM_MATH_TEST_FAILURE; 
+        } 
+         
+        /* ---------------------------------------------------------------------- 
+        ** Loop here if the signals fail the PASS check. 
+        ** This denotes a test failure 
+        ** ------------------------------------------------------------------- */ 
+         
+        if( status != ARM_MATH_SUCCESS) 
+        { 
+                while(1); 
+        } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_fir_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_fir_example_f32_8c-example.html
new file mode 100644
index 0000000000..cb7c1d97b5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_fir_example_f32_8c-example.html
@@ -0,0 +1,268 @@
+
+
+
+
+arm_fir_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_fir_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *  
+ * $Date:           29. November 2010  
+ * $Revision:       V1.0.3  
+ *  
+ * Project:         CMSIS DSP Library  
+ * Title:               arm_fir_example_f32.c             
+ *  
+ * Description: Example code demonstrating how an FIR filter can be used
+ *               as a low pass filter.
+ * 
+ * Target Processor: Cortex-M4/Cortex-M3  
+ *
+ *
+ * Version 1.0.3 2010/11/29 
+ *    Re-organized the CMSIS folders and updated documentation. 
+ * 
+ * Version 1.0.1 2010/10/05 KK 
+ *    Production release and review comments incorporated.  
+ *
+ * Version 1.0.0 2010/09/20 KK
+ *    Production release and review comments incorporated.
+ * ------------------------------------------------------------------- */ 
+ 
+/* ---------------------------------------------------------------------- 
+** Include Files  
+** ------------------------------------------------------------------- */ 
+
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Macro Defines  
+** ------------------------------------------------------------------- */ 
+
+#define TEST_LENGTH_SAMPLES 320 
+#define SNR_THRESHOLD_F32       140.0f 
+#define BLOCK_SIZE                      32 
+#define NUM_TAPS                        29 
+ 
+/* ------------------------------------------------------------------- 
+ * The input signal and reference output (computed with MATLAB)
+ * are defined externally in arm_fir_lpf_data.c.
+ * ------------------------------------------------------------------- */ 
+
+extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; 
+extern float32_t refOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare Test output buffer 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare State buffer of size (numTaps + blockSize - 1) 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; 
+ 
+/* ---------------------------------------------------------------------- 
+** FIR Coefficients buffer generated using fir1() MATLAB function. 
+** fir1(28, 6/24)
+** ------------------------------------------------------------------- */ 
+ 
+const float32_t firCoeffs32[NUM_TAPS] = { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}; 
+ 
+/* ------------------------------------------------------------------ 
+ * Global variables for FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+
+uint32_t blockSize = BLOCK_SIZE; 
+uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; 
+ 
+float32_t  snr; 
+ 
+/* ---------------------------------------------------------------------- 
+ * FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_fir_instance_f32 S; 
+  arm_status status; 
+  float32_t  *inputF32, *outputF32; 
+ 
+  /* Initialize input and output buffer pointers */ 
+  inputF32 = &testInput_f32_1kHz_15kHz[0];       
+  outputF32 = &testOutput[0]; 
+
+  /* Call FIR init function to initialize the instance structure. */
+  arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Call the FIR process function for every blockSize samples  
+  ** ------------------------------------------------------------------- */ 
+
+  for(i=0; i < numBlocks; i++)  
+    {    
+      arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);  
+    } 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Compare the generated output against the reference output computed
+  ** in MATLAB.
+  ** ------------------------------------------------------------------- */ 
+
+  snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); 
+ 
+  if (snr < SNR_THRESHOLD_F32) 
+    { 
+      status = ARM_MATH_TEST_FAILURE; 
+    } 
+  else
+    {
+      status = ARM_MATH_SUCCESS; 
+    }
+         
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+         
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_graphic_equalizer_example_q31_8c-example.html b/CMSIS/Documentation/DSP/html/arm_graphic_equalizer_example_q31_8c-example.html
new file mode 100644
index 0000000000..2ec867a568
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_graphic_equalizer_example_q31_8c-example.html
@@ -0,0 +1,435 @@
+
+
+
+
+arm_graphic_equalizer_example_q31.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_graphic_equalizer_example_q31.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:         29. November 2010  
+* $Revision:      V1.0.3 
+*  
+* Project:        CMSIS DSP Library  
+* Title:              arm_graphic_equalizer_example_q31.c                 
+*  
+* Description:  Example showing an audio graphic equalizer constructed
+*              out of Biquad filters.
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"
+
+/* Length of the overall data in the test */ 
+#define TESTLENGTH 320
+
+/* Block size for the underlying processing */
+#define BLOCKSIZE 32
+
+/* Total number of blocks to run */
+#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
+
+/* Number of 2nd order Biquad stages per filter */
+#define NUMSTAGES 2
+
+#define SNR_THRESHOLD_F32  98
+ 
+/* ------------------------------------------------------------------- 
+ * External Declarations for Input and Output buffers 
+ * ------------------------------------------------------------------- */
+ 
+extern float32_t testInput_f32[TESTLENGTH]; 
+static float32_t testOutput[TESTLENGTH]; 
+
+extern float32_t testRefOutput_f32[TESTLENGTH];
+
+/* ----------------------------------------------------------------------  
+** Q31 state buffers for Band1, Band2, Band3, Band4, Band5  
+** ------------------------------------------------------------------- */  
+   
+static q63_t biquadStateBand1Q31[4 * 2];   
+static q63_t biquadStateBand2Q31[4 * 2];   
+static q31_t biquadStateBand3Q31[4 * 2];   
+static q31_t biquadStateBand4Q31[4 * 2];   
+static q31_t biquadStateBand5Q31[4 * 2];   
+ 
+/* ----------------------------------------------------------------------  
+** Q31 input and output buffers  
+** ------------------------------------------------------------------- */  
+
+q31_t inputQ31[BLOCKSIZE];   
+q31_t outputQ31[BLOCKSIZE];  
+ 
+/* ----------------------------------------------------------------------
+** Entire coefficient table.  There are 10 coefficients per 4th order Biquad
+** cascade filter.  The first 10 coefficients correspond to the -9 dB gain
+** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
+** setting of band 1; and so on.  There are 10*19=190 coefficients in total
+** for band 1 (gains = -9, -8, -7, ..., 9).  After this come the 190 coefficients
+** for band 2.
+**
+** The coefficients are in Q29 format and require a postShift of 2.
+** ------------------------------------------------------------------- */
+
+const q31_t coeffTable[950] = {
+
+        /* Band 1, -9 dB gain */
+        535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, 
+        /* Band 1, -8 dB gain */
+        535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, 
+        535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, 
+        536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, 
+        536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, 
+        536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, 
+        536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, 
+        536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, 
+        536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, 
+        536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, 
+        537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, 
+        537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, 
+        537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, 
+        537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, 
+        537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, 
+        537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, 
+        537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, 
+        538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, 
+        538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, 
+        
+        /* Band 2, -9 dB gain */
+        531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
+        /* Band 2, -8 dB gain */ 
+        532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, 
+        532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, 
+        533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, 
+        534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, 
+        534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, 
+        535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, 
+        535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, 
+        536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, 
+        536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, 
+        537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, 
+        537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, 
+        538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, 
+        539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, 
+        539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, 
+        540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, 
+        540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, 
+        541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, 
+        542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, 
+        518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, 
+        520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, 
+        522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, 
+        524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, 
+        526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, 
+        528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, 
+        530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, 
+        532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, 
+        534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, 
+        536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, 
+        538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, 
+        540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, 
+        542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, 
+        544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, 
+        547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, 
+        549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, 
+        551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, 
+        553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, 
+        555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, 
+        494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, 
+        498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, 
+        503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, 
+        508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, 
+        512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, 
+        517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, 
+        522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, 
+        527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, 
+        531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, 
+        536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, 
+        541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, 
+        546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, 
+        551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, 
+        556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, 
+        562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, 
+        567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, 
+        572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, 
+        577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, 
+        583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, 
+        387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, 
+        401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, 
+        416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, 
+        431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, 
+        447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, 
+        464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, 
+        481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, 
+        499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, 
+        517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, 
+        536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, 
+        556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, 
+        577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, 
+        598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, 
+        620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, 
+        643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, 
+        667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, 
+        692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, 
+        717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, 
+        744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 
+
+};
+
+/* ----------------------------------------------------------------------
+** Desired gains, in dB, per band
+** ------------------------------------------------------------------- */
+
+int gainDB[5] = {0, -3, 6, 4, -6};
+
+float32_t snr;
+
+
+/* ---------------------------------------------------------------------- 
+ * Graphic equalizer Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  float32_t  *inputF32, *outputF32;  
+  arm_biquad_cas_df1_32x64_ins_q31 S1; 
+  arm_biquad_cas_df1_32x64_ins_q31 S2; 
+  arm_biquad_casd_df1_inst_q31 S3; 
+  arm_biquad_casd_df1_inst_q31 S4; 
+  arm_biquad_casd_df1_inst_q31 S5; 
+  int i;
+  int32_t status;
+         
+  inputF32 = &testInput_f32[0];  
+  outputF32 = &testOutput[0]; 
+         
+  /* Initialize the state and coefficient buffers for all Biquad sections */
+
+  arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, 
+                                    (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
+                                    &biquadStateBand1Q31[0], 2);
+
+  arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, 
+                                    (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
+                                    &biquadStateBand2Q31[0], 2);
+         
+  arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, 
+                                  (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
+                                  &biquadStateBand3Q31[0], 2);
+
+  arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, 
+                                  (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
+                                  &biquadStateBand4Q31[0], 2); 
+         
+  arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, 
+                                  (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
+                                  &biquadStateBand5Q31[0], 2); 
+         
+ 
+  /* Call the process functions and needs to change filter coefficients  
+     for varying the gain of each band */ 
+ 
+  for(i=0; i < NUMBLOCKS; i++) 
+    {    
+
+      /* ---------------------------------------------------------------------- 
+      ** Convert block of input data from float to Q31 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);     
+                 
+      /* ----------------------------------------------------------------------
+      ** Scale down by 1/8.  This provides additional headroom so that the
+      ** graphic EQ can apply gain.
+      ** ------------------------------------------------------------------- */
+
+      arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
+
+      /* ----------------------------------------------------------------------
+      ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
+      ** ------------------------------------------------------------------- */
+
+      arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); 
+
+      /* ---------------------------------------------------------------------- 
+      ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
+      ** ------------------------------------------------------------------- */            
+
+      arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);  
+      arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); 
+ 
+      /* ---------------------------------------------------------------------- 
+      ** Convert Q31 result back to float 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+
+      /* ---------------------------------------------------------------------- 
+      ** Scale back up
+      ** ------------------------------------------------------------------- */ 
+
+      arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+    }; 
+
+        snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
+
+        if (snr < SNR_THRESHOLD_F32) 
+        { 
+            status = ARM_MATH_TEST_FAILURE; 
+        } 
+        else
+        {
+            status = ARM_MATH_SUCCESS; 
+        }
+                 
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+         
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_linear_interp_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_linear_interp_example_f32_8c-example.html
new file mode 100644
index 0000000000..26b5c23cba
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+++ b/CMSIS/Documentation/DSP/html/arm_linear_interp_example_f32_8c-example.html
@@ -0,0 +1,273 @@
+
+
+
+
+arm_linear_interp_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_linear_interp_example_f32.c
  

+

+

+
/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date:        29. November 2010
+* $Revision:    V1.0.3
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_linear_interp_example_f32.c
+*
+* Description:  Example code demonstrating usage of sin function
+*               and uses linear interpolation to get higher precision
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+*
+* Version 1.0.3 2010/11/29
+*    Re-organized the CMSIS folders and updated documentation.
+*
+* Version 1.0.1 2010/10/05 KK
+*    Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+#define SNR_THRESHOLD           90
+#define TEST_LENGTH_SAMPLES     10
+#define XSPACING               (0.00005f)
+
+/* ----------------------------------------------------------------------
+* Test input data for F32 SIN function
+* Generated by the MATLAB rand() function
+* randn('state', 0)
+* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
+* --------------------------------------------------------------------*/
+float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =
+{
+   -0.649716504673081170, -2.501723745497831200,
+    0.188250329003310100,  0.432092748487532540,
+   -1.722010988459680800,  1.788766476323060600,
+    1.786136060975809500, -0.056525543169408797,
+    0.491596272728153760,  0.262309671126153390
+};
+
+/*------------------------------------------------------------------------------
+*  Reference out of SIN F32 function for Block Size = 10
+*  Calculated from sin(testInputSin_f32)
+*------------------------------------------------------------------------------*/
+float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =
+{
+   -0.604960695383043530, -0.597090287967934840,
+    0.187140422442966500,  0.418772124875992690,
+   -0.988588831792106880,  0.976338412038794010,
+    0.976903856413481100, -0.056495446835214236,
+    0.472033731854734240,  0.259311907228582830
+};
+
+/*------------------------------------------------------------------------------
+*  Method 1: Test out Buffer Calculated from Cubic Interpolation
+*------------------------------------------------------------------------------*/
+float32_t testOutput[TEST_LENGTH_SAMPLES];
+
+/*------------------------------------------------------------------------------
+*  Method 2: Test out buffer Calculated from Linear Interpolation
+*------------------------------------------------------------------------------*/
+float32_t testLinIntOutput[TEST_LENGTH_SAMPLES];
+
+/*------------------------------------------------------------------------------
+*  External table used for linear interpolation
+*------------------------------------------------------------------------------*/
+extern const float arm_linear_interep_table[188495];
+
+/* ----------------------------------------------------------------------
+* Global Variables for caluclating SNR's for Method1 & Method 2
+* ------------------------------------------------------------------- */
+float32_t snr1;
+float32_t snr2;
+
+/* ----------------------------------------------------------------------------
+* Calculation of Sine values from Cubic Interpolation and Linear interpolation
+* ---------------------------------------------------------------------------- */
+int32_t main(void)
+{
+   uint32_t i;
+   arm_status status;
+
+   arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, (float32_t *)&arm_linear_interep_table[0]};
+
+   /*------------------------------------------------------------------------------
+   *  Method 1: Test out Calculated from Cubic Interpolation
+   *------------------------------------------------------------------------------*/
+   for(i=0; i< TEST_LENGTH_SAMPLES; i++)
+   {
+      testOutput[i] = arm_sin_f32(testInputSin_f32[i]);
+   }
+
+   /*------------------------------------------------------------------------------
+   *  Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation
+   *------------------------------------------------------------------------------*/
+
+   for(i=0; i< TEST_LENGTH_SAMPLES; i++)
+   {
+        testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
+   }
+
+   /*------------------------------------------------------------------------------
+   *  SNR calculation for method 1
+   *------------------------------------------------------------------------------*/
+   snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2);
+
+   /*------------------------------------------------------------------------------
+   *  SNR calculation for method 2
+   *------------------------------------------------------------------------------*/
+   snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2);
+
+   /*------------------------------------------------------------------------------
+   *                                    Initialise status depending on SNR calculations
+   *------------------------------------------------------------------------------*/
+   if( snr2 > snr1)
+   {
+      status = ARM_MATH_SUCCESS;
+   }
+   else
+   {
+      status = ARM_MATH_TEST_FAILURE;
+   }
+
+   /* ----------------------------------------------------------------------
+   ** Loop here if the signals fail the PASS check.
+   ** This denotes a test failure
+   ** ------------------------------------------------------------------- */
+   if( status != ARM_MATH_SUCCESS)
+   {
+      while(1);
+   }
+
+   while(1);                             /* main function does not return */
+}
+
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_matrix_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_matrix_example_f32_8c-example.html
new file mode 100644
index 0000000000..ed1b6baa14
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_matrix_example_f32_8c-example.html
@@ -0,0 +1,296 @@
+
+
+
+
+arm_matrix_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_matrix_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_matrix_example_f32.c              
+*  
+* Description:  Example code demonstrating least square fit to data  
+*                               using matrix functions  
+*                                
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+#define SNR_THRESHOLD   90 
+ 
+/* -------------------------------------------------------------------------------- 
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize  
+* and tapSize 
+* --------------------------------------------------------------------------------- */ 
+ 
+const float32_t B_f32[4] =  
+{    
+        782.0, 7577.0, 470.0, 4505.0 
+}; 
+ 
+/* -------------------------------------------------------------------------------- 
+* Formula to fit is  C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize 
+* -------------------------------------------------------------------------------- */ 
+ 
+const float32_t A_f32[16] =  
+{ 
+        /* Const,       numTaps,        blockSize,      numTaps*blockSize */    
+        1.0,            32.0,           4.0,            128.0,  
+        1.0,            32.0,           64.0,           2048.0, 
+        1.0,            16.0,           4.0,            64.0, 
+        1.0,            16.0,           64.0,           1024.0, 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Temporary buffers  for storing intermediate values 
+* ------------------------------------------------------------------- */ 
+/* Transpose of A Buffer */ 
+float32_t AT_f32[16]; 
+/* (Transpose of A * A) Buffer */ 
+float32_t ATMA_f32[16]; 
+/* Inverse(Transpose of A * A)  Buffer */ 
+float32_t ATMAI_f32[16]; 
+/* Test Output Buffer */ 
+float32_t X_f32[4]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB  
+* ------------------------------------------------------------------- */ 
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; 
+ 
+float32_t snr; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+ 
+        arm_matrix_instance_f32 A;              /* Matrix A Instance */ 
+        arm_matrix_instance_f32 AT;             /* Matrix AT(A transpose) instance */ 
+        arm_matrix_instance_f32 ATMA;   /* Matrix ATMA( AT multiply with A) instance */ 
+        arm_matrix_instance_f32 ATMAI;  /* Matrix ATMAI(Inverse of ATMA) instance */ 
+        arm_matrix_instance_f32 B;              /* Matrix B instance */ 
+        arm_matrix_instance_f32 X;              /* Matrix X(Unknown Matrix) instance */ 
+ 
+        uint32_t srcRows, srcColumns;   /* Temporary variables */
+        arm_status status; 
+ 
+        /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ 
+        srcRows = 4; 
+    srcColumns = 4; 
+        arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); 
+ 
+        /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ 
+        srcRows = 4; 
+    srcColumns = 4; 
+        arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); 
+ 
+        /* calculation of A transpose */ 
+        status = arm_mat_trans_f32(&A, &AT); 
+         
+ 
+        /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ 
+        srcRows = 4; 
+    srcColumns = 4; 
+        arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); 
+ 
+        /* calculation of AT Multiply with A */ 
+        status = arm_mat_mult_f32(&AT, &A, &ATMA); 
+ 
+        /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ 
+        srcRows = 4; 
+    srcColumns = 4; 
+        arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); 
+ 
+        /* calculation of Inverse((Transpose(A) * A) */ 
+        status = arm_mat_inverse_f32(&ATMA, &ATMAI); 
+ 
+        /* calculation of (Inverse((Transpose(A) * A)) *  Transpose(A)) */ 
+        status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); 
+ 
+        /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ 
+        srcRows = 4; 
+    srcColumns = 1; 
+        arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);  
+ 
+        /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ 
+        srcRows = 4; 
+    srcColumns = 1; 
+        arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); 
+ 
+        /* calculation ((Inverse((Transpose(A) * A)) *  Transpose(A)) * B) */ 
+        status = arm_mat_mult_f32(&ATMA, &B, &X); 
+         
+        /* Comparison of reference with test output */     
+        snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); 
+ 
+        /*------------------------------------------------------------------------------ 
+        *                                       Initialise status depending on SNR calculations 
+        *------------------------------------------------------------------------------*/  
+        if( snr > SNR_THRESHOLD) 
+        { 
+                status = ARM_MATH_SUCCESS; 
+        } 
+        else 
+        { 
+                status = ARM_MATH_TEST_FAILURE; 
+        } 
+ 
+         
+        /* ---------------------------------------------------------------------- 
+        ** Loop here if the signals fail the PASS check. 
+        ** This denotes a test failure 
+        ** ------------------------------------------------------------------- */        
+        if( status != ARM_MATH_SUCCESS) 
+        { 
+          while(1); 
+        } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_signal_converge_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_signal_converge_example_f32_8c-example.html
new file mode 100644
index 0000000000..43dfc07784
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_signal_converge_example_f32_8c-example.html
@@ -0,0 +1,306 @@
+
+
+
+
+arm_signal_converge_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_signal_converge_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_signal_converge_example_f32.c             
+*  
+* Description:  Example code demonstrating convergence of an adaptive 
+*               filter. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Global defines for the simulation 
+* ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES 1536 
+#define NUMTAPS                         32 
+#define BLOCKSIZE                       32 
+#define DELTA_ERROR         0.000001f 
+#define DELTA_COEFF         0.0001f 
+#define MU                                      0.5f 
+ 
+#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare FIR state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t firStateF32[NUMTAPS + BLOCKSIZE];  
+arm_fir_instance_f32 LPF_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare LMSNorm state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];  
+float32_t errOutput[TEST_LENGTH_SAMPLES]; 
+arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Function Declarations for Signal Convergence Example  
+* ------------------------------------------------------------------- */ 
+ 
+arm_status test_signal_converge_example( void ); 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Internal functions 
+* ------------------------------------------------------------------- */ 
+arm_status test_signal_converge(float32_t* err_signal, 
+                                                     uint32_t blockSize); 
+ 
+void getinput(float32_t* input, 
+                 uint32_t fr_cnt,  
+             uint32_t blockSize);  
+ 
+/* ---------------------------------------------------------------------- 
+* External Declarations for FIR F32 module Test 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; 
+extern float32_t lmsNormCoeff_f32[32]; 
+extern const float32_t FIRCoeff_f32[32]; 
+extern arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+ 
+float32_t wire1[BLOCKSIZE]; 
+float32_t wire2[BLOCKSIZE]; 
+float32_t wire3[BLOCKSIZE]; 
+float32_t err_signal[BLOCKSIZE]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Signal converge test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_status status; 
+  uint32_t index; 
+  float32_t minValue; 
+ 
+  /* Initialize the LMSNorm data structure */ 
+  arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); 
+ 
+  /* Initialize the FIR data structure */ 
+  arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop over the frames of data and execute each of the processing 
+  * functions in the system. 
+  * ------------------------------------------------------------------- */ 
+ 
+  for(i=0; i < NUMFRAMES; i++)  
+    { 
+      /* Read the input data - uniformly distributed random noise - into wire1 */  
+      arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); 
+ 
+      /* Execute the FIR processing function.  Input wire1 and output wire2 */  
+      arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); 
+       
+      /* Execute the LMS Norm processing function*/  
+ 
+      arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ 
+                       wire1,                     /* Input signal */  
+                       wire2,                             /* Reference Signal */ 
+                       wire3,                             /* Converged Signal */ 
+                       err_signal,                        /* Error Signal, this will become small as the signal converges */ 
+                       BLOCKSIZE);                        /* BlockSize */ 
+ 
+      /* apply overall gain */  
+      arm_scale_f32(wire3, 5, wire3, BLOCKSIZE);         /* in-place buffer */  
+    } 
+ 
+  status = ARM_MATH_SUCCESS; 
+ 
+  /* ------------------------------------------------------------------------------- 
+  * Test whether the error signal has reached towards 0. 
+  * ----------------------------------------------------------------------------- */ 
+ 
+  arm_abs_f32(err_signal, err_signal, BLOCKSIZE); 
+  arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); 
+ 
+  if (minValue > DELTA_ERROR) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Test whether the filter coefficients have converged. 
+  * ------------------------------------------------------------------- */ 
+ 
+  arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+ 
+  arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+  arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); 
+ 
+  if (minValue > DELTA_COEFF) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop here if the signals did not pass the convergence check. 
+  * This denotes a test failure 
+  * ------------------------------------------------------------------- */ 
+ 
+  if( status != ARM_MATH_SUCCESS) 
+  { 
+      while(1); 
+  } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_sin_cos_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_sin_cos_example_f32_8c-example.html
new file mode 100644
index 0000000000..34bd230d43
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_sin_cos_example_f32_8c-example.html
@@ -0,0 +1,232 @@
+
+
+
+
+arm_sin_cos_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_sin_cos_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:          CMSIS DSP Library  
+* Title:            arm_sin_cos_example_f32.c             
+*  
+* Description:  Example code demonstrating sin and cos calculation of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point sin_cos example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+ 
+const float32_t testInput_f32[MAX_BLOCKSIZE] =  
+{    
+        -1.244916875853235400,  -4.793533929171324800,  0.360705030233248850,   0.827929644170887320,   -3.299532218312426900,  3.427441903227623800,   3.422401784294607700,   -0.108308165334010680,   
+        0.941943896490312180,   0.502609575000365850,   -0.537345278736373500,  2.088817392965764500,   -1.693168684143455700,  6.283185307179590700,   -0.392545884746175080,  0.327893095115825040,    
+        3.070147440456292300,   0.170611405884662230,   -0.275275082396073010,  -2.395492805446796300,  0.847311163536506600,   -3.845517018083148800,  2.055818378415868300,   4.672594161978930800,    
+        -1.990923030266425800,  2.469305197656249500,   3.609002606064021000,   -4.586736582331667500,  -4.147080139136136300,  1.643756718868359500,   -1.150866392366494800,  1.985805026477433800 
+ 
+ 
+};  
+ 
+const float32_t testRefOutput_f32 = 1.000000000; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t blockSize = 32; 
+float32_t  testOutput;  
+float32_t  cosOutput;  
+float32_t  sinOutput;  
+float32_t  cosSquareOutput;  
+float32_t  sinSquareOutput; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+
+arm_status status; 
+ 
+int32_t main(void) 
+{ 
+        float32_t diff; 
+        uint32_t i; 
+ 
+        for(i=0; i< blockSize; i++) 
+    { 
+        cosOutput = arm_cos_f32(testInput_f32[i]); 
+                sinOutput = arm_sin_f32(testInput_f32[i]); 
+ 
+                arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); 
+                arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); 
+ 
+                arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
+ 
+                /* absolute value of difference between ref and test */ 
+            diff = fabsf(testRefOutput_f32 - testOutput); 
+         
+            /* Comparison of sin_cos value with reference */ 
+            if(diff > DELTA) 
+            { 
+                   status = ARM_MATH_TEST_FAILURE; 
+            } 
+                 
+            if( status == ARM_MATH_TEST_FAILURE) 
+            { 
+               while(1); 
+            } 
+ 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+
 

+

+
+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/arm_variance_example_f32_8c-example.html b/CMSIS/Documentation/DSP/html/arm_variance_example_f32_8c-example.html
new file mode 100644
index 0000000000..b6555da7f0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/arm_variance_example_f32_8c-example.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_variance_example_f32.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
arm_variance_example_f32.c
  

+

+

+
/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.     
+*    
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*     
+* Project:          CMSIS DSP Library  
+* Title:            arm_variance_example_f32.c           
+* 
+* Description:  Example code demonstrating variance calculation of input sequence.
+*     
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */
+
+#include <math.h>    
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE   32
+#define DELTA           (0.000001f)
+
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers 
+* ------------------------------------------------------------------- */
+float32_t wire1[MAX_BLOCKSIZE];
+float32_t wire2[MAX_BLOCKSIZE];
+float32_t wire3[MAX_BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Variance example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+float32_t testInput_f32[32] = 
+{ 
+-0.432564811528221,     -1.665584378238097,     0.125332306474831,              0.287676420358549,      
+-1.146471350681464,     1.190915465642999,              1.189164201652103,              -0.037633276593318,     
+0.327292361408654,              0.174639142820925,              -0.186708577681439,     0.725790548293303,      
+-0.588316543014189,     2.183185818197101,              -0.136395883086596,     0.113931313520810,      
+1.066768211359189,              0.059281460523605,              -0.095648405483669,     -0.832349463650022,     
+0.294410816392640,              -1.336181857937804,     0.714324551818952,              1.623562064446271,      
+-0.691775701702287,     0.857996672828263,              1.254001421602532,              -1.593729576447477,     
+-1.440964431901020,     0.571147623658178,              -0.399885577715363,     0.689997375464345
+  
+};
+
+/* ----------------------------------------------------------------------
+* Declare Global variables 
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t  refVarianceOut = 0.903941793931839; 
+
+/* ----------------------------------------------------------------------
+* Variance calculation test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+        arm_status status;
+        float32_t mean, oneByBlockSize;
+        float32_t variance;
+        float32_t diff;
+        
+        status = ARM_MATH_SUCCESS;
+        
+        /* Calculation of mean value of input */
+        
+        /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+        
+        /* Fill wire1 buffer with 1.0 value */
+        arm_fill_f32(1.0,  wire1, blockSize);
+        
+        /* Calculate the dot product of wire1 and wire2 */
+        /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
+        arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
+        
+        /* Calculation of 1/blockSize */
+        oneByBlockSize = 1.0 / (blockSize);
+        
+        /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1)  */
+        arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
+        
+        
+        /* Calculation of variance value of input */
+        
+        /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+        
+        /* Fill wire2 with mean value x' */
+        arm_fill_f32(mean,  wire2, blockSize);
+        
+        /* wire3 contains (x-x') */             
+        arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
+        
+        /* wire2 contains (x-x') */                             
+        arm_copy_f32(wire3, wire2, blockSize);
+        
+        /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+        arm_dot_prod_f32(wire2, wire3, blockSize, &variance); 
+
+    /* Calculation of 1/blockSize */
+        oneByBlockSize = 1.0 / (blockSize - 1);
+
+        /* Calculation of variance */           
+        arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
+        
+        /* absolute value of difference between ref and test */
+        diff = fabsf(refVarianceOut - variance);
+        
+        /* Comparison of variance value with reference */
+        if(diff > DELTA)
+        {
+                status = ARM_MATH_TEST_FAILURE;
+        }
+                
+        if( status != ARM_MATH_SUCCESS)
+        {
+          while(1);
+        }
+
+    while(1);                             /* main function does not return */
+}
+
+
 

+

+
+  
+
+
+
+
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+++ b/CMSIS/Documentation/DSP/html/classes.html
@@ -0,0 +1,166 @@
+
+
+
+
+Data Structure Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Data Structure Index
  

+

+

+
B | C | D | F | I | L | M | P | R

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
  B  

+		arm_cfft_radix2_instance_q31   arm_fir_instance_q15   arm_iir_lattice_instance_q15   arm_matrix_instance_q31   
arm_cfft_radix4_instance_f32   arm_fir_instance_q31   arm_iir_lattice_instance_q31   
  P  

+
arm_bilinear_interp_instance_f32   arm_cfft_radix4_instance_q15   arm_fir_instance_q7   
  L  

+
arm_bilinear_interp_instance_q15   arm_cfft_radix4_instance_q31   arm_fir_interpolate_instance_f32   arm_pid_instance_f32   
arm_bilinear_interp_instance_q31   
  D  

+		arm_fir_interpolate_instance_q15   arm_linear_interp_instance_f32   arm_pid_instance_q15   
arm_bilinear_interp_instance_q7   arm_fir_interpolate_instance_q31   arm_lms_instance_f32   arm_pid_instance_q31   
arm_biquad_cas_df1_32x64_ins_q31   arm_dct4_instance_f32   arm_fir_lattice_instance_f32   arm_lms_instance_q15   
  R  

+
arm_biquad_cascade_df2T_instance_f32   arm_dct4_instance_q15   arm_fir_lattice_instance_q15   arm_lms_instance_q31   
arm_biquad_casd_df1_inst_f32   arm_dct4_instance_q31   arm_fir_lattice_instance_q31   arm_lms_norm_instance_f32   arm_rfft_instance_f32   
arm_biquad_casd_df1_inst_q15   
  F  

+		arm_fir_sparse_instance_f32   arm_lms_norm_instance_q15   arm_rfft_instance_q15   
arm_biquad_casd_df1_inst_q31   arm_fir_sparse_instance_q15   arm_lms_norm_instance_q31   arm_rfft_instance_q31   
  C  

+		arm_fir_decimate_instance_f32   arm_fir_sparse_instance_q31   
  M  

+
arm_fir_decimate_instance_q15   arm_fir_sparse_instance_q7   
arm_cfft_radix2_instance_f32   arm_fir_decimate_instance_q31   
  I  

+		arm_matrix_instance_f32   
arm_cfft_radix2_instance_q15   arm_fir_instance_f32   arm_matrix_instance_q15   
arm_iir_lattice_instance_f32   

+
B | C | D | F | I | L | M | P | R

+

+

+  
+
+
+
+
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index 0000000000..a5c4b8de50
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
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+	font-family:"Arial monospaced for SAP";
+}
+
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+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
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+	font-weight: bold;
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+
+div.multicol {
+	-moz-column-gap: 1em;
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+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
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+
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+	margin-bottom: 0px;
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+
+p.enddd {
+	margin-bottom: 4px;
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+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
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+
+div.navtab {
+	margin-right: 15px;
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+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
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+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
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+body {
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+	color: black;
+        margin: 0;
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+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
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+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
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+div.center img {
+	border: 0px;
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+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
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+}
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+}
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+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
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+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
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+
+td.tiny {
+	font-size: 75%;
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+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
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+	border: none;
+	margin: 4px;
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+        /* firefox specific markup */
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+        -moz-border-radius-topright: 8px;
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+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
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+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/CMSIS/Documentation/DSP/html/dct4FormatsQ15Table.gif b/CMSIS/Documentation/DSP/html/dct4FormatsQ15Table.gif
new file mode 100644
index 0000000000..050999cb1e
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dct4FormatsQ15Table.gif differ
diff --git a/CMSIS/Documentation/DSP/html/dct4FormatsQ31Table.gif b/CMSIS/Documentation/DSP/html/dct4FormatsQ31Table.gif
new file mode 100644
index 0000000000..7491187712
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dct4FormatsQ31Table.gif differ
diff --git a/CMSIS/Documentation/DSP/html/dct4NormalizingF32Table.gif b/CMSIS/Documentation/DSP/html/dct4NormalizingF32Table.gif
new file mode 100644
index 0000000000..f3536b8ca1
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dct4NormalizingF32Table.gif differ
diff --git a/CMSIS/Documentation/DSP/html/dct4NormalizingQ15Table.gif b/CMSIS/Documentation/DSP/html/dct4NormalizingQ15Table.gif
new file mode 100644
index 0000000000..625a4189a1
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dct4NormalizingQ15Table.gif differ
diff --git a/CMSIS/Documentation/DSP/html/dct4NormalizingQ31Table.gif b/CMSIS/Documentation/DSP/html/dct4NormalizingQ31Table.gif
new file mode 100644
index 0000000000..22d1f6588c
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dct4NormalizingQ31Table.gif differ
diff --git a/CMSIS/Documentation/DSP/html/dotProduct.gif b/CMSIS/Documentation/DSP/html/dotProduct.gif
new file mode 100644
index 0000000000..7a3af2891b
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/dotProduct.gif differ
diff --git a/CMSIS/Documentation/DSP/html/doxygen.png b/CMSIS/Documentation/DSP/html/doxygen.png
new file mode 100644
index 0000000000..635ed52fce
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/doxygen.png differ
diff --git a/CMSIS/Documentation/DSP/html/examples.html b/CMSIS/Documentation/DSP/html/examples.html
new file mode 100644
index 0000000000..5a002d215e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/examples.html
@@ -0,0 +1,154 @@
+
+
+
+
+Examples
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Examples
  

+

+

+
Here is a list of all examples:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/files.html b/CMSIS/Documentation/DSP/html/files.html
new file mode 100644
index 0000000000..f60ed2d181
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/files.html
@@ -0,0 +1,667 @@
+
+
+
+
+Files
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Files
  

+

+

+
Here is a list of all files with brief descriptions:

+  
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arm_abs_f32.c
arm_abs_f32.d
arm_abs_q15.c
arm_abs_q15.d
arm_abs_q31.c
arm_abs_q31.d
arm_abs_q7.c
arm_abs_q7.d
arm_add_f32.c
arm_add_f32.d
arm_add_q15.c
arm_add_q15.d
arm_add_q31.c
arm_add_q31.d
arm_add_q7.c
arm_add_q7.d
arm_biquad_cascade_df1_32x64_init_q31.c
arm_biquad_cascade_df1_32x64_init_q31.d
arm_biquad_cascade_df1_32x64_q31.c
arm_biquad_cascade_df1_32x64_q31.d
arm_biquad_cascade_df1_f32.c
arm_biquad_cascade_df1_f32.d
arm_biquad_cascade_df1_fast_q15.c
arm_biquad_cascade_df1_fast_q15.d
arm_biquad_cascade_df1_fast_q31.c
arm_biquad_cascade_df1_fast_q31.d
arm_biquad_cascade_df1_init_f32.c
arm_biquad_cascade_df1_init_f32.d
arm_biquad_cascade_df1_init_q15.c
arm_biquad_cascade_df1_init_q15.d
arm_biquad_cascade_df1_init_q31.c
arm_biquad_cascade_df1_init_q31.d
arm_biquad_cascade_df1_q15.c
arm_biquad_cascade_df1_q15.d
arm_biquad_cascade_df1_q31.c
arm_biquad_cascade_df1_q31.d
arm_biquad_cascade_df2T_f32.c
arm_biquad_cascade_df2t_f32.d
arm_biquad_cascade_df2T_init_f32.c
arm_biquad_cascade_df2t_init_f32.d
arm_bitreversal.c
arm_bitreversal.d
arm_cfft_radix2_f32.c
arm_cfft_radix2_f32.d
arm_cfft_radix2_init_f32.c
arm_cfft_radix2_init_f32.d
arm_cfft_radix2_init_q15.c
arm_cfft_radix2_init_q15.d
arm_cfft_radix2_init_q31.c
arm_cfft_radix2_init_q31.d
arm_cfft_radix2_q15.c
arm_cfft_radix2_q15.d
arm_cfft_radix2_q31.c
arm_cfft_radix2_q31.d
arm_cfft_radix4_f32.c
arm_cfft_radix4_f32.d
arm_cfft_radix4_init_f32.c
arm_cfft_radix4_init_f32.d
arm_cfft_radix4_init_q15.c
arm_cfft_radix4_init_q15.d
arm_cfft_radix4_init_q31.c
arm_cfft_radix4_init_q31.d
arm_cfft_radix4_q15.c
arm_cfft_radix4_q15.d
arm_cfft_radix4_q31.c
arm_cfft_radix4_q31.d
arm_class_marks_example_f32.c
arm_cmplx_conj_f32.c
arm_cmplx_conj_f32.d
arm_cmplx_conj_q15.c
arm_cmplx_conj_q15.d
arm_cmplx_conj_q31.c
arm_cmplx_conj_q31.d
arm_cmplx_dot_prod_f32.c
arm_cmplx_dot_prod_f32.d
arm_cmplx_dot_prod_q15.c
arm_cmplx_dot_prod_q15.d
arm_cmplx_dot_prod_q31.c
arm_cmplx_dot_prod_q31.d
arm_cmplx_mag_f32.c
arm_cmplx_mag_f32.d
arm_cmplx_mag_q15.c
arm_cmplx_mag_q15.d
arm_cmplx_mag_q31.c
arm_cmplx_mag_q31.d
arm_cmplx_mag_squared_f32.c
arm_cmplx_mag_squared_f32.d
arm_cmplx_mag_squared_q15.c
arm_cmplx_mag_squared_q15.d
arm_cmplx_mag_squared_q31.c
arm_cmplx_mag_squared_q31.d
arm_cmplx_mult_cmplx_f32.c
arm_cmplx_mult_cmplx_f32.d
arm_cmplx_mult_cmplx_q15.c
arm_cmplx_mult_cmplx_q15.d
arm_cmplx_mult_cmplx_q31.c
arm_cmplx_mult_cmplx_q31.d
arm_cmplx_mult_real_f32.c
arm_cmplx_mult_real_f32.d
arm_cmplx_mult_real_q15.c
arm_cmplx_mult_real_q15.d
arm_cmplx_mult_real_q31.c
arm_cmplx_mult_real_q31.d
arm_common_tables.c
arm_common_tables.d
arm_common_tables.h
arm_conv_f32.c
arm_conv_f32.d
arm_conv_fast_opt_q15.c
arm_conv_fast_opt_q15.d
arm_conv_fast_q15.c
arm_conv_fast_q15.d
arm_conv_fast_q31.c
arm_conv_fast_q31.d
arm_conv_opt_q15.c
arm_conv_opt_q15.d
arm_conv_opt_q7.c
arm_conv_opt_q7.d
arm_conv_partial_f32.c
arm_conv_partial_f32.d
arm_conv_partial_fast_opt_q15.c
arm_conv_partial_fast_opt_q15.d
arm_conv_partial_fast_q15.c
arm_conv_partial_fast_q15.d
arm_conv_partial_fast_q31.c
arm_conv_partial_fast_q31.d
arm_conv_partial_opt_q15.c
arm_conv_partial_opt_q15.d
arm_conv_partial_opt_q7.c
arm_conv_partial_opt_q7.d
arm_conv_partial_q15.c
arm_conv_partial_q15.d
arm_conv_partial_q31.c
arm_conv_partial_q31.d
arm_conv_partial_q7.c
arm_conv_partial_q7.d
arm_conv_q15.c
arm_conv_q15.d
arm_conv_q31.c
arm_conv_q31.d
arm_conv_q7.c
arm_conv_q7.d
arm_convolution_example_f32.c
arm_copy_f32.c
arm_copy_f32.d
arm_copy_q15.c
arm_copy_q15.d
arm_copy_q31.c
arm_copy_q31.d
arm_copy_q7.c
arm_copy_q7.d
arm_correlate_f32.c
arm_correlate_f32.d
arm_correlate_fast_opt_q15.c
arm_correlate_fast_opt_q15.d
arm_correlate_fast_q15.c
arm_correlate_fast_q15.d
arm_correlate_fast_q31.c
arm_correlate_fast_q31.d
arm_correlate_opt_q15.c
arm_correlate_opt_q15.d
arm_correlate_opt_q7.c
arm_correlate_opt_q7.d
arm_correlate_q15.c
arm_correlate_q15.d
arm_correlate_q31.c
arm_correlate_q31.d
arm_correlate_q7.c
arm_correlate_q7.d
arm_cos_f32.c
arm_cos_f32.d
arm_cos_q15.c
arm_cos_q15.d
arm_cos_q31.c
arm_cos_q31.d
arm_dct4_f32.c
arm_dct4_f32.d
arm_dct4_init_f32.c
arm_dct4_init_f32.d
arm_dct4_init_q15.c
arm_dct4_init_q15.d
arm_dct4_init_q31.c
arm_dct4_init_q31.d
arm_dct4_q15.c
arm_dct4_q15.d
arm_dct4_q31.c
arm_dct4_q31.d
arm_dot_prod_f32.c
arm_dot_prod_f32.d
arm_dot_prod_q15.c
arm_dot_prod_q15.d
arm_dot_prod_q31.c
arm_dot_prod_q31.d
arm_dot_prod_q7.c
arm_dot_prod_q7.d
arm_dotproduct_example_f32.c
arm_fft_bin_data.c
arm_fft_bin_example_f32.c
arm_fill_f32.c
arm_fill_f32.d
arm_fill_q15.c
arm_fill_q15.d
arm_fill_q31.c
arm_fill_q31.d
arm_fill_q7.c
arm_fill_q7.d
arm_fir_data.c
arm_fir_decimate_f32.c
arm_fir_decimate_f32.d
arm_fir_decimate_fast_q15.c
arm_fir_decimate_fast_q15.d
arm_fir_decimate_fast_q31.c
arm_fir_decimate_fast_q31.d
arm_fir_decimate_init_f32.c
arm_fir_decimate_init_f32.d
arm_fir_decimate_init_q15.c
arm_fir_decimate_init_q15.d
arm_fir_decimate_init_q31.c
arm_fir_decimate_init_q31.d
arm_fir_decimate_q15.c
arm_fir_decimate_q15.d
arm_fir_decimate_q31.c
arm_fir_decimate_q31.d
arm_fir_example_f32.c
arm_fir_f32.c
arm_fir_f32.d
arm_fir_fast_q15.c
arm_fir_fast_q15.d
arm_fir_fast_q31.c
arm_fir_fast_q31.d
arm_fir_init_f32.c
arm_fir_init_f32.d
arm_fir_init_q15.c
arm_fir_init_q15.d
arm_fir_init_q31.c
arm_fir_init_q31.d
arm_fir_init_q7.c
arm_fir_init_q7.d
arm_fir_interpolate_f32.c
arm_fir_interpolate_f32.d
arm_fir_interpolate_init_f32.c
arm_fir_interpolate_init_f32.d
arm_fir_interpolate_init_q15.c
arm_fir_interpolate_init_q15.d
arm_fir_interpolate_init_q31.c
arm_fir_interpolate_init_q31.d
arm_fir_interpolate_q15.c
arm_fir_interpolate_q15.d
arm_fir_interpolate_q31.c
arm_fir_interpolate_q31.d
arm_fir_lattice_f32.c
arm_fir_lattice_f32.d
arm_fir_lattice_init_f32.c
arm_fir_lattice_init_f32.d
arm_fir_lattice_init_q15.c
arm_fir_lattice_init_q15.d
arm_fir_lattice_init_q31.c
arm_fir_lattice_init_q31.d
arm_fir_lattice_q15.c
arm_fir_lattice_q15.d
arm_fir_lattice_q31.c
arm_fir_lattice_q31.d
arm_fir_q15.c
arm_fir_q15.d
arm_fir_q31.c
arm_fir_q31.d
arm_fir_q7.c
arm_fir_q7.d
arm_fir_sparse_f32.c
arm_fir_sparse_f32.d
arm_fir_sparse_init_f32.c
arm_fir_sparse_init_f32.d
arm_fir_sparse_init_q15.c
arm_fir_sparse_init_q15.d
arm_fir_sparse_init_q31.c
arm_fir_sparse_init_q31.d
arm_fir_sparse_init_q7.c
arm_fir_sparse_init_q7.d
arm_fir_sparse_q15.c
arm_fir_sparse_q15.d
arm_fir_sparse_q31.c
arm_fir_sparse_q31.d
arm_fir_sparse_q7.c
arm_fir_sparse_q7.d
arm_float_to_q15.c
arm_float_to_q15.d
arm_float_to_q31.c
arm_float_to_q31.d
arm_float_to_q7.c
arm_float_to_q7.d
arm_graphic_equalizer_data.c
arm_graphic_equalizer_example_q31.c
arm_iir_lattice_f32.c
arm_iir_lattice_f32.d
arm_iir_lattice_init_f32.c
arm_iir_lattice_init_f32.d
arm_iir_lattice_init_q15.c
arm_iir_lattice_init_q15.d
arm_iir_lattice_init_q31.c
arm_iir_lattice_init_q31.d
arm_iir_lattice_q15.c
arm_iir_lattice_q15.d
arm_iir_lattice_q31.c
arm_iir_lattice_q31.d
arm_linear_interp_data.c
arm_linear_interp_example_f32.c
arm_lms_f32.c
arm_lms_f32.d
arm_lms_init_f32.c
arm_lms_init_f32.d
arm_lms_init_q15.c
arm_lms_init_q15.d
arm_lms_init_q31.c
arm_lms_init_q31.d
arm_lms_norm_f32.c
arm_lms_norm_f32.d
arm_lms_norm_init_f32.c
arm_lms_norm_init_f32.d
arm_lms_norm_init_q15.c
arm_lms_norm_init_q15.d
arm_lms_norm_init_q31.c
arm_lms_norm_init_q31.d
arm_lms_norm_q15.c
arm_lms_norm_q15.d
arm_lms_norm_q31.c
arm_lms_norm_q31.d
arm_lms_q15.c
arm_lms_q15.d
arm_lms_q31.c
arm_lms_q31.d
arm_mat_add_f32.c
arm_mat_add_f32.d
arm_mat_add_q15.c
arm_mat_add_q15.d
arm_mat_add_q31.c
arm_mat_add_q31.d
arm_mat_init_f32.c
arm_mat_init_f32.d
arm_mat_init_q15.c
arm_mat_init_q15.d
arm_mat_init_q31.c
arm_mat_init_q31.d
arm_mat_inverse_f32.c
arm_mat_inverse_f32.d
arm_mat_mult_f32.c
arm_mat_mult_f32.d
arm_mat_mult_fast_q15.c
arm_mat_mult_fast_q15.d
arm_mat_mult_fast_q31.c
arm_mat_mult_fast_q31.d
arm_mat_mult_q15.c
arm_mat_mult_q15.d
arm_mat_mult_q31.c
arm_mat_mult_q31.d
arm_mat_scale_f32.c
arm_mat_scale_f32.d
arm_mat_scale_q15.c
arm_mat_scale_q15.d
arm_mat_scale_q31.c
arm_mat_scale_q31.d
arm_mat_sub_f32.c
arm_mat_sub_f32.d
arm_mat_sub_q15.c
arm_mat_sub_q15.d
arm_mat_sub_q31.c
arm_mat_sub_q31.d
arm_mat_trans_f32.c
arm_mat_trans_f32.d
arm_mat_trans_q15.c
arm_mat_trans_q15.d
arm_mat_trans_q31.c
arm_mat_trans_q31.d
arm_math.h
arm_matrix_example_f32.c
arm_max_f32.c
arm_max_f32.d
arm_max_q15.c
arm_max_q15.d
arm_max_q31.c
arm_max_q31.d
arm_max_q7.c
arm_max_q7.d
arm_mean_f32.c
arm_mean_f32.d
arm_mean_q15.c
arm_mean_q15.d
arm_mean_q31.c
arm_mean_q31.d
arm_mean_q7.c
arm_mean_q7.d
arm_min_f32.c
arm_min_f32.d
arm_min_q15.c
arm_min_q15.d
arm_min_q31.c
arm_min_q31.d
arm_min_q7.c
arm_min_q7.d
arm_mult_f32.c
arm_mult_f32.d
arm_mult_q15.c
arm_mult_q15.d
arm_mult_q31.c
arm_mult_q31.d
arm_mult_q7.c
arm_mult_q7.d
arm_negate_f32.c
arm_negate_f32.d
arm_negate_q15.c
arm_negate_q15.d
arm_negate_q31.c
arm_negate_q31.d
arm_negate_q7.c
arm_negate_q7.d
arm_offset_f32.c
arm_offset_f32.d
arm_offset_q15.c
arm_offset_q15.d
arm_offset_q31.c
arm_offset_q31.d
arm_offset_q7.c
arm_offset_q7.d
arm_pid_init_f32.c
arm_pid_init_f32.d
arm_pid_init_q15.c
arm_pid_init_q15.d
arm_pid_init_q31.c
arm_pid_init_q31.d
arm_pid_reset_f32.c
arm_pid_reset_f32.d
arm_pid_reset_q15.c
arm_pid_reset_q15.d
arm_pid_reset_q31.c
arm_pid_reset_q31.d
arm_power_f32.c
arm_power_f32.d
arm_power_q15.c
arm_power_q15.d
arm_power_q31.c
arm_power_q31.d
arm_power_q7.c
arm_power_q7.d
arm_q15_to_float.c
arm_q15_to_float.d
arm_q15_to_q31.c
arm_q15_to_q31.d
arm_q15_to_q7.c
arm_q15_to_q7.d
arm_q31_to_float.c
arm_q31_to_float.d
arm_q31_to_q15.c
arm_q31_to_q15.d
arm_q31_to_q7.c
arm_q31_to_q7.d
arm_q7_to_float.c
arm_q7_to_float.d
arm_q7_to_q15.c
arm_q7_to_q15.d
arm_q7_to_q31.c
arm_q7_to_q31.d
arm_rfft_f32.c
arm_rfft_f32.d
arm_rfft_init_f32.c
arm_rfft_init_f32.d
arm_rfft_init_q15.c
arm_rfft_init_q15.d
arm_rfft_init_q31.c
arm_rfft_init_q31.d
arm_rfft_q15.c
arm_rfft_q15.d
arm_rfft_q31.c
arm_rfft_q31.d
arm_rms_f32.c
arm_rms_f32.d
arm_rms_q15.c
arm_rms_q15.d
arm_rms_q31.c
arm_rms_q31.d
arm_scale_f32.c
arm_scale_f32.d
arm_scale_q15.c
arm_scale_q15.d
arm_scale_q31.c
arm_scale_q31.d
arm_scale_q7.c
arm_scale_q7.d
arm_shift_q15.c
arm_shift_q15.d
arm_shift_q31.c
arm_shift_q31.d
arm_shift_q7.c
arm_shift_q7.d
arm_signal_converge_data.c
arm_signal_converge_example_f32.c
arm_sin_cos_example_f32.c
arm_sin_cos_f32.c
arm_sin_cos_f32.d
arm_sin_cos_q31.c
arm_sin_cos_q31.d
arm_sin_f32.c
arm_sin_f32.d
arm_sin_q15.c
arm_sin_q15.d
arm_sin_q31.c
arm_sin_q31.d
arm_sqrt_q15.c
arm_sqrt_q15.d
arm_sqrt_q31.c
arm_sqrt_q31.d
arm_std_f32.c
arm_std_f32.d
arm_std_q15.c
arm_std_q15.d
arm_std_q31.c
arm_std_q31.d
arm_sub_f32.c
arm_sub_f32.d
arm_sub_q15.c
arm_sub_q15.d
arm_sub_q31.c
arm_sub_q31.d
arm_sub_q7.c
arm_sub_q7.d
arm_var_f32.c
arm_var_f32.d
arm_var_q15.c
arm_var_q15.d
arm_var_q31.c
arm_var_q31.d
arm_variance_example_f32.c
math_helper.c
math_helper.h
system_ARMCM0.cCMSIS Device System Source File for ARMCM0 Device Series 
system_ARMCM3.cCMSIS Device System Source File for ARMCM3 Device Series 
system_ARMCM4.cCMSIS Device System Source File for ARMCM4 Device Series 

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CMSIS-DSP
+    Verison 1.1.0
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CMSIS DSP Software Library

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CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

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+    
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+  
+  
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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+  
+  
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+  
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
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+

+    
+

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+  
+  
+  
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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+

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+Data Fields
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+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
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+  
+  
+  
+  
+

+

+  
+  

+  

+

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+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
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- f -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x69.html b/CMSIS/Documentation/DSP/html/functions_0x69.html
new file mode 100644
index 0000000000..976aab7475
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x69.html
@@ -0,0 +1,174 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- i -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x6b.html b/CMSIS/Documentation/DSP/html/functions_0x6b.html
new file mode 100644
index 0000000000..b9409b9e77
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x6b.html
@@ -0,0 +1,176 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- k -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x6c.html b/CMSIS/Documentation/DSP/html/functions_0x6c.html
new file mode 100644
index 0000000000..008ec66f9d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x6c.html
@@ -0,0 +1,166 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- l -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x6d.html b/CMSIS/Documentation/DSP/html/functions_0x6d.html
new file mode 100644
index 0000000000..7c71561391
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x6d.html
@@ -0,0 +1,180 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- m -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x6e.html b/CMSIS/Documentation/DSP/html/functions_0x6e.html
new file mode 100644
index 0000000000..1dd03c9796
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x6e.html
@@ -0,0 +1,229 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- n -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x6f.html b/CMSIS/Documentation/DSP/html/functions_0x6f.html
new file mode 100644
index 0000000000..62676ae2f8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x6f.html
@@ -0,0 +1,165 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x70.html b/CMSIS/Documentation/DSP/html/functions_0x70.html
new file mode 100644
index 0000000000..15bfc87485
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x70.html
@@ -0,0 +1,313 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- p -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x72.html b/CMSIS/Documentation/DSP/html/functions_0x72.html
new file mode 100644
index 0000000000..ec9494f137
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x72.html
@@ -0,0 +1,165 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- r -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x73.html b/CMSIS/Documentation/DSP/html/functions_0x73.html
new file mode 100644
index 0000000000..e8196a9ae6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x73.html
@@ -0,0 +1,172 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- s -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x74.html b/CMSIS/Documentation/DSP/html/functions_0x74.html
new file mode 100644
index 0000000000..d0b245f799
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x74.html
@@ -0,0 +1,174 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- t -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_0x78.html b/CMSIS/Documentation/DSP/html/functions_0x78.html
new file mode 100644
index 0000000000..d052baed2a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_0x78.html
@@ -0,0 +1,172 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+
+
- x -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars.html b/CMSIS/Documentation/DSP/html/functions_vars.html
new file mode 100644
index 0000000000..4b060c9245
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars.html
@@ -0,0 +1,175 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- a -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x62.html b/CMSIS/Documentation/DSP/html/functions_vars_0x62.html
new file mode 100644
index 0000000000..9dac09f719
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x62.html
@@ -0,0 +1,182 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- b -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x65.html b/CMSIS/Documentation/DSP/html/functions_vars_0x65.html
new file mode 100644
index 0000000000..c015571c43
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x65.html
@@ -0,0 +1,166 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- e -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x66.html b/CMSIS/Documentation/DSP/html/functions_vars_0x66.html
new file mode 100644
index 0000000000..178652931c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x66.html
@@ -0,0 +1,179 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- f -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x69.html b/CMSIS/Documentation/DSP/html/functions_vars_0x69.html
new file mode 100644
index 0000000000..785ac0cf3e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x69.html
@@ -0,0 +1,174 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- i -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x6b.html b/CMSIS/Documentation/DSP/html/functions_vars_0x6b.html
new file mode 100644
index 0000000000..9a98abab68
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x6b.html
@@ -0,0 +1,176 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- k -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x6c.html b/CMSIS/Documentation/DSP/html/functions_vars_0x6c.html
new file mode 100644
index 0000000000..51e709f1d3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x6c.html
@@ -0,0 +1,166 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- l -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x6d.html b/CMSIS/Documentation/DSP/html/functions_vars_0x6d.html
new file mode 100644
index 0000000000..9d98bbbf43
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x6d.html
@@ -0,0 +1,180 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- m -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x6e.html b/CMSIS/Documentation/DSP/html/functions_vars_0x6e.html
new file mode 100644
index 0000000000..b1338f686b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x6e.html
@@ -0,0 +1,229 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- n -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x6f.html b/CMSIS/Documentation/DSP/html/functions_vars_0x6f.html
new file mode 100644
index 0000000000..652d49565d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x6f.html
@@ -0,0 +1,165 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x70.html b/CMSIS/Documentation/DSP/html/functions_vars_0x70.html
new file mode 100644
index 0000000000..a5df849864
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x70.html
@@ -0,0 +1,313 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- p -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x72.html b/CMSIS/Documentation/DSP/html/functions_vars_0x72.html
new file mode 100644
index 0000000000..290e750e8a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x72.html
@@ -0,0 +1,165 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- r -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x73.html b/CMSIS/Documentation/DSP/html/functions_vars_0x73.html
new file mode 100644
index 0000000000..1aae9d28af
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x73.html
@@ -0,0 +1,172 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- s -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x74.html b/CMSIS/Documentation/DSP/html/functions_vars_0x74.html
new file mode 100644
index 0000000000..bba8e2a98f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x74.html
@@ -0,0 +1,174 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- t -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/functions_vars_0x78.html b/CMSIS/Documentation/DSP/html/functions_vars_0x78.html
new file mode 100644
index 0000000000..1a34852330
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/functions_vars_0x78.html
@@ -0,0 +1,172 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- x -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals.html b/CMSIS/Documentation/DSP/html/globals.html
new file mode 100644
index 0000000000..1111ed67ed
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals.html
@@ -0,0 +1,197 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- _ -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x61.html b/CMSIS/Documentation/DSP/html/globals_0x61.html
new file mode 100644
index 0000000000..49587565c9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x61.html
@@ -0,0 +1,257 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- a -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x62.html b/CMSIS/Documentation/DSP/html/globals_0x62.html
new file mode 100644
index 0000000000..f77c08766d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x62.html
@@ -0,0 +1,276 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- b -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x63.html b/CMSIS/Documentation/DSP/html/globals_0x63.html
new file mode 100644
index 0000000000..3f39166db4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x63.html
@@ -0,0 +1,535 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- c -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x64.html b/CMSIS/Documentation/DSP/html/globals_0x64.html
new file mode 100644
index 0000000000..bd4f70aad8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x64.html
@@ -0,0 +1,228 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- d -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x65.html b/CMSIS/Documentation/DSP/html/globals_0x65.html
new file mode 100644
index 0000000000..ef90a2a982
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x65.html
@@ -0,0 +1,173 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- e -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x66.html b/CMSIS/Documentation/DSP/html/globals_0x66.html
new file mode 100644
index 0000000000..6992f4a2bd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x66.html
@@ -0,0 +1,391 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- f -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x67.html b/CMSIS/Documentation/DSP/html/globals_0x67.html
new file mode 100644
index 0000000000..a136ae805e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x67.html
@@ -0,0 +1,173 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- g -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x69.html b/CMSIS/Documentation/DSP/html/globals_0x69.html
new file mode 100644
index 0000000000..ee4c61901e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x69.html
@@ -0,0 +1,215 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- i -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x6c.html b/CMSIS/Documentation/DSP/html/globals_0x6c.html
new file mode 100644
index 0000000000..22b9ed304b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x6c.html
@@ -0,0 +1,244 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- l -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x6d.html b/CMSIS/Documentation/DSP/html/globals_0x6d.html
new file mode 100644
index 0000000000..b420f18702
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x6d.html
@@ -0,0 +1,352 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- m -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x6e.html b/CMSIS/Documentation/DSP/html/globals_0x6e.html
new file mode 100644
index 0000000000..7d4171da52
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x6e.html
@@ -0,0 +1,213 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- n -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x6f.html b/CMSIS/Documentation/DSP/html/globals_0x6f.html
new file mode 100644
index 0000000000..500bcc1475
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x6f.html
@@ -0,0 +1,189 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x70.html b/CMSIS/Documentation/DSP/html/globals_0x70.html
new file mode 100644
index 0000000000..3793302a68
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x70.html
@@ -0,0 +1,236 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- p -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x71.html b/CMSIS/Documentation/DSP/html/globals_0x71.html
new file mode 100644
index 0000000000..741a73dda2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x71.html
@@ -0,0 +1,215 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- q -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x72.html b/CMSIS/Documentation/DSP/html/globals_0x72.html
new file mode 100644
index 0000000000..dbe44d9fd8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x72.html
@@ -0,0 +1,290 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- r -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x73.html b/CMSIS/Documentation/DSP/html/globals_0x73.html
new file mode 100644
index 0000000000..77e15aa428
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_0x73.html
@@ -0,0 +1,352 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
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+

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+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x74.html b/CMSIS/Documentation/DSP/html/globals_0x74.html
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+Index
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+
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+

+
+

+
+ 
+ 
+  
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+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

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+
diff --git a/CMSIS/Documentation/DSP/html/globals_0x75.html b/CMSIS/Documentation/DSP/html/globals_0x75.html
new file mode 100644
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+
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+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
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+
+
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+  
+  
+

+

+  
+  

+  

+

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+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

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diff --git a/CMSIS/Documentation/DSP/html/globals_0x76.html b/CMSIS/Documentation/DSP/html/globals_0x76.html
new file mode 100644
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+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
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+
+
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+  
+

+

+  
+  

+  

+

+
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+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

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diff --git a/CMSIS/Documentation/DSP/html/globals_0x77.html b/CMSIS/Documentation/DSP/html/globals_0x77.html
new file mode 100644
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+
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+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
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+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
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+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

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diff --git a/CMSIS/Documentation/DSP/html/globals_0x78.html b/CMSIS/Documentation/DSP/html/globals_0x78.html
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

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diff --git a/CMSIS/Documentation/DSP/html/globals_defs.html b/CMSIS/Documentation/DSP/html/globals_defs.html
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+
+

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+ 
+ 
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+  
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

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+
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+    
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+
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+  
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+ 
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- _ -

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- a -

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- d -

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- u -

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- x -

+

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+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_enum.html b/CMSIS/Documentation/DSP/html/globals_enum.html
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+ 
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+  
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

+
+
+

+    
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+
+
+  
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+

+  
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+  

+

+
+

+

+ 
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+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_eval.html b/CMSIS/Documentation/DSP/html/globals_eval.html
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+
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+ 
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+  
+  
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+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

+
+
+

+    
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+  
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+  

+

+
+

+

+ 
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+  
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+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func.html b/CMSIS/Documentation/DSP/html/globals_func.html
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+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
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+   
CMSIS-DSP
+    Verison 1.1.0
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+   
CMSIS DSP Software Library

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+

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+    
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+  
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+

+

+ 
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- a -

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+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x62.html b/CMSIS/Documentation/DSP/html/globals_func_0x62.html
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+ 
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+  
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+   
CMSIS-DSP
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CMSIS DSP Software Library

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+    
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+

+ 
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+
- b -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x63.html b/CMSIS/Documentation/DSP/html/globals_func_0x63.html
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+
+

+
+ 
+ 
+  
+  
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+ 
+ 
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+   
CMSIS-DSP
+    Verison 1.1.0
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+   
CMSIS DSP Software Library

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+    
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+  
+  

+  

+

+
+

+

+ 
+
+
- c -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x64.html b/CMSIS/Documentation/DSP/html/globals_func_0x64.html
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+++ b/CMSIS/Documentation/DSP/html/globals_func_0x64.html
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+Index
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+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
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CMSIS DSP Software Library

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+    
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+

+

+ 
+
+
- d -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x66.html b/CMSIS/Documentation/DSP/html/globals_func_0x66.html
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+++ b/CMSIS/Documentation/DSP/html/globals_func_0x66.html
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+Index
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+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
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+ 
+

+   
CMSIS-DSP
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+   
CMSIS DSP Software Library

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+    
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+  
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+
+

+

+ 
+
+
- f -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x67.html b/CMSIS/Documentation/DSP/html/globals_func_0x67.html
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+Index
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+
+
+
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+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

+
+
+

+    
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+
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+  
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+  
+  

+  

+

+
+

+

+ 
+
+
- g -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x69.html b/CMSIS/Documentation/DSP/html/globals_func_0x69.html
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+++ b/CMSIS/Documentation/DSP/html/globals_func_0x69.html
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+
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+Index
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+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- i -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x6c.html b/CMSIS/Documentation/DSP/html/globals_func_0x6c.html
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+
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+
+Index
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+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- l -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x6d.html b/CMSIS/Documentation/DSP/html/globals_func_0x6d.html
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+
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+
+Index
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+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- m -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x6e.html b/CMSIS/Documentation/DSP/html/globals_func_0x6e.html
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+Index
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- n -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x6f.html b/CMSIS/Documentation/DSP/html/globals_func_0x6f.html
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+Index
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+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
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+
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+  
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+

+  
+  

+  

+

+
+

+

+ 
+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x70.html b/CMSIS/Documentation/DSP/html/globals_func_0x70.html
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+Index
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+

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+
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+    
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+  
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+  
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+  

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+
+

+

+ 
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- p -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x71.html b/CMSIS/Documentation/DSP/html/globals_func_0x71.html
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+
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+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
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+    
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+
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+  
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+  
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+  

+

+
+

+

+ 
+
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- q -

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+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x72.html b/CMSIS/Documentation/DSP/html/globals_func_0x72.html
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index 0000000000..d16531f090
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+++ b/CMSIS/Documentation/DSP/html/globals_func_0x72.html
@@ -0,0 +1,252 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- r -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x73.html b/CMSIS/Documentation/DSP/html/globals_func_0x73.html
new file mode 100644
index 0000000000..46e0b73251
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_func_0x73.html
@@ -0,0 +1,279 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- s -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x74.html b/CMSIS/Documentation/DSP/html/globals_func_0x74.html
new file mode 100644
index 0000000000..4d0a03e4ec
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_func_0x74.html
@@ -0,0 +1,168 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- t -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_func_0x76.html b/CMSIS/Documentation/DSP/html/globals_func_0x76.html
new file mode 100644
index 0000000000..58c1de43f9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_func_0x76.html
@@ -0,0 +1,174 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- v -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_type.html b/CMSIS/Documentation/DSP/html/globals_type.html
new file mode 100644
index 0000000000..999de5786d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_type.html
@@ -0,0 +1,157 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/globals_vars.html b/CMSIS/Documentation/DSP/html/globals_vars.html
new file mode 100644
index 0000000000..44590033cb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/globals_vars.html
@@ -0,0 +1,632 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- a -

+
+
+
- b -

+
+
+
- c -

+
+
+
- d -

+
+
+
- e -

+
+
+
- f -

+
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+
- g -

+
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- i -

+
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+
- l -

+
+
+
- m -

+
+
+
- n -

+
+
+
- o -

+
+
+
- r -

+
+
+
- s -

+
+
+
- t -

+
+
+
- v -

+
+
+
- w -

+
+
+
- x -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___basic_abs.html b/CMSIS/Documentation/DSP/html/group___basic_abs.html
new file mode 100644
index 0000000000..9775a223f6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___basic_abs.html
@@ -0,0 +1,336 @@
+
+
+
+
+Vector Absolute Value
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Absolute Value
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  

+
Description

+
Computes the absolute value of a vector on an element-by-element basis.

+
        
+     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.        
+ 
The operation can be done in-place by setting the input and output pointers to the same buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
References blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___basic_add.html b/CMSIS/Documentation/DSP/html/group___basic_add.html
new file mode 100644
index 0000000000..1ed974cf11
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___basic_add.html
@@ -0,0 +1,363 @@
+
+
+
+
+Vector Addition
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Addition
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  

+
Description

+
Element-by-element addition of two vectors.

+
        
+     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References blockSize, and clip_q63_to_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___basic_mult.html b/CMSIS/Documentation/DSP/html/group___basic_mult.html
new file mode 100644
index 0000000000..c1dec00305
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___basic_mult.html
@@ -0,0 +1,367 @@
+
+
+
+
+Vector Multiplication
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Multiplication
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  

+
Description

+
Element-by-element multiplication of two vectors.

+
        
+     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
References blockSize.

+
+
Referenced by arm_dct4_f32(), and main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+
Referenced by arm_dct4_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References blockSize, and clip_q63_to_q31().

+
+
Referenced by arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___basic_sub.html b/CMSIS/Documentation/DSP/html/group___basic_sub.html
new file mode 100644
index 0000000000..61dce2c88c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___basic_sub.html
@@ -0,0 +1,363 @@
+
+
+
+
+Vector Subtraction
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Subtraction
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  

+
Description

+
Element-by-element subtraction of two vectors.

+
        
+     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References blockSize, and clip_q63_to_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___bilinear_interpolate.html b/CMSIS/Documentation/DSP/html/group___bilinear_interpolate.html
new file mode 100644
index 0000000000..a16dc072db
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___bilinear_interpolate.html
@@ -0,0 +1,344 @@
+
+
+
+
+Bilinear Interpolation
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Bilinear Interpolation
  

+
Interpolation Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
__STATIC_INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
 Floating-point bilinear interpolation.  
__STATIC_INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
 Q31 bilinear interpolation.  
__STATIC_INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
 Q15 bilinear interpolation.  
__STATIC_INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)
 Q7 bilinear interpolation.  

+
Description

+
Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. The underlying function f(x, y) is sampled on a regular grid and the interpolation process determines values between the grid points. Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. Bilinear interpolation is often used in image processing to rescale images. The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.

+
Algorithm 

+
The instance structure used by the bilinear interpolation functions describes a two dimensional data table. For floating-point, the instance structure is defined as: 
+   typedef struct
+   {
+     uint16_t numRows;
+     uint16_t numCols;
+     float32_t *pData;
+ } arm_bilinear_interp_instance_f32;
+ 

+
where numRows specifies the number of rows in the table; numCols specifies the number of columns in the table; and pData points to an array of size numRows*numCols values. The data table pTable is organized in row order and the supplied data values fall on integer indexes. That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.

+
Let (x, y) specify the desired interpolation point. Then define: 
+     XF = floor(x)
+     YF = floor(y)
+ 
 

+
The interpolated output point is computed as: 
+  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ 
 Note that the coordinates (x, y) contain integer and fractional components. The integer components specify which portion of the table to use while the fractional components control the interpolation processor.

+
if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 * S, 
float32_t X, 
float32_t Y 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate. 
[in]Yinterpolation coordinate. 

+  

+

+
Returns:
out interpolated value. 

+
+
References arm_bilinear_interp_instance_f32::numCols, arm_bilinear_interp_instance_f32::numRows, and arm_bilinear_interp_instance_f32::pData.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 * S, 
q31_t X, 
q31_t Y 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
References arm_bilinear_interp_instance_q15::numCols, arm_bilinear_interp_instance_q15::numRows, and arm_bilinear_interp_instance_q15::pData.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 * S, 
q31_t X, 
q31_t Y 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
References arm_bilinear_interp_instance_q31::numCols, arm_bilinear_interp_instance_q31::numRows, and arm_bilinear_interp_instance_q31::pData.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 * S, 
q31_t X, 
q31_t Y 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
References arm_bilinear_interp_instance_q7::numCols, arm_bilinear_interp_instance_q7::numRows, and arm_bilinear_interp_instance_q7::pData.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1.html b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1.html
new file mode 100644
index 0000000000..3bba0f97e7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1.html
@@ -0,0 +1,664 @@
+
+
+
+
+Biquad Cascade IIR Filters Using Direct Form I Structure
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using Direct Form I Structure
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  

+
Description

+
This set of functions implements arbitrary order recursive (IIR) filters. The filters are implemented as a cascade of second order Biquad sections. The functions support Q15, Q31 and floating-point data types. Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.

+
The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
    
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+

+Single Biquad filter stage

+ Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
    
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+

+8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Init Functions 
There is also an associated initialization function for each data type. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
    
+     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    
+     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    
+     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied.

+
Fixed-Point Behavior 
Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of coefficients:  Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift which allow the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+

+Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
    
+    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ 
 set the pCoeffs array to: 
    
+    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ 
 and set postShift=1

+
Filter gain:  The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
Overflow and saturation:  For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

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void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
References blockSize, arm_biquad_casd_df1_inst_f32::numStages, arm_biquad_casd_df1_inst_f32::pCoeffs, and arm_biquad_casd_df1_inst_f32::pState.

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void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.

+
Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure. 

+
+
References __SIMD32, arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.

+
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void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function arm_biquad_cascade_df1_init_q31() to initialize filter structure.

+
Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure. 

+
+
References arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.

+
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void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 * S, 
uint8_t numStages, 
float32_t * pCoeffs, 
float32_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients array. 
[in]*pStatepoints to the state array. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
    
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
References arm_biquad_casd_df1_inst_f32::numStages, arm_biquad_casd_df1_inst_f32::pCoeffs, and arm_biquad_casd_df1_inst_f32::pState.

+
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void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 * S, 
uint8_t numStages, 
q15_t * pCoeffs, 
q15_t * pState, 
int8_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied to the accumulator result. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
    
+     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 6*numStages values. The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.

+
The state variables are stored in the array pState. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
References arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.

+
+

+

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void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 * S, 
uint8_t numStages, 
q31_t * pCoeffs, 
q31_t * pState, 
int8_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
    
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.

+
+
Referenced by main().

+
+

+

+
+

+

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void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. Finally, the result is saturated to 1.15 format.

+
Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.

+
+

+

+
+

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+          
+          
+        
+      
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References blockSize, arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.

+
+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1__32x64.html b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1__32x64.html
new file mode 100644
index 0000000000..d791335810
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1__32x64.html
@@ -0,0 +1,310 @@
+
+
+
+
+High Precision Q31 Biquad Cascade Filter
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
High Precision Q31 Biquad Cascade Filter
  

+
Filtering Functions

+

+
+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+
Description

+
This function implements a high precision Biquad cascade filter which operates on Q31 data values. The filter coefficients are in 1.31 format and the state variables are in 1.63 format. The double precision state variables reduce quantization noise in the filter and provide a cleaner output. These filters are particularly useful when implementing filters in which the singularities are close to the unit circle. This is common for low pass or high pass filters with very low cutoff frequencies.

+
The function operates on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize Q31 values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
    
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+

+Single Biquad filter stage

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
    
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+

+8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array . Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. The state variables are arranged in the array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values of data in 1.63 format. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Function 
There is also an associated initialization function which performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the filter instance structure use 
    
+     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below. 

+
Fixed-Point Behavior 
Care must be taken while using Biquad Cascade 32x64 filter function. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Filter coefficients are represented as fractional values and restricted to lie in the range [-1 +1). The processing function has an additional scaling parameter postShift which allows the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+

+Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
    
+    {1.5, -0.8, 1.2, 1.6, -0.9}    
+ 
 set the Coefficient array to: 
    
+    {0.75, -0.4, 0.6, 0.8, -0.45}    
+ 
 and set postShift=1

+
The second thing to keep in mind is the gain through the filter. The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. This is described in the function specific documentation below. 

+
Function Documentation

+
+

+

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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 * S, 
uint8_t numStages, 
q31_t * pCoeffs, 
q63_t * pState, 
uint8_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the high precision Q31 Biquad cascade filter structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
    
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array and size of each state variable is 1.63 format. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the state array as: 
    
+     {x[n-1], x[n-2], y[n-1], y[n-2]}    
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References arm_biquad_cas_df1_32x64_ins_q31::numStages, arm_biquad_cas_df1_32x64_ins_q31::pCoeffs, arm_biquad_cas_df1_32x64_ins_q31::postShift, and arm_biquad_cas_df1_32x64_ins_q31::pState.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the high precision Q31 Biquad cascade filter. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Two related functions are provided in the CMSIS DSP library. arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References blockSize, mult32x64(), arm_biquad_cas_df1_32x64_ins_q31::numStages, arm_biquad_cas_df1_32x64_ins_q31::pCoeffs, arm_biquad_cas_df1_32x64_ins_q31::postShift, and arm_biquad_cas_df1_32x64_ins_q31::pState.

+
+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f2_t.html b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f2_t.html
new file mode 100644
index 0000000000..72a29f42d9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f2_t.html
@@ -0,0 +1,280 @@
+
+
+
+
+Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
  

+
Filtering Functions

+

+
+
+
+
+
+
+

+Functions
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  

+
Description

+
This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. The filters are implemented as a cascade of second order Biquad sections. These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. Only floating-point data is supported.

+
This function operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
       
+    y[n] = b0 * x[n] + d1       
+    d1 = b1 * x[n] + a1 * y[n] + d2       
+    d2 = b2 * x[n] + a2 * y[n]       
+ 
 where d1 and d2 represent the two state values.

+
A Biquad filter using a transposed Direct Form II structure is shown below. 

+BiquadDF2Transposed.gif
+

+Single transposed Direct Form II Biquad

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools flip the sign of the feedback coefficients: 
       
+    y[n] = b0 * x[n] + d1;       
+    d1 = b1 * x[n] - a1 * y[n] + d2;       
+    d2 = b2 * x[n] - a2 * y[n];       
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
pState points to the state variable array. Each Biquad stage has 2 state variables d1 and d2. The state variables are arranged in the pState array as: 
       
+     {d11, d12, d21, d22, ...}       
+ 
 where d1x refers to the state variables for the first Biquad and d2x refers to the state variables for the second Biquad. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. That is why the Direct Form I structure supports Q15 and Q31 data types. The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Functions 
There is also an associated initialization function. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the instance structure use 
       
+     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer. pCoeffs is the address of the coefficient buffer; 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+          
+        
+      
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the filter data structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References blockSize, arm_biquad_cascade_df2T_instance_f32::numStages, arm_biquad_cascade_df2T_instance_f32::pCoeffs, and arm_biquad_cascade_df2T_instance_f32::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 * S, 
uint8_t numStages, 
float32_t * pCoeffs, 
float32_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the filter data structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering: 

+
The coefficients are stored in the array pCoeffs in the following order: 
    
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 2 state variables d1, and d2. The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
References arm_biquad_cascade_df2T_instance_f32::numStages, arm_biquad_cascade_df2T_instance_f32::pCoeffs, and arm_biquad_cascade_df2T_instance_f32::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___c_f_f_t___c_i_f_f_t.html b/CMSIS/Documentation/DSP/html/group___c_f_f_t___c_i_f_f_t.html
new file mode 100644
index 0000000000..2d3912c8f2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___c_f_f_t___c_i_f_f_t.html
@@ -0,0 +1,243 @@
+
+
+
+
+Complex FFT Tables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables  

+  

+
Complex FFT Tables
  

+
Transform Functions

+

+
+
+
+
+
+
+

+Variables
const uint16_t armBitRevTable [1024]
const float32_t twiddleCoef [6144]
const q31_t twiddleCoefQ31 [6144]
const q15_t ALIGN4 twiddleCoefQ15 [6144]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const uint16_t armBitRevTable[1024]

+

+

+
Pseudo code for Generation of Bit reversal Table is 

+
for(l=1;l <= N/4;l++)    
+ {    
+   for(i=0;i<logN2;i++)    
+   {     
+     a[i]=l&(1<<i);    
+   }    
+   for(j=0; j<logN2; j++)    
+   {    
+     if (a[j]!=0)    
+     y[l]+=(1<<((logN2-1)-j));    
+   }    
+   y[l] = y[l] >> 1;    
+  } 
 

+
where N = 4096 logN2 = 12 

+
N is the maximum FFT Size supported 

+
+
Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), and arm_cfft_radix4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t twiddleCoef[6144]

+

+

+
Example code for Floating-point Twiddle factors Generation: 

+
for(i = 0; i< 3N/4; i++)    
+ {    
+	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
+	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
+ } 
 

+
where N = 4096 and PI = 3.14159265358979 

+
Cos and Sin values are in interleaved fashion 

+
+
Referenced by arm_cfft_radix2_init_f32(), and arm_cfft_radix4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 twiddleCoefQ15[6144]

+

+

+
Example code for Q15 Twiddle factors Generation:: 

+
for(i = 0; i< 3N/4; i++)    
+ {    
+	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);    
+	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);    
+ } 
 

+
where N = 4096 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q15(Fixed point 1.15): round(twiddleCoefQ15(i) * pow(2, 15)) 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t twiddleCoefQ31[6144]

+

+

+
Example code for Q31 Twiddle factors Generation:: 

+
for(i = 0; i< 3N/4; i++)    
+ {    
+    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
+    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
+ } 
 

+
where N = 4096 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q31(Fixed point 1.31): round(twiddleCoefQ31(i) * pow(2, 31)) 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix4_init_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___class_marks.html b/CMSIS/Documentation/DSP/html/group___class_marks.html
new file mode 100644
index 0000000000..579436fafa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___class_marks.html
@@ -0,0 +1,156 @@
+
+
+
+
+Class Marks Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Class Marks Example
  

+
Examples

+

+
Description: 

+
Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance and Matrix functions to calculate statistical values of marks obtained in a class.

+
Note:
This example also demonstrates the usage of static initialization.

+
Variables Description:

+
    
+
  • testMarks_f32 points to the marks scored by 20 students in 4 subjects 
    • 
+
  • max_marks Maximum of all marks 
    • 
+
  • min_marks Minimum of all marks 
    • 
+
  • mean Mean of all marks 
    • 
+
  • var Variance of the marks 
    • 
+
  • std Standard deviation of the marks 
    • 
+
  • numStudents Total number of students in the class
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_class_marks_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___cmplx_by_cmplx_mult.html b/CMSIS/Documentation/DSP/html/group___cmplx_by_cmplx_mult.html
new file mode 100644
index 0000000000..f80004dba5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___cmplx_by_cmplx_mult.html
@@ -0,0 +1,308 @@
+
+
+
+
+Complex-by-Complex Multiplication
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex-by-Complex Multiplication
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  

+
Description

+
Multiplies a complex vector by another complex vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values.

+
The underlying algorithm is used:

+
        
+ for(n=0; n<numSamples; n++) {        
+     pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];        
+     pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];        
+ }        
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
+      
void arm_cmplx_mult_cmplx_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
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+          
+          
+        
+      
void arm_cmplx_mult_cmplx_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+

+

+
+

+

+      
+        
+          
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+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mult_cmplx_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+
Referenced by arm_dct4_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___cmplx_by_real_mult.html b/CMSIS/Documentation/DSP/html/group___cmplx_by_real_mult.html
new file mode 100644
index 0000000000..b53ae11c34
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___cmplx_by_real_mult.html
@@ -0,0 +1,307 @@
+
+
+
+
+Complex-by-Real Multiplication
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex-by-Real Multiplication
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  

+
Description

+
Multiplies a complex vector by a real vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values while the real array has a total of numSamples real values.

+
The underlying algorithm is used:

+
        
+ for(n=0; n<numSamples; n++) {        
+     pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];        
+     pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];        
+ }        
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
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+        
+      
void arm_cmplx_mult_real_f32 (float32_t * pSrcCmplx, 
float32_t * pSrcReal, 
float32_t * pCmplxDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+        
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+      
void arm_cmplx_mult_real_q15 (q15_t * pSrcCmplx, 
q15_t * pSrcReal, 
q15_t * pCmplxDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32.

+
+

+

+
+

+

+      
+        
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+        
+      
void arm_cmplx_mult_real_q31 (q31_t * pSrcCmplx, 
q31_t * pSrcReal, 
q31_t * pCmplxDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References clip_q63_to_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___conv.html b/CMSIS/Documentation/DSP/html/group___conv.html
new file mode 100644
index 0000000000..2055032304
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___conv.html
@@ -0,0 +1,768 @@
+
+
+
+
+Convolution
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Convolution
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  

+
Description

+
Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. Convolution is similar to correlation and is frequently used in filtering and data analysis. The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. Then the convolution

+
    
+                   c[n] = a[n] * b[n]    
+ 
is defined as 

+ConvolutionEquation.gif
+

+ 

+
Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.

+
Conceptually, when two signals a[n] and b[n] are convolved, the signal b[n] slides over a[n]. For each offset n, the overlapping portions of a[n] and b[n] are multiplied and summed together.

+
Note that convolution is a commutative operation:

+
    
+                   a[n] * b[n] = b[n] * a[n].    
+ 
This means that switching the A and B arguments to the convolution functions has no effect.

+
Fixed-Point Behavior

+
Convolution requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used.

+
Fast Versions

+
Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires the input signals should be scaled down to avoid intermediate overflows.

+
Opt Versions

+
Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 

+
Function Documentation

+
+

+

+      
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+      
void arm_conv_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
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+        
+        
+          
+          
+          
+        
+      
void arm_conv_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
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+        
+      
void arm_conv_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 

+
+
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+        
+      
void arm_conv_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally.

+
See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+        
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+        
+        
+          
+          
+          
+        
+      
void arm_conv_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
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+        
+      
void arm_conv_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. 

+
+
References __PACKq7, __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+        
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+        
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+          
+          
+          
+        
+      
void arm_conv_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.

+
Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. 

+
+
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_conv_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_conv_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.

+
Refer the function arm_conv_opt_q7() for a faster implementation of this function. 

+
+
References srcALen, and srcBLen.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___convolution_example.html b/CMSIS/Documentation/DSP/html/group___convolution_example.html
new file mode 100644
index 0000000000..610a56eed9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___convolution_example.html
@@ -0,0 +1,163 @@
+
+
+
+
+Convolution Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Convolution Example
  

+
Examples

+

+
Description: 

+
Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex Multiplication, and Support Functions.

+
Algorithm:

+
The convolution theorem states that convolution in the time domain corresponds to multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of two signals is equal to the product of their individual Fourier transforms. The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). 

+
Two input signals, a[n] and b[n], with lengths n1 and n2 respectively, are zero padded so that their lengths become N, which is greater than or equal to (n1+n2-1) and is a power of 4 as FFT implementation is radix-4. The convolution of a[n] and b[n] is obtained by taking the FFT of the input signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of the multiplied result. 

+
This is denoted by the following equations: 
 A[k] = FFT(a[n],N)
+ B[k] = FFT(b[n],N)
+ conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
 where A[k] and B[k] are the N-point FFTs of the signals a[n] and b[n] respectively. The length of the convolved signal is (n1+n2-1).

+
Block Diagram:

+

+Convolution.gif
+

+

+
Variables Description:

+
    
+
  • testInputA_f32 points to the first input sequence 
    • 
+
  • srcALen length of the first input sequence 
    • 
+
  • testInputB_f32 points to the second input sequence 
    • 
+
  • srcBLen length of the second input sequence 
    • 
+
  • outLen length of convolution output sequence, (srcALen + srcBLen - 1) 
    • 
+
  • AxB points to the output array where the product of individual FFTs of inputs is stored.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_convolution_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___corr.html b/CMSIS/Documentation/DSP/html/group___corr.html
new file mode 100644
index 0000000000..6b12f61222
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___corr.html
@@ -0,0 +1,753 @@
+
+
+
+
+Correlation
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Correlation
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  
void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  
void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  

+
Description

+
Correlation is a mathematical operation that is similar to convolution. As with convolution, correlation uses two signals to produce a third signal. The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. Correlation is commonly used to measure the similarity between two signals. It has applications in pattern recognition, cryptanalysis, and searching. The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. Fast versions of the Q15 and Q31 functions are also provided.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. The convolution of the two signals is denoted by 
    
+                   c[n] = a[n] * b[n]    
+ 
 In correlation, one of the signals is flipped in time 
    
+                   c[n] = a[n] * b[-n]    
+ 

+
and this is mathematically defined as 

+CorrelateEquation.gif
+

+ 

+
The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.

+
Note 

+
The pDst should be initialized to all zeros before being used.

+
Fixed-Point Behavior 

+
Correlation requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used.

+
Fast Versions

+
Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires the input signals should be scaled down to avoid intermediate overflows.

+
Opt Versions

+
Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratchpoints to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally.

+
See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratchpoints to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.

+
Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. 

+
+
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References srcALen, and srcBLen.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_correlate_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.

+
Refer the function arm_correlate_opt_q7() for a faster implementation of this function. 

+
+
References srcALen, and srcBLen.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___d_c_t4___i_d_c_t4.html b/CMSIS/Documentation/DSP/html/group___d_c_t4___i_d_c_t4.html
new file mode 100644
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+
+
+
+
+DCT Type IV Functions
+
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+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
DCT Type IV Functions
  

+
Transform Functions

+

+
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+

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t Weights_8192 [16384]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]
static const float32_t cos_factors_8192 [8192]
static const q15_t ALIGN4 WeightsQ15_128 [256]
static const q15_t ALIGN4 WeightsQ15_512 [1024]
static const q15_t ALIGN4 WeightsQ15_2048 [4096]
static const q15_t ALIGN4 WeightsQ15_8192 [16384]
static const q15_t ALIGN4 cos_factorsQ15_128 [128]
static const q15_t ALIGN4 cos_factorsQ15_512 [512]
static const q15_t ALIGN4 cos_factorsQ15_2048 [2048]
static const q15_t ALIGN4 cos_factorsQ15_8192 [8192]
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t WeightsQ31_8192 [16384]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]
static const q31_t cos_factorsQ31_8192 [8192]

+Functions
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  

+
Description

+
Representation of signals by minimum number of values is important for storage and transmission. The possibility of large discontinuity between the beginning and end of a period of a signal in DFT can be avoided by extending the signal so that it is even-symmetric. Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the spectrum and is very widely used in signal and image coding applications. The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.

+
DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. Reordering of the input data makes the computation of DCT just a problem of computing the DFT of a real signal with a few additional operations. This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.

+
DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. DCT2 implementation can be described in the following steps:

+
    
+
  • Re-ordering input
    • 
+
  • Calculating Real FFT
    • 
+
  • Multiplication of weights and Real FFT output and getting real part from the product.
    • 
+

+
This process is explained by the block diagram below: 

+

+DCT4.gif
+

+Discrete Cosine Transform - type-IV

+
Algorithm: 
The N-point type-IV DCT is defined as a real, linear transformation by the formula: 

+DCT4Equation.gif
+

+ where k = 0,1,2,.....N-1 

+
Its inverse is defined as follows: 

+IDCT4Equation.gif
+

+ where n = 0,1,2,.....N-1 

+
The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). The symmetry of the transform matrix indicates that the fast algorithms for the forward and inverse transform computation are identical. Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.

+
Lengths supported by the transform: 
As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32(). The library provides separate functions for Q15, Q31, and floating-point data types. 

+
Instance Structure 
The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. A separate instance structure must be defined for each transform. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32(). 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
    
+arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    
+arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ 
 where N is the length of the DCT4; Nby2 is half of the length of the DCT4; normalize is normalizing factor used and is equal to sqrt(2/N); pTwiddle points to the twiddle factor table; pCosFactor points to the cosFactor table; pRfft points to the real FFT instance; pCfft points to the complex FFT instance; The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() and arm_rfft_f32() respectively for details regarding static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the DCT4 transform functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 

+
 for(i = 0; i< N; i++)    
+ {    
+    cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_2048[2048] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_512[512] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_8192[8192] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 cos_factorsQ15_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
 

+
C command to generate the table 
    
+ for(i = 0; i< N; i++)    
+ {    
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q15 format by multiplying with 2^31 and saturated if required. 

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 cos_factorsQ15_2048[2048] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 cos_factorsQ15_512[512] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 cos_factorsQ15_8192[8192] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 
    
+ for(i = 0; i< N; i++)    
+ {    
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q31 format by multiplying with 2^31 and saturated if required. 

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_2048[2048] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_512[512] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_8192[8192] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
    
+ for(i = 0; i< N; i++)    
+ {    
+    weights[2*i]= cos(i*c);    
+    weights[(2*i)+1]= -sin(i * c);    
+ } 
 

+
Where N is the Number of weights to be calculated and c is pi/(2*N) 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_2048[4096] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_512[1024] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_8192[16384] [static]

+

+

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 WeightsQ15_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
    
+ for(i = 0; i< N; i++)    
+ {    
+   weights[2*i]= cos(i*c);    
+   weights[(2*i)+1]= -sin(i * c);    
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Converted the output to q15 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 WeightsQ15_2048[4096] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 WeightsQ15_512[1024] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 WeightsQ15_8192[16384] [static]

+

+

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
    
+ for(i = 0; i< N; i++)    
+ {    
+   weights[2*i]= cos(i*c);    
+   weights[(2*i)+1]= -sin(i * c);    
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Convert the output to q31 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_2048[4096] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_512[1024] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_8192[16384] [static]

+

+

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dct4_f32 (const arm_dct4_instance_f32 * S, 
float32_t * pState, 
float32_t * pInlineBuffer 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point DCT4/IDCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
+
References arm_mult_f32(), arm_scale_f32(), arm_dct4_instance_f32::N, arm_dct4_instance_f32::Nby2, arm_dct4_instance_f32::pCosFactor, and arm_dct4_instance_f32::pTwiddle.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 * S, 
arm_rfft_instance_f32 * S_RFFT, 
arm_cfft_radix4_instance_f32 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
float32_t normalize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of floating-point DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of floating-point RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of floating-point CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Floating-point normalizing factors are mentioned in the table below for different DCT sizes: 

+dct4NormalizingF32Table.gif
+

+ 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_f32(), cos_factors_128, cos_factors_2048, cos_factors_512, cos_factors_8192, arm_dct4_instance_f32::N, arm_dct4_instance_f32::Nby2, arm_dct4_instance_f32::normalize, arm_dct4_instance_f32::pCfft, arm_dct4_instance_f32::pCosFactor, arm_dct4_instance_f32::pRfft, arm_dct4_instance_f32::pTwiddle, status, Weights_128, Weights_2048, Weights_512, and Weights_8192.

+
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+

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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 * S, 
arm_rfft_instance_q15 * S_RFFT, 
arm_cfft_radix4_instance_q15 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
q15_t normalize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q15 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of Q15 CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ15Table.gif
+

+ 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_q15(), cos_factorsQ15_128, cos_factorsQ15_2048, cos_factorsQ15_512, cos_factorsQ15_8192, arm_dct4_instance_q15::N, arm_dct4_instance_q15::Nby2, arm_dct4_instance_q15::normalize, arm_dct4_instance_q15::pCfft, arm_dct4_instance_q15::pCosFactor, arm_dct4_instance_q15::pRfft, arm_dct4_instance_q15::pTwiddle, status, WeightsQ15_128, WeightsQ15_2048, WeightsQ15_512, and WeightsQ15_8192.

+
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+

+
+

+

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arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 * S, 
arm_rfft_instance_q31 * S_RFFT, 
arm_cfft_radix4_instance_q31 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
q31_t normalize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q31 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q31 RFFT/RIFFT structure 
[in]*S_CFFTpoints to an instance of Q31 CFFT/CIFFT structure 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ31Table.gif
+

+ 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_q31(), cos_factorsQ31_128, cos_factorsQ31_2048, cos_factorsQ31_512, cos_factorsQ31_8192, arm_dct4_instance_q31::N, arm_dct4_instance_q31::Nby2, arm_dct4_instance_q31::normalize, arm_dct4_instance_q31::pCfft, arm_dct4_instance_q31::pCosFactor, arm_dct4_instance_q31::pRfft, arm_dct4_instance_q31::pTwiddle, status, WeightsQ31_128, WeightsQ31_2048, WeightsQ31_512, and WeightsQ31_8192.

+
+

+

+
+

+

+      
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+        
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+          
+          
+        
+      
void arm_dct4_q15 (const arm_dct4_instance_q15 * S, 
q15_t * pState, 
q15_t * pInlineBuffer 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 
Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ15Table.gif
+

+ 
+
References arm_mult_q15(), arm_shift_q15(), arm_dct4_instance_q15::N, arm_dct4_instance_q15::Nby2, arm_dct4_instance_q15::pCosFactor, and arm_dct4_instance_q15::pTwiddle.

+
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+

+
+

+

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+      
void arm_dct4_q31 (const arm_dct4_instance_q31 * S, 
q31_t * pState, 
q31_t * pInlineBuffer 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
Input an output formats: 
Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, as the conversion from DCT2 to DCT4 involves one subtraction. Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ31Table.gif
+

+ 
+
References arm_cmplx_mult_cmplx_q31(), arm_mult_q31(), arm_rfft_q31(), arm_shift_q31(), arm_dct4_instance_q31::N, arm_dct4_instance_q31::Nby2, arm_dct4_instance_q31::normalize, arm_dct4_instance_q31::pCosFactor, arm_dct4_instance_q31::pRfft, and arm_dct4_instance_q31::pTwiddle.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___dotproduct_example.html b/CMSIS/Documentation/DSP/html/group___dotproduct_example.html
new file mode 100644
index 0000000000..7acebaf502
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___dotproduct_example.html
@@ -0,0 +1,154 @@
+
+
+
+
+Dot Product Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Dot Product Example
  

+
Examples

+

+
Description: 

+
Demonstrates the use of the Multiply and Add functions to perform the dot product. The dot product of two vectors is obtained by multiplying corresponding elements and summing the products.

+
Algorithm:

+
The two input vectors A and B with length n, are multiplied element-by-element and then added to obtain dot product. 

+
This is denoted by the following equation: 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]

+
Block Diagram:

+

+dotProduct.gif
+

+

+
Variables Description:

+
    
+
  • srcA_buf_f32 points to first input vector 
    • 
+
  • srcB_buf_f32 points to second input vector 
    • 
+
  • testOutput stores dot product of the two input vectors.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_dotproduct_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r.html b/CMSIS/Documentation/DSP/html/group___f_i_r.html
new file mode 100644
index 0000000000..5144e8f128
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r.html
@@ -0,0 +1,777 @@
+
+
+
+
+Finite Impulse Response (FIR) Filters
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
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+
+
+
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+

+Functions
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  

+
Description

+
This set of functions implements Finite Impulse Response (FIR) filters for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize values.

+
Algorithm: 
The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. 
  
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  
+ 
 

+

+FIR.gif
+

+Finite Impulse Response filter

+ 

+
pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
  
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the following order. 

+
  
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
  
+arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  
+arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  
+arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  
+arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  
+ 

+
where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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void arm_fir_f32 (const arm_fir_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
References arm_fir_instance_f32::numTaps, arm_fir_instance_f32::pCoeffs, and arm_fir_instance_f32::pState.

+
+
Referenced by main().

+
+

+

+
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+

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+      
void arm_fir_fast_q15 (const arm_fir_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q15() to initialize the filter structure. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, and arm_fir_instance_q15::pState.

+
+

+

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void arm_fir_fast_q31 (const arm_fir_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.

+
Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q31() to initialize the filter structure. 

+
+
References arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.

+
+

+

+
+

+

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void arm_fir_init_f32 (arm_fir_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32(). 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
References arm_fir_instance_f32::numTaps, arm_fir_instance_f32::pCoeffs, and arm_fir_instance_f32::pState.

+
+
Referenced by main().

+
+

+

+
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+

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+      
arm_status arm_fir_init_q15 (arm_fir_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. Must be even and greater than or equal to 4. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizeis number of samples processed per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if numTaps is not greater than or equal to 4 and even.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 Note that numTaps must be even and greater than or equal to 4. To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. For example, to implement a filter with numTaps=3 and coefficients 
    
+     {0.3, -0.8, 0.3}    
+ 
 set numTaps=4 and use the coefficients: 
    
+     {0.3, -0.8, 0.3, 0}.    
+ 
 Similarly, to implement a two point filter 
    
+     {0.3, -0.3}    
+ 
 set numTaps=4 and use the coefficients: 
    
+     {0.3, -0.3, 0, 0}.    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, arm_fir_instance_q15::pState, and status.

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void arm_fir_init_q31 (arm_fir_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31(). 

+
+
References arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.

+
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void arm_fir_init_q7 (arm_fir_instance_q7 * S, 
uint16_t numTaps, 
q7_t * pCoeffs, 
q7_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). 

+
+
References arm_fir_instance_q7::numTaps, arm_fir_instance_q7::pCoeffs, and arm_fir_instance_q7::pState.

+
+

+

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void arm_fir_q15 (const arm_fir_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, and arm_fir_instance_q15::pState.

+
+

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void arm_fir_q31 (const arm_fir_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
References blockSize, arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.

+
+

+

+
+

+

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+      
void arm_fir_q7 (const arm_fir_instance_q7 * S, 
q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
References blockSize, arm_fir_instance_q7::numTaps, arm_fir_instance_q7::pCoeffs, and arm_fir_instance_q7::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r___interpolate.html b/CMSIS/Documentation/DSP/html/group___f_i_r___interpolate.html
new file mode 100644
index 0000000000..2d5dfda308
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r___interpolate.html
@@ -0,0 +1,552 @@
+
+
+
+
+Finite Impulse Response (FIR) Interpolator
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Interpolator
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  

+
Description

+
These functions combine an upsampler (zero stuffer) and an FIR filter. They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRInterpolator.gif
+

+Components included in the FIR Interpolator functions

+
 After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. The user of the function is responsible for providing the filter coefficients.

+
The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. The upsampler inserts L-1 zeros between each sample. Instead of multiplying by these zero values, the FIR filter is designed to skip them. This leads to an efficient implementation without any wasted effort. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize*L output values.

+
The library provides separate functions for Q15, Q31, and floating-point data types.

+
Algorithm: 
The functions use a polyphase filter structure: 
    
+    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    
+    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    
+    ...    
+    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    
+ 
 This approach is more efficient than straightforward upsample-then-filter algorithms. With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. 

+
pCoeffs points to a coefficient array of size numTaps. numTaps must be a multiple of the interpolation factor L and this is checked by the initialization functions. Internally, the function divides the FIR filter's impulse response into shorter filters of length phaseLength=numTaps/L. Coefficients are stored in time reversed order. 

+
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to a state array of size blockSize + phaseLength - 1. Samples in the state buffer are stored in the order: 

+
    
+    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the length of the filter is a multiple of the interpolation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
    
+ arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    
+ arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    
+ arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    
+ 
 where L is the interpolation factor; phaseLength=numTaps/L is the length of each of the shorter FIR filters used internally, pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
References arm_fir_interpolate_instance_f32::L, arm_fir_interpolate_instance_f32::pCoeffs, arm_fir_interpolate_instance_f32::phaseLength, and arm_fir_interpolate_instance_f32::pState.

+
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+

+
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arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 * S, 
uint8_t L, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_f32::L, arm_fir_interpolate_instance_f32::pCoeffs, arm_fir_interpolate_instance_f32::phaseLength, arm_fir_interpolate_instance_f32::pState, and status.

+
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+

+
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arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 * S, 
uint8_t L, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_q15::L, arm_fir_interpolate_instance_q15::pCoeffs, arm_fir_interpolate_instance_q15::phaseLength, arm_fir_interpolate_instance_q15::pState, and status.

+
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+

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arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 * S, 
uint8_t L, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_q31::L, arm_fir_interpolate_instance_q31::pCoeffs, arm_fir_interpolate_instance_q31::phaseLength, arm_fir_interpolate_instance_q31::pState, and status.

+
+

+

+
+

+

+      
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+          
+          
+          
+        
+      
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, arm_fir_interpolate_instance_q15::L, arm_fir_interpolate_instance_q15::pCoeffs, arm_fir_interpolate_instance_q15::phaseLength, and arm_fir_interpolate_instance_q15::pState.

+
+

+

+
+

+

+      
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+      
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). since numTaps/L additions occur per output sample. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
+
References arm_fir_interpolate_instance_q31::L, arm_fir_interpolate_instance_q31::pCoeffs, arm_fir_interpolate_instance_q31::phaseLength, and arm_fir_interpolate_instance_q31::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r___lattice.html b/CMSIS/Documentation/DSP/html/group___f_i_r___lattice.html
new file mode 100644
index 0000000000..4f79fc235e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r___lattice.html
@@ -0,0 +1,488 @@
+
+
+
+
+Finite Impulse Response (FIR) Lattice Filters
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Lattice Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  

+
Description

+
This set of functions implements Finite Impulse Response (FIR) lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure is feedforward and the net impulse response is finite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+FIRLattice.gif
+

+Finite Impulse Response Lattice filter

+ The following difference equation is implemented: 
    
+    f0[n] = g0[n] = x[n]    
+    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    
+    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    
+    y[n] = fM[n]    
+ 
 

+
pCoeffs points to tha array of reflection coefficients of size numStages. Reflection Coefficients are stored in the following order. 

+
    
+    {k1, k2, ..., kM}    
+ 
 where M is number of stages 

+
pState points to a state array of size numStages. The state variables (g values) hold previous inputs and are stored in the following order. 
    
+    {g0[n], g1[n], g2[n] ...gM-1[n]}    
+ 
 The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
    
+arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    
+arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    
+arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    
+ 
 

+
where numStages is the number of stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References blockSize, arm_fir_lattice_instance_f32::numStages, arm_fir_lattice_instance_f32::pCoeffs, and arm_fir_lattice_instance_f32::pState.

+
+

+

+
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+

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+      
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 * S, 
uint16_t numStages, 
float32_t * pCoeffs, 
float32_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
References arm_fir_lattice_instance_f32::numStages, arm_fir_lattice_instance_f32::pCoeffs, and arm_fir_lattice_instance_f32::pState.

+
+

+

+
+

+

+      
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void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 * S, 
uint16_t numStages, 
q15_t * pCoeffs, 
q15_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
References arm_fir_lattice_instance_q15::numStages, arm_fir_lattice_instance_q15::pCoeffs, and arm_fir_lattice_instance_q15::pState.

+
+

+

+
+

+

+      
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+      
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 * S, 
uint16_t numStages, 
q31_t * pCoeffs, 
q31_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
References arm_fir_lattice_instance_q31::numStages, arm_fir_lattice_instance_q31::pCoeffs, and arm_fir_lattice_instance_q31::pState.

+
+

+

+
+

+

+      
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+      
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, blockSize, arm_fir_lattice_instance_q15::numStages, arm_fir_lattice_instance_q15::pCoeffs, and arm_fir_lattice_instance_q15::pState.

+
+

+

+
+

+

+      
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+      
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. 

+
+
References arm_fir_lattice_instance_q31::numStages, arm_fir_lattice_instance_q31::pCoeffs, and arm_fir_lattice_instance_q31::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r___sparse.html b/CMSIS/Documentation/DSP/html/group___f_i_r___sparse.html
new file mode 100644
index 0000000000..dbb2b1dab3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r___sparse.html
@@ -0,0 +1,727 @@
+
+
+
+
+Finite Impulse Response (FIR) Sparse Filters
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Sparse Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  

+
Description

+
This group of functions implements sparse FIR filters. Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. Sparse filters are used for simulating reflections in communications and audio applications.

+
There are separate functions for Q7, Q15, Q31, and floating-point data types. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays respectively containing blockSize values.

+
Algorithm: 
The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. This is in addition to the coefficient array b. The implementation essentially skips the multiplications by zero and leads to an efficient realization. 
   
+     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    
+ 
 

+

+FIRSparse.gif
+

+Sparse FIR filter. b[n] represents the filter coefficients

+ 

+
pCoeffs points to a coefficient array of size numTaps; pTapDelay points to an array of nonzero indices and is also of size numTaps; pState points to a state array of size maxDelay + blockSize, where maxDelay is the largest offset value that is ever used in the pTapDelay array. Some of the processing functions also require temporary working buffers.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
    
+arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
+ 
 

+

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the sparse FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+        
+      
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
float32_t * pScratchIn, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
References arm_circularRead_f32(), arm_circularWrite_f32(), blockSize, arm_fir_sparse_instance_f32::maxDelay, arm_fir_sparse_instance_f32::numTaps, arm_fir_sparse_instance_f32::pCoeffs, arm_fir_sparse_instance_f32::pState, arm_fir_sparse_instance_f32::pTapDelay, and arm_fir_sparse_instance_f32::stateIndex.

+
+

+

+
+

+

+      
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+          
+          
+          
+        
+      
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_f32() function. 

+
+
References arm_fir_sparse_instance_f32::maxDelay, arm_fir_sparse_instance_f32::numTaps, arm_fir_sparse_instance_f32::pCoeffs, arm_fir_sparse_instance_f32::pState, arm_fir_sparse_instance_f32::pTapDelay, and arm_fir_sparse_instance_f32::stateIndex.

+
+

+

+
+

+

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+        
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+          
+          
+        
+      
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q15() function. 

+
+
References arm_fir_sparse_instance_q15::maxDelay, arm_fir_sparse_instance_q15::numTaps, arm_fir_sparse_instance_q15::pCoeffs, arm_fir_sparse_instance_q15::pState, arm_fir_sparse_instance_q15::pTapDelay, and arm_fir_sparse_instance_q15::stateIndex.

+
+

+

+
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+

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+          
+          
+        
+      
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q31() function. 

+
+
References arm_fir_sparse_instance_q31::maxDelay, arm_fir_sparse_instance_q31::numTaps, arm_fir_sparse_instance_q31::pCoeffs, arm_fir_sparse_instance_q31::pState, arm_fir_sparse_instance_q31::pTapDelay, and arm_fir_sparse_instance_q31::stateIndex.

+
+

+

+
+

+

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+        
+        
+          
+          
+          
+        
+      
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 * S, 
uint16_t numTaps, 
q7_t * pCoeffs, 
q7_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_q7() function. 

+
+
References arm_fir_sparse_instance_q7::maxDelay, arm_fir_sparse_instance_q7::numTaps, arm_fir_sparse_instance_q7::pCoeffs, arm_fir_sparse_instance_q7::pState, arm_fir_sparse_instance_q7::pTapDelay, and arm_fir_sparse_instance_q7::stateIndex.

+
+

+

+
+

+

+      
+        
+          
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+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
q15_t * pScratchIn, 
q31_t * pScratchOut, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. If the accumulator result overflows it will wrap around rather than saturate. After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
References __SIMD32, arm_circularRead_q15(), arm_circularWrite_q15(), blockSize, arm_fir_sparse_instance_q15::maxDelay, arm_fir_sparse_instance_q15::numTaps, arm_fir_sparse_instance_q15::pCoeffs, arm_fir_sparse_instance_q15::pState, arm_fir_sparse_instance_q15::pTapDelay, and arm_fir_sparse_instance_q15::stateIndex.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
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+        
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+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
q31_t * pScratchIn, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.31 x 1.31 multiplications are truncated to 2.30 format. This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. If the accumulator result overflows, it wraps around rather than saturate. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
References arm_circularRead_f32(), arm_circularWrite_f32(), blockSize, arm_fir_sparse_instance_q31::maxDelay, arm_fir_sparse_instance_q31::numTaps, arm_fir_sparse_instance_q31::pCoeffs, arm_fir_sparse_instance_q31::pState, arm_fir_sparse_instance_q31::pTapDelay, and arm_fir_sparse_instance_q31::stateIndex.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 * S, 
q7_t * pSrc, 
q7_t * pDst, 
q7_t * pScratchIn, 
q31_t * pScratchOut, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
References __PACKq7, __SIMD32, arm_circularRead_q7(), arm_circularWrite_q7(), blockSize, arm_fir_sparse_instance_q7::maxDelay, arm_fir_sparse_instance_q7::numTaps, arm_fir_sparse_instance_q7::pCoeffs, arm_fir_sparse_instance_q7::pState, arm_fir_sparse_instance_q7::pTapDelay, and arm_fir_sparse_instance_q7::stateIndex.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r__decimate.html b/CMSIS/Documentation/DSP/html/group___f_i_r__decimate.html
new file mode 100644
index 0000000000..d71971cc0f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r__decimate.html
@@ -0,0 +1,664 @@
+
+
+
+
+Finite Impulse Response (FIR) Decimator
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Decimator
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  

+
Description

+
These functions combine an FIR filter together with a decimator. They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRDecimator.gif
+

+Components included in the FIR Decimator functions

+
 When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized cutoff frequency of 1/M in order to prevent aliasing distortion. The user of the function is responsible for providing the filter coefficients.

+
The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the samples output by the decimator are computed. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize/M output values. In order to have an integer number of output samples blockSize must always be a multiple of the decimation factor M.

+
The library provides separate functions for Q15, Q31 and floating-point data types.

+
Algorithm: 
The FIR portion of the algorithm uses the standard form filter: 
    
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ 
 where, b[n] are the filter coefficients. 

+
The pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
    
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the size of the input is a multiple of the decimation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
    
+arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    
+arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    
+arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    
+ 
 where M is the decimation factor; numTaps is the number of filter coefficients in the filter; pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR decimate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
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+        
+      
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
References arm_fir_decimate_instance_f32::M, arm_fir_decimate_instance_f32::numTaps, arm_fir_decimate_instance_f32::pCoeffs, and arm_fir_decimate_instance_f32::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q15() to initialize the filter structure. 

+
+
References __SIMD32, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, and arm_fir_decimate_instance_q15::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).

+
Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q31() to initialize the filter structure. 

+
+
References arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, and arm_fir_decimate_instance_q31::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 * S, 
uint16_t numTaps, 
uint8_t M, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). M is the decimation factor. 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_f32::M, arm_fir_decimate_instance_f32::numTaps, arm_fir_decimate_instance_f32::pCoeffs, arm_fir_decimate_instance_f32::pState, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 * S, 
uint16_t numTaps, 
uint8_t M, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples to the call arm_fir_decimate_q15(). M is the decimation factor. 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, arm_fir_decimate_instance_q15::pState, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 * S, 
uint16_t numTaps, 
uint8_t M, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). M is the decimation factor. 

+
+
References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, arm_fir_decimate_instance_q31::pState, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, and arm_fir_decimate_instance_q15::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.

+
Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, and arm_fir_decimate_instance_q31::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___f_i_r_l_p_f.html b/CMSIS/Documentation/DSP/html/group___f_i_r_l_p_f.html
new file mode 100644
index 0000000000..73021b2745
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___f_i_r_l_p_f.html
@@ -0,0 +1,179 @@
+
+
+
+
+FIR Lowpass Filter Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
FIR Lowpass Filter Example
  

+
Examples

+

+
Description: 

+
Removes high frequency signal components from the input using an FIR lowpass filter. The example demonstrates how to configure an FIR filter and then pass data through it in a block-by-block fashion. 

+FIRLPF_signalflow.gif
+

+

+
Algorithm:

+
The input signal is a sum of two sine waves: 1 kHz and 15 kHz. This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. 

+
The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and a length of 29 points. The MATLAB code to generate the filter coefficients is shown below: 
+     h = fir1(28, 6/24);
+ 
 The first argument is the "order" of the filter and is always one less than the desired length. The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. The CMSIS FIR filter function requires the coefficients to be in time reversed order. 
+     fliplr(h)
+ 
 The resulting filter coefficients and are shown below. Note that the filter is symmetric (a property of linear phase FIR filters) and the point of symmetry is sample 14. Thus the filter will have a delay of 14 samples for all frequencies. 

+

+FIRLPF_coeffs.gif
+

+ 

+
The frequency response of the filter is shown next. The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. 

+

+FIRLPF_response.gif
+

+ 

+
The input signal is shown below. The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. The two sine wave components can be clearly seen. 

+

+FIRLPF_input.gif
+

+ 

+
The output of the filter is shown below. The 15 kHz component has been eliminated. 

+

+FIRLPF_output.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32_1kHz_15kHz points to the input data 
    • 
+
  • refOutput points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • firStateF32 points to state buffer 
    • 
+
  • firCoeffs32 points to coefficient buffer 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • numBlocks number of frames
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fir_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___fill.html b/CMSIS/Documentation/DSP/html/group___fill.html
new file mode 100644
index 0000000000..b9bcb16457
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___fill.html
@@ -0,0 +1,331 @@
+
+
+
+
+Vector Fill
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Fill
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  

+
Description

+
Fills the destination vector with a constant value.

+
    
+ 	pDst[n] = value;   0 <= n < blockSize.    
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fill_f32 (float32_t value, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_variance_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fill_q15 (q15_t value, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and blockSize.

+
+
Referenced by arm_conv_fast_opt_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_correlate_fast_opt_q15(), arm_correlate_opt_q15(), and arm_correlate_opt_q7().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fill_q31 (q31_t value, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fill_q7 (q7_t value, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___frequency_bin.html b/CMSIS/Documentation/DSP/html/group___frequency_bin.html
new file mode 100644
index 0000000000..d4bd81fb3b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___frequency_bin.html
@@ -0,0 +1,169 @@
+
+
+
+
+Frequency Bin Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Frequency Bin Example
  

+
Examples

+

+
Description

+
Demonstrates the calculation of the maximum energy bin in the frequency domain of the input signal with the use of Complex FFT, Complex Magnitude, and Maximum functions.

+
Algorithm:

+
The input test signal contains a 10 kHz signal with uniformly distributed white noise. Calculating the FFT of the input signal will give us the maximum energy of the bin corresponding to the input frequency of 10 kHz.

+
Block Diagram:

+FFTBin.gif
+

+Block Diagram

+ 

+
The figure below shows the time domain signal of 10 kHz signal with uniformly distributed white noise, and the next figure shows the input in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. 

+

+FFTBinInput.gif
+

+Input signal in Time domain

+ 

+FFTBinOutput.gif
+

+Input signal in Frequency domain

+ 

+
Variables Description:

+
    
+
  • testInput_f32_10khz points to the input data 
    • 
+
  • testOutput points to the output data 
    • 
+
  • fftSize length of FFT 
    • 
+
  • ifftFlag flag for the selection of CFFT/CIFFT 
    • 
+
  • doBitReverse Flag for selection of normal order or bit reversed order 
    • 
+
  • refIndex reference index value at which maximum energy of bin ocuurs 
    • 
+
  • testIndex calculated index value at which maximum energy of bin ocuurs
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fft_bin_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___g_e_q5_band.html b/CMSIS/Documentation/DSP/html/group___g_e_q5_band.html
new file mode 100644
index 0000000000..1a67daa956
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___g_e_q5_band.html
@@ -0,0 +1,188 @@
+
+
+
+
+Graphic Audio Equalizer Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Graphic Audio Equalizer Example
  

+
Examples

+

+
Description: 

+
This example demonstrates how a 5-band graphic equalizer can be constructed using the Biquad cascade functions. A graphic equalizer is used in audio applications to vary the tonal quality of the audio.

+
Block Diagram:

+
The design is based on a cascade of 5 filter sections. 

+GEQ_signalflow.gif
+

+ Each filter section is 4th order and consists of a cascade of two Biquads. Each filter has a nominal gain of 0 dB (1.0 in linear units) and boosts or cuts signals within a specific frequency range. The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. Each band has an adjustable boost or cut in the range of +/- 9 dB. For example, the band that extends from 500 to 2000 Hz has the response shown below: 

+

+GEQ_bandresponse.gif
+

+ 

+
With 1 dB steps, each filter has a total of 19 different settings. The filter coefficients for all possible 19 settings were precomputed in MATLAB and stored in a table. With 5 different tables, there are a total of 5 x 19 = 95 different 4th order filters. All 95 responses are shown below: 

+

+GEQ_allbandresponse.gif
+

+ 

+
Each 4th order filter has 10 coefficents for a grand total of 950 different filter coefficients that must be tabulated. The input and output data is in Q31 format. For better noise performance, the two low frequency bands are implemented using the high precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. 

+

+GEQ_inputchirp.gif
+

+ 

+
The array bandGains specifies the gain in dB to apply in each band. For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: 

+

+GEQ_outputchirp.gif
+

+ 

+

+
Note:
The output chirp signal follows the gain or boost of each band. 

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • testRefOutput_f32 points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • inputQ31 temporary input buffer 
    • 
+
  • outputQ31 temporary output buffer 
    • 
+
  • biquadStateBand1Q31 points to state buffer for band1 
    • 
+
  • biquadStateBand2Q31 points to state buffer for band2 
    • 
+
  • biquadStateBand3Q31 points to state buffer for band3 
    • 
+
  • biquadStateBand4Q31 points to state buffer for band4 
    • 
+
  • biquadStateBand5Q31 points to state buffer for band5 
    • 
+
  • coeffTable points to coefficient buffer for all bands 
    • 
+
  • gainDB gain buffer which has gains applied for all the bands
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_graphic_equalizer_example_q31.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___i_i_r___lattice.html b/CMSIS/Documentation/DSP/html/group___i_i_r___lattice.html
new file mode 100644
index 0000000000..e63a8d811c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___i_i_r___lattice.html
@@ -0,0 +1,533 @@
+
+
+
+
+Infinite Impulse Response (IIR) Lattice Filters
+
+
+
+
+
+
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+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Infinite Impulse Response (IIR) Lattice Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
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+
+
+
+
+
+
+

+Functions
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  

+
Description

+
This set of functions implements lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure has feedforward and feedback components and the net impulse response is infinite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+IIRLattice.gif
+

+Infinite Impulse Response Lattice filter

+ 
    
+    fN(n)   =  x(n)    
+    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    
+    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    
+    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    
+ 
 

+
pkCoeffs points to array of reflection coefficients of size numStages. Reflection coefficients are stored in time-reversed order. 

+
    
+    {kN, kN-1, ....k1}    
+ 
 pvCoeffs points to the array of ladder coefficients of size (numStages+1). Ladder coefficients are stored in time-reversed order. 

+
    
+    {vN, vN-1, ...v0}    
+ 
 pState points to a state array of size numStages + blockSize. The state variables shown in the figure above (the g values) are stored in the pState array. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
    
+arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    
+ 
 

+
where numStages is the number of stages in the filter; pState points to the state buffer array; pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the IIR lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References blockSize, arm_iir_lattice_instance_f32::numStages, arm_iir_lattice_instance_f32::pkCoeffs, arm_iir_lattice_instance_f32::pState, and arm_iir_lattice_instance_f32::pvCoeffs.

+
+

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void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 * S, 
uint16_t numStages, 
float32_t * pkCoeffs, 
float32_t * pvCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References arm_iir_lattice_instance_f32::numStages, arm_iir_lattice_instance_f32::pkCoeffs, arm_iir_lattice_instance_f32::pState, and arm_iir_lattice_instance_f32::pvCoeffs.

+
+

+

+
+

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void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 * S, 
uint16_t numStages, 
q15_t * pkCoeffs, 
q15_t * pvCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
References arm_iir_lattice_instance_q15::numStages, arm_iir_lattice_instance_q15::pkCoeffs, arm_iir_lattice_instance_q15::pState, and arm_iir_lattice_instance_q15::pvCoeffs.

+
+

+

+
+

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+      
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void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 * S, 
uint16_t numStages, 
q31_t * pkCoeffs, 
q31_t * pvCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References arm_iir_lattice_instance_q31::numStages, arm_iir_lattice_instance_q31::pkCoeffs, arm_iir_lattice_instance_q31::pState, and arm_iir_lattice_instance_q31::pvCoeffs.

+
+

+

+
+

+

+      
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+      
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, blockSize, arm_iir_lattice_instance_q15::numStages, arm_iir_lattice_instance_q15::pkCoeffs, arm_iir_lattice_instance_q15::pState, and arm_iir_lattice_instance_q15::pvCoeffs.

+
+

+

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void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. 

+
+
References blockSize, clip_q63_to_q31(), arm_iir_lattice_instance_q31::numStages, arm_iir_lattice_instance_q31::pkCoeffs, arm_iir_lattice_instance_q31::pState, and arm_iir_lattice_instance_q31::pvCoeffs.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___l_m_s.html b/CMSIS/Documentation/DSP/html/group___l_m_s.html
new file mode 100644
index 0000000000..d76d28b62c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___l_m_s.html
@@ -0,0 +1,612 @@
+
+
+
+
+Least Mean Square (LMS) Filters
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Least Mean Square (LMS) Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  

+
Description

+
LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. Adaptive filters are often used in communication systems, equalizers, and noise removal. The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.

+
An LMS filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The LMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+

+Internal structure of the Least Mean Square filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
    
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
    
+     e[n] = d[n] - y[n].    
+ 

+
After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: 
    
+     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
    
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
    
+    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    
+    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    
+    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    
+ 
 where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

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+        
+      
void arm_lms_f32 (const arm_lms_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pRef, 
float32_t * pOut, 
float32_t * pErr, 
uint32_t blockSize 
)

+

+

+
This function operates on floating-point data types.

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
References blockSize, arm_lms_instance_f32::mu, arm_lms_instance_f32::numTaps, arm_lms_instance_f32::pCoeffs, and arm_lms_instance_f32::pState.

+
+

+

+
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+        
+      
void arm_lms_init_f32 (arm_lms_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
float32_t mu, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). 

+
+
References arm_lms_instance_f32::mu, arm_lms_instance_f32::numTaps, arm_lms_instance_f32::pCoeffs, and arm_lms_instance_f32::pState.

+
+

+

+
+

+

+      
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+        
+        
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+          
+          
+        
+      
void arm_lms_init_q15 (arm_lms_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
q15_t mu, 
uint32_t blockSize, 
uint32_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q15(). 

+
+
References arm_lms_instance_q15::mu, arm_lms_instance_q15::numTaps, arm_lms_instance_q15::pCoeffs, arm_lms_instance_q15::postShift, and arm_lms_instance_q15::pState.

+
+

+

+
+

+

+      
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+        
+        
+          
+          
+          
+        
+      
void arm_lms_init_q31 (arm_lms_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
q31_t mu, 
uint32_t blockSize, 
uint32_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q31(). 

+
+
References arm_lms_instance_q31::mu, arm_lms_instance_q31::numTaps, arm_lms_instance_q31::pCoeffs, arm_lms_instance_q31::postShift, and arm_lms_instance_q31::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
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+        
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_q15 (const arm_lms_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pRef, 
q15_t * pOut, 
q15_t * pErr, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
References __SIMD32, blockSize, arm_lms_instance_q15::mu, arm_lms_instance_q15::numTaps, arm_lms_instance_q15::pCoeffs, arm_lms_instance_q15::postShift, and arm_lms_instance_q15::pState.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_q31 (const arm_lms_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pRef, 
q31_t * pOut, 
q31_t * pErr, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clips. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
References blockSize, clip_q63_to_q31(), arm_lms_instance_q31::mu, arm_lms_instance_q31::numTaps, arm_lms_instance_q31::pCoeffs, arm_lms_instance_q31::postShift, and arm_lms_instance_q31::pState.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___l_m_s___n_o_r_m.html b/CMSIS/Documentation/DSP/html/group___l_m_s___n_o_r_m.html
new file mode 100644
index 0000000000..56c32e3f71
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___l_m_s___n_o_r_m.html
@@ -0,0 +1,619 @@
+
+
+
+
+Normalized LMS Filters
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Normalized LMS Filters
  

+
Filtering Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  

+
Description

+
This set of functions implements a commonly used adaptive filter. It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization factor which increases the adaptation rate of the filter. The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.

+
A normalized least mean square (NLMS) filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The NLMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+

+Internal structure of the NLMS adaptive filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
    
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
    
+     e[n] = d[n] - y[n].    
+ 

+
After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: 
    
+    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    
+ 
 The filter coefficients b[k] are then updated on a sample-by-sample basis: 
    
+     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
    
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+        
+      
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pRef, 
float32_t * pOut, 
float32_t * pErr, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
References blockSize, arm_lms_norm_instance_f32::energy, arm_lms_norm_instance_f32::mu, arm_lms_norm_instance_f32::numTaps, arm_lms_norm_instance_f32::pCoeffs, arm_lms_norm_instance_f32::pState, and arm_lms_norm_instance_f32::x0.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
float32_t mu, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
References arm_lms_norm_instance_f32::energy, arm_lms_norm_instance_f32::mu, arm_lms_norm_instance_f32::numTaps, arm_lms_norm_instance_f32::pCoeffs, arm_lms_norm_instance_f32::pState, and arm_lms_norm_instance_f32::x0.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
q15_t mu, 
uint32_t blockSize, 
uint8_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q15(). 

+
+
References armRecipTableQ15, arm_lms_norm_instance_q15::energy, arm_lms_norm_instance_q15::mu, arm_lms_norm_instance_q15::numTaps, arm_lms_norm_instance_q15::pCoeffs, arm_lms_norm_instance_q15::postShift, arm_lms_norm_instance_q15::pState, arm_lms_norm_instance_q15::recipTable, and arm_lms_norm_instance_q15::x0.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
q31_t mu, 
uint32_t blockSize, 
uint8_t postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). 

+
+
References armRecipTableQ31, arm_lms_norm_instance_q31::energy, arm_lms_norm_instance_q31::mu, arm_lms_norm_instance_q31::numTaps, arm_lms_norm_instance_q31::pCoeffs, arm_lms_norm_instance_q31::postShift, arm_lms_norm_instance_q31::pState, arm_lms_norm_instance_q31::recipTable, and arm_lms_norm_instance_q31::x0.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pRef, 
q15_t * pOut, 
q15_t * pErr, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
References __SIMD32, arm_recip_q15(), blockSize, DELTA_Q15, arm_lms_norm_instance_q15::energy, arm_lms_norm_instance_q15::mu, arm_lms_norm_instance_q15::numTaps, arm_lms_norm_instance_q15::pCoeffs, arm_lms_norm_instance_q15::postShift, arm_lms_norm_instance_q15::pState, arm_lms_norm_instance_q15::recipTable, and arm_lms_norm_instance_q15::x0.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
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+        
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+          
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+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pRef, 
q31_t * pOut, 
q31_t * pErr, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
References arm_recip_q31(), blockSize, clip_q63_to_q31(), DELTA_Q31, arm_lms_norm_instance_q31::energy, arm_lms_norm_instance_q31::mu, arm_lms_norm_instance_q31::numTaps, arm_lms_norm_instance_q31::pCoeffs, arm_lms_norm_instance_q31::postShift, arm_lms_norm_instance_q31::pState, arm_lms_norm_instance_q31::recipTable, and arm_lms_norm_instance_q31::x0.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___linear_interp_example.html b/CMSIS/Documentation/DSP/html/group___linear_interp_example.html
new file mode 100644
index 0000000000..0088e47c7e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___linear_interp_example.html
@@ -0,0 +1,160 @@
+
+
+
+
+Linear Interpolate Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Linear Interpolate Example
  

+
Examples

+

+
 CMSIS DSP Software Library -- Linear Interpolate Example 

+
 Description  This example demonstrates usage of linear interpolate modules and fast math modules. Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses linear interpolation function and results are compared to reference output. Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.

+
Block Diagram:

+

+linearInterpExampleMethod1.gif
+

+Method 1: Sine caluclation using fast math

+ 

+

+linearInterpExampleMethod2.gif
+

+Method 2: Sine caluclation using interpolation function

+ 

+
Variables Description:

+
    
+
  • testInputSin_f32 points to the input values for sine calculation 
    • 
+
  • testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function 
    • 
+
  • testOutput points to output buffer calculation from cubic interpolation 
    • 
+
  • testLinIntOutput points to output buffer calculation from linear interpolation 
    • 
+
  • snr1 Signal to noise ratio for reference and cubic interpolation output 
    • 
+
  • snr2 Signal to noise ratio for reference and linear interpolation output
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_linear_interp_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___linear_interpolate.html b/CMSIS/Documentation/DSP/html/group___linear_interpolate.html
new file mode 100644
index 0000000000..6ae14acda6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___linear_interpolate.html
@@ -0,0 +1,329 @@
+
+
+
+
+Linear Interpolation
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Linear Interpolation
  

+
Interpolation Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
__STATIC_INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
 Process function for the floating-point Linear Interpolation Function.  
__STATIC_INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q31 Linear Interpolation Function.  
__STATIC_INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q15 Linear Interpolation Function.  
__STATIC_INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q7 Linear Interpolation Function.  

+
Description

+
Linear interpolation is a method of curve fitting using linear polynomials. Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line

+

+LinearInterp.gif
+

+Linear interpolation

+ 

+
A Linear Interpolate function calculates an output value(y), for the input(x) using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)

+
Algorithm:
+       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+       where x0, x1 are nearest values of input x
+             y0, y1 are nearest values to output y
+ 

+
This set of functions implements Linear interpolation process for Q7, Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the Linear Interpolate function data structure. x is the input sample value. The functions returns the output value.

+
if x is outside of the table boundary, Linear interpolation returns first value of the table if x is below input range and returns last value of table if x is above range. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+      
__STATIC_INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 * S, 
float32_t x 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point Linear Interpolation structure 
[in]xinput sample to process 

+  

+

+
Returns:
y processed output sample. 

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
References arm_linear_interp_instance_f32::nValues, arm_linear_interp_instance_f32::pYData, arm_linear_interp_instance_f32::x1, and arm_linear_interp_instance_f32::xSpacing.

+
+
Referenced by main().

+
+

+

+
+

+

+      
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+          
+        
+      
__STATIC_INLINE q15_t arm_linear_interp_q15 (q15_t * pYData, 
q31_t x, 
uint32_t nValues 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q15 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+

+

+
+

+

+      
+        
+          
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+        
+      
__STATIC_INLINE q31_t arm_linear_interp_q31 (q31_t * pYData, 
q31_t x, 
uint32_t nValues 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q31 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+        
+          
+          
+          
+        
+      
__STATIC_INLINE q7_t arm_linear_interp_q7 (q7_t * pYData, 
q31_t x, 
uint32_t nValues 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q7 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_add.html b/CMSIS/Documentation/DSP/html/group___matrix_add.html
new file mode 100644
index 0000000000..78426c9859
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_add.html
@@ -0,0 +1,286 @@
+
+
+
+
+Matrix Addition
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Matrix Addition
  

+
Matrix Functions

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  

+
Description

+
Adds two matrices. 

+

+MatrixAddition.gif
+

+Addition of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+      
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
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+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_example.html b/CMSIS/Documentation/DSP/html/group___matrix_example.html
new file mode 100644
index 0000000000..a439f836ec
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_example.html
@@ -0,0 +1,158 @@
+
+
+
+
+Matrix Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Matrix Example
  

+
Examples

+

+
Description: 

+
Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse functions to apply least squares fitting to input data. Least squares fitting is the procedure for finding the best-fitting curve that minimizes the sum of the squares of the offsets (least square error) from a given set of data.

+
Algorithm:

+
The linear combination of parameters considered is as follows: 

+
A * X = B, where X is the unknown value and can be estimated from A & B. 

+
The least squares estimate X is given by the following equation: 

+
X = Inverse(AT * A) * AT * B

+
Block Diagram:

+

+matrixExample.gif
+

+

+
Variables Description:

+
    
+
  • A_f32 input matrix in the linear combination equation 
    • 
+
  • B_f32 output matrix in the linear combination equation 
    • 
+
  • X_f32 unknown matrix estimated using A_f32 & B_f32 matrices
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_matrix_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_init.html b/CMSIS/Documentation/DSP/html/group___matrix_init.html
new file mode 100644
index 0000000000..d74a00b708
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_init.html
@@ -0,0 +1,301 @@
+
+
+
+
+Matrix Initialization
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Matrix Initialization
  

+
Matrix Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  

+
Description

+
Initializes the underlying matrix data structure. The functions set the numRows, numCols, and pData fields of the matrix data structure. 

+
Function Documentation

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void arm_mat_init_f32 (arm_matrix_instance_f32 * S, 
uint16_t nRows, 
uint16_t nColumns, 
float32_t * pData 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
References arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, and arm_matrix_instance_f32::pData.

+
+
Referenced by main().

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void arm_mat_init_q15 (arm_matrix_instance_q15 * S, 
uint16_t nRows, 
uint16_t nColumns, 
q15_t * pData 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
References arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, and arm_matrix_instance_q15::pData.

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void arm_mat_init_q31 (arm_matrix_instance_q31 * S, 
uint16_t nRows, 
uint16_t nColumns, 
q31_t * pData 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
References arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, and arm_matrix_instance_q31::pData.

+
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+

+

+

+  
+
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diff --git a/CMSIS/Documentation/DSP/html/group___matrix_inv.html b/CMSIS/Documentation/DSP/html/group___matrix_inv.html
new file mode 100644
index 0000000000..b69c68957b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_inv.html
@@ -0,0 +1,188 @@
+
+
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+
+Matrix Inverse
+
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+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

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+    
+

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+
+  
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+  
+  

+  

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+  

+Functions  

+  

+
Matrix Inverse
  

+
Matrix Functions

+

+
+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix inverse.  

+
Description

+
Computes the inverse of a matrix.

+
The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). The function checks that the input and output matrices are square and of the same size.

+
Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix inversion of floating-point matrices.

+
Algorithm 
The Gauss-Jordan method is used to find the inverse. The algorithm performs a sequence of elementary row-operations till it reduces the input matrix to an identity matrix. Applying the same sequence of elementary row-operations to an identity matrix yields the inverse matrix. If the input matrix is singular, then the algorithm terminates and returns error status ARM_MATH_SINGULAR. 

+MatrixInverse.gif
+

+Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method

+ 

+
Function Documentation

+
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arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 * pSrc, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size of the output matrix does not match the size of the input matrix. If the input matrix is found to be singular (non-invertible), then the function returns ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
References ARM_MATH_SINGULAR, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
+
Referenced by main().

+
+

+

+

+

+  
+
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+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_mult.html b/CMSIS/Documentation/DSP/html/group___matrix_mult.html
new file mode 100644
index 0000000000..b83fd95667
--- /dev/null
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+
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+
+Matrix Multiplication
+
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+

+
+

+
+ 
+ 
+  
+  
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+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Matrix Multiplication
  

+
Matrix Functions

+

+
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+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication.  
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  

+
Description

+
Multiplies two matrices.

+

+MatrixMultiplication.gif
+

+Multiplication of two 3 x 3 matrices

+
Matrix multiplication is only defined if the number of columns of the first matrix equals the number of rows of the second matrix. Multiplying an M x N matrix with an N x P matrix results in an M x P matrix. When matrix size checking is enabled, the functions check: (1) that the inner dimensions of pSrcA and pSrcB are equal; and (2) that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. 

+
Function Documentation

+
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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
+
Referenced by main().

+
+

+

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arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst, 
q15_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q15() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.15 x 1.15 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.15 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 16 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q15() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

+
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arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q31() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst, 
q15_t * pState 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The inputs to the multiplications are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

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arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. The input is thus scaled down by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are performed internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
+

+

+

+

+  
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+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_scale.html b/CMSIS/Documentation/DSP/html/group___matrix_scale.html
new file mode 100644
index 0000000000..7b1ee1db41
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_scale.html
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+
+
+
+
+Matrix Scale
+
+
+
+
+
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+
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+
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+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

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+

+  

+Functions  

+  

+
Matrix Scale
  

+
Matrix Functions

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  

+
Description

+
Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the matrix by the scalar. For example: 

+

+MatrixScale.gif
+

+Matrix Scaling of a 3 x 3 matrix

+
The function checks to make sure that the input and output matrices are of the same size.

+
In the fixed-point Q15 and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The overall scale factor applied to the fixed-point data is 

+
        
+     scale = scaleFract * 2^shift.        
+ 
 
Function Documentation

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arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 * pSrc, 
float32_t scale, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[in]scalescale factor to be applied 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
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arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 * pSrc, 
q15_t scaleFract, 
int32_t shift, 
arm_matrix_instance_q15 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
References _SIMD32_OFFSET, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

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arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 * pSrc, 
q31_t scaleFract, 
int32_t shift, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_sub.html b/CMSIS/Documentation/DSP/html/group___matrix_sub.html
new file mode 100644
index 0000000000..0ff58bf6e0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_sub.html
@@ -0,0 +1,286 @@
+
+
+
+
+Matrix Subtraction
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Matrix Subtraction
  

+
Matrix Functions

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  

+
Description

+
Subtract two matrices. 

+

+MatrixSubtraction.gif
+

+Subraction of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___matrix_trans.html b/CMSIS/Documentation/DSP/html/group___matrix_trans.html
new file mode 100644
index 0000000000..2f39dd86fd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___matrix_trans.html
@@ -0,0 +1,263 @@
+
+
+
+
+Matrix Transpose
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Matrix Transpose
  

+
Matrix Functions

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  

+
Description

+
Tranposes a matrix. Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. 

+

+MatrixTranspose.gif
+

+Transpose of a 3 x 3 matrix

+ 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 * pSrc, 
arm_matrix_instance_f32 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 * pSrc, 
arm_matrix_instance_q15 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 * pSrc, 
arm_matrix_instance_q31 * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___max.html b/CMSIS/Documentation/DSP/html/group___max.html
new file mode 100644
index 0000000000..a86b476731
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___max.html
@@ -0,0 +1,346 @@
+
+
+
+
+Maximum
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Maximum
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  

+
Description

+
Computes the maximum value of an array of data. The function returns both the maximum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_max_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_max_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_max_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_max_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___min.html b/CMSIS/Documentation/DSP/html/group___min.html
new file mode 100644
index 0000000000..fd3a28be40
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___min.html
@@ -0,0 +1,346 @@
+
+
+
+
+Minimum
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Minimum
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Minimum value of a Q7 vector.  

+
Description

+
Computes the minimum value of an array of data. The function returns both the minimum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_min_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_min_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_min_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_min_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult, 
uint32_t * pIndex 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___p_i_d.html b/CMSIS/Documentation/DSP/html/group___p_i_d.html
new file mode 100644
index 0000000000..eeefb0e388
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___p_i_d.html
@@ -0,0 +1,495 @@
+
+
+
+
+PID Motor Control
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
PID Motor Control
  

+
Controller Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  
__STATIC_INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
 Process function for the floating-point PID Control.  
__STATIC_INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
 Process function for the Q31 PID Control.  
__STATIC_INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
 Process function for the Q15 PID Control.  

+
Description

+
A Proportional Integral Derivative (PID) controller is a generic feedback control loop mechanism widely used in industrial control systems. A PID controller is the most commonly used type of feedback controller.

+
This set of functions implements (PID) controllers for Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the PID control data structure. in is the input sample value. The functions return the output value.

+
Algorithm:
+    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+    A0 = Kp + Ki + Kd
+    A1 = (-Kp ) - (2 * Kd )
+    A2 = Kd  

+
where Kp is proportional constant, Ki is Integral constant and Kd is Derivative constant

+

+PID.gif
+

+Proportional Integral Derivative Controller

+

+
The PID controller calculates an "error" value as the difference between the measured output and the reference input. The controller attempts to minimize the error by adjusting the process control inputs. The proportional value determines the reaction to the current error, the integral value determines the reaction based on the sum of recent errors, and the derivative value determines the reaction based on the rate at which the error has been changing.

+
Instance Structure 
The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. A separate instance structure must be defined for each PID Controller. There are separate instance structure declarations for each of the 3 supported data types.

+
Reset Functions 
There is also an associated reset function for each data type which clears the state array.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the PID Controller functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

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__STATIC_INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 * S, 
float32_t in 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample. 

+
+
References arm_pid_instance_f32::A0, arm_pid_instance_f32::A1, arm_pid_instance_f32::A2, and arm_pid_instance_f32::state.

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void arm_pid_init_f32 (arm_pid_instance_f32 * S, 
int32_t resetStateFlag 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state & 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
References arm_pid_instance_f32::A0, arm_pid_instance_f32::A1, arm_pid_instance_f32::A2, arm_pid_instance_f32::Kd, arm_pid_instance_f32::Ki, arm_pid_instance_f32::Kp, and arm_pid_instance_f32::state.

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void arm_pid_init_q15 (arm_pid_instance_q15 * S, 
int32_t resetStateFlag 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
References arm_pid_instance_q15::A0, arm_pid_instance_q15::A1, arm_pid_instance_q15::Kd, arm_pid_instance_q15::Ki, arm_pid_instance_q15::Kp, and arm_pid_instance_q15::state.

+
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void arm_pid_init_q31 (arm_pid_instance_q31 * S, 
int32_t resetStateFlag 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
References arm_pid_instance_q31::A0, arm_pid_instance_q31::A1, arm_pid_instance_q31::A2, clip_q63_to_q31(), arm_pid_instance_q31::Kd, arm_pid_instance_q31::Ki, arm_pid_instance_q31::Kp, and arm_pid_instance_q31::state.

+
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__STATIC_INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 * S, 
q15_t in 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, arm_pid_instance_q15::A0, arm_pid_instance_q15::A1, and arm_pid_instance_q15::state.

+
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__STATIC_INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 * S, 
q31_t in 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
+
References arm_pid_instance_q31::A0, arm_pid_instance_q31::A1, arm_pid_instance_q31::A2, and arm_pid_instance_q31::state.

+
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+

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void arm_pid_reset_f32 (arm_pid_instance_f32 * S)

+

+

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
References arm_pid_instance_f32::state.

+
+

+

+
+

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void arm_pid_reset_q15 (arm_pid_instance_q15 * S)

+

+

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
References arm_pid_instance_q15::state.

+
+

+

+
+

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void arm_pid_reset_q31 (arm_pid_instance_q31 * S)

+

+

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
References arm_pid_instance_q31::state.

+
+

+

+

+

+  
+
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+Partial Convolution
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CMSIS-DSP
+    Verison 1.1.0
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+   
CMSIS DSP Software Library

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+Functions  

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Partial Convolution
  

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Filtering Functions

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+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  
arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  
arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  
arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  

+
Description

+
Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. Each function has two additional arguments. firstIndex specifies the starting index of the subset of output samples. numPoints is the number of output samples to compute. The function computes the output in the range [firstIndex, ..., firstIndex+numPoints-1]. The output array pDst contains numPoints values.

+
The allowable range of output indices is [0 srcALen+srcBLen-2]. If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. Otherwise the functions return ARM_MATH_SUCCESS. 

+
Note:
Refer arm_conv_f32() for details on fixed point behavior.

+
Fast Versions

+
Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires the input signals should be scaled down to avoid intermediate overflows.

+
Opt Versions

+
Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution 

+
Function Documentation

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arm_status arm_conv_partial_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
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arm_status arm_conv_partial_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

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arm_status arm_conv_partial_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
References __SIMD32, _SIMD32_OFFSET, ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
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arm_status arm_conv_partial_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

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arm_status arm_conv_partial_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit

+
Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
+

+

+
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+      
arm_status arm_conv_partial_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit 

+
+
References __PACKq7, __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
+

+

+
+

+

+      
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+      
arm_status arm_conv_partial_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.

+
Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. 

+
+
References __SIMD32, _SIMD32_OFFSET, ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
+

+

+
+

+

+      
+        
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+        
+        
+          
+          
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+        
+        
+          
+          
+          
+        
+      
arm_status arm_conv_partial_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+        
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+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_conv_partial_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___r_f_f_t___r_i_f_f_t.html b/CMSIS/Documentation/DSP/html/group___r_f_f_t___r_i_f_f_t.html
new file mode 100644
index 0000000000..0bfa69b638
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___r_f_f_t___r_i_f_f_t.html
@@ -0,0 +1,679 @@
+
+
+
+
+Real FFT Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
Real FFT Functions
  

+
Transform Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const float32_t realCoefA [8192]
static const float32_t realCoefB [8192]
static const q15_t ALIGN4 realCoefAQ15 [8192]
static const q15_t ALIGN4 realCoefBQ15 [8192]
static const q31_t realCoefAQ31 [8192]
static const q31_t realCoefBQ31 [8192]

+Functions
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  

+
Description

+
Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain. Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.

+
This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT) for Q15, Q31, and floating-point data types.

+
Algorithm: 

+
Real Fast Fourier Transform: 

+
Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure. 

+

+RFFT.gif
+

+Real Fast Fourier Transform

+ 

+
The RFFT functions operate on blocks of input and output data and each call to the function processes fftLenR samples through the transform. pSrc points to input array containing fftLenR values. pDst points to output array containing 2*fftLenR values. 

+ Input for real FFT is in the order of 
{real[0], real[1], real[2], real[3], ..}
 Output for real FFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}

+
Real Inverse Fast Fourier Transform: 

+
Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure. 

+

+RIFFT.gif
+

+Real Inverse Fast Fourier Transform

+ 

+
The RIFFT functions operate on blocks of input and output data and each call to the function processes 2*fftLenR samples through the transform. pSrc points to input array containing 2*fftLenR values. pDst points to output array containing fftLenR values. 

+ Input for real IFFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}
 Output for real IFFT is real and in the order of 
{real[0], real[1], real[2], real[3], ..}

+
Lengths supported by the transform: 

+
Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor tables.
    • 
+
  • Initializes CFFT data structure fields. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
    
+arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
+ 
 where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT. ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT); bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order); twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table; pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients; pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding static initialization of cfft structure.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the RFFT/RIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefA[8192] [static]

+

+

+
Generation of realCoefA array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+  {    
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+  } 
 

+
+
Referenced by arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 realCoefAQ15[8192] [static]

+

+

+
Generation floating point real_CoefA array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+  {    
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+  } 
 

+
Convert to fixed point Q15 format round(pATable[i] * pow(2, 15)) 

+
+
Referenced by arm_rfft_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefAQ31[8192] [static]

+

+

+
Generation floating point realCoefAQ31 array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+ {    
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+ }
 

+
Convert to fixed point Q31 format round(pATable[i] * pow(2, 31)) 

+
+
Referenced by arm_rfft_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefB[8192] [static]

+

+

+
Generation of realCoefB array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+ {    
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+  } 
 

+
+
Referenced by arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t ALIGN4 realCoefBQ15[8192] [static]

+

+

+
Generation of real_CoefB array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+  {    
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+  } 
 

+
Convert to fixed point Q15 format round(pBTable[i] * pow(2, 15)) 

+
+
Referenced by arm_rfft_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefBQ31[8192] [static]

+

+

+
Generation of realCoefBQ31 array: 

+
n = 4096 
for (i = 0; i < n; i++)    
+ {    
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
+ } 
 

+
Convert to fixed point Q31 format round(pBTable[i] * pow(2, 31)) 

+
+
Referenced by arm_rfft_init_q31().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_rfft_f32 (const arm_rfft_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none. 

+
+
References arm_bitreversal_f32(), arm_radix4_butterfly_f32(), arm_radix4_butterfly_inverse_f32(), arm_split_rfft_f32(), arm_split_rifft_f32(), arm_rfft_instance_f32::bitReverseFlagR, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, arm_rfft_instance_f32::fftLenBy2, arm_rfft_instance_f32::ifftFlagR, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_rfft_instance_f32::pCfft, arm_cfft_radix4_instance_f32::pTwiddle, arm_rfft_instance_f32::pTwiddleAReal, arm_rfft_instance_f32::pTwiddleBReal, arm_cfft_radix4_instance_f32::twidCoefModifier, and arm_rfft_instance_f32::twidCoefRModifier.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 * S, 
arm_cfft_radix4_instance_f32 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
References arm_cfft_radix4_init_f32(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_f32::bitReverseFlagR, arm_rfft_instance_f32::fftLenBy2, arm_rfft_instance_f32::fftLenReal, arm_rfft_instance_f32::ifftFlagR, arm_rfft_instance_f32::pCfft, arm_rfft_instance_f32::pTwiddleAReal, arm_rfft_instance_f32::pTwiddleBReal, realCoefA, realCoefB, status, and arm_rfft_instance_f32::twidCoefRModifier.

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
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+          
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arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 * S, 
arm_cfft_radix4_instance_q15 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
References arm_cfft_radix4_init_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_q15::bitReverseFlagR, arm_rfft_instance_q15::fftLenBy2, arm_rfft_instance_q15::fftLenReal, arm_rfft_instance_q15::ifftFlagR, arm_rfft_instance_q15::pCfft, arm_rfft_instance_q15::pTwiddleAReal, arm_rfft_instance_q15::pTwiddleBReal, realCoefAQ15, realCoefBQ15, status, and arm_rfft_instance_q15::twidCoefRModifier.

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+          
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+        
+      
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 * S, 
arm_cfft_radix4_instance_q31 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
References arm_cfft_radix4_init_q31(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_q31::bitReverseFlagR, arm_rfft_instance_q31::fftLenBy2, arm_rfft_instance_q31::fftLenReal, arm_rfft_instance_q31::ifftFlagR, arm_rfft_instance_q31::pCfft, arm_rfft_instance_q31::pTwiddleAReal, arm_rfft_instance_q31::pTwiddleBReal, realCoefAQ31, realCoefBQ31, status, and arm_rfft_instance_q31::twidCoefRModifier.

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_rfft_q15 (const arm_rfft_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ15.gif
+

+Input and Output Formats for Q15 RFFT

+ 

+

+RIFFTQ15.gif
+

+Input and Output Formats for Q15 RIFFT

+ 

+
+
References arm_bitreversal_q15(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_split_rfft_q15(), arm_split_rifft_q15(), arm_rfft_instance_q15::bitReverseFlagR, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, arm_rfft_instance_q15::fftLenBy2, arm_rfft_instance_q15::ifftFlagR, arm_cfft_radix4_instance_q15::pBitRevTable, arm_rfft_instance_q15::pCfft, arm_cfft_radix4_instance_q15::pTwiddle, arm_rfft_instance_q15::pTwiddleAReal, arm_rfft_instance_q15::pTwiddleBReal, arm_cfft_radix4_instance_q15::twidCoefModifier, and arm_rfft_instance_q15::twidCoefRModifier.

+
+

+

+
+

+

+      
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+        
+      
void arm_rfft_q31 (const arm_rfft_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ31.gif
+

+Input and Output Formats for Q31 RFFT

+

+

+RIFFTQ31.gif
+

+Input and Output Formats for Q31 RIFFT

+ 

+
+
References arm_bitreversal_q31(), arm_radix4_butterfly_inverse_q31(), arm_radix4_butterfly_q31(), arm_split_rfft_q31(), arm_split_rifft_q31(), arm_rfft_instance_q31::bitReverseFlagR, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, arm_rfft_instance_q31::fftLenBy2, arm_rfft_instance_q31::ifftFlagR, arm_cfft_radix4_instance_q31::pBitRevTable, arm_rfft_instance_q31::pCfft, arm_cfft_radix4_instance_q31::pTwiddle, arm_rfft_instance_q31::pTwiddleAReal, arm_rfft_instance_q31::pTwiddleBReal, arm_cfft_radix4_instance_q31::twidCoefModifier, and arm_rfft_instance_q31::twidCoefRModifier.

+
+
Referenced by arm_dct4_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___r_m_s.html b/CMSIS/Documentation/DSP/html/group___r_m_s.html
new file mode 100644
index 0000000000..01cb033266
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___r_m_s.html
@@ -0,0 +1,284 @@
+
+
+
+
+Root mean square (RMS)
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Root mean square (RMS)
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  

+
Description

+
Calculates the Root Mean Sqaure of the elements in the input vector. The underlying algorithm is used:

+
    
+ 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
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+        
+      
void arm_rms_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none. 

+
+
References arm_sqrt_f32(), and blockSize.

+
+

+

+
+

+

+      
+        
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+        
+      
void arm_rms_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, arm_sqrt_q15(), and blockSize.

+
+

+

+
+

+

+      
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+          
+        
+      
void arm_rms_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows, it wraps around and distorts the result. In order to avoid overflows completely, the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
References arm_sqrt_q31(), and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___radix2___c_f_f_t___c_i_f_f_t.html b/CMSIS/Documentation/DSP/html/group___radix2___c_f_f_t___c_i_f_f_t.html
new file mode 100644
index 0000000000..8cf8777b99
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___radix2___c_f_f_t___c_i_f_f_t.html
@@ -0,0 +1,486 @@
+
+
+
+
+Radix-2 Complex FFT Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Radix-2 Complex FFT Functions
  

+
Transform Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-2 CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  
arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  

+
Description

+
Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 

+
This set of functions implements CFFT/CIFFT for Q15, Q31, and floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output. Complex input is stored in input buffer in an interleaved fashion.

+
The functions operate on blocks of input and output data and each call to the function processes 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values. 

+
The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 

+
Lengths supported by the transform: 

+
Internally, the function utilize a radix-2 decimation in frequency(DIF) algorithm and the size of the FFT supported are of the lengths [16, 32, 64, 128, 256, 512, 1024, 2048, 4096].

+
Algorithm: 

+
Complex Fast Fourier Transform: 

+
Input real and imaginary data: 
   
+ x(n) = xa + j * ya   
+ x(n+N/2 ) = xb + j * yb   
+ 
 where N is length of FFT 

+
Output real and imaginary data: 
   
+ X(2r) = xa'+ j * ya'   
+ X(2r+1) = xb'+ j * yb'   
+ 
 

+
Twiddle factors for radix-2 FFT: 
   
+ Wn = cosVal + j * (- sinVal)   
+ 

+

+CFFT_Radix2.gif
+

+Radix-2 Decimation-in Frequency Complex Fast Fourier Transform

+

+
Output from Radix-2 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output. 

+
 Butterfly CFFT equations: 
   
+ xa' = xa + xb  
+ ya' = ya + yb  
+ xb' = (xa-xb)* cosVal + (ya-yb) * sinVal   
+ yb' = (ya-yb)* cosVal - (xa-xb) * sinVal   
+ 

+
Complex Inverse Fast Fourier Transform: 

+
CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.

+
 Modified Butterfly CIFFT equations: 
   
+ xa' = xa + xb  
+ ya' = ya + yb  
+ xb' = (xa-xb)* cosVal - (ya-yb) * sinVal   
+ yb' = (ya-yb)* cosVal + (xa-xb) * sinVal   
+ 

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor table and bit reversal table pointers 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_cfft_radix2_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ 
 

+
where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT); bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT;

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the CFFT/CIFFT function. Refer to the function specific documentation below for usage guidelines.

+
Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
+        
+          
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+        
+      
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 * S, 
float32_t * pSrc 
)

+

+

+
Processing function for the floating-point CFFT/CIFFT.

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the floating-point Radix-2 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
+
References arm_bitreversal_f32(), arm_radix2_butterfly_f32(), arm_radix2_butterfly_inverse_f32(), arm_cfft_radix2_instance_f32::bitReverseFlag, arm_cfft_radix2_instance_f32::bitRevFactor, arm_cfft_radix2_instance_f32::fftLen, arm_cfft_radix2_instance_f32::ifftFlag, arm_cfft_radix2_instance_f32::onebyfftLen, arm_cfft_radix2_instance_f32::pBitRevTable, arm_cfft_radix2_instance_f32::pTwiddle, and arm_cfft_radix2_instance_f32::twidCoefModifier.

+
+

+

+
+

+

+      
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+          
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+          
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+        
+        
+          
+          
+          
+        
+      
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_f32::bitReverseFlag, arm_cfft_radix2_instance_f32::bitRevFactor, arm_cfft_radix2_instance_f32::fftLen, ifftFlag, arm_cfft_radix2_instance_f32::ifftFlag, arm_cfft_radix2_instance_f32::onebyfftLen, arm_cfft_radix2_instance_f32::pBitRevTable, arm_cfft_radix2_instance_f32::pTwiddle, status, arm_cfft_radix2_instance_f32::twidCoefModifier, and twiddleCoef.

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arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_q15::bitReverseFlag, arm_cfft_radix2_instance_q15::bitRevFactor, arm_cfft_radix2_instance_q15::fftLen, ifftFlag, arm_cfft_radix2_instance_q15::ifftFlag, arm_cfft_radix2_instance_q15::pBitRevTable, arm_cfft_radix2_instance_q15::pTwiddle, status, arm_cfft_radix2_instance_q15::twidCoefModifier, and twiddleCoefQ15.

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arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Initialization function for the Radix-2 Q31 CFFT/CIFFT.

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_q31::bitReverseFlag, arm_cfft_radix2_instance_q31::bitRevFactor, arm_cfft_radix2_instance_q31::fftLen, ifftFlag, arm_cfft_radix2_instance_q31::ifftFlag, arm_cfft_radix2_instance_q31::pBitRevTable, arm_cfft_radix2_instance_q31::pTwiddle, status, arm_cfft_radix2_instance_q31::twidCoefModifier, and twiddleCoefQ31.

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void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 * S, 
q15_t * pSrc 
)

+

+

+
Processing function for the Q15 CFFT/CIFFT.

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the fixed-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
+
References arm_bitreversal_q15(), arm_radix2_butterfly_inverse_q15(), arm_radix2_butterfly_q15(), arm_cfft_radix2_instance_q15::bitRevFactor, arm_cfft_radix2_instance_q15::fftLen, arm_cfft_radix2_instance_q15::ifftFlag, arm_cfft_radix2_instance_q15::pBitRevTable, arm_cfft_radix2_instance_q15::pTwiddle, and arm_cfft_radix2_instance_q15::twidCoefModifier.

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void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 * S, 
q31_t * pSrc 
)

+

+

+
Processing function for the Radix-2 Q31 CFFT/CIFFT.

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the fixed-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
+
References arm_bitreversal_q31(), arm_radix2_butterfly_inverse_q31(), arm_radix2_butterfly_q31(), arm_cfft_radix2_instance_q31::bitRevFactor, arm_cfft_radix2_instance_q31::fftLen, arm_cfft_radix2_instance_q31::ifftFlag, arm_cfft_radix2_instance_q31::pBitRevTable, arm_cfft_radix2_instance_q31::pTwiddle, and arm_cfft_radix2_instance_q31::twidCoefModifier.

+
+

+

+

+

+  
+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/group___radix4___c_f_f_t___c_i_f_f_t.html b/CMSIS/Documentation/DSP/html/group___radix4___c_f_f_t___c_i_f_f_t.html
new file mode 100644
index 0000000000..090c9aa3a8
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+Radix-4 Complex FFT Functions
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CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

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+    
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+Functions  

+  

+
Radix-4 Complex FFT Functions
  

+
Transform Functions

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+Functions
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-4 CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  

+
Description

+
Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 

+
This set of functions implements CFFT/CIFFT for Q15, Q31, and floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output. Complex input is stored in input buffer in an interleaved fashion.

+
The functions operate on blocks of input and output data and each call to the function processes 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values. 

+
The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 

+
Lengths supported by the transform: 

+
Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm and the size of the FFT supported are of the lengths [16, 64, 256, 1024].

+
Algorithm: 

+
Complex Fast Fourier Transform: 

+
Input real and imaginary data: 
    
+ x(n) = xa + j * ya    
+ x(n+N/4 ) = xb + j * yb    
+ x(n+N/2 ) = xc + j * yc    
+ x(n+3N 4) = xd + j * yd    
+ 
 where N is length of FFT 

+
Output real and imaginary data: 
    
+ X(4r) = xa'+ j * ya'    
+ X(4r+1) = xb'+ j * yb'    
+ X(4r+2) = xc'+ j * yc'    
+ X(4r+3) = xd'+ j * yd'    
+ 
 

+
Twiddle factors for radix-4 FFT: 
    
+ Wn = co1 + j * (- si1)    
+ W2n = co2 + j * (- si2)    
+ W3n = co3 + j * (- si3)    
+ 

+

+CFFT.gif
+

+Radix-4 Decimation-in Frequency Complex Fast Fourier Transform

+

+
Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output. 

+
 Butterfly CFFT equations: 
    
+ xa' = xa + xb + xc + xd    
+ ya' = ya + yb + yc + yd    
+ xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
+ yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
+ xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
+ yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
+ xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
+ yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
+ 

+
Complex Inverse Fast Fourier Transform: 

+
CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.

+
 Modified Butterfly CIFFT equations: 
    
+ xa' = xa + xb + xc + xd    
+ ya' = ya + yb + yc + yd    
+ xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
+ yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
+ xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
+ yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
+ xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
+ yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
+ 

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor table and bit reversal table pointers 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
    
+arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};    
+arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
+arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
+ 
 

+
where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT); bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT;

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the CFFT/CIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
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void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 * S, 
float32_t * pSrc 
)

+

+

+
Processing function for the floating-point CFFT/CIFFT.

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the floating-point Radix-4 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
References arm_bitreversal_f32(), arm_radix4_butterfly_f32(), arm_radix4_butterfly_inverse_f32(), arm_cfft_radix4_instance_f32::bitReverseFlag, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, arm_cfft_radix4_instance_f32::ifftFlag, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_cfft_radix4_instance_f32::pTwiddle, and arm_cfft_radix4_instance_f32::twidCoefModifier.

+
+
Referenced by main().

+
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arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_f32::bitReverseFlag, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, ifftFlag, arm_cfft_radix4_instance_f32::ifftFlag, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_cfft_radix4_instance_f32::pTwiddle, status, arm_cfft_radix4_instance_f32::twidCoefModifier, and twiddleCoef.

+
+
Referenced by arm_rfft_init_f32(), and main().

+
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arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_q15::bitReverseFlag, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, ifftFlag, arm_cfft_radix4_instance_q15::ifftFlag, arm_cfft_radix4_instance_q15::pBitRevTable, arm_cfft_radix4_instance_q15::pTwiddle, status, arm_cfft_radix4_instance_q15::twidCoefModifier, and twiddleCoefQ15.

+
+
Referenced by arm_rfft_init_q15().

+
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arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_q31::bitReverseFlag, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, ifftFlag, arm_cfft_radix4_instance_q31::ifftFlag, arm_cfft_radix4_instance_q31::pBitRevTable, arm_cfft_radix4_instance_q31::pTwiddle, status, arm_cfft_radix4_instance_q31::twidCoefModifier, and twiddleCoefQ31.

+
+
Referenced by arm_rfft_init_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 * S, 
q15_t * pSrc 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ15.gif
+

+Input and Output Formats for Q15 CFFT

+ 

+CIFFTQ15.gif
+

+Input and Output Formats for Q15 CIFFT

+ 

+
+
References arm_bitreversal_q15(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_cfft_radix4_instance_q15::bitReverseFlag, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, arm_cfft_radix4_instance_q15::ifftFlag, arm_cfft_radix4_instance_q15::pBitRevTable, arm_cfft_radix4_instance_q15::pTwiddle, and arm_cfft_radix4_instance_q15::twidCoefModifier.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 * S, 
q31_t * pSrc 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ31.gif
+

+Input and Output Formats for Q31 CFFT

+ 

+CIFFTQ31.gif
+

+Input and Output Formats for Q31 CIFFT

+ 

+
+
References arm_bitreversal_q31(), arm_radix4_butterfly_inverse_q31(), arm_radix4_butterfly_q31(), arm_cfft_radix4_instance_q31::bitReverseFlag, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, arm_cfft_radix4_instance_q31::ifftFlag, arm_cfft_radix4_instance_q31::pBitRevTable, arm_cfft_radix4_instance_q31::pTwiddle, and arm_cfft_radix4_instance_q31::twidCoefModifier.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___s_q_r_t.html b/CMSIS/Documentation/DSP/html/group___s_q_r_t.html
new file mode 100644
index 0000000000..0b7338dcdf
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___s_q_r_t.html
@@ -0,0 +1,268 @@
+
+
+
+
+Square Root
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Square Root
  

+
Fast Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  
__STATIC_INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
 Floating-point square root function.  

+
Description

+
Computes the square root of a number. There are separate functions for Q15, Q31, and floating-point data types. The square root function is computed using the Newton-Raphson algorithm. This is an iterative algorithm of the form: 

+
+      x1 = x0 - f(x0)/f'(x0)
+ 
 where x1 is the current estimate, x0 is the previous estimate and f'(x0) is the derivative of f() evaluated at x0. For the square root function, the algorithm reduces to: 

+
+     x0 = in/2                         [initial guess]
+     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE arm_status arm_sqrt_f32 (float32_t in, 
float32_t * pOut 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]ininput value. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.

+
+
Referenced by arm_cmplx_mag_f32(), arm_rms_f32(), and arm_std_f32().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q15 (q15_t in, 
q15_t * pOut 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.

+
+
Referenced by arm_cmplx_mag_q15(), arm_rms_q15(), and arm_std_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q31 (q31_t in, 
q31_t * pOut 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.

+
+
Referenced by arm_cmplx_mag_q31(), arm_rms_q31(), and arm_std_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___s_t_d.html b/CMSIS/Documentation/DSP/html/group___s_t_d.html
new file mode 100644
index 0000000000..543504e1f5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___s_t_d.html
@@ -0,0 +1,287 @@
+
+
+
+
+Standard deviation
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Standard deviation
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  

+
Description

+
Calculates the standard deviation of the elements in the input vector. The underlying algorithm is used:

+
    
+ 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
References arm_sqrt_f32(), blockSize, mean, and var.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, arm_sqrt_q15(), blockSize, and mean.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
References arm_sqrt_q31(), blockSize, and mean.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___signal_convergence.html b/CMSIS/Documentation/DSP/html/group___signal_convergence.html
new file mode 100644
index 0000000000..2f1c8e64eb
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___signal_convergence.html
@@ -0,0 +1,165 @@
+
+
+
+
+Signal Convergence Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Signal Convergence Example
  

+
Examples

+

+
Description: 

+
Demonstrates the ability of an adaptive filter to "learn" the transfer function of a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse Response (FIR) Filter, and Basic Math Functions.

+
Algorithm:

+
The figure below illustrates the signal flow in this example. Uniformly distributed white noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the reference input of the adaptive filter (normalized LMS filter). The white noise is input to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and (2) the error signal which is the difference between the adaptive filter and the reference output of the FIR filter. Over time as the adaptive filter learns the transfer function of the FIR filter, the first output approaches the reference output of the FIR filter, and the error signal approaches zero. 

+
The adaptive filter converges properly even if the input signal has a large dynamic range (i.e., varies from small to large values). The coefficients of the adaptive filter are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() implements the stopping condition. The function checks if all of the values of the error signal have a magnitude below a threshold DELTA.

+
Block Diagram:

+

+SignalFlow.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • firStateF32 points to FIR state buffer 
    • 
+
  • lmsStateF32 points to Normalised Least mean square FIR filter state buffer 
    • 
+
  • FIRCoeff_f32 points to coefficient buffer 
    • 
+
  • lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • errOutput, err_signal temporary error buffers
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_signal_converge_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___sin_cos.html b/CMSIS/Documentation/DSP/html/group___sin_cos.html
new file mode 100644
index 0000000000..99f8ee0c03
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___sin_cos.html
@@ -0,0 +1,326 @@
+
+
+
+
+Sine Cosine
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
Sine Cosine
  

+
Controller Functions

+

+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
 Floating-point sin_cos function.  
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  

+
Description

+
Computes the trigonometric sine and cosine values using a combination of table lookup and linear interpolation. There are separate functions for Q31 and floating-point data types. The input to the floating-point version is in degrees while the fixed-point Q31 have a scaled input with the range [-1 0.9999] mapping to [-180 179] degrees.

+
The implementation is based on table lookup using 360 values together with linear interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index.
    2. 
+
  2. Compute the fractional portion (fract) of the input.
    3. 
+
  3. Fetch the value corresponding to index from sine table to y0 and also value from index+1 to y1.
    4. 
+
  4. Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).
    5. 
+
  5. Fetch the value corresponding to index from cosine table to y0 and also value from index+1 to y1.
    6. 
+
  6. Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)). 
    7. 
+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)    
+ {    
+    cosTable[i]= cos((i-180) * PI/180.0);    
+ } 
 

+
+
Referenced by arm_sin_cos_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t cosTableQ31[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)    
+ {    
+    cosTable[i]= cos((i-180) * PI/180.0);    
+ } 
 

+
Convert above coefficients to fixed point 1.31 format. 

+
+
Referenced by arm_sin_cos_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)    
+ {    
+    sinTable[i]= sin((i-180) * PI/180.0);    
+ } 
 

+
+
Referenced by arm_sin_cos_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t sinTableQ31[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)    
+ {    
+    sinTable[i]= sin((i-180) * PI/180.0);    
+ } 
 Convert above coefficients to fixed point 1.31 format. 

+
+
Referenced by arm_sin_cos_q31().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sin_cos_f32 (float32_t theta, 
float32_t * pSinVal, 
float32_t * pCosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]thetainput value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cos output. 

+  

+

+
Returns:
none. 

+
+
References cosTable, and sinTable.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sin_cos_q31 (q31_t theta, 
q31_t * pSinVal, 
q31_t * pCosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]thetascaled input value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cosine output. 

+  

+

+
Returns:
none.

+
The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. 

+
+
References cosTableQ31, INPUT_SPACING, and sinTableQ31.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___sin_cos_example.html b/CMSIS/Documentation/DSP/html/group___sin_cos_example.html
new file mode 100644
index 0000000000..549ffe0e89
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___sin_cos_example.html
@@ -0,0 +1,154 @@
+
+
+
+
+SineCosine Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
SineCosine Example
  

+
Examples

+

+
Description:

+
Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector Multiplication, and Vector Addition functions.

+
Algorithm:

+
Mathematically, the Pythagorean trignometric identity is defined by the following equation: 
sin(x) * sin(x) + cos(x) * cos(x) = 1
 where x is the angle in radians.

+
Block Diagram:

+

+sinCos.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 array of input angle in radians 
    • 
+
  • testOutput stores sum of the squares of sine and cosine values of input angle
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_sin_cos_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group___variance_example.html b/CMSIS/Documentation/DSP/html/group___variance_example.html
new file mode 100644
index 0000000000..10fda6224d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group___variance_example.html
@@ -0,0 +1,159 @@
+
+
+
+
+Variance Example
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Variance Example
  

+
Examples

+

+
Description: 

+
Demonstrates the use of Basic Math and Support Functions to calculate the variance of an input sequence with N samples. Uniformly distributed white noise is taken as input.

+
Algorithm:

+
The variance of a sequence is the mean of the squared deviation of the sequence from its mean. 

+
This is denoted by the following equation: 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
 where, x[n] is the input sequence, N is the number of input samples, and x' is the mean value of the input sequence, x[n]. 

+
The mean value x' is defined as: 
 x' = (x[0] + x[1] + ... + x[n-1]) / N

+
Block Diagram:

+

+Variance.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • refVarianceOut reference variance value
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_variance_example_f32.c 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__clarke.html b/CMSIS/Documentation/DSP/html/group__clarke.html
new file mode 100644
index 0000000000..c48414822e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__clarke.html
@@ -0,0 +1,254 @@
+
+
+
+
+Vector Clarke Transform
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Clarke Transform
  

+
Controller Functions

+

+
+
+
+
+
+
+

+Functions
__STATIC_INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
 Floating-point Clarke transform.  
__STATIC_INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
 Clarke transform for Q31 version.  

+
Description

+
Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents in the two-phase orthogonal stator axis Ialpha and Ibeta. When Ialpha is superposed with Ia as shown in the figure below 

+

+clarke.gif
+

+Stator current space vector and its components in (a,b).

+
 and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta can be calculated using only Ia and Ib.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeFormula.gif
+

+ where Ia and Ib are the instantaneous stator phases and pIalpha and pIbeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_clarke_f32 (float32_t Ia, 
float32_t Ib, 
float32_t * pIalpha, 
float32_t * pIbeta 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_clarke_q31 (q31_t Ia, 
q31_t Ib, 
q31_t * pIalpha, 
q31_t * pIbeta 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__cmplx__conj.html b/CMSIS/Documentation/DSP/html/group__cmplx__conj.html
new file mode 100644
index 0000000000..9d9e812205
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__cmplx__conj.html
@@ -0,0 +1,284 @@
+
+
+
+
+Complex Conjugate
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex Conjugate
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  

+
Description

+
Conjugates the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values. The underlying algorithm is used:

+
        
+ for(n=0; n<numSamples; n++) {        
+     pDst[(2*n)+0)] = pSrc[(2*n)+0];     // real part        
+     pDst[(2*n)+1)] = -pSrc[(2*n)+1];    // imag part        
+ }        
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
References __SIMD32.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__cmplx__dot__prod.html b/CMSIS/Documentation/DSP/html/group__cmplx__dot__prod.html
new file mode 100644
index 0000000000..a5bfb3d79c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__cmplx__dot__prod.html
@@ -0,0 +1,327 @@
+
+
+
+
+Complex Dot Product
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex Dot Product
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  

+
Description

+
Computes the dot product of two complex vectors. The vectors are multiplied element-by-element and then summed.

+
The pSrcA points to the first complex input vector and pSrcB points to the second complex input vector. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values.

+
The underlying algorithm is used: 

+
    
+ realResult=0;    
+ imagResult=0;    
+ for(n=0; n<numSamples; n++) {    
+     realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];    
+     imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];    
+ }    
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
uint32_t numSamples, 
float32_t * realResult, 
float32_t * imagResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
uint32_t numSamples, 
q31_t * realResult, 
q31_t * imagResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. These are accumulated in a 64-bit accumulator with 34.30 precision. As a final step, the accumulators are converted to 8.24 format. The return results realResult and imagResult are in 8.24 format. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
uint32_t numSamples, 
q63_t * realResult, 
q63_t * imagResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. The return results realResult and imagResult are in 16.48 format. Input down scaling is not required. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__cmplx__mag.html b/CMSIS/Documentation/DSP/html/group__cmplx__mag.html
new file mode 100644
index 0000000000..e790eee07a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__cmplx__mag.html
@@ -0,0 +1,290 @@
+
+
+
+
+Complex Magnitude
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex Magnitude
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  

+
Description

+
Computes the magnitude of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values. The underlying algorithm is used:

+
    
+ for(n=0; n<numSamples; n++) {    
+     pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);    
+ }    
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to complex input buffer 
[out]*pDstpoints to real output buffer 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
References arm_sqrt_f32().

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. 

+
+
References __SIMD32, and arm_sqrt_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. Input down scaling is not required. 

+
+
References arm_sqrt_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__cmplx__mag__squared.html b/CMSIS/Documentation/DSP/html/group__cmplx__mag__squared.html
new file mode 100644
index 0000000000..d1780921ed
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__cmplx__mag__squared.html
@@ -0,0 +1,284 @@
+
+
+
+
+Complex Magnitude Squared
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Complex Magnitude Squared
  

+
Complex Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  

+
Description

+
Computes the magnitude squared of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values.

+
The underlying algorithm is used:

+
        
+ for(n=0; n<numSamples; n++) {        
+     pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;        
+ }        
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the complex input vector 
[out]*pDstpoints to the real output vector 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+
References __SIMD32.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__copy.html b/CMSIS/Documentation/DSP/html/group__copy.html
new file mode 100644
index 0000000000..e1d0275cb5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__copy.html
@@ -0,0 +1,331 @@
+
+
+
+
+Vector Copy
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Copy
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  

+
Description

+
Copies sample by sample from source vector to destination vector.

+
    
+ 	pDst[n] = pSrc[n];   0 <= n < blockSize.    
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and blockSize.

+
+
Referenced by arm_conv_fast_opt_q15(), arm_conv_opt_q15(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_opt_q15(), arm_correlate_fast_opt_q15(), and arm_correlate_opt_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__cos.html b/CMSIS/Documentation/DSP/html/group__cos.html
new file mode 100644
index 0000000000..a108e0bbac
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__cos.html
@@ -0,0 +1,317 @@
+
+
+
+
+Cosine
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
Cosine
  

+
Fast Math Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const float32_t cosTable [260]
static const q15_t cosTableQ15 [259]
static const q31_t cosTableQ31 [259]

+Functions
float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  
q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  
q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  

+
Description

+
Computes the trigonometric cosine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
    
+    a=Table[index-1];    
+    b=Table[index+0];    
+    c=Table[index+1];    
+    d=Table[index+2];    
+ 
 and 

+
    
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ 
 
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[260] [static]

+

+

+
Example code for Generation of Cos Table: tableSize = 256; 
for(n = -1; n < (tableSize + 2); n++)    
+ {    
+	cosTable[n+1]= cos(2*pi*n/tableSize);    
+ } 
 where pi value is 3.14159265358979 

+
+
Referenced by arm_cos_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cosTableQ15[259] [static]

+

+

+
Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps 

+
First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)    
+ {    
+	cosTable[n+1]= cos(2*pi*n/tableSize);    
+ }
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q15(Fixed point): (cosTable[i] * pow(2, 15)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Referenced by arm_cos_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cosTableQ31[259] [static]

+

+

+
Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)    
+ {    
+	cosTable[n+1]= cos(2*pi*n/tableSize);    
+ } 
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q31(Fixed point): (cosTable[i] * pow(2, 31)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Referenced by arm_cos_q31().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_cos_f32 (float32_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
cos(x). 

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
References cosTable, and TABLE_SIZE.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_cos_q15 (q15_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. 

+
+
References cosTableQ15, and TABLE_SPACING_Q15.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_cos_q31 (q31_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. 

+
+
References cosTableQ31, and TABLE_SPACING_Q31.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__dot__prod.html b/CMSIS/Documentation/DSP/html/group__dot__prod.html
new file mode 100644
index 0000000000..7c021d6e32
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__dot__prod.html
@@ -0,0 +1,360 @@
+
+
+
+
+Vector Dot Product
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Dot Product
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  

+
Description

+
Computes the dot product of two vectors. The vectors are multiplied element-by-element and then summed. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
uint32_t blockSize, 
float32_t * result 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_variance_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
uint32_t blockSize, 
q63_t * result 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these results are added to a 64-bit accumulator in 34.30 format. Nonsaturating additions are used and given that there are 33 guard bits in the accumulator there is no risk of overflow. The return result is in 34.30 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
uint32_t blockSize, 
q63_t * result 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these are truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. There are 15 guard bits in the accumulator and there is no risk of overflow as long as the length of the vectors is less than 2^16 elements. The return result is in 16.48 format. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
uint32_t blockSize, 
q31_t * result 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these results are added to an accumulator in 18.14 format. Nonsaturating additions are used and there is no danger of wrap around as long as the vectors are less than 2^18 elements long. The return result is in 18.14 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__float__to__x.html b/CMSIS/Documentation/DSP/html/group__float__to__x.html
new file mode 100644
index 0000000000..6a0b261e5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__float__to__x.html
@@ -0,0 +1,299 @@
+
+
+
+
+Convert 32-bit floating point value
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Convert 32-bit floating point value
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q15 (float32_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
    
+ 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q31 (float32_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    
+ 
 Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References blockSize, and clip_q63_to_q31().

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q7 (float32_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
    
+ 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
References blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_cmplx_math.html b/CMSIS/Documentation/DSP/html/group__group_cmplx_math.html
new file mode 100644
index 0000000000..7bfba58e01
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_cmplx_math.html
@@ -0,0 +1,144 @@
+
+
+
+
+Complex Math Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Complex Math Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Complex Conjugate
 Complex Dot Product
 Complex Magnitude
 Complex Magnitude Squared
 Complex-by-Complex Multiplication
 Complex-by-Real Multiplication

+
Description

+
This set of functions operates on complex data vectors. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). In the API functions, the number of samples in a complex array refers to the number of complex values; the array contains twice this number of real values. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_controller.html b/CMSIS/Documentation/DSP/html/group__group_controller.html
new file mode 100644
index 0000000000..59ced8de1b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_controller.html
@@ -0,0 +1,142 @@
+
+
+
+
+Controller Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Controller Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Sine Cosine
 PID Motor Control
 Vector Clarke Transform
 Vector Inverse Clarke Transform
 Vector Park Transform
 Vector Inverse Park transform

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_examples.html b/CMSIS/Documentation/DSP/html/group__group_examples.html
new file mode 100644
index 0000000000..5ab8705728
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_examples.html
@@ -0,0 +1,147 @@
+
+
+
+
+Examples
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Examples
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Class Marks Example
 Convolution Example
 Dot Product Example
 Frequency Bin Example
 FIR Lowpass Filter Example
 Graphic Audio Equalizer Example
 Linear Interpolate Example
 Matrix Example
 Signal Convergence Example
 SineCosine Example
 Variance Example

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_fast_math.html b/CMSIS/Documentation/DSP/html/group__group_fast_math.html
new file mode 100644
index 0000000000..73f6de9875
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_fast_math.html
@@ -0,0 +1,141 @@
+
+
+
+
+Fast Math Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Fast Math Functions
  

+

+

+
+
+
+
+
+

+Modules
 Cosine
 Sine
 Square Root

+
Description

+
This set of functions provides a fast approximation to sine, cosine, and square root. As compared to most of the other functions in the CMSIS math library, the fast math functions operate on individual values and not arrays. There are separate functions for Q15, Q31, and floating-point data. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_filters.html b/CMSIS/Documentation/DSP/html/group__group_filters.html
new file mode 100644
index 0000000000..bc9e62eb5f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_filters.html
@@ -0,0 +1,150 @@
+
+
+
+
+Filtering Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Filtering Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 High Precision Q31 Biquad Cascade Filter
 Biquad Cascade IIR Filters Using Direct Form I Structure
 Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
 Convolution
 Partial Convolution
 Correlation
 Finite Impulse Response (FIR) Decimator
 Finite Impulse Response (FIR) Filters
 Finite Impulse Response (FIR) Lattice Filters
 Finite Impulse Response (FIR) Sparse Filters
 Infinite Impulse Response (IIR) Lattice Filters
 Least Mean Square (LMS) Filters
 Normalized LMS Filters
 Finite Impulse Response (FIR) Interpolator

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_interpolation.html b/CMSIS/Documentation/DSP/html/group__group_interpolation.html
new file mode 100644
index 0000000000..ab1d7ad7c6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_interpolation.html
@@ -0,0 +1,140 @@
+
+
+
+
+Interpolation Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Interpolation Functions
  

+

+

+
+
+
+
+

+Modules
 Linear Interpolation
 Bilinear Interpolation

+
Description

+
These functions perform 1- and 2-dimensional interpolation of data. Linear interpolation is used for 1-dimensional data and bilinear interpolation is used for 2-dimensional data. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_math.html b/CMSIS/Documentation/DSP/html/group__group_math.html
new file mode 100644
index 0000000000..168b89d3fc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_math.html
@@ -0,0 +1,145 @@
+
+
+
+
+Basic Math Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Basic Math Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Vector Absolute Value
 Vector Addition
 Vector Dot Product
 Vector Multiplication
 Vector Negate
 Vector Offset
 Vector Scale
 Vector Shift
 Vector Subtraction

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_matrix.html b/CMSIS/Documentation/DSP/html/group__group_matrix.html
new file mode 100644
index 0000000000..8b433fc90b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_matrix.html
@@ -0,0 +1,169 @@
+
+
+
+
+Matrix Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Matrix Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Matrix Addition
 Matrix Initialization
 Matrix Inverse
 Matrix Multiplication
 Matrix Scale
 Matrix Subtraction
 Matrix Transpose

+
Description

+
This set of functions provides basic matrix math operations. The functions operate on matrix data structures. For example, the type definition for the floating-point matrix structure is shown below: 

+
+     typedef struct
+     {
+       uint16_t numRows;     // number of rows of the matrix.
+       uint16_t numCols;     // number of columns of the matrix.
+       float32_t *pData;     // points to the data of the matrix.
+     } arm_matrix_instance_f32;
+ 
 There are similar definitions for Q15 and Q31 data types.

+
The structure specifies the size of the matrix and then points to an array of data. The array is of size numRows X numCols and the values are arranged in row order. That is, the matrix element (i, j) is stored at: 

+
+     pData[i*numCols + j]
+ 
Init Functions
There is an associated initialization function for each type of matrix data structure. The initialization function sets the values of the internal structure fields. Refer to the function arm_mat_init_f32(), arm_mat_init_q31() and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.

+
Use of the initialization function is optional. However, if initialization function is used then the instance structure cannot be placed into a const data section. To place the instance structure in a const data section, manually initialize the data structure. For example: 
+ arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ 
 where nRows specifies the number of rows, nColumns specifies the number of columns, and pData points to the data array.

+
Size Checking
By default all of the matrix functions perform size checking on the input and output matrices. For example, the matrix addition function verifies that the two input matrices and the output matrix all have the same number of rows and columns. If the size check fails the functions return: 
+     ARM_MATH_SIZE_MISMATCH
+ 
 Otherwise the functions return 
+     ARM_MATH_SUCCESS
+ 
 There is some overhead associated with this matrix size checking. The matrix size checking is enabled via the #define 
+     ARM_MATH_MATRIX_CHECK
+ 
 within the library project settings. By default this macro is defined and size checking is enabled. By changing the project settings and undefining this macro size checking is eliminated and the functions run a bit faster. With size checking disabled the functions always return ARM_MATH_SUCCESS. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_stats.html b/CMSIS/Documentation/DSP/html/group__group_stats.html
new file mode 100644
index 0000000000..1a6b138d29
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_stats.html
@@ -0,0 +1,143 @@
+
+
+
+
+Statistics Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Statistics Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Maximum
 Mean
 Minimum
 Power
 Root mean square (RMS)
 Standard deviation
 Variance

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_support.html b/CMSIS/Documentation/DSP/html/group__group_support.html
new file mode 100644
index 0000000000..cca30cd671
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_support.html
@@ -0,0 +1,142 @@
+
+
+
+
+Support Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Support Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Vector Copy
 Vector Fill
 Convert 32-bit floating point value
 Convert 16-bit Integer value
 Convert 32-bit Integer value
 Convert 8-bit Integer value

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__group_transforms.html b/CMSIS/Documentation/DSP/html/group__group_transforms.html
new file mode 100644
index 0000000000..e3550d9925
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__group_transforms.html
@@ -0,0 +1,141 @@
+
+
+
+
+Transform Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Transform Functions
  

+

+

+
+
+
+
+
+
+
+

+Modules
 Radix-2 Complex FFT Functions
 Radix-4 Complex FFT Functions
 DCT Type IV Functions
 Real FFT Functions
 Complex FFT Tables

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__inv__clarke.html b/CMSIS/Documentation/DSP/html/group__inv__clarke.html
new file mode 100644
index 0000000000..0cea14db46
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__inv__clarke.html
@@ -0,0 +1,249 @@
+
+
+
+
+Vector Inverse Clarke Transform
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Inverse Clarke Transform
  

+
Controller Functions

+

+
+
+
+
+
+
+

+Functions
__STATIC_INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
 Floating-point Inverse Clarke transform.  
__STATIC_INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
 Inverse Clarke transform for Q31 version.  

+
Description

+
Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeInvFormula.gif
+

+ where pIa and pIb are the instantaneous stator phases and Ialpha and Ibeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+        
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+        
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+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_inv_clarke_f32 (float32_t Ialpha, 
float32_t Ibeta, 
float32_t * pIa, 
float32_t * pIb 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_inv_clarke_q31 (q31_t Ialpha, 
q31_t Ibeta, 
q31_t * pIa, 
q31_t * pIb 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the subtraction, hence there is no risk of overflow. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__inv__park.html b/CMSIS/Documentation/DSP/html/group__inv__park.html
new file mode 100644
index 0000000000..46a0c8c0fc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__inv__park.html
@@ -0,0 +1,277 @@
+
+
+
+
+Vector Inverse Park transform
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Inverse Park transform
  

+
Controller Functions

+

+
+
+
+
+
+
+

+Functions
__STATIC_INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
 Floating-point Inverse Park transform.  
__STATIC_INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
 Inverse Park transform for Q31 version.  

+
Description

+
Inverse Park transform converts the input flux and torque components to two-coordinate vector.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkInvFormula.gif
+

+ where pIalpha and pIbeta are the stator vector components, Id and Iq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+        
+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_inv_park_f32 (float32_t Id, 
float32_t Iq, 
float32_t * pIalpha, 
float32_t * pIbeta, 
float32_t sinVal, 
float32_t cosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_inv_park_q31 (q31_t Id, 
q31_t Iq, 
q31_t * pIalpha, 
q31_t * pIbeta, 
q31_t sinVal, 
q31_t cosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__mean.html b/CMSIS/Documentation/DSP/html/group__mean.html
new file mode 100644
index 0000000000..414d0878ab
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__mean.html
@@ -0,0 +1,335 @@
+
+
+
+
+Mean
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Mean
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Mean value of a Q31 vector.  
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  

+
Description

+
Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. The underlying algorithm is used:

+
    
+ 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    
+ 
There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_mean_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+        
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+        
+        
+          
+          
+          
+        
+      
void arm_mean_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.15 format and is accumulated in a 32-bit accumulator in 17.15 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is saturated and truncated to yield a result of 1.15 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mean_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format and is accumulated in a 64-bit accumulator in 33.31 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.31 format. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mean_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format and is accumulated in a 32-bit accumulator in 25.7 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.7 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__negate.html b/CMSIS/Documentation/DSP/html/group__negate.html
new file mode 100644
index 0000000000..0bf6aaa069
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__negate.html
@@ -0,0 +1,332 @@
+
+
+
+
+Vector Negate
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Negate
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  

+
Description

+
Negates the elements of a vector.

+
        
+     pDst[n] = -pSrc[n],   0 <= n < blockSize.        
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
References _SIMD32_OFFSET, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__offset.html b/CMSIS/Documentation/DSP/html/group__offset.html
new file mode 100644
index 0000000000..95e10c6acd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__offset.html
@@ -0,0 +1,360 @@
+
+
+
+
+Vector Offset
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Offset
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  

+
Description

+
Adds a constant offset to each element of a vector.

+
        
+     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_f32 (float32_t * pSrc, 
float32_t offset, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q15 (q15_t * pSrc, 
q15_t offset, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q31 (q31_t * pSrc, 
q31_t offset, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. 

+
+
References blockSize, and clip_q63_to_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q7 (q7_t * pSrc, 
q7_t offset, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] are saturated. 

+
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__park.html b/CMSIS/Documentation/DSP/html/group__park.html
new file mode 100644
index 0000000000..acd0531ef1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__park.html
@@ -0,0 +1,282 @@
+
+
+
+
+Vector Park Transform
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Park Transform
  

+
Controller Functions

+

+
+
+
+
+
+
+

+Functions
__STATIC_INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
 Floating-point Park transform.  
__STATIC_INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
 Park transform for Q31 version.  

+
Description

+
Forward Park transform converts the input two-coordinate vector to flux and torque components. The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents from the stationary to the moving reference frame and control the spatial relationship between the stator vector current and rotor flux vector. If we consider the d axis aligned with the rotor flux, the diagram below shows the current vector and the relationship from the two reference frames: 

+

+park.gif
+

+Stator current space vector and its component in (a,b) and in the d,q rotating reference frame

+
 The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkFormula.gif
+

+ where Ialpha and Ibeta are the stator vector components, pId and pIq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_park_f32 (float32_t Ialpha, 
float32_t Ibeta, 
float32_t * pId, 
float32_t * pIq, 
float32_t sinVal, 
float32_t cosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
The function implements the forward Park transform. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
__STATIC_INLINE void arm_park_q31 (q31_t Ialpha, 
q31_t Ibeta, 
q31_t * pId, 
q31_t * pIq, 
q31_t sinVal, 
q31_t cosVal 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition and subtraction, hence there is no risk of overflow. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__power.html b/CMSIS/Documentation/DSP/html/group__power.html
new file mode 100644
index 0000000000..2fbf7d2b0f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__power.html
@@ -0,0 +1,332 @@
+
+
+
+
+Power
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Power
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  

+
Description

+
Calculates the sum of the squares of the elements in the input vector. The underlying algorithm is used:

+
    
+ 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 34.30 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format. Intermediate multiplication yields a 2.62 format, and this result is truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. With 15 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 16.48 format. 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format. Intermediate multiplication yields a 2.14 format, and this result is added without saturation to an accumulator in 18.14 format. With 17 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 18.14 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__q15__to__x.html b/CMSIS/Documentation/DSP/html/group__q15__to__x.html
new file mode 100644
index 0000000000..625e22d8cd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__q15__to__x.html
@@ -0,0 +1,287 @@
+
+
+
+
+Convert 16-bit Integer value
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Convert 16-bit Integer value
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_float (q15_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    
+ 
 
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_q31 (q15_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
+ 
 
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q15_to_q7 (q15_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    
+ 
 
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__q31__to__x.html b/CMSIS/Documentation/DSP/html/group__q31__to__x.html
new file mode 100644
index 0000000000..a01505e854
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__q31__to__x.html
@@ -0,0 +1,290 @@
+
+
+
+
+Convert 32-bit Integer value
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Convert 32-bit Integer value
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_float (q31_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    
+ 
 
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_q15 (q31_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    
+ 
 
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q31_to_q7 (q31_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     
+ 
 
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__q7__to__x.html b/CMSIS/Documentation/DSP/html/group__q7__to__x.html
new file mode 100644
index 0000000000..95955c4864
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__q7__to__x.html
@@ -0,0 +1,287 @@
+
+
+
+
+Convert 8-bit Integer value
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Convert 8-bit Integer value
  

+
Support Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_float (q7_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    
+ 
 
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_q15 (q7_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    
+ 
 
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_q7_to_q31 (q7_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
    
+ 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   
+ 
 
+
References __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__scale.html b/CMSIS/Documentation/DSP/html/group__scale.html
new file mode 100644
index 0000000000..5d45f86536
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__scale.html
@@ -0,0 +1,392 @@
+
+
+
+
+Vector Scale
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Scale
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  

+
Description

+
Multiply a vector by a scalar value. For floating-point data, the algorithm used is:

+
        
+     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        
+ 
In the fixed-point Q7, Q15, and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The algorithm used with fixed-point data is:

+
        
+     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        
+ 
The overall scale factor applied to the fixed-point data is 

+
        
+     scale = scaleFract * 2^shift.        
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_f32 (float32_t * pSrc, 
float32_t scale, 
float32_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scalescale factor to be applied 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
References blockSize.

+
+
Referenced by arm_dct4_f32(), and main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q15 (q15_t * pSrc, 
q15_t scaleFract, 
int8_t shift, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
References __SIMD32, and blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q31 (q31_t * pSrc, 
q31_t scaleFract, 
int8_t shift, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
References blockSize.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_scale_q7 (q7_t * pSrc, 
q7_t scaleFract, 
int8_t shift, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.7 format. These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. 

+
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__shift.html b/CMSIS/Documentation/DSP/html/group__shift.html
new file mode 100644
index 0000000000..fc5a4a584f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__shift.html
@@ -0,0 +1,312 @@
+
+
+
+
+Vector Shift
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Vector Shift
  

+
Basic Math Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  

+
Description

+
Shifts the elements of a fixed-point vector by a specified number of bits. There are separate functions for Q7, Q15, and Q31 data types. The underlying algorithm used is:

+
        
+     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        
+ 
If shift is positive then the elements of the vector are shifted to the left. If shift is negative then the elements of the vector are shifted to the right. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q15 (q15_t * pSrc, 
int8_t shiftBits, 
q15_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
References __SIMD32, and blockSize.

+
+
Referenced by arm_dct4_q15().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q31 (q31_t * pSrc, 
int8_t shiftBits, 
q31_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
References blockSize, and clip_q63_to_q31().

+
+
Referenced by arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q7 (q7_t * pSrc, 
int8_t shiftBits, 
q7_t * pDst, 
uint32_t blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. 

+
+
References __PACKq7, __SIMD32, and blockSize.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__sin.html b/CMSIS/Documentation/DSP/html/group__sin.html
new file mode 100644
index 0000000000..6cdd994d7b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__sin.html
@@ -0,0 +1,320 @@
+
+
+
+
+Sine
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Variables |
+Functions  

+  

+
Sine
  

+
Fast Math Functions

+

+
+
+
+
+
+
+
+
+
+
+
+
+

+Variables
static const float32_t sinTable [259]
static const q15_t sinTableQ15 [259]
static const q31_t sinTableQ31 [259]

+Functions
float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  
q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  
q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  

+
Description

+
Computes the trigonometric sine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
    
+    a=Table[index-1];    
+    b=Table[index+0];    
+    c=Table[index+1];    
+    d=Table[index+2];    
+ 
 and 

+
    
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
+    wd=(1/6)*fract.^3 - (1/6)*fract;    
+ 
 
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[259] [static]

+

+

+
Example code for Generation of Floating-point Sin Table: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)    
+ {    
+	sinTable[n+1]=sin(2*pi*n/tableSize);    
+ }
 

+
where pi value is 3.14159265358979 

+
+
Referenced by arm_sin_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t sinTableQ15[259] [static]

+

+

+
Example code for Generation of Q15 Sin Table: 

+
tableSize = 256;    
+ for(n = -1; n < (tableSize + 1); n++)    
+ {    
+	sinTable[n+1]=sin(2*pi*n/tableSize);    
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q15(Fixed point): (sinTable[i] * pow(2, 15)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Referenced by arm_sin_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t sinTableQ31[259] [static]

+

+

+
Tables generated are in Q31(1.31 Fixed point format) Generation of sin values in floating point: 
tableSize = 256;      
+ for(n = -1; n < (tableSize + 1); n++)    
+ {    
+	sinTable[n+1]= sin(2*pi*n/tableSize);    
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q31(Fixed point): (sinTable[i] * pow(2, 31)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Referenced by arm_sin_q31().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_sin_f32 (float32_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
sin(x). 

+
Examples: 
arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
References sinTable, and TABLE_SIZE.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_sin_q15 (q15_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. 

+
+
References sinTableQ15, and TABLE_SPACING_Q15.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_sin_q31 (q31_t x)

+

+

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. 

+
+
References sinTableQ31, and TABLE_SPACING_Q31.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/group__variance.html b/CMSIS/Documentation/DSP/html/group__variance.html
new file mode 100644
index 0000000000..927e80ccd4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/group__variance.html
@@ -0,0 +1,287 @@
+
+
+
+
+Variance
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
Variance
  

+
Statistics Functions

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  

+
Description

+
Calculates the variance of the elements in the input vector. The underlying algorithm is used:

+
    
+ 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
References blockSize, and mean.

+
+
Referenced by main().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
References __SIMD32, blockSize, and mean.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
References blockSize, and mean.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/index.html b/CMSIS/Documentation/DSP/html/index.html
new file mode 100644
index 0000000000..30bc9a7967
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/index.html
@@ -0,0 +1,204 @@
+
+
+
+
+CMSIS DSP Software Library
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
CMSIS DSP Software Library 
  

+

+

+
Introduction

+
This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M processor based devices.

+
The library is divided into a number of functions each covering a specific category:

+
    
+
  • Basic math functions
    • 
+
  • Fast math functions
    • 
+
  • Complex math functions
    • 
+
  • Filters
    • 
+
  • Matrix functions
    • 
+
  • Transforms
    • 
+
  • Motor control functions
    • 
+
  • Statistical functions
    • 
+
  • Support functions
    • 
+
  • Interpolation functions
    • 
+

+
The library has separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.

+
Pre-processor Macros

+
Each library project have differant pre-processor macros.

+
    
+
  • UNALIGNED_SUPPORT_DISABLE:
    • 
+

+
Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access

+
    
+
  • ARM_MATH_BIG_ENDIAN:
    • 
+

+
Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

+
    
+
  • ARM_MATH_MATRIX_CHECK:
    • 
+

+
Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices

+
    
+
  • ARM_MATH_ROUNDING:
    • 
+

+
Define macro ARM_MATH_ROUNDING for rounding on support functions

+
    
+
  • ARM_MATH_CMx:
    • 
+

+
Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target and ARM_MATH_CM0 for building library on cortex-M0 target.

+
    
+
  • __FPU_PRESENT:
    • 
+

+
Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

+
Toolchain Support

+
The library has been developed and tested with MDK-ARM version 4.23. The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

+
Using the Library

+
The library installer contains prebuilt versions of the libraries in the Lib folder.

+
    
+
  • arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4l_math.lib (Little endian on Cortex-M4)
    • 
+
  • arm_cortexM4b_math.lib (Big endian on Cortex-M4)
    • 
+
  • arm_cortexM3l_math.lib (Little endian on Cortex-M3)
    • 
+
  • arm_cortexM3b_math.lib (Big endian on Cortex-M3)
    • 
+
  • arm_cortexM0l_math.lib (Little endian on Cortex-M0)
    • 
+
  • arm_cortexM0b_math.lib (Big endian on Cortex-M3)
    • 
+

+
The library functions are declared in the public file arm_math.h which is placed in the Include folder. Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or ARM_MATH_CM0 depending on the target processor in the application.

+
Examples

+
The library ships with a number of examples which demonstrate how to use the library functions.

+
Building the Library

+
The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder.

+
    
+
  • arm_cortexM0b_math.uvproj
    • 
+
  • arm_cortexM0l_math.uvproj
    • 
+
  • arm_cortexM3b_math.uvproj
    • 
+
  • arm_cortexM3l_math.uvproj
    • 
+
  • arm_cortexM4b_math.uvproj
    • 
+
  • arm_cortexM4l_math.uvproj
    • 
+
  • arm_cortexM4bf_math.uvproj
    • 
+
  • arm_cortexM4lf_math.uvproj
    • 
+

+
The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.

+
Copyright Notice

+
Copyright (C) 2010 ARM Limited. All rights reserved. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/installdox b/CMSIS/Documentation/DSP/html/installdox
new file mode 100644
index 0000000000..edf5bbfe3e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/installdox
@@ -0,0 +1,112 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet   = 0;
+
+while ( @ARGV ) {
+  $_ = shift @ARGV;
+  if ( s/^-// ) {
+    if ( /^l(.*)/ ) {
+      $v = ($1 eq "") ? shift @ARGV : $1;
+      ($v =~ /\/$/) || ($v .= "/");
+      $_ = $v;
+      if ( /(.+)\@(.+)/ ) {
+        if ( exists $subst{$1} ) {
+          $subst{$1} = $2;
+        } else {
+          print STDERR "Unknown tag file $1 given with option -l\n";
+          &usage();
+        }
+      } else {
+        print STDERR "Argument $_ is invalid for option -l\n";
+        &usage();
+      }
+    }
+    elsif ( /^q/ ) {
+      $quiet = 1;
+    }
+    elsif ( /^\?|^h/ ) {
+      &usage();
+    }
+    else {
+      print STDERR "Illegal option -$_\n";
+      &usage();
+    }
+  }
+  else {
+    push (@files, $_ );
+  }
+}
+
+foreach $sub (keys %subst)
+{
+  if ( $subst{$sub} eq "" ) 
+  {
+    print STDERR "No substitute given for tag file `$sub'\n";
+    &usage();
+  }
+  elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+  {
+    print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; 
+  }
+}
+
+if ( ! @files ) {
+  if (opendir(D,".")) {
+    foreach $file ( readdir(D) ) {
+      $match = ".html";
+      next if ( $file =~ /^\.\.?$/ );
+      ($file =~ /$match/) && (push @files, $file);
+      ($file =~ /\.svg/) && (push @files, $file);
+      ($file =~ "navtree.js") && (push @files, $file);
+    }
+    closedir(D);
+  }
+}
+
+if ( ! @files ) {
+  print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+  if ( ! $quiet ) {
+    print "Editing: $f...\n";
+  }
+  $oldf = $f;
+  $f   .= ".bak";
+  unless (rename $oldf,$f) {
+    print STDERR "Error: cannot rename file $oldf\n";
+    exit 1;
+  }
+  if (open(F,"<$f")) {
+    unless (open(G,">$oldf")) {
+      print STDERR "Error: opening file $oldf for writing\n";
+      exit 1;
+    }
+    if ($oldf ne "tree.js") {
+      while () {
+        s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+    else {
+      while () {
+        s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+  } 
+  else {
+    print STDERR "Warning file $f does not exist\n";
+  }
+  unlink $f;
+}
+
+sub usage {
+  print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+  print STDERR "Options:\n";
+  print STDERR "     -l tagfile\@linkName   tag file + URL or directory \n";
+  print STDERR "     -q                    Quiet mode\n\n";
+  exit 1;
+}
diff --git a/CMSIS/Documentation/DSP/html/jquery.js b/CMSIS/Documentation/DSP/html/jquery.js
new file mode 100644
index 0000000000..c052173a89
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var 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h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return 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d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var 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f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/CMSIS/Documentation/DSP/html/linearInterpExampleMethod1.gif b/CMSIS/Documentation/DSP/html/linearInterpExampleMethod1.gif
new file mode 100644
index 0000000000..615ac75244
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/linearInterpExampleMethod1.gif differ
diff --git a/CMSIS/Documentation/DSP/html/linearInterpExampleMethod2.gif b/CMSIS/Documentation/DSP/html/linearInterpExampleMethod2.gif
new file mode 100644
index 0000000000..ed5da60e28
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/linearInterpExampleMethod2.gif differ
diff --git a/CMSIS/Documentation/DSP/html/math__helper_8c.html b/CMSIS/Documentation/DSP/html/math__helper_8c.html
new file mode 100644
index 0000000000..e24fce0535
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/math__helper_8c.html
@@ -0,0 +1,755 @@
+
+
+
+
+math_helper.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
math_helper.c File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
float arm_snr_f32 (float *pRef, float *pTest, uint32_t buffSize)
 Caluclation of SNR.  
void arm_provide_guard_bits_q15 (q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  
void arm_float_to_q12_20 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed in q12.20 format.  
uint32_t arm_compare_fixed_q15 (q15_t *pIn, q15_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  
uint32_t arm_compare_fixed_q31 (q31_t *pIn, q31_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  
void arm_provide_guard_bits_q31 (q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  
void arm_provide_guard_bits_q7 (q7_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  
uint32_t arm_calc_guard_bits (uint32_t num_adds)
 Caluclates number of guard bits.  
void arm_apply_guard_bits (float32_t *pIn, uint32_t numSamples, uint32_t guard_bits)
 Converts Q15 to floating-point.  
uint32_t arm_calc_2pow (uint32_t numShifts)
 Calculates pow(2, numShifts)  
void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
 Converts float to fixed q14.  
void arm_float_to_q30 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  
void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  
void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q28 format.  
void arm_clip_f32 (float *pIn, uint32_t numSamples)
 Clip the float values to +/- 1.  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_apply_guard_bits (float32_t * pIn, 
uint32_t numSamples, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+
References arm_calc_2pow().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t arm_calc_2pow (uint32_t numShifts)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of shifts 

+  

+

+
Returns:
pow(2, numShifts) 

+
+
Referenced by arm_apply_guard_bits().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t arm_calc_guard_bits (uint32_t num_adds)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of additions 

+  

+

+
Returns:
none The function Caluclates the number of guard bits depending on the numtaps 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_clip_f32 (float * pIn, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+  
pIninput buffer 
numSamplesnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t arm_compare_fixed_q15 (q15_t * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q15_t*Pointer to Ref buffer 
q15_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t arm_compare_fixed_q31 (q31_t * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q31_t*Pointer to Ref buffer 
q31_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q12_20 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point(q12.20) values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q14 (float * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q28 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q29 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q30 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_provide_guard_bits_q15 (q15_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q15_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 

+  

+

+
Returns:
none The function Provides the guard bits for the buffer to avoid overflow 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_provide_guard_bits_q31 (q31_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 

+  

+

+
Returns:
none The function Provides the guard bits for the buffer to avoid overflow 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_provide_guard_bits_q7 (q7_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 

+  

+

+
Returns:
none The function Provides the guard bits for the buffer to avoid overflow 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
float arm_snr_f32 (float * pRef, 
float * pTest, 
uint32_t buffSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
float*Pointer to the reference buffer 
float*Pointer to the test buffer 
uint32_ttotal number of samples 

+  

+

+
Returns:
float SNR The function Caluclates signal to noise ratio for the reference output and test output 

+
+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/math__helper_8h.html b/CMSIS/Documentation/DSP/html/math__helper_8h.html
new file mode 100644
index 0000000000..f952557854
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/math__helper_8h.html
@@ -0,0 +1,710 @@
+
+
+
+
+math_helper.h File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Functions  

+  

+
math_helper.h File Reference
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
float arm_snr_f32 (float *pRef, float *pTest, uint32_t buffSize)
 Caluclation of SNR.  
void arm_float_to_q12_20 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed in q12.20 format.  
void arm_provide_guard_bits_q15 (q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  
void arm_provide_guard_bits_q31 (q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  
void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
 Converts float to fixed q14.  
void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  
void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q28 format.  
void arm_float_to_q30 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  
void arm_clip_f32 (float *pIn, uint32_t numSamples)
 Clip the float values to +/- 1.  
uint32_t arm_calc_guard_bits (uint32_t num_adds)
 Caluclates number of guard bits.  
void arm_apply_guard_bits (float32_t *pIn, uint32_t numSamples, uint32_t guard_bits)
 Converts Q15 to floating-point.  
uint32_t arm_compare_fixed_q15 (q15_t *pIn, q15_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  
uint32_t arm_compare_fixed_q31 (q31_t *pIn, q31_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  
uint32_t arm_calc_2pow (uint32_t guard_bits)
 Calculates pow(2, numShifts)  

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_apply_guard_bits (float32_t * pIn, 
uint32_t numSamples, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+
References arm_calc_2pow().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t arm_calc_2pow (uint32_t numShifts)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of shifts 

+  

+

+
Returns:
pow(2, numShifts) 

+
+
Referenced by arm_apply_guard_bits().

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
uint32_t arm_calc_guard_bits (uint32_t num_adds)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of additions 

+  

+

+
Returns:
none The function Caluclates the number of guard bits depending on the numtaps 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_clip_f32 (float * pIn, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+  
pIninput buffer 
numSamplesnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t arm_compare_fixed_q15 (q15_t * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q15_t*Pointer to Ref buffer 
q15_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
uint32_t arm_compare_fixed_q31 (q31_t * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q31_t*Pointer to Ref buffer 
q31_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q12_20 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point(q12.20) values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q14 (float * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q28 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q29 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q30 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)

+

+

+
Parameters:

+  
+    
+  
uint32_tnumber of samples in the buffer 

+  

+

+
Returns:
none The function converts floating point values to fixed point values 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_provide_guard_bits_q15 (q15_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q15_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 

+  

+

+
Returns:
none The function Provides the guard bits for the buffer to avoid overflow 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_provide_guard_bits_q31 (q31_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 

+  

+

+
Returns:
none The function Provides the guard bits for the buffer to avoid overflow 

+
+
References blockSize.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
float arm_snr_f32 (float * pRef, 
float * pTest, 
uint32_t buffSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
float*Pointer to the reference buffer 
float*Pointer to the test buffer 
uint32_ttotal number of samples 

+  

+

+
Returns:
float SNR The function Caluclates signal to noise ratio for the reference output and test output 

+
Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_matrix_example_f32.c.

+

+
Referenced by main().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/matrixExample.gif b/CMSIS/Documentation/DSP/html/matrixExample.gif
new file mode 100644
index 0000000000..bb2510d54c
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/matrixExample.gif differ
diff --git a/CMSIS/Documentation/DSP/html/modules.html b/CMSIS/Documentation/DSP/html/modules.html
new file mode 100644
index 0000000000..de7c2b6c09
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/modules.html
@@ -0,0 +1,241 @@
+
+
+
+
+Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Reference
  

+

+

+
Here is a list of all modules:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/nav_f.png b/CMSIS/Documentation/DSP/html/nav_f.png
new file mode 100644
index 0000000000..1b07a16207
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/nav_f.png differ
diff --git a/CMSIS/Documentation/DSP/html/nav_h.png b/CMSIS/Documentation/DSP/html/nav_h.png
new file mode 100644
index 0000000000..01f5fa6a59
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/nav_h.png differ
diff --git a/CMSIS/Documentation/DSP/html/navtree.css b/CMSIS/Documentation/DSP/html/navtree.css
new file mode 100644
index 0000000000..e46ffcd6e0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/navtree.css
@@ -0,0 +1,123 @@
+#nav-tree .children_ul {
+  margin:0;
+  padding:4px;
+}
+
+#nav-tree ul {
+  list-style:none outside none;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree li {
+  white-space:nowrap;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .plus {
+  margin:0px;
+}
+
+#nav-tree .selected {
+  background-image: url('tab_a.png');
+  background-repeat:repeat-x;
+  color: #fff;
+  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
+
+#nav-tree img {
+  margin:0px;
+  padding:0px;
+  border:0px;
+  vertical-align: middle;
+}
+
+#nav-tree a {
+  text-decoration:none;
+  padding:0px;
+  margin:0px;
+  outline:none;
+}
+
+#nav-tree .label {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .label a {
+  padding:2px;
+}
+
+#nav-tree .selected a {
+  text-decoration:none;
+  padding:2px;
+  margin:0px;
+  color:#fff;
+}
+
+#nav-tree .children_ul {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree {
+  padding: 0px 0px;
+  background-color: #FAFAFF; 
+  font-size:14px;
+  overflow:auto;
+}
+
+#doc-content {
+  overflow:auto;
+  display:block;
+  padding:0px;
+  margin:0px;
+}
+
+#side-nav {
+  padding:0 6px 0 0;
+  margin: 0px;
+  display:block;
+  position: absolute;
+  left: 0px;
+  width: 300px;
+}
+
+.ui-resizable .ui-resizable-handle {
+  display:block;
+}
+
+.ui-resizable-e {
+  background:url("ftv2splitbar.png") repeat scroll right center transparent;
+  cursor:e-resize;
+  height:100%;
+  right:0;
+  top:0;
+  width:6px;
+}
+
+.ui-resizable-handle {
+  display:none;
+  font-size:0.1px;
+  position:absolute;
+  z-index:1;
+}
+
+#nav-tree-contents {
+  margin: 6px 0px 0px 0px;
+}
+
+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/navtree.js b/CMSIS/Documentation/DSP/html/navtree.js
new file mode 100644
index 0000000000..1ebd32e1ef
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/navtree.js
@@ -0,0 +1,961 @@
+var NAVTREE =
+[
+  [ "CMSIS-DSP", "index.html", [
+    [ "CMSIS DSP Software Library", "index.html", null ],
+    [ "Reference", "modules.html", [
+      [ "Basic Math Functions", "group__group_math.html", [
+        [ "Vector Absolute Value", "group___basic_abs.html", null ],
+        [ "Vector Addition", "group___basic_add.html", null ],
+        [ "Vector Dot Product", "group__dot__prod.html", null ],
+        [ "Vector Multiplication", "group___basic_mult.html", null ],
+        [ "Vector Negate", "group__negate.html", null ],
+        [ "Vector Offset", "group__offset.html", null ],
+        [ "Vector Scale", "group__scale.html", null ],
+        [ "Vector Shift", "group__shift.html", null ],
+        [ "Vector Subtraction", "group___basic_sub.html", null ]
+      ] ],
+      [ "Fast Math Functions", "group__group_fast_math.html", [
+        [ "Cosine", "group__cos.html", null ],
+        [ "Sine", "group__sin.html", null ],
+        [ "Square Root", "group___s_q_r_t.html", null ]
+      ] ],
+      [ "Complex Math Functions", "group__group_cmplx_math.html", [
+        [ "Complex Conjugate", "group__cmplx__conj.html", null ],
+        [ "Complex Dot Product", "group__cmplx__dot__prod.html", null ],
+        [ "Complex Magnitude", "group__cmplx__mag.html", null ],
+        [ "Complex Magnitude Squared", "group__cmplx__mag__squared.html", null ],
+        [ "Complex-by-Complex Multiplication", "group___cmplx_by_cmplx_mult.html", null ],
+        [ "Complex-by-Real Multiplication", "group___cmplx_by_real_mult.html", null ]
+      ] ],
+      [ "Filtering Functions", "group__group_filters.html", [
+        [ "High Precision Q31 Biquad Cascade Filter", "group___biquad_cascade_d_f1__32x64.html", null ],
+        [ "Biquad Cascade IIR Filters Using Direct Form I Structure", "group___biquad_cascade_d_f1.html", null ],
+        [ "Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure", "group___biquad_cascade_d_f2_t.html", null ],
+        [ "Convolution", "group___conv.html", null ],
+        [ "Partial Convolution", "group___partial_conv.html", null ],
+        [ "Correlation", "group___corr.html", null ],
+        [ "Finite Impulse Response (FIR) Decimator", "group___f_i_r__decimate.html", null ],
+        [ "Finite Impulse Response (FIR) Filters", "group___f_i_r.html", null ],
+        [ "Finite Impulse Response (FIR) Lattice Filters", "group___f_i_r___lattice.html", null ],
+        [ "Finite Impulse Response (FIR) Sparse Filters", "group___f_i_r___sparse.html", null ],
+        [ "Infinite Impulse Response (IIR) Lattice Filters", "group___i_i_r___lattice.html", null ],
+        [ "Least Mean Square (LMS) Filters", "group___l_m_s.html", null ],
+        [ "Normalized LMS Filters", "group___l_m_s___n_o_r_m.html", null ],
+        [ "Finite Impulse Response (FIR) Interpolator", "group___f_i_r___interpolate.html", null ]
+      ] ],
+      [ "Matrix Functions", "group__group_matrix.html", [
+        [ "Matrix Addition", "group___matrix_add.html", null ],
+        [ "Matrix Initialization", "group___matrix_init.html", null ],
+        [ "Matrix Inverse", "group___matrix_inv.html", null ],
+        [ "Matrix Multiplication", "group___matrix_mult.html", null ],
+        [ "Matrix Scale", "group___matrix_scale.html", null ],
+        [ "Matrix Subtraction", "group___matrix_sub.html", null ],
+        [ "Matrix Transpose", "group___matrix_trans.html", null ]
+      ] ],
+      [ "Transform Functions", "group__group_transforms.html", [
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+        [ "Radix-4 Complex FFT Functions", "group___radix4___c_f_f_t___c_i_f_f_t.html", null ],
+        [ "DCT Type IV Functions", "group___d_c_t4___i_d_c_t4.html", null ],
+        [ "Real FFT Functions", "group___r_f_f_t___r_i_f_f_t.html", null ],
+        [ "Complex FFT Tables", "group___c_f_f_t___c_i_f_f_t.html", null ]
+      ] ],
+      [ "Controller Functions", "group__group_controller.html", [
+        [ "Sine Cosine", "group___sin_cos.html", null ],
+        [ "PID Motor Control", "group___p_i_d.html", null ],
+        [ "Vector Clarke Transform", "group__clarke.html", null ],
+        [ "Vector Inverse Clarke Transform", "group__inv__clarke.html", null ],
+        [ "Vector Park Transform", "group__park.html", null ],
+        [ "Vector Inverse Park transform", "group__inv__park.html", null ]
+      ] ],
+      [ "Statistics Functions", "group__group_stats.html", [
+        [ "Maximum", "group___max.html", null ],
+        [ "Mean", "group__mean.html", null ],
+        [ "Minimum", "group___min.html", null ],
+        [ "Power", "group__power.html", null ],
+        [ "Root mean square (RMS)", "group___r_m_s.html", null ],
+        [ "Standard deviation", "group___s_t_d.html", null ],
+        [ "Variance", "group__variance.html", null ]
+      ] ],
+      [ "Support Functions", "group__group_support.html", [
+        [ "Vector Copy", "group__copy.html", null ],
+        [ "Vector Fill", "group___fill.html", null ],
+        [ "Convert 32-bit floating point value", "group__float__to__x.html", null ],
+        [ "Convert 16-bit Integer value", "group__q15__to__x.html", null ],
+        [ "Convert 32-bit Integer value", "group__q31__to__x.html", null ],
+        [ "Convert 8-bit Integer value", "group__q7__to__x.html", null ]
+      ] ],
+      [ "Interpolation Functions", "group__group_interpolation.html", [
+        [ "Linear Interpolation", "group___linear_interpolate.html", null ],
+        [ "Bilinear Interpolation", "group___bilinear_interpolate.html", null ]
+      ] ],
+      [ "Examples", "group__group_examples.html", [
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+        [ "Convolution Example", "group___convolution_example.html", null ],
+        [ "Dot Product Example", "group___dotproduct_example.html", null ],
+        [ "Frequency Bin Example", "group___frequency_bin.html", null ],
+        [ "FIR Lowpass Filter Example", "group___f_i_r_l_p_f.html", null ],
+        [ "Graphic Audio Equalizer Example", "group___g_e_q5_band.html", null ],
+        [ "Linear Interpolate Example", "group___linear_interp_example.html", null ],
+        [ "Matrix Example", "group___matrix_example.html", null ],
+        [ "Signal Convergence Example", "group___signal_convergence.html", null ],
+        [ "SineCosine Example", "group___sin_cos_example.html", null ],
+        [ "Variance Example", "group___variance_example.html", null ]
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+      [ "arm_dct4_instance_q31", "structarm__dct4__instance__q31.html", null ],
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+      [ "arm_fir_instance_q7", "structarm__fir__instance__q7.html", null ],
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+      [ "arm_rfft_instance_q31", "structarm__rfft__instance__q31.html", null ]
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+    [ "Data Structure Index", "classes.html", null ],
+    [ "Data Fields", "functions.html", null ],
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diff --git a/CMSIS/Documentation/DSP/html/search/all_5f.html b/CMSIS/Documentation/DSP/html/search/all_5f.html
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index 0000000000..3f9fce5406
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+
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+
Loading...

+

+ 

+  __CMSIS_GENERIC
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+ 

+

+

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diff --git a/CMSIS/Documentation/DSP/html/search/all_61.html b/CMSIS/Documentation/DSP/html/search/all_61.html
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index 0000000000..33c2399d54
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+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  A_f32
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+ 

+

+

+ 

+  Ak
+  arm_convolution_example_f32.c
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+

+

+ 

+  ALIGN4
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+

+
+

+ 

+  arm_abs_f32.c
+ 

+

+

+ 

+  arm_abs_f32.d
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+

+
+

+ 

+  arm_abs_q15.c
+ 

+

+

+ 

+  arm_abs_q15.d
+ 

+

+
+

+ 

+  arm_abs_q31.c
+ 

+

+

+ 

+  arm_abs_q31.d
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+

+
+

+ 

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+

+

+ 

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+

+
+

+ 

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+ 

+

+

+ 

+  arm_add_f32.d
+ 

+

+
+

+ 

+  arm_add_q15.c
+ 

+

+

+ 

+  arm_add_q15.d
+ 

+

+
+

+ 

+  arm_add_q31.c
+ 

+

+

+ 

+  arm_add_q31.d
+ 

+

+
+

+ 

+  arm_add_q7.c
+ 

+

+

+ 

+  arm_add_q7.d
+ 

+

+
+

+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+
+
+
+
+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

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+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
+
+
+
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+
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+
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+

+ 

+  arm_conv_q7.c
+ 

+

+

+ 

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+ 

+

+
+
+
+
+
+
+
+
+
+
+
+

+ 

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+ 

+

+

+ 

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+ 

+

+
+
+
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+
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+
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+
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+ 

+  arm_cos_f32.c
+ 

+

+

+ 

+  arm_cos_f32.d
+ 

+

+
+

+ 

+  arm_cos_q15.c
+ 

+

+

+ 

+  arm_cos_q15.d
+ 

+

+
+

+ 

+  arm_cos_q31.c
+ 

+

+

+ 

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+

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+ 

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+ 

+

+

+ 

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+ 

+

+
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+ 

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+

+

+ 

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+ 

+

+
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+
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+ 

+  arm_fir_q15.c
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+

+

+ 

+  arm_fir_q15.d
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+

+
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+ 

+  arm_fir_q31.c
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+

+

+ 

+  arm_fir_q31.d
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+

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+ 

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+
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+
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+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+
+
+
+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+
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+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

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+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+

+ 

+  arm_lms_f32.c
+ 

+

+

+ 

+  arm_lms_f32.d
+ 

+

+
+
+
+
+
+
+
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+  arm_rfft_f32.c
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+  arm_rfft_q15.c
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+ 

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+  arm_sqrt_q31.c
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+ 

+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

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Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_62.html b/CMSIS/Documentation/DSP/html/search/all_62.html
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+
+
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+
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+

+ 

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+  arm_matrix_example_f32.c
+ 

+

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+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  BLOCK_SIZE
+  arm_fir_example_f32.c
+ 

+

+
+
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+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_63.html b/CMSIS/Documentation/DSP/html/search/all_63.html
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+
+
+
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+
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+

+ 

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+ 

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+
+

+ 

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+  arm_cos_q15.c
+ 

+

+
+
Searching...

+
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diff --git a/CMSIS/Documentation/DSP/html/search/all_64.html b/CMSIS/Documentation/DSP/html/search/all_64.html
new file mode 100644
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+
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+
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+ 

+  DELTA_COEFF
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+ 

+

+

+ 

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+  arm_signal_converge_example_f32.c
+ 

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+ 

+

+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
+
+
+
Searching...

+
No Matches

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+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_65.html b/CMSIS/Documentation/DSP/html/search/all_65.html
new file mode 100644
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+
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+
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+  arm_signal_converge_example_f32.c
+ 

+

+

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+  arm_signal_converge_example_f32.c
+ 

+

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+
No Matches

+
+

+
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diff --git a/CMSIS/Documentation/DSP/html/search/all_66.html b/CMSIS/Documentation/DSP/html/search/all_66.html
new file mode 100644
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diff --git a/CMSIS/Documentation/DSP/html/search/all_67.html b/CMSIS/Documentation/DSP/html/search/all_67.html
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+++ b/CMSIS/Documentation/DSP/html/search/all_67.html
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+
Loading...

+

+ 

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+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  getinput
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_69.html b/CMSIS/Documentation/DSP/html/search/all_69.html
new file mode 100644
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+
Loading...

+
+
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+  INDEX_MASK
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+ 

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+  arm_math.h
+ 

+

+

+ 

+  inputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
No Matches

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+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_6b.html b/CMSIS/Documentation/DSP/html/search/all_6b.html
new file mode 100644
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+
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+
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diff --git a/CMSIS/Documentation/DSP/html/search/all_6c.html b/CMSIS/Documentation/DSP/html/search/all_6c.html
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+++ b/CMSIS/Documentation/DSP/html/search/all_6c.html
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+
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+

+
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+
+

+ 

+  lmsNorm_instance
+  arm_signal_converge_example_f32.c
+ 

+

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+

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+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_6d.html b/CMSIS/Documentation/DSP/html/search/all_6d.html
new file mode 100644
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+
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+
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+
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+
+
+

+ 

+  math_helper.c
+ 

+

+

+ 

+  math_helper.h
+ 

+

+
+

+ 

+  max_marks
+  arm_class_marks_example_f32.c
+ 

+

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+

+ 

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+  arm_class_marks_example_f32.c
+ 

+

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+ 

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+  arm_class_marks_example_f32.c
+ 

+

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+

+ 

+  mult32x64
+  arm_math.h
+ 

+

+

+ 

+  multOutput
+  arm_dotproduct_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_6e.html b/CMSIS/Documentation/DSP/html/search/all_6e.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/all_6e.html
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+
+
+
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+
+
+
+

+
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+
+
+
+

+ 

+  NUM_TAPS
+  arm_fir_example_f32.c
+ 

+

+
+
+

+ 

+  NUMFRAMES
+  arm_signal_converge_example_f32.c
+ 

+

+
+
+
+
+
+

+ 

+  nValues
+  arm_linear_interp_instance_f32
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_6f.html b/CMSIS/Documentation/DSP/html/search/all_6f.html
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+
+
+
+
+
+
+
+

+
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+
+

+ 

+  outLen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  outputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_70.html b/CMSIS/Documentation/DSP/html/search/all_70.html
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+
+
+
+
+
+
+
+

+
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+
+
+
+
+
+
+

+ 

+  PI
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  pYData
+  arm_linear_interp_instance_f32
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_71.html b/CMSIS/Documentation/DSP/html/search/all_71.html
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+
+
+
+
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+
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+

+
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+

+ 

+  q15_t
+  arm_math.h
+ 

+

+

+ 

+  q31_t
+  arm_math.h
+ 

+

+

+ 

+  q63_t
+  arm_math.h
+ 

+

+

+ 

+  q7_t
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_72.html b/CMSIS/Documentation/DSP/html/search/all_72.html
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+
+
+
+
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+
+
+

+
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+

+ 

+  realCoefA
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefAQ15
+  arm_rfft_init_q15.c
+ 

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+  arm_rfft_init_f32.c
+ 

+

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+ 

+  realCoefBQ15
+  arm_rfft_init_q15.c
+ 

+

+
+
+

+ 

+  refDotProdOut
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  refIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_73.html b/CMSIS/Documentation/DSP/html/search/all_73.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  sinOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  sinSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  sinTableQ15
+  arm_sin_q15.c
+ 

+

+
+
+

+ 

+  snr1
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  snr2
+  arm_linear_interp_example_f32.c
+ 

+

+
+
+

+ 

+  srcA_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcALen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  srcB_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcBLen
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+

+ 

+  std
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  student_num
+  arm_class_marks_example_f32.c
+ 

+

+
+
+
+
+
+
+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_74.html b/CMSIS/Documentation/DSP/html/search/all_74.html
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+++ b/CMSIS/Documentation/DSP/html/search/all_74.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  TABLE_SIZE
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q15
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q31
+  arm_math.h
+ 

+

+
+

+ 

+  test_signal_converge
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  test_signal_converge_example
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  testIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+
+
+

+ 

+  testInputA_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputB_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  testLinIntOutput
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  testRefSinOutput32_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+
+
+
+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_75.html b/CMSIS/Documentation/DSP/html/search/all_75.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  USE_STATIC_INIT
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_76.html b/CMSIS/Documentation/DSP/html/search/all_76.html
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+++ b/CMSIS/Documentation/DSP/html/search/all_76.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  var
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_77.html b/CMSIS/Documentation/DSP/html/search/all_77.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  Weights_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_2048
+  arm_dct4_init_f32.c
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+  WeightsQ15_512
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+

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+  WeightsQ31_512
+  arm_dct4_init_q31.c
+ 

+

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+ 

+  WeightsQ31_8192
+  arm_dct4_init_q31.c
+ 

+

+
+
+
+
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+
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+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/search/all_78.html b/CMSIS/Documentation/DSP/html/search/all_78.html
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+
+
+
+
+
+
+
+

+
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+
+

+ 

+  x1
+  arm_linear_interp_instance_f32
+ 

+

+

+ 

+  X_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xRef_f32
+  arm_matrix_example_f32.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/classes_61.html b/CMSIS/Documentation/DSP/html/search/classes_61.html
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+
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diff --git a/CMSIS/Documentation/DSP/html/search/defines_5f.html b/CMSIS/Documentation/DSP/html/search/defines_5f.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  __CMSIS_GENERIC
+  arm_math.h
+ 

+

+

+ 

+  __HSI
+  

+    __HSI(): system_ARMCM0.c
+    __HSI(): system_ARMCM3.c
+    __HSI(): system_ARMCM4.c
+  

+ 

+

+

+ 

+  __PACKq7
+  arm_math.h
+ 

+

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+ 

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+  arm_math.h
+ 

+

+

+ 

+  __SIMD64
+  arm_math.h
+ 

+

+

+ 

+  __SYSTEM_CLOCK
+  

+    __SYSTEM_CLOCK(): system_ARMCM0.c
+    __SYSTEM_CLOCK(): system_ARMCM3.c
+    __SYSTEM_CLOCK(): system_ARMCM4.c
+  

+ 

+

+

+ 

+  __XTAL
+  

+    __XTAL(): system_ARMCM0.c
+    __XTAL(): system_ARMCM3.c
+    __XTAL(): system_ARMCM4.c
+  

+ 

+

+

+ 

+  _SIMD32_OFFSET
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_61.html b/CMSIS/Documentation/DSP/html/search/defines_61.html
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+
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+

+
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+

+ 

+  ALIGN4
+  arm_math.h
+ 

+

+
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+
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+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_62.html b/CMSIS/Documentation/DSP/html/search/defines_62.html
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+
+
+
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+
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+

+
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+

+ 

+  BLOCK_SIZE
+  arm_fir_example_f32.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_64.html b/CMSIS/Documentation/DSP/html/search/defines_64.html
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+
+
+
+
+
+
+
+

+
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+
+

+ 

+  DELTA_COEFF
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_ERROR
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_Q15
+  arm_math.h
+ 

+

+

+ 

+  DELTA_Q31
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_69.html b/CMSIS/Documentation/DSP/html/search/defines_69.html
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+
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+

+
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+

+ 

+  INDEX_MASK
+  arm_math.h
+ 

+

+

+ 

+  INPUT_SPACING
+  arm_math.h
+ 

+

+
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+
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+
+

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+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_6d.html b/CMSIS/Documentation/DSP/html/search/defines_6d.html
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+
+
+
+
+
+
+
+

+
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+
+

+ 

+  MU
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_6e.html b/CMSIS/Documentation/DSP/html/search/defines_6e.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  NUM_TAPS
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  NUMBLOCKS
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMFRAMES
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  NUMSTAGES
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMSTUDENTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMSUBJECTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMTAPS
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_70.html b/CMSIS/Documentation/DSP/html/search/defines_70.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  PI
+  arm_math.h
+ 

+

+
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+
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+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_73.html b/CMSIS/Documentation/DSP/html/search/defines_73.html
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+
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diff --git a/CMSIS/Documentation/DSP/html/search/defines_74.html b/CMSIS/Documentation/DSP/html/search/defines_74.html
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+

+
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+

+ 

+  TABLE_SIZE
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q15
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q31
+  arm_math.h
+ 

+

+
+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_75.html b/CMSIS/Documentation/DSP/html/search/defines_75.html
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+
+
+
+
+
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+
+

+
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+

+ 

+  USE_STATIC_INIT
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/defines_78.html b/CMSIS/Documentation/DSP/html/search/defines_78.html
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+
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+
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+
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+

+
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+

+ 

+  XSPACING
+  arm_linear_interp_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/enums_61.html b/CMSIS/Documentation/DSP/html/search/enums_61.html
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+
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+
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+

+
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+

+ 

+  arm_status
+  arm_math.h
+ 

+

+
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+
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+
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+
+
diff --git a/CMSIS/Documentation/DSP/html/search/enumvalues_61.html b/CMSIS/Documentation/DSP/html/search/enumvalues_61.html
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+

+
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+

+ 

+  ARM_MATH_ARGUMENT_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_LENGTH_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_NANINF
+  arm_math.h
+ 

+

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+  arm_math.h
+ 

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+  arm_math.h
+ 

+

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+  arm_math.h
+ 

+

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+ 

+  ARM_MATH_TEST_FAILURE
+  arm_math.h
+ 

+

+
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+
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+
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+
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diff --git a/CMSIS/Documentation/DSP/html/search/files_61.html b/CMSIS/Documentation/DSP/html/search/files_61.html
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+

+
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+

+ 

+  arm_abs_f32.c
+ 

+

+

+ 

+  arm_abs_f32.d
+ 

+

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+  arm_abs_q15.c
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+ 

+  arm_conv_q7.c
+ 

+

+

+ 

+  arm_conv_q7.d
+ 

+

+
+
+
+
+
+
+
+

+ 

+  arm_copy_q7.c
+ 

+

+

+ 

+  arm_copy_q7.d
+ 

+

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+ 

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+ 

+

+

+ 

+  arm_cos_f32.d
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+

+

+ 

+  arm_cos_q15.c
+ 

+

+

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+  arm_cos_q15.d
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+

+ 

+  arm_cos_q31.c
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+
+
+
+
+
+

+ 

+  arm_fill_q7.c
+ 

+

+

+ 

+  arm_fill_q7.d
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fir_f32.c
+ 

+

+

+ 

+  arm_fir_f32.d
+ 

+

+
+
+
+
+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+

+ 

+  arm_fir_q15.c
+ 

+

+

+ 

+  arm_fir_q15.d
+ 

+

+

+ 

+  arm_fir_q31.c
+ 

+

+

+ 

+  arm_fir_q31.d
+ 

+

+

+ 

+  arm_fir_q7.c
+ 

+

+

+ 

+  arm_fir_q7.d
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_lms_f32.c
+ 

+

+

+ 

+  arm_lms_f32.d
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_lms_q15.c
+ 

+

+

+ 

+  arm_lms_q15.d
+ 

+

+

+ 

+  arm_lms_q31.c
+ 

+

+

+ 

+  arm_lms_q31.d
+ 

+

+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_math.h
+ 

+

+
+

+ 

+  arm_max_f32.c
+ 

+

+

+ 

+  arm_max_f32.d
+ 

+

+

+ 

+  arm_max_q15.c
+ 

+

+

+ 

+  arm_max_q15.d
+ 

+

+

+ 

+  arm_max_q31.c
+ 

+

+

+ 

+  arm_max_q31.d
+ 

+

+

+ 

+  arm_max_q7.c
+ 

+

+

+ 

+  arm_max_q7.d
+ 

+

+
+
+
+
+
+
+

+ 

+  arm_mean_q7.c
+ 

+

+

+ 

+  arm_mean_q7.d
+ 

+

+

+ 

+  arm_min_f32.c
+ 

+

+

+ 

+  arm_min_f32.d
+ 

+

+

+ 

+  arm_min_q15.c
+ 

+

+

+ 

+  arm_min_q15.d
+ 

+

+

+ 

+  arm_min_q31.c
+ 

+

+

+ 

+  arm_min_q31.d
+ 

+

+

+ 

+  arm_min_q7.c
+ 

+

+

+ 

+  arm_min_q7.d
+ 

+

+
+
+
+
+
+
+

+ 

+  arm_mult_q7.c
+ 

+

+

+ 

+  arm_mult_q7.d
+ 

+

+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_rms_f32.c
+ 

+

+

+ 

+  arm_rms_f32.d
+ 

+

+

+ 

+  arm_rms_q15.c
+ 

+

+

+ 

+  arm_rms_q15.d
+ 

+

+

+ 

+  arm_rms_q31.c
+ 

+

+

+ 

+  arm_rms_q31.d
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_sin_f32.c
+ 

+

+

+ 

+  arm_sin_f32.d
+ 

+

+

+ 

+  arm_sin_q15.c
+ 

+

+

+ 

+  arm_sin_q15.d
+ 

+

+

+ 

+  arm_sin_q31.c
+ 

+

+

+ 

+  arm_sin_q31.d
+ 

+

+
+
+
+
+

+ 

+  arm_std_f32.c
+ 

+

+

+ 

+  arm_std_f32.d
+ 

+

+

+ 

+  arm_std_q15.c
+ 

+

+

+ 

+  arm_std_q15.d
+ 

+

+

+ 

+  arm_std_q31.c
+ 

+

+

+ 

+  arm_std_q31.d
+ 

+

+

+ 

+  arm_sub_f32.c
+ 

+

+

+ 

+  arm_sub_f32.d
+ 

+

+

+ 

+  arm_sub_q15.c
+ 

+

+

+ 

+  arm_sub_q15.d
+ 

+

+

+ 

+  arm_sub_q31.c
+ 

+

+

+ 

+  arm_sub_q31.d
+ 

+

+

+ 

+  arm_sub_q7.c
+ 

+

+

+ 

+  arm_sub_q7.d
+ 

+

+

+ 

+  arm_var_f32.c
+ 

+

+

+ 

+  arm_var_f32.d
+ 

+

+

+ 

+  arm_var_q15.c
+ 

+

+

+ 

+  arm_var_q15.d
+ 

+

+

+ 

+  arm_var_q31.c
+ 

+

+

+ 

+  arm_var_q31.d
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/files_64.html b/CMSIS/Documentation/DSP/html/search/files_64.html
new file mode 100644
index 0000000000..2cf1cdf81b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/files_64.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/files_6d.html b/CMSIS/Documentation/DSP/html/search/files_6d.html
new file mode 100644
index 0000000000..ebb6beda68
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/files_6d.html
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  math_helper.c
+ 

+

+

+ 

+  math_helper.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/files_73.html b/CMSIS/Documentation/DSP/html/search/files_73.html
new file mode 100644
index 0000000000..a1422d9496
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/files_73.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_61.html b/CMSIS/Documentation/DSP/html/search/functions_61.html
new file mode 100644
index 0000000000..9c03798724
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_61.html
@@ -0,0 +1,2771 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+
+
+
+
+
+

+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_f32
+  arm_math.h
+ 

+

+
+
+
+

+ 

+  arm_pid_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  arm_provide_guard_bits_q7
+  math_helper.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_recip_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_recip_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_split_rfft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rfft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rfft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_split_rifft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rifft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rifft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_sqrt_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_sqrt_q15
+  arm_sqrt_q15.c
+ 

+

+

+ 

+  arm_sqrt_q31
+  arm_sqrt_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_63.html b/CMSIS/Documentation/DSP/html/search/functions_63.html
new file mode 100644
index 0000000000..eac1a7ef32
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_63.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  clip_q31_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q31_to_q7
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q31
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_66.html b/CMSIS/Documentation/DSP/html/search/functions_66.html
new file mode 100644
index 0000000000..232468d82e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_66.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_67.html b/CMSIS/Documentation/DSP/html/search/functions_67.html
new file mode 100644
index 0000000000..0a70c9ecd7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_67.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  getinput
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_6d.html b/CMSIS/Documentation/DSP/html/search/functions_6d.html
new file mode 100644
index 0000000000..a625d12bd9
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_6d.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  mult32x64
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_73.html b/CMSIS/Documentation/DSP/html/search/functions_73.html
new file mode 100644
index 0000000000..7a48389e6e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_73.html
@@ -0,0 +1,40 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/functions_74.html b/CMSIS/Documentation/DSP/html/search/functions_74.html
new file mode 100644
index 0000000000..bf5b59a4b8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/functions_74.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  test_signal_converge
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  test_signal_converge_example
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/mag_sel.png b/CMSIS/Documentation/DSP/html/search/mag_sel.png
new file mode 100644
index 0000000000..81f6040a20
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/search/mag_sel.png differ
diff --git a/CMSIS/Documentation/DSP/html/search/nomatches.html b/CMSIS/Documentation/DSP/html/search/nomatches.html
new file mode 100644
index 0000000000..b1ded27e9a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/nomatches.html
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+

+
No Matches

+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/search.css b/CMSIS/Documentation/DSP/html/search/search.css
new file mode 100644
index 0000000000..1746d13fd6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
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+#searchli {
+    float: right;
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+#MSearchBox .left
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+    font: 9pt Arial, Verdana, sans-serif;
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+#FSearchBox #MSearchField {
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+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
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+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
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+.MSearchBoxActive #MSearchField {
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+#MSearchSelectWindow {
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+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/CMSIS/Documentation/DSP/html/search/search.js b/CMSIS/Documentation/DSP/html/search/search.js
new file mode 100644
index 0000000000..0c612c9c20
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/search.js
@@ -0,0 +1,742 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111101011111111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000100000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001100000100000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101011111101110111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100001000110100111001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "typedefs",
+  6: "enums",
+  7: "enumvalues",
+  8: "defines"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of .
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/CMSIS/Documentation/DSP/html/search/search_l.png b/CMSIS/Documentation/DSP/html/search/search_l.png
new file mode 100644
index 0000000000..c872f4da4a
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/search/search_l.png differ
diff --git a/CMSIS/Documentation/DSP/html/search/search_m.png b/CMSIS/Documentation/DSP/html/search/search_m.png
new file mode 100644
index 0000000000..b429a16ba6
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/search/search_m.png differ
diff --git a/CMSIS/Documentation/DSP/html/search/search_r.png b/CMSIS/Documentation/DSP/html/search/search_r.png
new file mode 100644
index 0000000000..97ee8b4396
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/search/search_r.png differ
diff --git a/CMSIS/Documentation/DSP/html/search/typedefs_66.html b/CMSIS/Documentation/DSP/html/search/typedefs_66.html
new file mode 100644
index 0000000000..3f3d94fd5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/typedefs_66.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  float32_t
+  arm_math.h
+ 

+

+

+ 

+  float64_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/typedefs_71.html b/CMSIS/Documentation/DSP/html/search/typedefs_71.html
new file mode 100644
index 0000000000..c889272b96
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/typedefs_71.html
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  q15_t
+  arm_math.h
+ 

+

+

+ 

+  q31_t
+  arm_math.h
+ 

+

+

+ 

+  q63_t
+  arm_math.h
+ 

+

+

+ 

+  q7_t
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_61.html b/CMSIS/Documentation/DSP/html/search/variables_61.html
new file mode 100644
index 0000000000..0c1e1d40e5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_61.html
@@ -0,0 +1,121 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  A_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  Ak
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+
+

+ 

+  AT_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMA_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMAI_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_62.html b/CMSIS/Documentation/DSP/html/search/variables_62.html
new file mode 100644
index 0000000000..5bc0c81ac4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_62.html
@@ -0,0 +1,108 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  B_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  biquadStateBand1Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand2Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand3Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand4Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand5Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
+
+
+

+ 

+  Bk
+  arm_convolution_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_63.html b/CMSIS/Documentation/DSP/html/search/variables_63.html
new file mode 100644
index 0000000000..197e64b7bd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_63.html
@@ -0,0 +1,134 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  coeffTable
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  cos_factors_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_8192
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factorsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_8192
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_8192
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cosOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  cosSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  cosTableQ15
+  arm_cos_q15.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_64.html b/CMSIS/Documentation/DSP/html/search/variables_64.html
new file mode 100644
index 0000000000..7da528e30b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_64.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_65.html b/CMSIS/Documentation/DSP/html/search/variables_65.html
new file mode 100644
index 0000000000..c06f61fb41
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_65.html
@@ -0,0 +1,42 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  err_signal
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  errOutput
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_66.html b/CMSIS/Documentation/DSP/html/search/variables_66.html
new file mode 100644
index 0000000000..9c87f4234d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_66.html
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_67.html b/CMSIS/Documentation/DSP/html/search/variables_67.html
new file mode 100644
index 0000000000..e2b59957a0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_67.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  gainDB
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_69.html b/CMSIS/Documentation/DSP/html/search/variables_69.html
new file mode 100644
index 0000000000..915b1aea5a
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_69.html
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+

+ 

+  inputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_6b.html b/CMSIS/Documentation/DSP/html/search/variables_6b.html
new file mode 100644
index 0000000000..286eb6dbff
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_6b.html
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_6c.html b/CMSIS/Documentation/DSP/html/search/variables_6c.html
new file mode 100644
index 0000000000..61ba9d07b4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_6c.html
@@ -0,0 +1,57 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  lmsNorm_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
+

+ 

+  lmsStateF32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_6d.html b/CMSIS/Documentation/DSP/html/search/variables_6d.html
new file mode 100644
index 0000000000..45f41dae9f
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_6d.html
@@ -0,0 +1,78 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  max_marks
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  mean
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  min_marks
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  multOutput
+  arm_dotproduct_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_6e.html b/CMSIS/Documentation/DSP/html/search/variables_6e.html
new file mode 100644
index 0000000000..e3578fbce0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_6e.html
@@ -0,0 +1,144 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  numBlocks
+  arm_fir_example_f32.c
+ 

+

+
+
+
+

+ 

+  numStudents
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  numSubjects
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  nValues
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_6f.html b/CMSIS/Documentation/DSP/html/search/variables_6f.html
new file mode 100644
index 0000000000..f957621c5d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_6f.html
@@ -0,0 +1,41 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  outLen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  outputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_70.html b/CMSIS/Documentation/DSP/html/search/variables_70.html
new file mode 100644
index 0000000000..9d47ed3700
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_70.html
@@ -0,0 +1,250 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  pYData
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_72.html b/CMSIS/Documentation/DSP/html/search/variables_72.html
new file mode 100644
index 0000000000..e244780034
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_72.html
@@ -0,0 +1,98 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  realCoefA
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefAQ15
+  arm_rfft_init_q15.c
+ 

+

+
+

+ 

+  realCoefB
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefBQ15
+  arm_rfft_init_q15.c
+ 

+

+
+
+

+ 

+  refDotProdOut
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  refIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_73.html b/CMSIS/Documentation/DSP/html/search/variables_73.html
new file mode 100644
index 0000000000..eac4ed7e79
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_73.html
@@ -0,0 +1,155 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  sinOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  sinSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  sinTableQ15
+  arm_sin_q15.c
+ 

+

+
+
+

+ 

+  snr1
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  snr2
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  srcA_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcALen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  srcB_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcBLen
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+

+ 

+  std
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  student_num
+  arm_class_marks_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_74.html b/CMSIS/Documentation/DSP/html/search/variables_74.html
new file mode 100644
index 0000000000..1667fac6de
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_74.html
@@ -0,0 +1,174 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  testIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+
+
+

+ 

+  testInputA_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputB_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testLinIntOutput
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  testRefSinOutput32_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_76.html b/CMSIS/Documentation/DSP/html/search/variables_76.html
new file mode 100644
index 0000000000..4366f2a098
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_76.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  var
+  arm_class_marks_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_77.html b/CMSIS/Documentation/DSP/html/search/variables_77.html
new file mode 100644
index 0000000000..1582012bce
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_77.html
@@ -0,0 +1,119 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  Weights_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_8192
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  WeightsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_8192
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_8192
+  arm_dct4_init_q31.c
+ 

+

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/search/variables_78.html b/CMSIS/Documentation/DSP/html/search/variables_78.html
new file mode 100644
index 0000000000..8bffbb6b09
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/search/variables_78.html
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  x1
+  arm_linear_interp_instance_f32
+ 

+

+

+ 

+  X_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xRef_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xSpacing
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/DSP/html/sinCos.gif b/CMSIS/Documentation/DSP/html/sinCos.gif
new file mode 100644
index 0000000000..b31221f9c2
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/sinCos.gif differ
diff --git a/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__f32.html
new file mode 100644
index 0000000000..d8542b3d13
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__f32.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_bilinear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point bilinear interpolation function.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numCols

+

+

+
number of columns in the data table. 

+
+
Referenced by arm_bilinear_interp_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numRows

+

+

+
number of rows in the data table. 

+
+
Referenced by arm_bilinear_interp_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_bilinear_interp_instance_f32::pData

+

+

+
points to the data table. 

+
+
Referenced by arm_bilinear_interp_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q15.html
new file mode 100644
index 0000000000..5edbffcf17
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q15.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_bilinear_interp_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numCols

+

+

+
number of columns in the data table. 

+
+
Referenced by arm_bilinear_interp_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numRows

+

+

+
number of rows in the data table. 

+
+
Referenced by arm_bilinear_interp_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_bilinear_interp_instance_q15::pData

+

+

+
points to the data table. 

+
+
Referenced by arm_bilinear_interp_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q31.html
new file mode 100644
index 0000000000..1219df1f52
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q31.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_bilinear_interp_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 bilinear interpolation function.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numCols

+

+

+
number of columns in the data table. 

+
+
Referenced by arm_bilinear_interp_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numRows

+

+

+
number of rows in the data table. 

+
+
Referenced by arm_bilinear_interp_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_bilinear_interp_instance_q31::pData

+

+

+
points to the data table. 

+
+
Referenced by arm_bilinear_interp_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q7.html b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q7.html
new file mode 100644
index 0000000000..bab81f0ec1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__bilinear__interp__instance__q7.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_bilinear_interp_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q7_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numCols

+

+

+
number of columns in the data table. 

+
+
Referenced by arm_bilinear_interp_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numRows

+

+

+
number of rows in the data table. 

+
+
Referenced by arm_bilinear_interp_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_bilinear_interp_instance_q7::pData

+

+

+
points to the data table. 

+
+
Referenced by arm_bilinear_interp_q7().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__biquad__cas__df1__32x64__ins__q31.html b/CMSIS/Documentation/DSP/html/structarm__biquad__cas__df1__32x64__ins__q31.html
new file mode 100644
index 0000000000..bbaa295e33
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__biquad__cas__df1__32x64__ins__q31.html
@@ -0,0 +1,219 @@
+
+
+
+
+arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
  

+

+

+
+
Instance structure for the high precision Q31 Biquad cascade filter.  
+ More...

+
+
+
+
+
+
+

+Data Fields
uint8_t numStages
q63_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Description

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_cas_df1_32x64_ins_q31::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::postShift

+

+

+
additional shift, in bits, applied to each output sample. 

+
+
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t* arm_biquad_cas_df1_32x64_ins_q31::pState

+

+

+
points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__biquad__cascade__df2_t__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__biquad__cascade__df2_t__instance__f32.html
new file mode 100644
index 0000000000..1114e512dd
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__biquad__cascade__df2_t__instance__f32.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_biquad_cascade_df2T_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_biquad_cascade_df2T_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point transposed direct form II Biquad cascade filter.  
+

+
+
+
+
+
+

+Data Fields
uint8_t numStages
float32_t * pState
float32_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cascade_df2T_instance_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pState

+

+

+
points to the array of state coefficients. The array is of length 2*numStages. 

+
+
Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__f32.html b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__f32.html
new file mode 100644
index 0000000000..2ab87171c7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__f32.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_biquad_casd_df1_inst_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Biquad cascade filter.  
+

+
+
+
+
+
+

+Data Fields
uint32_t numStages
float32_t * pState
float32_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q15.html b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q15.html
new file mode 100644
index 0000000000..eba465d11d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q15.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_biquad_casd_df1_inst_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 Biquad cascade filter.  
+

+
+
+
+
+
+
+

+Data Fields
int8_t numStages
q15_t * pState
q15_t * pCoeffs
int8_t postShift

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q31.html b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q31.html
new file mode 100644
index 0000000000..663b9bcf9e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__biquad__casd__df1__inst__q31.html
@@ -0,0 +1,219 @@
+
+
+
+
+arm_biquad_casd_df1_inst_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 Biquad cascade filter.  
+ More...

+
+
+
+
+
+
+

+Data Fields
uint32_t numStages
q31_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Description

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_casd_df1_inst_q31::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__f32.html
new file mode 100644
index 0000000000..d107c1a34c
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__f32.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_cfft_radix2_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix2_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point CFFT/CIFFT function.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
float32_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor
float32_t onebyfftLen

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_f32::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_f32::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_f32::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_f32::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_cfft_radix2_instance_f32::onebyfftLen

+

+

+
value of 1/fftLen. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix2_instance_f32::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_cfft_radix2_instance_f32::pTwiddle

+

+

+
points to the Twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_f32::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q15.html
new file mode 100644
index 0000000000..24a5638ac5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q15.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_cfft_radix2_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix2_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 CFFT/CIFFT function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q15_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_q15::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix2_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q15::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q15::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_q15::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix2_instance_q15::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_cfft_radix2_instance_q15::pTwiddle

+

+

+
points to the Sin twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q15::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q31.html
new file mode 100644
index 0000000000..adbb17ee20
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q31.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_cfft_radix2_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix2_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Radix-2 Q31 CFFT/CIFFT function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q31_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_q31::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix2_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q31::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q31::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix2_instance_q31::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix2_instance_q31::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_cfft_radix2_instance_q31::pTwiddle

+

+

+
points to the Twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix2_instance_q31::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__f32.html
new file mode 100644
index 0000000000..c8149e528b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__f32.html
@@ -0,0 +1,287 @@
+
+
+
+
+arm_cfft_radix4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point CFFT/CIFFT function.  
+ More...

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
float32_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor
float32_t onebyfftLen

+
Description

+
Examples: 

+
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_cfft_radix4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix4_f32(), and arm_cfft_radix4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_cfft_radix4_instance_f32::onebyfftLen

+

+

+
value of 1/fftLen. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_f32::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_cfft_radix4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q15.html
new file mode 100644
index 0000000000..66255ded0e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q15.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_cfft_radix4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 CFFT/CIFFT function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q15_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix4_init_q15(), and arm_cfft_radix4_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix4_init_q15(), and arm_cfft_radix4_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q15::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_cfft_radix4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q31.html
new file mode 100644
index 0000000000..9d7062b636
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q31.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_cfft_radix4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 CFFT/CIFFT function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q31_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Referenced by arm_cfft_radix4_init_q31(), and arm_cfft_radix4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::fftLen

+

+

+
length of the FFT. 

+
+
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Referenced by arm_cfft_radix4_init_q31(), and arm_cfft_radix4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q31::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_cfft_radix4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__dct4__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__f32.html
new file mode 100644
index 0000000000..631e07aa09
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__f32.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_dct4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_dct4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point DCT4/IDCT4 function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
float32_t normalize
float32_t * pTwiddle
float32_t * pCosFactor
arm_rfft_instance_f32 * pRfft
arm_cfft_radix4_instance_f32 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::N

+

+

+
length of the DCT4. 

+
+
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_dct4_instance_f32::normalize

+

+

+
normalizing factor. 

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_dct4_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_f32* arm_dct4_instance_f32::pRfft

+

+

+
points to the real FFT instance. 

+
+
Referenced by arm_dct4_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q15.html
new file mode 100644
index 0000000000..1ca536a2fa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q15.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_dct4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_dct4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 DCT4/IDCT4 function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q15_t normalize
q15_t * pTwiddle
q15_t * pCosFactor
arm_rfft_instance_q15 * pRfft
arm_cfft_radix4_instance_q15 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::N

+

+

+
length of the DCT4. 

+
+
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_dct4_instance_q15::normalize

+

+

+
normalizing factor. 

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_dct4_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q15* arm_dct4_instance_q15::pRfft

+

+

+
points to the real FFT instance. 

+
+
Referenced by arm_dct4_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q31.html
new file mode 100644
index 0000000000..9f6cb64a45
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q31.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_dct4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_dct4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 DCT4/IDCT4 function.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q31_t normalize
q31_t * pTwiddle
q31_t * pCosFactor
arm_rfft_instance_q31 * pRfft
arm_cfft_radix4_instance_q31 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::N

+

+

+
length of the DCT4. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_dct4_instance_q31::normalize

+

+

+
normalizing factor. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_dct4_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_dct4_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q31* arm_dct4_instance_q31::pRfft

+

+

+
points to the real FFT instance. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__f32.html
new file mode 100644
index 0000000000..8f0de44700
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__f32.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_decimate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR decimator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
float32_t * pCoeffs
float32_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_f32::M

+

+

+
decimation factor. 

+
+
Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q15.html
new file mode 100644
index 0000000000..e90661de7e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q15.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_decimate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR decimator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q15_t * pCoeffs
q15_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q15::M

+

+

+
decimation factor. 

+
+
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q31.html
new file mode 100644
index 0000000000..69c03cfdb0
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q31.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_decimate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR decimator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q31_t * pCoeffs
q31_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q31::M

+

+

+
decimation factor. 

+
+
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__fir__instance__f32.html
new file mode 100644
index 0000000000..b874a2f8a7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__instance__f32.html
@@ -0,0 +1,202 @@
+
+
+
+
+arm_fir_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR filter.  
+ More...

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs

+
Description

+
Examples: 

+
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_f32::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Referenced by arm_fir_f32(), and arm_fir_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_f32(), and arm_fir_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_f32(), and arm_fir_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q15.html
new file mode 100644
index 0000000000..f98f0d7aff
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q15.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q15::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q31.html
new file mode 100644
index 0000000000..d9ce797fce
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q31.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q31::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__instance__q7.html b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q7.html
new file mode 100644
index 0000000000..8ed65ddbad
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__instance__q7.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 FIR filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q7_t * pState
q7_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q7::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Referenced by arm_fir_init_q7(), and arm_fir_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_init_q7(), and arm_fir_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_fir_init_q7(), and arm_fir_q7().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__f32.html
new file mode 100644
index 0000000000..e6c3ae5984
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__f32.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_interpolate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR interpolator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
float32_t * pCoeffs
float32_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_f32::L

+

+

+
upsample factor. 

+
+
Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_f32::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length phaseLength+numTaps-1. 

+
+
Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q15.html
new file mode 100644
index 0000000000..7541902c2e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q15.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_interpolate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR interpolator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q15_t * pCoeffs
q15_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q15::L

+

+

+
upsample factor. 

+
+
Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q15::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q31.html
new file mode 100644
index 0000000000..8eebc7509d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q31.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_fir_interpolate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR interpolator.  
+

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q31_t * pCoeffs
q31_t * pState

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q31::L

+

+

+
upsample factor. 

+
+
Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q31::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__f32.html
new file mode 100644
index 0000000000..4c2e060fe2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__f32.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR lattice filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_f32::numStages

+

+

+
number of filter stages. 

+
+
Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q15.html
new file mode 100644
index 0000000000..abe0f4755d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q15.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR lattice filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q15::numStages

+

+

+
number of filter stages. 

+
+
Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q31.html
new file mode 100644
index 0000000000..df30268df2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q31.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_fir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR lattice filter.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q31::numStages

+

+

+
number of filter stages. 

+
+
Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__f32.html
new file mode 100644
index 0000000000..ace8f56cd3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__f32.html
@@ -0,0 +1,249 @@
+
+
+
+
+arm_fir_sparse_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point sparse FIR filter.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
float32_t * pState
float32_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_f32::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q15.html
new file mode 100644
index 0000000000..4e7ca441fc
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q15.html
@@ -0,0 +1,249 @@
+
+
+
+
+arm_fir_sparse_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 sparse FIR filter.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q15_t * pState
q15_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q15::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q31.html
new file mode 100644
index 0000000000..5472024ef1
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q31.html
@@ -0,0 +1,249 @@
+
+
+
+
+arm_fir_sparse_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 sparse FIR filter.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q31_t * pState
q31_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q31::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q7.html b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q7.html
new file mode 100644
index 0000000000..f41f98a895
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q7.html
@@ -0,0 +1,249 @@
+
+
+
+
+arm_fir_sparse_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 sparse FIR filter.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q7_t * pState
q7_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q7::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__f32.html
new file mode 100644
index 0000000000..923c70dca4
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__f32.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_iir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point IIR lattice filter.  
+

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pkCoeffs
float32_t * pvCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_f32::numStages

+

+

+
number of stages in the filter. 

+
+
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q15.html
new file mode 100644
index 0000000000..e068928190
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q15.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_iir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 IIR lattice filter.  
+

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pkCoeffs
q15_t * pvCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q15::numStages

+

+

+
number of stages in the filter. 

+
+
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q31.html
new file mode 100644
index 0000000000..e891fee80d
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q31.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_iir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 IIR lattice filter.  
+

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pkCoeffs
q31_t * pvCoeffs

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q31::numStages

+

+

+
number of stages in the filter. 

+
+
Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__linear__interp__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__linear__interp__instance__f32.html
new file mode 100644
index 0000000000..c543676de5
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__linear__interp__instance__f32.html
@@ -0,0 +1,219 @@
+
+
+
+
+arm_linear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_linear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Linear Interpolate function.  
+ More...

+
+
+
+
+
+
+

+Data Fields
uint32_t nValues
float32_t x1
float32_t xSpacing
float32_t * pYData

+
Description

+
Examples: 

+
arm_linear_interp_example_f32.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_linear_interp_instance_f32::nValues

+

+

+
nValues 

+
+
Referenced by arm_linear_interp_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_linear_interp_instance_f32::pYData

+

+

+
pointer to the table of Y values 

+
+
Referenced by arm_linear_interp_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::x1

+

+

+
x1 

+
+
Referenced by arm_linear_interp_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::xSpacing

+

+

+
xSpacing 

+
+
Referenced by arm_linear_interp_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__lms__instance__f32.html
new file mode 100644
index 0000000000..b812715f7e
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__instance__f32.html
@@ -0,0 +1,215 @@
+
+
+
+
+arm_lms_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point LMS filter.  
+

+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_instance_f32::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Referenced by arm_lms_f32(), and arm_lms_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_lms_f32(), and arm_lms_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_f32(), and arm_lms_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_f32(), and arm_lms_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__lms__instance__q15.html
new file mode 100644
index 0000000000..b627f07fab
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__instance__q15.html
@@ -0,0 +1,232 @@
+
+
+
+
+arm_lms_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 LMS filter.  
+

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint32_t postShift

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Referenced by arm_lms_init_q15(), and arm_lms_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_lms_init_q15(), and arm_lms_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_init_q15(), and arm_lms_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Referenced by arm_lms_init_q15(), and arm_lms_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_init_q15(), and arm_lms_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__lms__instance__q31.html
new file mode 100644
index 0000000000..b1845c6eab
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__instance__q31.html
@@ -0,0 +1,232 @@
+
+
+
+
+arm_lms_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 LMS filter.  
+

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint32_t postShift

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Referenced by arm_lms_init_q31(), and arm_lms_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_lms_init_q31(), and arm_lms_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_init_q31(), and arm_lms_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Referenced by arm_lms_init_q31(), and arm_lms_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_init_q31(), and arm_lms_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__f32.html
new file mode 100644
index 0000000000..ff09244af6
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__f32.html
@@ -0,0 +1,253 @@
+
+
+
+
+arm_lms_norm_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point normalized LMS filter.  
+ More...

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu
float32_t energy
float32_t x0

+
Description

+
Examples: 

+
arm_signal_converge_example_f32.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::energy

+

+

+
saves previous frame energy. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::mu

+

+

+
step size that control filter coefficient updates. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::x0

+

+

+
saves previous input sample. 

+
+
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q15.html
new file mode 100644
index 0000000000..ec637263af
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q15.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_lms_norm_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 normalized LMS filter.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint8_t postShift
q15_t * recipTable
q15_t energy
q15_t x0

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::energy

+

+

+
saves previous frame energy. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q15::numTaps

+

+

+
Number of coefficients in the filter. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::recipTable

+

+

+
Points to the reciprocal initial value table. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::x0

+

+

+
saves previous input sample. 

+
+
Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q31.html
new file mode 100644
index 0000000000..0470082eb2
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q31.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_lms_norm_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 normalized LMS filter.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint8_t postShift
q31_t * recipTable
q31_t energy
q31_t x0

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::energy

+

+

+
saves previous frame energy. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::recipTable

+

+

+
points to the reciprocal initial value table. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::x0

+

+

+
saves previous input sample. 

+
+
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__matrix__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__f32.html
new file mode 100644
index 0000000000..012c13e8e8
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__f32.html
@@ -0,0 +1,202 @@
+
+
+
+
+arm_matrix_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_matrix_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point matrix structure.  
+ More...

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Description

+
Examples: 

+
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numCols

+

+

+
number of columns of the matrix. 

+
+
Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numRows

+

+

+
number of rows of the matrix. 

+
+
Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_matrix_instance_f32::pData

+

+

+
points to the data of the matrix. 

+
+
Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q15.html
new file mode 100644
index 0000000000..f1089cd275
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q15.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_matrix_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_matrix_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 matrix structure.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numCols

+

+

+
number of columns of the matrix. 

+
+
Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numRows

+

+

+
number of rows of the matrix. 

+
+
Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_matrix_instance_q15::pData

+

+

+
points to the data of the matrix. 

+
+
Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q31.html
new file mode 100644
index 0000000000..ec9cbbb4d7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q31.html
@@ -0,0 +1,198 @@
+
+
+
+
+arm_matrix_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_matrix_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 matrix structure.  
+

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numCols

+

+

+
number of columns of the matrix. 

+
+
Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numRows

+

+

+
number of rows of the matrix. 

+
+
Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_matrix_instance_q31::pData

+

+

+
points to the data of the matrix. 

+
+
Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__pid__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__pid__instance__f32.html
new file mode 100644
index 0000000000..84eeb4203b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__pid__instance__f32.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_pid_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_pid_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point PID Control.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
float32_t A0
float32_t A1
float32_t A2
float32_t state [3]
float32_t Kp
float32_t Ki
float32_t Kd

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Referenced by arm_pid_f32(), and arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Referenced by arm_pid_f32(), and arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Referenced by arm_pid_f32(), and arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kd

+

+

+
The derivative gain. 

+
+
Referenced by arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Ki

+

+

+
The integral gain. 

+
+
Referenced by arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kp

+

+

+
The proportional gain. 

+
+
Referenced by arm_pid_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::state[3]

+

+

+
The state array of length 3. 

+
+
Referenced by arm_pid_f32(), arm_pid_init_f32(), and arm_pid_reset_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__pid__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__pid__instance__q15.html
new file mode 100644
index 0000000000..4783cbad31
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__pid__instance__q15.html
@@ -0,0 +1,249 @@
+
+
+
+
+arm_pid_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_pid_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 PID Control.  
+

+
+
+
+
+
+
+
+
+

+Data Fields
q15_t A0
q31_t A1
q15_t state [3]
q15_t Kp
q15_t Ki
q15_t Kd

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Referenced by arm_pid_init_q15(), and arm_pid_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q15::A1

+

+

+
The derived gain A1 = -Kp - 2Kd | Kd. 

+
+
Referenced by arm_pid_init_q15(), and arm_pid_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kd

+

+

+
The derivative gain. 

+
+
Referenced by arm_pid_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Ki

+

+

+
The integral gain. 

+
+
Referenced by arm_pid_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kp

+

+

+
The proportional gain. 

+
+
Referenced by arm_pid_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::state[3]

+

+

+
The state array of length 3. 

+
+
Referenced by arm_pid_init_q15(), arm_pid_q15(), and arm_pid_reset_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__pid__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__pid__instance__q31.html
new file mode 100644
index 0000000000..46f345f307
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__pid__instance__q31.html
@@ -0,0 +1,266 @@
+
+
+
+
+arm_pid_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_pid_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 PID Control.  
+

+
+
+
+
+
+
+
+
+
+

+Data Fields
q31_t A0
q31_t A1
q31_t A2
q31_t state [3]
q31_t Kp
q31_t Ki
q31_t Kd

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Referenced by arm_pid_init_q31(), and arm_pid_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Referenced by arm_pid_init_q31(), and arm_pid_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Referenced by arm_pid_init_q31(), and arm_pid_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kd

+

+

+
The derivative gain. 

+
+
Referenced by arm_pid_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Ki

+

+

+
The integral gain. 

+
+
Referenced by arm_pid_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kp

+

+

+
The proportional gain. 

+
+
Referenced by arm_pid_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::state[3]

+

+

+
The state array of length 3. 

+
+
Referenced by arm_pid_init_q31(), arm_pid_q31(), and arm_pid_reset_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__rfft__instance__f32.html b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__f32.html
new file mode 100644
index 0000000000..bd2fc862e3
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__f32.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_rfft_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_rfft_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point RFFT/RIFFT function.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint16_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
float32_t * pTwiddleAReal
float32_t * pTwiddleBReal
arm_cfft_radix4_instance_f32 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_rfft_instance_f32::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::fftLenReal

+

+

+
length of the real FFT. 

+
+
Referenced by arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_rfft_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q15.html b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q15.html
new file mode 100644
index 0000000000..b3238655aa
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q15.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_rfft_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_rfft_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 RFFT/RIFFT function.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q15_t * pTwiddleAReal
q15_t * pTwiddleBReal
arm_cfft_radix4_instance_q15 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenReal

+

+

+
length of the real FFT. 

+
+
Referenced by arm_rfft_init_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_rfft_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q31.html b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q31.html
new file mode 100644
index 0000000000..afc228be99
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q31.html
@@ -0,0 +1,283 @@
+
+
+
+
+arm_rfft_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
arm_rfft_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 RFFT/RIFFT function.  
+

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q31_t * pTwiddleAReal
q31_t * pTwiddleBReal
arm_cfft_radix4_instance_q31 * pCfft

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenReal

+

+

+
length of the real FFT. 

+
+
Referenced by arm_rfft_init_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_rfft_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Referenced by arm_rfft_init_q31(), and arm_rfft_q31().

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/system___a_r_m_c_m0_8c.html b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m0_8c.html
new file mode 100644
index 0000000000..9a4d351e7b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m0_8c.html
@@ -0,0 +1,265 @@
+
+
+
+
+system_ARMCM0.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
system_ARMCM0.c File Reference
  

+

+

+
+
CMSIS Device System Source File for ARMCM0 Device Series.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define __HSI
#define __XTAL
#define __SYSTEM_CLOCK

+Variables
uint32_t SystemCoreClock

+Functions
void SystemCoreClockUpdate (void)
void SystemInit (void)
 Setup the microcontroller system. Initialize the System.  

+
Description

+
Version:
V1.07 

+
Date:
30. January 2012

+
Note:
Copyright (C) 2012 ARM Limited. All rights reserved.

+
ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

+
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define __HSI

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __SYSTEM_CLOCK

+

+

+
+
Referenced by SystemCoreClockUpdate(), and SystemInit().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __XTAL

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t SystemCoreClock

+

+

+
System Clock Frequency (Core Clock) 

+
+
Referenced by SystemCoreClockUpdate(), and SystemInit().

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemCoreClockUpdate (void )

+

+

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemInit (void )

+

+

+
Initialize the system

+
Parameters:

+  
+    
+  
none

+  

+

+
Returns:
none 

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/system___a_r_m_c_m3_8c.html b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m3_8c.html
new file mode 100644
index 0000000000..875f1f6e2b
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m3_8c.html
@@ -0,0 +1,263 @@
+
+
+
+
+system_ARMCM3.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
system_ARMCM3.c File Reference
  

+

+

+
+
CMSIS Device System Source File for ARMCM3 Device Series.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define __HSI
#define __XTAL
#define __SYSTEM_CLOCK

+Variables
uint32_t SystemCoreClock

+Functions
void SystemCoreClockUpdate (void)
void SystemInit (void)
 Setup the microcontroller system. Initialize the System.  

+
Description

+
Version:
V1.07 

+
Date:
30. January 2012

+
Note:
Copyright (C) 2012 ARM Limited. All rights reserved.

+
ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

+
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define __HSI

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __SYSTEM_CLOCK

+

+

+
+
Referenced by SystemCoreClockUpdate(), and SystemInit().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __XTAL

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t SystemCoreClock

+

+

+
System Clock Frequency (Core Clock) 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemCoreClockUpdate (void )

+

+

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemInit (void )

+

+

+
Initialize the system

+
Parameters:

+  
+    
+  
none

+  

+

+
Returns:
none 

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/system___a_r_m_c_m4_8c.html b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m4_8c.html
new file mode 100644
index 0000000000..7d930a0604
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/system___a_r_m_c_m4_8c.html
@@ -0,0 +1,263 @@
+
+
+
+
+system_ARMCM4.c File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-DSP
+    Verison 1.1.0
+   

+   
CMSIS DSP Software Library

+  

+

+
+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Variables |
+Functions  

+  

+
system_ARMCM4.c File Reference
  

+

+

+
+
CMSIS Device System Source File for ARMCM4 Device Series.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define __HSI
#define __XTAL
#define __SYSTEM_CLOCK

+Variables
uint32_t SystemCoreClock

+Functions
void SystemCoreClockUpdate (void)
void SystemInit (void)
 Setup the microcontroller system. Initialize the System.  

+
Description

+
Version:
V1.07 

+
Date:
30. January 2012

+
Note:
Copyright (C) 2012 ARM Limited. All rights reserved.

+
ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

+
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define __HSI

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __SYSTEM_CLOCK

+

+

+
+
Referenced by SystemCoreClockUpdate(), and SystemInit().

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define __XTAL

+

+

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t SystemCoreClock

+

+

+
System Clock Frequency (Core Clock) 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemCoreClockUpdate (void )

+

+

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void SystemInit (void )

+

+

+
Initialize the system

+
Parameters:

+  
+    
+  
none

+  

+

+
Returns:
none 

+
+
References __SYSTEM_CLOCK, and SystemCoreClock.

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/DSP/html/tab_a.png b/CMSIS/Documentation/DSP/html/tab_a.png
new file mode 100644
index 0000000000..2d99ef23fe
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/tab_a.png differ
diff --git a/CMSIS/Documentation/DSP/html/tab_b.png b/CMSIS/Documentation/DSP/html/tab_b.png
new file mode 100644
index 0000000000..b2c3d2be3c
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/tab_b.png differ
diff --git a/CMSIS/Documentation/DSP/html/tab_h.png b/CMSIS/Documentation/DSP/html/tab_h.png
new file mode 100644
index 0000000000..c11f48f19b
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/tab_h.png differ
diff --git a/CMSIS/Documentation/DSP/html/tab_s.png b/CMSIS/Documentation/DSP/html/tab_s.png
new file mode 100644
index 0000000000..978943ac80
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/tab_s.png differ
diff --git a/CMSIS/Documentation/DSP/html/tab_topnav.png b/CMSIS/Documentation/DSP/html/tab_topnav.png
new file mode 100644
index 0000000000..b257b7780f
Binary files /dev/null and b/CMSIS/Documentation/DSP/html/tab_topnav.png differ
diff --git a/CMSIS/Documentation/DSP/html/tabs.css b/CMSIS/Documentation/DSP/html/tabs.css
new file mode 100644
index 0000000000..ffbab509d7
--- /dev/null
+++ b/CMSIS/Documentation/DSP/html/tabs.css
@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
+    font-size: 12px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
+}
+
+.tabs1 .tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_topnav.png');
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png b/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000000..2056b7e747
Binary files /dev/null and b/CMSIS/Documentation/General/html/CMSIS_Logo_Final.png differ
diff --git a/CMSIS/Documentation/General/html/CMSIS_V3_small.png b/CMSIS/Documentation/General/html/CMSIS_V3_small.png
new file mode 100644
index 0000000000..a4dabb045f
Binary files /dev/null and b/CMSIS/Documentation/General/html/CMSIS_V3_small.png differ
diff --git a/CMSIS/Documentation/General/html/bc_s.png b/CMSIS/Documentation/General/html/bc_s.png
new file mode 100644
index 0000000000..51ba0066de
Binary files /dev/null and b/CMSIS/Documentation/General/html/bc_s.png differ
diff --git a/CMSIS/Documentation/General/html/closed.png b/CMSIS/Documentation/General/html/closed.png
new file mode 100644
index 0000000000..b7d4bd9fef
Binary files /dev/null and b/CMSIS/Documentation/General/html/closed.png differ
diff --git a/CMSIS/Documentation/General/html/cmsis.css b/CMSIS/Documentation/General/html/cmsis.css
new file mode 100644
index 0000000000..a5c4b8de50
--- /dev/null
+++ b/CMSIS/Documentation/General/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/CMSIS/Documentation/General/html/doxygen.png b/CMSIS/Documentation/General/html/doxygen.png
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--- /dev/null
+++ b/CMSIS/Documentation/General/html/index.html
@@ -0,0 +1,158 @@
+
+
+
+
+Introduction
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS
+    Version 3.01
+   

+   
Cortex Microcontroller Software Interface Standard

+  

+

+
+

+    
+

+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Introduction 
  

+

+

+
The Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.

+
The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.

+
The CMSIS components are:

+
    
+
  • CMSIS-CORE: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300. Included are also SIMD intrinsic functions for Cortex-M4 SIMD instructions.
    • 
+

+
    
+
  • CMSIS-DSP: DSP Library Collection with over 60 Functions for various data types: fix-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for Cortex-M0, Cortex-M3, and Cortex-M4. The Cortex-M4 implementation is optimized for the SIMD instruction set.
    • 
+

+
    
+
  • CMSIS-RTOS API: Common API for Real-Time operating systems. It provides a standardized programming interface that is portable to many RTOS and enables therefore software templates, middleware, libraries, and other components that can work acrosss supported the RTOS systems.
    • 
+

+
    
+
  • CMSIS-SVD: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.
    • 
+

+

+CMSIS_V3_small.png
+

+CMSIS Structure

+ 

+Motivation

+
CMSIS has been created to help the industry in standardization. It is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard. In detail the benefits of the CMSIS are:

+
    
+
  • Consistent software interfaces improve the software portability and re-usability. Generic software libraries can interface with device libraries from various silicon vendors.
    • 
+
  • Reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through an easy to use and standardized software interface.
    • 
+
  • Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR, and GNU).
    • 
+
  • Enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output and RTOS kernel awareness.
    • 
+

+

+Coding Rules

+
The CMSIS uses the following essential coding rules and conventions:

+
    
+
  • Compliant with ANSI C and C++.
    • 
+
  • Uses ANSI C standard data types defined in <stdint.h>.
    • 
+
  • Variables and parameters have a complete data type.
    • 
+
  • Expressions for #define constants are enclosed in parenthesis.
    • 
+
  • Conforms to MISRA 2004. MIRSA rule violations are documented.
    • 
+

+
In addition, the CMSIS recommends the following conventions for identifiers:

+
    
+
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • 
+
  • CamelCase names to identify function names and interrupt functions.
    • 
+
  • Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).
    • 
+

+
The CMSIS is documented within the source files with: 

+
    
+
  • Comments that use the C or C++ style. 
    • 
+
  • Doxygen compliant function comments that provide:
      
+
    • brief function overview.
      • 
+
    • detailed description of the function.
      • 
+
    • detailed parameter explanation.
      • 
+
    • detailed information about return values.
      • 
+
    
+
    • 
+

+
Doxygen comment example: 

+
+/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
+

+Licence

+
The CMSIS is provided free of charge by ARM and can be used for all Cortex-M based devices. View the LICENCE AGREEMENT for CMSIS in detail. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/General/html/jquery.js b/CMSIS/Documentation/General/html/jquery.js
new file mode 100644
index 0000000000..c052173a89
--- /dev/null
+++ b/CMSIS/Documentation/General/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function 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m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var 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false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/CMSIS/Documentation/General/html/nav_f.png b/CMSIS/Documentation/General/html/nav_f.png
new file mode 100644
index 0000000000..1b07a16207
Binary files /dev/null and b/CMSIS/Documentation/General/html/nav_f.png differ
diff --git a/CMSIS/Documentation/General/html/nav_h.png b/CMSIS/Documentation/General/html/nav_h.png
new file mode 100644
index 0000000000..01f5fa6a59
Binary files /dev/null and b/CMSIS/Documentation/General/html/nav_h.png differ
diff --git a/CMSIS/Documentation/General/html/navtree.css b/CMSIS/Documentation/General/html/navtree.css
new file mode 100644
index 0000000000..e46ffcd6e0
--- /dev/null
+++ b/CMSIS/Documentation/General/html/navtree.css
@@ -0,0 +1,123 @@
+#nav-tree .children_ul {
+  margin:0;
+  padding:4px;
+}
+
+#nav-tree ul {
+  list-style:none outside none;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree li {
+  white-space:nowrap;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .plus {
+  margin:0px;
+}
+
+#nav-tree .selected {
+  background-image: url('tab_a.png');
+  background-repeat:repeat-x;
+  color: #fff;
+  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
+
+#nav-tree img {
+  margin:0px;
+  padding:0px;
+  border:0px;
+  vertical-align: middle;
+}
+
+#nav-tree a {
+  text-decoration:none;
+  padding:0px;
+  margin:0px;
+  outline:none;
+}
+
+#nav-tree .label {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .label a {
+  padding:2px;
+}
+
+#nav-tree .selected a {
+  text-decoration:none;
+  padding:2px;
+  margin:0px;
+  color:#fff;
+}
+
+#nav-tree .children_ul {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree {
+  padding: 0px 0px;
+  background-color: #FAFAFF; 
+  font-size:14px;
+  overflow:auto;
+}
+
+#doc-content {
+  overflow:auto;
+  display:block;
+  padding:0px;
+  margin:0px;
+}
+
+#side-nav {
+  padding:0 6px 0 0;
+  margin: 0px;
+  display:block;
+  position: absolute;
+  left: 0px;
+  width: 300px;
+}
+
+.ui-resizable .ui-resizable-handle {
+  display:block;
+}
+
+.ui-resizable-e {
+  background:url("ftv2splitbar.png") repeat scroll right center transparent;
+  cursor:e-resize;
+  height:100%;
+  right:0;
+  top:0;
+  width:6px;
+}
+
+.ui-resizable-handle {
+  display:none;
+  font-size:0.1px;
+  position:absolute;
+  z-index:1;
+}
+
+#nav-tree-contents {
+  margin: 6px 0px 0px 0px;
+}
+
+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
+
diff --git a/CMSIS/Documentation/General/html/navtree.js b/CMSIS/Documentation/General/html/navtree.js
new file mode 100644
index 0000000000..5bcb5c7b7e
--- /dev/null
+++ b/CMSIS/Documentation/General/html/navtree.js
@@ -0,0 +1,252 @@
+var NAVTREE =
+[
+  [ "CMSIS", "index.html", [
+    [ "Introduction", "index.html", null ]
+  ] ]
+];
+
+function createIndent(o,domNode,node,level)
+{
+  if (node.parentNode && node.parentNode.parentNode)
+  {
+    createIndent(o,domNode,node.parentNode,level+1);
+  }
+  var imgNode = document.createElement("img");
+  if (level==0 && node.childrenData)
+  {
+    node.plus_img = imgNode;
+    node.expandToggle = document.createElement("a");
+    node.expandToggle.href = "javascript:void(0)";
+    node.expandToggle.onclick = function() 
+    {
+      if (node.expanded) 
+      {
+        $(node.getChildrenUL()).slideUp("fast");
+        if (node.isLast)
+        {
+          node.plus_img.src = node.relpath+"ftv2plastnode.png";
+        }
+        else
+        {
+          node.plus_img.src = node.relpath+"ftv2pnode.png";
+        }
+        node.expanded = false;
+      } 
+      else 
+      {
+        expandNode(o, node, false);
+      }
+    }
+    node.expandToggle.appendChild(imgNode);
+    domNode.appendChild(node.expandToggle);
+  }
+  else
+  {
+    domNode.appendChild(imgNode);
+  }
+  if (level==0)
+  {
+    if (node.isLast)
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2plastnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2lastnode.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+    else
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2pnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2node.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+  }
+  else
+  {
+    if (node.isLast)
+    {
+      imgNode.src = node.relpath+"ftv2blank.png";
+    }
+    else
+    {
+      imgNode.src = node.relpath+"ftv2vertline.png";
+    }
+  }
+  imgNode.border = "0";
+}
+
+function newNode(o, po, text, link, childrenData, lastNode)
+{
+  var node = new Object();
+  node.children = Array();
+  node.childrenData = childrenData;
+  node.depth = po.depth + 1;
+  node.relpath = po.relpath;
+  node.isLast = lastNode;
+
+  node.li = document.createElement("li");
+  po.getChildrenUL().appendChild(node.li);
+  node.parentNode = po;
+
+  node.itemDiv = document.createElement("div");
+  node.itemDiv.className = "item";
+
+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
+
+  createIndent(o,node.itemDiv,node,0);
+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
+
+  var a = document.createElement("a");
+  node.labelSpan.appendChild(a);
+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
+    a.href = node.relpath+link;
+  } 
+  else 
+  {
+    if (childrenData != null) 
+    {
+      a.className = "nolink";
+      a.href = "javascript:void(0)";
+      a.onclick = node.expandToggle.onclick;
+      node.expanded = false;
+    }
+  }
+
+  node.childrenUL = null;
+  node.getChildrenUL = function() 
+  {
+    if (!node.childrenUL) 
+    {
+      node.childrenUL = document.createElement("ul");
+      node.childrenUL.className = "children_ul";
+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
+    }
+    return node.childrenUL;
+  };
+
+  return node;
+}
+
+function showRoot()
+{
+  var headerHeight = $("#top").height();
+  var footerHeight = $("#nav-path").height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
+
+function expandNode(o, node, imm)
+{
+  if (node.childrenData && !node.expanded) 
+  {
+    if (!node.childrenVisited) 
+    {
+      getNode(o, node);
+    }
+    if (imm)
+    {
+      $(node.getChildrenUL()).show();
+    } 
+    else 
+    {
+      $(node.getChildrenUL()).slideDown("fast",showRoot);
+    }
+    if (node.isLast)
+    {
+      node.plus_img.src = node.relpath+"ftv2mlastnode.png";
+    }
+    else
+    {
+      node.plus_img.src = node.relpath+"ftv2mnode.png";
+    }
+    node.expanded = true;
+  }
+}
+
+function getNode(o, po)
+{
+  po.childrenVisited = true;
+  var l = po.childrenData.length-1;
+  for (var i in po.childrenData) 
+  {
+    var nodeData = po.childrenData[i];
+    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
+        i==l);
+  }
+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
+      }
+    }
+  }
+  return null;
+}
+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
+  o.node.depth = 0;
+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
+
+  o.breadcrumbs = findNavTreePage(toroot, NAVTREE);
+  if (o.breadcrumbs == null)
+  {
+    o.breadcrumbs = findNavTreePage("index.html",NAVTREE);
+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
+    var p = o.node;
+    for (var i in o.breadcrumbs) 
+    {
+      var j = o.breadcrumbs[i];
+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/CMSIS/Documentation/General/html/open.png b/CMSIS/Documentation/General/html/open.png
new file mode 100644
index 0000000000..7b35d2c2c3
Binary files /dev/null and b/CMSIS/Documentation/General/html/open.png differ
diff --git a/CMSIS/Documentation/General/html/resize.js b/CMSIS/Documentation/General/html/resize.js
new file mode 100644
index 0000000000..04fa95ce97
--- /dev/null
+++ b/CMSIS/Documentation/General/html/resize.js
@@ -0,0 +1,81 @@
+var cookie_namespace = 'doxygen'; 
+var sidenav,navtree,content,header;
+
+function readCookie(cookie) 
+{
+  var myCookie = cookie_namespace+"_"+cookie+"=";
+  if (document.cookie) 
+  {
+    var index = document.cookie.indexOf(myCookie);
+    if (index != -1) 
+    {
+      var valStart = index + myCookie.length;
+      var valEnd = document.cookie.indexOf(";", valStart);
+      if (valEnd == -1) 
+      {
+        valEnd = document.cookie.length;
+      }
+      var val = document.cookie.substring(valStart, valEnd);
+      return val;
+    }
+  }
+  return 0;
+}
+
+function writeCookie(cookie, val, expiration) 
+{
+  if (val==undefined) return;
+  if (expiration == null) 
+  {
+    var date = new Date();
+    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week
+    expiration = date.toGMTString();
+  }
+  document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/";
+}
+ 
+function resizeWidth() 
+{
+  var windowWidth = $(window).width() + "px";
+  var sidenavWidth = $(sidenav).width();
+  content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar
+  writeCookie('width',sidenavWidth, null);
+}
+
+function restoreWidth(navWidth)
+{
+  var windowWidth = $(window).width() + "px";
+  content.css({marginLeft:parseInt(navWidth)+6+"px"});
+  sidenav.css({width:navWidth + "px"});
+}
+
+function resizeHeight() 
+{
+  var headerHeight = header.height();
+  var footerHeight = footer.height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  content.css({height:windowHeight + "px"});
+  navtree.css({height:windowHeight + "px"});
+  sidenav.css({height:windowHeight + "px",top: headerHeight+"px"});
+}
+
+function initResizable()
+{
+  header  = $("#top");
+  sidenav = $("#side-nav");
+  content = $("#doc-content");
+  navtree = $("#nav-tree");
+  footer  = $("#nav-path");
+  $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } });
+  $(window).resize(function() { resizeHeight(); });
+  var width = readCookie('width');
+  if (width) { restoreWidth(width); } else { resizeWidth(); }
+  resizeHeight();
+  var url = location.href;
+  var i=url.indexOf("#");
+  if (i>=0) window.location.hash=url.substr(i);
+  var _preventDefault = function(evt) { evt.preventDefault(); };
+  $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault);
+}
+
+
diff --git a/CMSIS/Documentation/General/html/tab_a.png b/CMSIS/Documentation/General/html/tab_a.png
new file mode 100644
index 0000000000..2d99ef23fe
Binary files /dev/null and b/CMSIS/Documentation/General/html/tab_a.png differ
diff --git a/CMSIS/Documentation/General/html/tab_b.png b/CMSIS/Documentation/General/html/tab_b.png
new file mode 100644
index 0000000000..b2c3d2be3c
Binary files /dev/null and b/CMSIS/Documentation/General/html/tab_b.png differ
diff --git a/CMSIS/Documentation/General/html/tab_h.png b/CMSIS/Documentation/General/html/tab_h.png
new file mode 100644
index 0000000000..c11f48f19b
Binary files /dev/null and b/CMSIS/Documentation/General/html/tab_h.png differ
diff --git a/CMSIS/Documentation/General/html/tab_s.png b/CMSIS/Documentation/General/html/tab_s.png
new file mode 100644
index 0000000000..978943ac80
Binary files /dev/null and b/CMSIS/Documentation/General/html/tab_s.png differ
diff --git a/CMSIS/Documentation/General/html/tab_topnav.png b/CMSIS/Documentation/General/html/tab_topnav.png
new file mode 100644
index 0000000000..b257b7780f
Binary files /dev/null and b/CMSIS/Documentation/General/html/tab_topnav.png differ
diff --git a/CMSIS/Documentation/General/html/tabs.css b/CMSIS/Documentation/General/html/tabs.css
new file mode 100644
index 0000000000..ffbab509d7
--- /dev/null
+++ b/CMSIS/Documentation/General/html/tabs.css
@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
+    font-size: 12px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
+}
+
+.tabs1 .tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_topnav.png');
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/CMSIS/Documentation/RTOS/html/API_Structure.png b/CMSIS/Documentation/RTOS/html/API_Structure.png
new file mode 100644
index 0000000000..832753b447
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/API_Structure.png differ
diff --git a/CMSIS/Documentation/RTOS/html/CMSIS_Logo_Final.png b/CMSIS/Documentation/RTOS/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000000..2056b7e747
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/CMSIS_Logo_Final.png differ
diff --git a/CMSIS/Documentation/RTOS/html/CMSIS_RTOS_Files.png b/CMSIS/Documentation/RTOS/html/CMSIS_RTOS_Files.png
new file mode 100644
index 0000000000..136bc6d5a4
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/CMSIS_RTOS_Files.png differ
diff --git a/CMSIS/Documentation/RTOS/html/MailQueue.png b/CMSIS/Documentation/RTOS/html/MailQueue.png
new file mode 100644
index 0000000000..9e75ff4e13
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/MailQueue.png differ
diff --git a/CMSIS/Documentation/RTOS/html/MessageQueue.png b/CMSIS/Documentation/RTOS/html/MessageQueue.png
new file mode 100644
index 0000000000..712eeacb51
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/MessageQueue.png differ
diff --git a/CMSIS/Documentation/RTOS/html/Mutex.png b/CMSIS/Documentation/RTOS/html/Mutex.png
new file mode 100644
index 0000000000..7eec93b6fa
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/Mutex.png differ
diff --git a/CMSIS/Documentation/RTOS/html/Semaphore.png b/CMSIS/Documentation/RTOS/html/Semaphore.png
new file mode 100644
index 0000000000..f1939c01b9
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/Semaphore.png differ
diff --git a/CMSIS/Documentation/RTOS/html/ThreadStatus.png b/CMSIS/Documentation/RTOS/html/ThreadStatus.png
new file mode 100644
index 0000000000..45a05645ba
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/ThreadStatus.png differ
diff --git a/CMSIS/Documentation/RTOS/html/Timer.png b/CMSIS/Documentation/RTOS/html/Timer.png
new file mode 100644
index 0000000000..63c666be5b
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/Timer.png differ
diff --git a/CMSIS/Documentation/RTOS/html/_function_overview.html b/CMSIS/Documentation/RTOS/html/_function_overview.html
new file mode 100644
index 0000000000..d4b08b453a
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/_function_overview.html
@@ -0,0 +1,217 @@
+
+
+
+
+Function Overview
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Function Overview 
  

+

+

+
The following list provides a brief overview of all CMSIS-RTOS functions. Functions marked with $ are optional. A CMSIS RTOS implementation may not provided functions, but this is clearly indicated with osFeatureXXXX defines.

+
+
+
+
+
+
+
+
+
+
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/_using_o_s.html b/CMSIS/Documentation/RTOS/html/_using_o_s.html
new file mode 100644
index 0000000000..89bffb72a7
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/_using_o_s.html
@@ -0,0 +1,164 @@
+
+
+
+
+Using a CMSIS RTOS Implementation
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Using a CMSIS RTOS Implementation 
  

+

+

+
A CMSIS RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based application the RTOS library (and typically a configuration file) needs to be added. The available functionality of the RTOS library is defined in the file cmsis_os.h that is specific for each RTOS implementation.

+

+CMSIS_RTOS_Files.png
+

+CMSIS-RTOS File Structure

+
 Depending on the CMSIS-RTOS implementation, execution may start with the main function as the first thread. This has the benefit that an application programmer may use other middleware libraries that create threads internally, but the remaining part of the user application just uses the main thread. Therefore, the usage of the RTOS can be invisible to the application programmer, but libraries can use CMSIS-RTOS features.

+
Once the files are added to a project, the user can start using the CMSIS-RTOS functions. A code example is provided below:

+
#include "cmsis_os.h"                           // CMSIS RTOS header file
+
+void job1 (void const *argument)  {             // thread function 'job1'
+  while (1)  {
+     :                                          // execute some code
+    osDelay (10);                               // delay execution for 10 milli seconds
+  }
+}
+// define job1 as thread function
+osThreadDef(job1, osPriorityAboveNormal, 1, 0); // define job1 as thread function
+
+
+void job2 (void const *argument)  {             // thread function 'job2'
+  osThreadCreate(osThread(job1),NULL);          // create job1 thread
+  while (1)   {
+    :                                           // execute some code
+  }
+}
+
+osThreadDef(job2, osPriorityNormal, 1, 0);      // define job2 as thread function
+
+
+int main (void) {                               // program execution starts here
+    :                                           // setup and initialize
+  osKernelStart (osThread(job2), NULL);         // start kernel with job2 execution
+  while (1);                                    // program will never reach this point
+}
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/annotated.html b/CMSIS/Documentation/RTOS/html/annotated.html
new file mode 100644
index 0000000000..2c03c28163
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/annotated.html
@@ -0,0 +1,148 @@
+
+
+
+
+Data Structures
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Data Structures
  

+

+

+
Here are the data structures with brief descriptions:

+  
+  
+  
+  
+  
+  
+  
+  
+  
+
os_mailQ
osEventEvent structure contains detailed information about an event 
osMailQDef_tDefinition structure for mail queue 
osMessageQDef_tDefinition structure for message queue 
osMutexDef_tMutex Definition structure contains setup information for a mutex 
osPoolDef_tDefinition structure for memory block allocation 
osSemaphoreDef_tSemaphore Definition structure contains setup information for a semaphore 
osThreadDef_tThread Definition structure contains startup information of a thread 
osTimerDef_tTimer Definition structure contains timer parameters 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/bc_s.png b/CMSIS/Documentation/RTOS/html/bc_s.png
new file mode 100644
index 0000000000..51ba0066de
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/bc_s.png differ
diff --git a/CMSIS/Documentation/RTOS/html/classes.html b/CMSIS/Documentation/RTOS/html/classes.html
new file mode 100644
index 0000000000..f0636b3e2d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/classes.html
@@ -0,0 +1,146 @@
+
+
+
+
+Data Structure Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Data Structure Index
  

+

+

+
O

+
+
+
+
+
+
  O  

+		osEvent   osMutexDef_t   osThreadDef_t   
osMailQDef_t   osPoolDef_t   osTimerDef_t   
os_mailQ   osMessageQDef_t   osSemaphoreDef_t   

+
O

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/closed.png b/CMSIS/Documentation/RTOS/html/closed.png
new file mode 100644
index 0000000000..b7d4bd9fef
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/closed.png differ
diff --git a/CMSIS/Documentation/RTOS/html/cmsis.css b/CMSIS/Documentation/RTOS/html/cmsis.css
new file mode 100644
index 0000000000..a5c4b8de50
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html b/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html
new file mode 100644
index 0000000000..57998d6e1d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html
@@ -0,0 +1,636 @@
+
+
+
+
+cmsis_os.h File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Structures |
+Defines |
+Typedefs |
+Enumerations |
+Functions  

+  

+
cmsis_os.h File Reference
  

+

+

+
+
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+Data Structures
struct  osThreadDef_t
 Thread Definition structure contains startup information of a thread.  More...
struct  osTimerDef_t
 Timer Definition structure contains timer parameters.  More...
struct  osMutexDef_t
 Mutex Definition structure contains setup information for a mutex.  More...
struct  osSemaphoreDef_t
 Semaphore Definition structure contains setup information for a semaphore.  More...
struct  osPoolDef_t
 Definition structure for memory block allocation.  More...
struct  osMessageQDef_t
 Definition structure for message queue.  More...
struct  osMailQDef_t
 Definition structure for mail queue.  More...
struct  osEvent
 Event structure contains detailed information about an event.  More...

+Defines
#define osCMSIS   0x00003
 API version (main [31:16] .sub [15:0])  
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0])  
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string.  
#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available  
#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available.  
#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available.  
#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available.  
#define osFeature_Signals   8
 maximum number of Signal Flags available per thread  
#define osFeature_Semaphore   30
 maximum count for SemaphoreInit function  
#define osFeature_Wait   1
 osWait function: 1=available, 0=not available  
#define osWaitForever   0xFFFFFFFF
 Timeout value.  
#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements.  
#define osThread(name)   &os_thread_def_##name
 Access a Thread defintion.  
#define osTimerDef(name, function)
 Define a Timer object.  
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition.  
#define osMutexDef(name)   osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex.  
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex defintion.  
#define osSemaphoreDef(name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object.  
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition.  
#define osPoolDef(name, no, type)
 Define a Memory Pool.  
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition.  
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition.  
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition.  
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition.  
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition.  

+Typedefs
typedef void(* os_pthread )(void const *argument)
 Entry point of a thread.  
typedef void(* os_ptimer )(void const *argument)
 Entry point of a timer call back function.  
typedef struct os_thread_cb * osThreadId
 Thread ID identifies the thread (pointer to a thread control block).  
typedef struct os_timer_cb * osTimerId
 Timer ID identifies the timer (pointer to a timer control block).  
typedef struct os_mutex_cb * osMutexId
 Mutex ID identifies the mutex (pointer to a mutex control block).  
typedef struct os_semaphore_cb * osSemaphoreId
 Semaphore ID identifies the semaphore (pointer to a semaphore control block).  
typedef struct os_pool_cb * osPoolId
 Pool ID identifies the memory pool (pointer to a memory pool control block).  
typedef struct os_messageQ_cb * osMessageQId
 Message ID identifies the message queue (pointer to a message queue control block).  
typedef struct os_mailQ_cb * osMailQId
 Mail ID identifies the mail queue (pointer to a mail queue control block).  

+Enumerations
enum  osPriority { 

+  osPriorityIdle =  -3, 
+

+  osPriorityLow =  -2, 
+

+  osPriorityBelowNormal =  -1, 
+

+  osPriorityNormal =  0, 
+

+  osPriorityAboveNormal =  +1, 
+

+  osPriorityHigh =  +2, 
+

+  osPriorityRealtime =  +3, 
+

+  osPriorityError =  0x84
+

+ }
 Priority used for thread control.  More...
enum  osStatus { 

+  osOK =  0, 
+

+  osEventSignal =  0x08, 
+

+  osEventMessage =  0x10, 
+

+  osEventMail =  0x20, 
+

+  osEventTimeout =  0x40, 
+

+  osErrorParameter =  0x80, 
+

+  osErrorResource =  0x81, 
+

+  osErrorTimeoutResource =  0xC1, 
+

+  osErrorISR =  0x82, 
+

+  osErrorISRRecursive =  0x83, 
+

+  osErrorPriority =  0x84, 
+

+  osErrorNoMemory =  0x85, 
+

+  osErrorValue =  0x86, 
+

+  osErrorOS =  0xFF, 
+

+  os_status_reserved =  0x7FFFFFFF
+

+ }
 Status code values returned by CMSIS-RTOS functions.  More...
enum  os_timer_type { 

+  osTimerOnce =  0, 
+

+  osTimerPeriodic =  1
+

+ }
 Timer type value for the timer definition.  More...

+Functions
osStatus osKernelStart (osThreadDef_t *thread_def, void *argument)
 Start the RTOS Kernel with executing the specified thread.  
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started.  
osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY.  
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread.  
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads.  
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY.  
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread.  
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread.  
osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay)  
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout.  
osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer.  
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer.  
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer.  
int32_t osSignalSet (osThreadId thread_id, int32_t signal)
 Set the specified Signal Flags of an active thread.  
int32_t osSignalClear (osThreadId thread_id, int32_t signal)
 Clear the specified Signal Flags of an active thread.  
int32_t osSignalGet (osThreadId thread_id)
 Get Signal Flags status of an active thread.  
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread.  
osMutexId osMutexCreate (osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object.  
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available.  
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait.  
osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources.  
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available.  
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token.  
osPoolId osPoolCreate (osPoolDef_t *pool_def)
 Create and Initialize a memory pool.  
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool.  
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero.  
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool.  
osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue.  
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue.  
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue.  
osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue.  
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail.  
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero.  
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue.  
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue.  
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail.  

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osWaitForever   0xFFFFFFFF

+

+

+
Note:
MUST REMAIN UNCHANGED: osWaitForever shall be consistent in every CMSIS-RTOS. wait forever timeout value 

+
+

+

+
Typedef Documentation

+
+

+

+      
+        
+          
+        
+      
typedef void(* os_pthread)(void const *argument)

+

+

+
Note:
MUST REMAIN UNCHANGED: os_pthread shall be consistent in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef void(* os_ptimer)(void const *argument)

+

+

+
Note:
MUST REMAIN UNCHANGED: os_ptimer shall be consistent in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_mailQ_cb* osMailQId

+

+

+
Note:
CAN BE CHANGED: os_mailQ_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_messageQ_cb* osMessageQId

+

+

+
Note:
CAN BE CHANGED: os_messageQ_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_mutex_cb* osMutexId

+

+

+
Note:
CAN BE CHANGED: os_mutex_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_pool_cb* osPoolId

+

+

+
Note:
CAN BE CHANGED: os_pool_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_semaphore_cb* osSemaphoreId

+

+

+
Note:
CAN BE CHANGED: os_semaphore_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_thread_cb* osThreadId

+

+

+
Note:
CAN BE CHANGED: os_thread_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
typedef struct os_timer_cb* osTimerId

+

+

+
Note:
CAN BE CHANGED: os_timer_cb is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Enumeration Type Documentation

+
+

+

+      
+        
+          
+        
+      
enum os_timer_type

+

+

+
Note:
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. 

+
Enumerator: 

+
+
+
osTimerOnce 
+
one-shot timer 

+
osTimerPeriodic 
+
repeating timer 

+

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
enum osPriority

+

+

+
Note:
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS. 

+
Enumerator: 

+
+
+
+
+
+
+
+
+
osPriorityIdle 
+
priority: idle (lowest) 

+
osPriorityLow 
+
priority: low 

+
osPriorityBelowNormal 
+
priority: below normal 

+
osPriorityNormal 
+
priority: normal (default) 

+
osPriorityAboveNormal 
+
priority: above normal 

+
osPriorityHigh 
+
priority: high 

+
osPriorityRealtime 
+
priority: realtime (highest) 

+
osPriorityError 
+
system cannot determine priority or thread has illegal priority 

+

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
enum osStatus

+

+

+
Note:
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS. 

+
Enumerator: 

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
osOK 
+
function completed; no event occurred. 

+
osEventSignal 
+
function completed; signal event occurred. 

+
osEventMessage 
+
function completed; message event occurred. 

+
osEventMail 
+
function completed; mail event occurred. 

+
osEventTimeout 
+
function completed; timeout occurred. 

+
osErrorParameter 
+
parameter error: a mandatory parameter was missing or specified an incorrect object. 

+
osErrorResource 
+
resource not available: a specified resource was not available. 

+
osErrorTimeoutResource 
+
resource not available within given time: a specified resource was not available within the timeout period. 

+
osErrorISR 
+
not allowed in ISR context: the function cannot be called from interrupt service routines. 

+
osErrorISRRecursive 
+
function called multiple times from ISR with same object. 

+
osErrorPriority 
+
system cannot determine priority or thread has illegal priority. 

+
osErrorNoMemory 
+
system is out of memory: it was impossible to allocate or reserve memory for the operation. 

+
osErrorValue 
+
value of a parameter is out of range. 

+
osErrorOS 
+
unspecified RTOS error: run-time error but no other error message fits. 

+
os_status_reserved 
+
prevent from enum down-size compiler optimization. 

+

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html b/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html
new file mode 100644
index 0000000000..7dceb42ca8
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html
@@ -0,0 +1,193 @@
+
+
+
+
+cmsis_os.txt File Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Enumerations  

+  

+
cmsis_os.txt File Reference
  

+

+

+
+
+
+
+
+

+Enumerations
enum  osPriority { 

+  osPriorityIdle =  -3, 
+

+  osPriorityLow =  -2, 
+

+  osPriorityBelowNormal =  -1, 
+

+  osPriorityNormal =  0, 
+

+  osPriorityAboveNormal =  +1, 
+

+  osPriorityHigh =  +2, 
+

+  osPriorityRealtime =  +3, 
+

+  osPriorityError =  0x84
+

+ }
enum  os_timer_type { 

+  osTimerOnce =  0, 
+

+  osTimerPeriodic =  1
+

+ }
enum  osStatus { 

+  osOK =  0, 
+

+  osEventSignal =  0x08, 
+

+  osEventMessage =  0x10, 
+

+  osEventMail =  0x20, 
+

+  osEventTimeout =  0x40, 
+

+  osErrorParameter =  0x80, 
+

+  osErrorResource =  0x81, 
+

+  osErrorTimeoutResource =  0xC1, 
+

+  osErrorISR =  0x82, 
+

+  osErrorISRRecursive =  0x83, 
+

+  osErrorPriority =  0x84, 
+

+  osErrorNoMemory =  0x85, 
+

+  osErrorValue =  0x86, 
+

+  osErrorOS =  0xFF, 
+

+  os_status_reserved =  0x7FFFFFFF
+

+ }

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/cmsis_os_h.html b/CMSIS/Documentation/RTOS/html/cmsis_os_h.html
new file mode 100644
index 0000000000..05bb6982d4
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/cmsis_os_h.html
@@ -0,0 +1,169 @@
+
+
+
+
+Header File Template: cmsis_os.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Header File Template: cmsis_os.h 
  

+

+

+
The file cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). Each RTOS that is compliant with CMSIS-RTOS shall provide a specific cmsis_os.h header file that represents its implementation.

+
The file cmsis_os.h contains:

+
    
+
  • CMSIS-RTOS API function definitions
    • 
+
  • struct definitions for parameters and return types
    • 
+
  • status and priority values used by CMSIS-RTOS API functions
    • 
+
  • macros for defining threads and other kernel objects
    • 
+

+
Name conventions and header file modifications

+
All definitions are prefixed with os to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed os_ are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. osThread.

+
Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel.

+
Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.

+
Function calls from interrupt service routines

+
The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):

+
+
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.

+
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code osErrorISRRecursive.

+
Define and reference object definitions

+
With #define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file that is used troughtout a project as shown below:

+
Header File 

+
#include <cmsis_os.h>                                         // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);                      
+
This header file defines all objects when included in a C/C++ source file. When #define osObjectsExternal is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project.

+
Example 

+
#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+
#define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/doxygen.png b/CMSIS/Documentation/RTOS/html/doxygen.png
new file mode 100644
index 0000000000..635ed52fce
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diff --git a/CMSIS/Documentation/RTOS/html/files.html b/CMSIS/Documentation/RTOS/html/files.html
new file mode 100644
index 0000000000..87714d440d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/files.html
@@ -0,0 +1,133 @@
+
+
+
+
+Files
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Files
  

+

+

+
Here is a list of all files with brief descriptions:

+  
+
cmsis_os.h

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/ftv2blank.png b/CMSIS/Documentation/RTOS/html/ftv2blank.png
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index 0000000000..3b7a29cb81
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diff --git a/CMSIS/Documentation/RTOS/html/ftv2doc.png b/CMSIS/Documentation/RTOS/html/ftv2doc.png
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diff --git a/CMSIS/Documentation/RTOS/html/ftv2vertline.png b/CMSIS/Documentation/RTOS/html/ftv2vertline.png
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diff --git a/CMSIS/Documentation/RTOS/html/functions.html b/CMSIS/Documentation/RTOS/html/functions.html
new file mode 100644
index 0000000000..4a29e5ac78
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/functions.html
@@ -0,0 +1,201 @@
+
+
+
+
+Data Fields
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all struct and union fields with links to the structures/unions they belong to:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/functions_vars.html b/CMSIS/Documentation/RTOS/html/functions_vars.html
new file mode 100644
index 0000000000..fbbec81932
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/functions_vars.html
@@ -0,0 +1,201 @@
+
+
+
+
+Data Fields - Variables
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals.html b/CMSIS/Documentation/RTOS/html/globals.html
new file mode 100644
index 0000000000..56b52f9df4
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals.html
@@ -0,0 +1,442 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals_defs.html b/CMSIS/Documentation/RTOS/html/globals_defs.html
new file mode 100644
index 0000000000..f332c01afd
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals_defs.html
@@ -0,0 +1,213 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals_enum.html b/CMSIS/Documentation/RTOS/html/globals_enum.html
new file mode 100644
index 0000000000..86612caf13
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals_enum.html
@@ -0,0 +1,150 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals_eval.html b/CMSIS/Documentation/RTOS/html/globals_eval.html
new file mode 100644
index 0000000000..6ea2f575c0
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals_eval.html
@@ -0,0 +1,213 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals_func.html b/CMSIS/Documentation/RTOS/html/globals_func.html
new file mode 100644
index 0000000000..4da7758641
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals_func.html
@@ -0,0 +1,253 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+
+
- o -

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/globals_type.html b/CMSIS/Documentation/RTOS/html/globals_type.html
new file mode 100644
index 0000000000..ad6be333b9
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/globals_type.html
@@ -0,0 +1,165 @@
+
+
+
+
+Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+ 
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html
new file mode 100644
index 0000000000..79f2a640a0
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS-RTOS API
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
CMSIS-RTOS API
  

+

+

+
+
This section describes the CMSIS-RTOS API.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Kernel Information and Control
 
Provide version/system information and start the RTOS Kernel. 

+
 Thread Management
 
Define, create, and control thread functions. 

+
 Generic Wait Functions
 
Wait for a time period or unspecified events. 

+
 Timer Management
 
Create and control timer and timer callback functions. 

+
 Signal Management
 
Control or wait for signal flags. 

+
 Mutex Management
 
Synchronize thread execution with a Mutex. 

+
 Semaphore Management
 
Control access to shared resources. 

+
 Memory Pool Management
 
Define and manage fixed-size memory pools. 

+
 Message Queue Management
 
Control, send, receive, or wait for messages. 

+
 Mail Queue Management
 
Control, send, receive, or wait for mail. 

+
 Generic Data Types and Definitions
 
Data Type Definitions used by the CMSIS-RTOS API functions. 

+
 Status and Error Codes
 
Status and Error Codes returned by CMSIS-RTOS API functions. 

+

+
Description

+
The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel. It provides the following functional modules: 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html
new file mode 100644
index 0000000000..81dd20d2fc
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html
@@ -0,0 +1,300 @@
+
+
+
+
+Generic Data Types and Definitions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Structures  

+  

+
Generic Data Types and Definitions
  

+
CMSIS-RTOS API

+

+
+
Data Type Definitions used by the CMSIS-RTOS API functions.  
+More...

+
+
+
+
+
+

+Data Structures
struct  osEvent
 Event structure contains detailed information about an event.  More...
struct  os_mailQ

+
Description

+
The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions. 

+
Data Structure Documentation

+
+

+

+      
+        
+          
+        
+      
struct osEvent

+

+

+
Note:
MUST REMAIN UNCHANGED: os_event shall be consistent in every CMSIS-RTOS. However the struct may be extended at the end.

+
The osEvent structure describes the events returned by CMSIS-RTOS functions. 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Data Fields
osStatus status
 status code: event or error information  
union {
   uint32_t   v
 message as 32-bit value  
   void *   p
 message or mail as void pointer  
   int32_t   signals
 signal flags  
} value
 event value  
union {
   osMailQId   mail_id
 mail id obtained by osMailCreate  
   osMessageQId   message_id
 message id obtained by osMessageCreate  
} def
 event definition  

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
union { ... }   def

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
osMailQId mail_id

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
osMessageQId message_id

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
void* p

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t signals

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
osStatus status

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t v

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
union { ... }   value

+

+

+
+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
struct os_mailQ

+

+

+
The osEvent structure describes the events returned by CMSIS-RTOS functions. 

+

+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html
new file mode 100644
index 0000000000..cd2f1e994d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html
@@ -0,0 +1,284 @@
+
+
+
+
+Kernel Information and Control
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Kernel Information and Control
  

+
CMSIS-RTOS API

+

+
+
Provide version/system information and start the RTOS Kernel.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available  
#define osCMSIS   0x00003
 API version (main [31:16] .sub [15:0])  
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0])  
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string.  

+Functions
osStatus osKernelStart (osThreadDef_t *thread_def, void *argument)
 Start the RTOS Kernel with executing the specified thread.  
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started.  

+
Description

+
The Kernel Information and Control function group allow to:

+
    
+
  • obtain information about the system and the underlaying kernel.
    • 
+
  • obtain version information about the CMSIS RTOS API.
    • 
+
  • the start of the RTOS kernel.
    • 
+
  • checking the execution status of the RTOS kernel.
    • 
+

+
The function main is a special thread function that may be started at system initialization. In this case it has the initial priority osPriorityNormal. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osCMSIS   0x00003

+

+

+
Version information of the CMSIS RTOS API whereby major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

+
Note:
MUST REMAIN UNCHANGED: osCMSIS identifies the CMSIS-RTOS API version 

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define osCMSIS_KERNEL   0x10000

+

+

+
Identifies the underlaying RTOS kernel and version number. The actual name of that define depends on the RTOS Kernel used in the implementation. For example, osCMSIS_FreeRTOS identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

+
Note:
CAN BE CHANGED: osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define osFeature_MainThread   1

+

+

+
A CMSIS-RTOS implementation may support to start thread execution with the function 'main'. When the value osFeature_MainThread is 1 the RTOS offers to start with 'main'. The RTOS kernel is in this case already started. When the value osFeature_MainThread is 0 the RTOS requries explicit start with osKernelStart.

+
Note:
MUST REMAIN UNCHANGED: osFeature_xxx shall be consistent in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define osKernelSystemId   "KERNEL V1.00"

+

+

+
Defines a string that identifies the underlaying RTOS Kernel and provides version information. The lenght of that string is limited to 21 bytes. A valid indenification string is for example, "FreeRTOS V1.00".

+
Note:
MUST REMAIN UNCHANGED: osKernelSystemId shall be consistent in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t osKernelRunning (void )

+

+

+
Note:
MUST REMAIN UNCHANGED: osKernelRunning shall be consistent in every CMSIS-RTOS. 

+
Returns:
0 RTOS is not started, 1 RTOS is started.

+
Identifies if the RTOS kernel is started. For systems with the option to start the 'main' function as a thread this allows to identify that the RTOS kernel is already running. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void osKernelStart (osThreadDef_t * thread_def, 
void * argument 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]thread_defthread definition referenced with osThread. 
[in]argumentpointer that is passed to the thread function as start argument. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osKernelStart shall be consistent in every CMSIS-RTOS.

+
Start the RTOS Kernel and begin execution of the thread function specified by thread_def. The argument is passed to the thread function.

+
When the CMSIS-RTOS starts thread execution with 'main', the function osKernelStart terminates this 'main; thread and starts execution with the specified thread function. This ensures that the code is portable regardless weather the function 'main' is started as thread or executed without control of the RTOS kernel.

+
Note:
The thread ID of the started thread can be obtained with the function osThreadGetId. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html
new file mode 100644
index 0000000000..a6390e5fcf
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html
@@ -0,0 +1,499 @@
+
+
+
+
+Mail Queue Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Mail Queue Management
  

+
CMSIS-RTOS API

+

+
+
Control, send, receive, or wait for mail.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available.  
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition.  
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition.  

+Functions
osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue.  
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail.  
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero.  
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue.  
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue.  
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail.  

+
Description

+
The Mail Queue Management function group allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine.

+

+MailQueue.png
+

+CMSIS-RTOS Mail Queue

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_MailQ   1

+

+

+
A CMSIS-RTOS implementation may support mail queues. When the value osFeature_MailQ is 1 mail queues are supported. When the value osFeature_MailQ is 0 no mail queues are supported. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osMailQ( name)   &os_mailQ_def_##name

+

+

+
Access to the mail queue definition for the function osMailCreate.

+
Parameters:

+  
+    
+  
namename of the queue 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMailQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
#define osMailQDef( name, 
 queue_sz, 
 type 
)

+

+

+
Define the attributes of a mail queue that can by the function osMailCreate using osMailQ.

+
Parameters:

+  
+    
+    
+    
+  
namename of the queue 
queue_szmaximum number of messages in queue 
typedata type of a single message element 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMailQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void * osMailAlloc (osMailQId queue_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 

+  

+

+
Returns:
pointer to memory block that can be filled with mail or NULL in case error. 

+
Note:
MUST REMAIN UNCHANGED: osMailAlloc shall be consistent in every CMSIS-RTOS.

+
Allocate a memory block from the mail queue that is filled with the mail information. When no memory block slot is available, the tread is put into the state WAITING for the time specified with millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a mail queue slot becomes available.

+
A NULL pointer is returned when no memory slot can be obtained or queue specifies an illegal parameter.

+
Note:
The parameter millisec must be 0 for using this function in an ISR. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void * osMailCAlloc (osMailQId queue_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 

+  

+

+
Returns:
pointer to memory block that can shall filled with mail or NULL in case error. 

+
Note:
MUST REMAIN UNCHANGED: osMailCAlloc shall be consistent in every CMSIS-RTOS.

+
Allocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared. When no memory block is available, the tread is put into the state WAITING for the time specified with millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a mail queue slot becomes available.

+
A NULL pointer is returned when no memory block can be obtained or queue specifies an illegal parameter.

+
Note:
The parameter millisec must be 0 for using this function in an ISR. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osMailQId osMailCreate (osMailQDef_t * queue_def, 
osThreadId thread_id 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_defreference to the mail queue definition obtain with osMailQ 
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL. 

+  

+

+
Returns:
mail queue ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osMailCreate shall be consistent in every CMSIS-RTOS.

+
Initialize and create a mail queue. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osMailFree (osMailQId queue_id, 
void * mail 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]mailpointer to the memory block that was obtained with osMailGet. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osMailFree shall be consistent in every CMSIS-RTOS.

+
Free the memory block specified by mail and return it to the mail queue.

+
Status and Error Codes

+

+
    
+
  • osOK: the mail block is released.
    • 
+
  • osErrorValue: mail block does not belong to the mail queue pool.
    • 
+
  • osErrorParameter: the value to the parameter queue is incorrect. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osEvent osMailGet (osMailQId queue_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 

+  

+

+
Returns:
event that contains mail information or error code. 

+
Note:
MUST REMAIN UNCHANGED: osMailGet shall be consistent in every CMSIS-RTOS.

+
Suspend the execution of the current RUNNING thread until a mail arrives. When a mail is already in the queue, the function returns instantly with the mail information. When millisec is 0, the function returns instantly with status osOK. Otherwise the thread is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a mail arrives.

+
Note:
The parameter millisec must be 0 for using this function in an ISR.

+
Status and Error Codes

+

+
    
+
  • osOK: no mail is available in the queue and no timeout was specified
    • 
+
  • osEventTimeout: no mail has arrived during the given timeout period.
    • 
+
  • osEventMail: mail received, value.p contains the pointer to mail content.
    • 
+
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osMailPut (osMailQId queue_id, 
void * mail 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]mailmemory block previously allocated with osMailAlloc or osMailCAlloc. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osMailPut shall be consistent in every CMSIS-RTOS.

+
Put the memory block specified with mail into the mail queue specified by queue.

+
Status and Error Codes

+

+
    
+
  • osOK: the message is put into the queue.
    • 
+
  • osErrorValue: mail was previously not allocated as memory slot.
    • 
+
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html
new file mode 100644
index 0000000000..7e383fa62d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html
@@ -0,0 +1,380 @@
+
+
+
+
+Message Queue Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Message Queue Management
  

+
CMSIS-RTOS API

+

+
+
Control, send, receive, or wait for messages.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available.  
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition.  
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition.  

+Functions
osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue.  
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue.  
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue.  

+
Description

+
Message Queue Management functions allow to control, send, receive, or wait for messages. A message can be an integer or pointer value that is send to a thread or interrupt service routine.

+

+MessageQueue.png
+

+CMSIS-RTOS Message Queue

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_MessageQ   1

+

+

+
A CMSIS-RTOS implementation may support message queues. When the value osFeature_MailQ is 1 message queues are supported. When the value osFeature_MailQ is 0 no message queues are supported. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osMessageQ( name)   &os_messageQ_def_##name

+

+

+
Access to the message queue definition for the function osMessageCreate.

+
Parameters:

+  
+    
+  
namename of the queue 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMessageQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
#define osMessageQDef( name, 
 queue_sz, 
 type 
)

+

+

+
Define the attributes of a message queue created by the function osMessageCreate using osMessageQ.

+
Parameters:

+  
+    
+    
+    
+  
namename of the queue. 
queue_szmaximum number of messages in the queue. 
typedata type of a single message element (for debugger). 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMessageQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osMessageQId osMessageCreate (osMessageQDef_t * queue_def, 
osThreadId thread_id 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_defqueue definition referenced with osMessageQ. 
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL. 

+  

+

+
Returns:
message queue ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osMessageCreate shall be consistent in every CMSIS-RTOS.

+
Create and initialize a message queue. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osEvent osMessageGet (osMessageQId queue_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]queue_idmessage queue ID obtained with osMessageCreate. 
[in]millisectimeout value or 0 in case of no time-out. 

+  

+

+
Returns:
event information that includes status code. 

+
Note:
MUST REMAIN UNCHANGED: osMessageGet shall be consistent in every CMSIS-RTOS.

+
Suspend the execution of the current RUNNING thread until a message arrives. When a message is already in the queue, the function returns instantly with the message information. When millisec is 0, the function returns instantly with status osOK. Otherwise the thread is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a message arrives.

+
Note:
The parameter millisec must be 0 for using this function in an ISR.

+
Status and Error Codes

+

+
    
+
  • osOK: no message is available in the queue and no timeout was specified.
    • 
+
  • osEventTimeout: no message has arrived during the given timeout period.
    • 
+
  • osEventMessage: message received, value.p contains the pointer to message.
    • 
+
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osMessagePut (osMessageQId queue_id, 
uint32_t info, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]queue_idmessage queue ID obtained with osMessageCreate. 
[in]infomessage information. 
[in]millisectimeout value or 0 in case of no time-out. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osMessagePut shall be consistent in every CMSIS-RTOS.

+
Put the message info in a message queue specified by queue_id. When the message queue is full, the system retry for a specified time with millisec. In this case, the tread is put into the state WAITING. When millisec is set to osWaitForever, the function will wait for an infinite time until a message queue slot becomes available.

+
Note:
The parameter millisec must be 0 for using this function in an ISR.

+
Status and Error Codes

+

+
    
+
  • osOK: the message is put into the queue.
    • 
+
  • osErrorResource: no memory in the queue was available.
    • 
+
  • osErrorTimeoutResource: no memory in the queue was available during the given time limit.
    • 
+
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html
new file mode 100644
index 0000000000..5474e134d8
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html
@@ -0,0 +1,317 @@
+
+
+
+
+Mutex Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Mutex Management
  

+
CMSIS-RTOS API

+

+
+
Synchronize thread execution with a Mutex.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osMutexDef(name)   osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex.  
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex defintion.  

+Functions
osMutexId osMutexCreate (osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object.  
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available.  
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait.  

+
Description

+
The Mutex Management function group is used to synchronize the execution of threads. This is for example used to protect access to a shared resource, for example a shared memory image.

+
Note:
Mutex Management functions cannot be called from interrupt service routines (ISR).

+

+Mutex.png
+

+CMSIS-RTOS Mutex

+
Define Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osMutex( name)   &os_mutex_def_##name

+

+

+
Access to mutex object for the functions osMutexCreate.

+
Parameters:

+  
+    
+  
namename of the mutex object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMutex shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osMutexDef( name)   osMutexDef_t os_mutex_def_##name = { 0 }

+

+

+
Define a mutex object that is referenced by osMutex.

+
Parameters:

+  
+    
+  
namename of the mutex object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osMutexDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osMutexId osMutexCreate (osMutexDef_t * mutex_def)

+

+

+
Parameters:

+  
+    
+  
[in]mutex_defmutex definition referenced with osMutex. 

+  

+

+
Returns:
mutex ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osMutexCreate shall be consistent in every CMSIS-RTOS.

+
Create and initialize a Mutex object. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osMutexRelease (osMutexId mutex_id)

+

+

+
Parameters:

+  
+    
+  
[in]mutex_idmutex ID obtained by osMutexCreate. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osMutexRelease shall be consistent in every CMSIS-RTOS.

+
Release a Mutex that was obtained with osMutexWait. Other threads that currently wait for the same mutex will be now put into the state READY.

+
Status and Error Codes

+

+
    
+
  • osOK: the mutex has been correctly released.
    • 
+
  • osErrorResource: the mutex was not obtained before.
    • 
+
  • osErrorParameter: the parameter mutex_id is incorrect.
    • 
+
  • osErrorISR: osMutexRelease cannot be called from interrupt service routines. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osMutexWait (osMutexId mutex_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]mutex_idmutex ID obtained by osMutexCreate. 
[in]millisectimeout value or 0 in case of no time-out. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osMutexWait shall be consistent in every CMSIS-RTOS.

+
Wait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object.

+
Status and Error Codes

+

+
    
+
  • osOK: the mutex has been obtain.
    • 
+
  • osErrorTimeoutResource: the mutex could not be obtained in the given time.
    • 
+
  • osErrorResource: the mutex could not be obtained when no timeout was specified.
    • 
+
  • osErrorParameter: the parameter mutex_id is incorrect.
    • 
+
  • osErrorISR: osMutexWait cannot be called from interrupt service routines. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html
new file mode 100644
index 0000000000..b42bd16bcc
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html
@@ -0,0 +1,364 @@
+
+
+
+
+Memory Pool Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Memory Pool Management
  

+
CMSIS-RTOS API

+

+
+
Define and manage fixed-size memory pools.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available.  
#define osPoolDef(name, no, type)
 Define a Memory Pool.  
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition.  

+Functions
osPoolId osPoolCreate (osPoolDef_t *pool_def)
 Create and Initialize a memory pool.  
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool.  
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero.  
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool.  

+
Description

+
The Memory Pool Management function group is used to define and manage fixed-sized memory pools. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_Pool   1

+

+

+
A CMSIS-RTOS implementation may support fixed-size memory pools. When the value osFeature_Pool is 1 memory pools are supported. When the value osFeature_Pool is 0 no memory pools are supported. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osPool( name)   &os_pool_def_##name

+

+

+
Access a memory pool for the functions osPoolCreate.

+
Parameters:

+  
+    
+  
namename of the memory pool 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osPool shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
#define osPoolDef( name, 
 no, 
 type 
)

+

+

+
Define a memory pool that is referenced by osPool.

+
Parameters:

+  
+    
+    
+    
+  
namename of the memory pool. 
nomaximum number of objects (elements) in the memory pool. 
typedata type of a single object (element). 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osPoolDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void * osPoolAlloc (osPoolId pool_id)

+

+

+
Parameters:

+  
+    
+  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 

+  

+

+
Returns:
address of the allocated memory block or NULL in case of no memory available. 

+
Note:
MUST REMAIN UNCHANGED: osPoolAlloc shall be consistent in every CMSIS-RTOS.

+
Allocate a memory block from the memory pool. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void * osPoolCAlloc (osPoolId pool_id)

+

+

+
Parameters:

+  
+    
+  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 

+  

+

+
Returns:
address of the allocated memory block or NULL in case of no memory available. 

+
Note:
MUST REMAIN UNCHANGED: osPoolCAlloc shall be consistent in every CMSIS-RTOS.

+
Allocate a memory block from the memory pool. The block is initialized to zero. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osPoolId osPoolCreate (osPoolDef_t * pool_def)

+

+

+
Parameters:

+  
+    
+  
[in]pool_defmemory pool definition referenced with osPool. 

+  

+

+
Returns:
memory pool ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osPoolCreate shall be consistent in every CMSIS-RTOS.

+
Create and initialize a memory pool. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osPoolFree (osPoolId pool_id, 
void * block 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 
[in]blockaddress of the allocated memory block that is returned to the memory pool. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osPoolFree shall be consistent in every CMSIS-RTOS.

+
Return a memory block to a memory pool.

+
Status and Error Codes

+

+
    
+
  • osOK: the memory block is released.
    • 
+
  • osErrorValue: block does not belong to the memory pool.
    • 
+
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html
new file mode 100644
index 0000000000..4a46700c5a
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html
@@ -0,0 +1,335 @@
+
+
+
+
+Semaphore Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Semaphore Management
  

+
CMSIS-RTOS API

+

+
+
Control access to shared resources.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_Semaphore   30
 maximum count for SemaphoreInit function  
#define osSemaphoreDef(name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object.  
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition.  

+Functions
osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources.  
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available.  
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token.  

+
Description

+
The Semaphore Management function group is used to manage and protect access to shared resources. For example, with a Semaphore the access to a group of identical peripherals can be managed. The number of available resources is specified as parameter of the osSemaphoreCreate function.

+
Each time a Semaphore token is obtained with osSemaphoreWait the semaphore count is decremented. When the semaphore count is 0, no Semaphore token can be obtained. Semaphores are released with osSemaphoreRelease; this function increments the semaphore count.

+

+Semaphore.png
+

+CMSIS-RTOS Semaphore

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_Semaphore   30

+

+

+
A CMSIS-RTOS implementation may support semaphores. The value osFeature_Semaphore indicates the maximum index count for a semaphore. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osSemaphore( name)   &os_semaphore_def_##name

+

+

+
Access to semaphore object for the functions osSemaphoreCreate.

+
Parameters:

+  
+    
+  
namename of the semaphore object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osSemaphore shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osSemaphoreDef( name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }

+

+

+
Define a semaphore object that is referenced by osSemaphore.

+
Parameters:

+  
+    
+  
namename of the semaphore object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osSemaphoreDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t * semaphore_def, 
int32_t count 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]semaphore_defsemaphore definition referenced with osSemaphore. 
[in]countnumber of available resources. 

+  

+

+
Returns:
semaphore ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osSemaphoreCreate shall be consistent in every CMSIS-RTOS.

+
Create and initialize a Semaphore object that is used to manage access to shared resources. The parameter count specifies the number of available resources. The count value 1 creates a binary semaphore. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)

+

+

+
Parameters:

+  
+    
+  
[in]semaphore_idsemaphore object referenced with osSemaphore. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osSemaphoreRelease shall be consistent in every CMSIS-RTOS.

+
Release a Semaphore token. This increments the count of avaiable semaphore tokens.

+
Note:
osSemaphoreRelease can be called also from interrupt service routines.

+
Status and Error Codes

+

+
    
+
  • osOK: the semaphore has been released.
    • 
+
  • osErrorResource: all tokens have already been released.
    • 
+
  • osErrorParameter: the parameter semaphore_id is incorrect. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]semaphore_idsemaphore object referenced with osSemaphore. 
[in]millisectimeout value or 0 in case of no time-out. 

+  

+

+
Returns:
number of available tokens, or -1 in case of incorrect parameters. 

+
Note:
MUST REMAIN UNCHANGED: osSemaphoreWait shall be consistent in every CMSIS-RTOS.

+
Wait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter millisec. When millisec is set to osWaitForever, the function will wait for an infinite time until a Semaphore token becomes available. The return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available. 

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html
new file mode 100644
index 0000000000..7c519ba92c
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html
@@ -0,0 +1,317 @@
+
+
+
+
+Signal Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Signal Management
  

+
CMSIS-RTOS API

+

+
+
Control or wait for signal flags.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_Signals   8
 maximum number of Signal Flags available per thread  

+Functions
int32_t osSignalSet (osThreadId thread_id, int32_t signal)
 Set the specified Signal Flags of an active thread.  
int32_t osSignalClear (osThreadId thread_id, int32_t signal)
 Clear the specified Signal Flags of an active thread.  
int32_t osSignalGet (osThreadId thread_id)
 Get Signal Flags status of an active thread.  
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread.  

+
Description

+
The Signal Management function group allows to control or wait signal flags. Each thread has assigned signal flags. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_Signals   8

+

+

+
The CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available per thread. The maximum value is 31 signal flags per thread. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
int32_t osSignalClear (osThreadId thread_id, 
int32_t signals 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]signalsspecifies the signal flags of the thread that shall be cleared. 

+  

+

+
Returns:
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. 

+
Note:
MUST REMAIN UNCHANGED: osSignalClear shall be consistent in every CMSIS-RTOS.

+
Clear the signal flags of an active thread. This function may be used also within interrupt service routines. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t osSignalGet (osThreadId thread_id)

+

+

+
Parameters:

+  
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 

+  

+

+
Returns:
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. 

+
Note:
MUST REMAIN UNCHANGED: osSignalGet shall be consistent in every CMSIS-RTOS.

+
Return the event flags of an active thread. This function may be used also within interrupt service routines. Signal flags that are returned are automatically cleared. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
int32_t osSignalSet (osThreadId thread_id, 
int32_t signals 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]signalsspecifies the signal flags of the thread that should be set. 

+  

+

+
Returns:
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. 

+
Note:
MUST REMAIN UNCHANGED: osSignalSet shall be consistent in every CMSIS-RTOS.

+
Set the signal flags of an active thread. This function may be used also within interrupt service routines. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osEvent osSignalWait (int32_t signals, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]signalswait until all specified signal flags set or 0 for any single signal flag. 
[in]millisectimeout value or 0 in case of no time-out. 

+  

+

+
Returns:
event flag information or error code. 

+
Note:
MUST REMAIN UNCHANGED: osSignalWait shall be consistent in every CMSIS-RTOS.

+
Suspend the execution of the current RUNNING thread until all specified signal flags with the parameter signals are set. When this signal flags are already set, the function returns instantly. Otherwise the thread is put into the state WAITING. Signal flags that are reported as event are automatically cleared.

+
When millisec is set to osWaitForever the function will wait for an inifinite time until a message queue slot becomes available.

+
Status and Error Codes

+

+
    
+
  • osOK: no signal received when the timeout value millisec was zero.
    • 
+
  • osEventTimeout: signal not occurred within timeout
    • 
+
  • osEventSignal: signal occurred, value.signals contains the signal flags; these signal flags are cleared.
    • 
+
  • osErrorValue: the value signals is outside of the permitted range.
    • 
+
  • osErrorISR: osSignalWait cannot be called from interrupt service routines. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html
new file mode 100644
index 0000000000..5923c836a6
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html
@@ -0,0 +1,238 @@
+
+
+
+
+Status and Error Codes
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Enumerations  

+  

+
Status and Error Codes
  

+
CMSIS-RTOS API

+

+
+
Status and Error Codes returned by CMSIS-RTOS API functions.  
+More...

+
+
+
+

+Enumerations
enum  osStatus { 

+  osOK =  0, 
+

+  osEventSignal =  0x08, 
+

+  osEventMessage =  0x10, 
+

+  osEventMail =  0x20, 
+

+  osEventTimeout =  0x40, 
+

+  osErrorParameter =  0x80, 
+

+  osErrorResource =  0x81, 
+

+  osErrorTimeoutResource =  0xC1, 
+

+  osErrorISR =  0x82, 
+

+  osErrorISRRecursive =  0x83, 
+

+  osErrorPriority =  0x84, 
+

+  osErrorNoMemory =  0x85, 
+

+  osErrorValue =  0x86, 
+

+  osErrorOS =  0xFF, 
+

+  os_status_reserved =  0x7FFFFFFF
+

+ }

+
Description

+
The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return. 

+
Enumeration Type Documentation

+
+

+

+      
+        
+          
+        
+      
enum osStatus

+

+

+
Note:
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.

+
The osStatus enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions. 

+
Enumerator: 

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
osOK 
+
function completed; no event occurred. 

+
osEventSignal 
+
function completed; signal event occurred. 

+
osEventMessage 
+
function completed; message event occurred. 

+
osEventMail 
+
function completed; mail event occurred. 

+
osEventTimeout 
+
function completed; timeout occurred. 

+
osErrorParameter 
+
parameter error: a mandatory parameter was missing or specified an incorrect object. 

+
osErrorResource 
+
resource not available: a specified resource was not available. 

+
osErrorTimeoutResource 
+
resource not available within given time: a specified resource was not available within the timeout period. 

+
osErrorISR 
+
not allowed in ISR context: the function cannot be called from interrupt service routines. 

+
osErrorISRRecursive 
+
function called multiple times from ISR with same object. 

+
osErrorPriority 
+
system cannot determine priority or thread has illegal priority. 

+
osErrorNoMemory 
+
system is out of memory: it was impossible to allocate or reserve memory for the operation. 

+
osErrorValue 
+
value of a parameter is out of range. 

+
osErrorOS 
+
unspecified RTOS error: run-time error but no other error message fits. 

+
os_status_reserved 
+
prevent from enum down-size compiler optimization. 

+

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html
new file mode 100644
index 0000000000..205640f26d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html
@@ -0,0 +1,511 @@
+
+
+
+
+Thread Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Enumerations |
+Functions  

+  

+
Thread Management
  

+
CMSIS-RTOS API

+

+
+
Define, create, and control thread functions.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements.  
#define osThread(name)   &os_thread_def_##name
 Access a Thread defintion.  

+Enumerations
enum  osPriority { 

+  osPriorityIdle =  -3, 
+

+  osPriorityLow =  -2, 
+

+  osPriorityBelowNormal =  -1, 
+

+  osPriorityNormal =  0, 
+

+  osPriorityAboveNormal =  +1, 
+

+  osPriorityHigh =  +2, 
+

+  osPriorityRealtime =  +3, 
+

+  osPriorityError =  0x84
+

+ }

+Functions
osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY.  
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread.  
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads.  
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread.  
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread.  
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY.  

+
Description

+
The Thread Management function group allow defining, creating, and controlling thread functions in the system. The function main is a special thread function that is started at system initialization and has the initial priority osPriorityNormal.

+
Threads can be in the following states:

+
    
+
  • RUNNING: The thread that is currently running is in the RUNNING state. Only one thread at a time can be in this state.
    • 
+
  • READY: Threads which are ready to run are in the READY state. Once the RUNNING thread has terminated or is WAITING the next READY thread with the highest priority becomes the RUNNING thread.
    • 
+
  • WAITING: Threads that are waiting for an event to occur are in the WAITING state.
    • 
+
  • INACTIVE: Threads that are not created or terminated are in the INACTIVE state. These threads typically consume no system resources.
    • 
+

+

+ThreadStatus.png
+

+Thread State and State Transitions

+
 The CMSIS-RTOS assumes that threads are scheduled as shown in the figure Thread State and State Transitions. The thread states change as described below:

+
    
+
  • A thread is created using the function osThreadCreate. This puts the thread into the READY or RUNNING state (depending on the thread priority).
    • 
+
  • CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the RUNNING thread provided it does not wait for any event. The initial priority of a thread is defined with the osThreadDef but may be changed during execution using the function osThreadSetPriority.
    • 
+
  • The RUNNING thread transfers into the WAITING state when it is waiting for an event.
    • 
+
  • Active threads can be terminated any time using the function osThreadTerminate. Threads can terminate also by just returning from the thread function. Threads that are terminated are in the INACTIVE state and typically do not consume any dynamic memory resources. 
    • 
+

+
Define Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osThread( name)   &os_thread_def_##name

+

+

+
Access to the thread definition for the function osThreadCreate.

+
Parameters:

+  
+    
+  
namename of the thread definition object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osThread shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
#define osThreadDef( name, 
 priority, 
 instances, 
 stacksz 
)

+

+

+
Define the attributes of a thread functions that can be created by the function osThreadCreate using osThread.

+
Parameters:

+  
+    
+    
+    
+    
+  
namename of the thread function. 
priorityinitial priority of the thread function. 
instancesnumber of possible thread instances. 
stackszstack size (in bytes) requirements for the thread function. 

+  

+

+
Note:
CAN BE CHANGED: The parameters to osThreadDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Enumeration Type Documentation

+
+

+

+      
+        
+          
+        
+      
enum osPriority

+

+

+
Note:
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.

+
The osPriority value specifies the priority for a thread. The default thread priority should be osPriorityNormal. If a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately to execute the new task.

+
To prevent from a priority inversion, a CMSIS-RTOS complained OS may optionally implement a priority inheritance method. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread with a lower priority. 

+
Enumerator: 

+
+
+
+
+
+
+
+
+
osPriorityIdle 
+
priority: idle (lowest) 

+
osPriorityLow 
+
priority: low 

+
osPriorityBelowNormal 
+
priority: below normal 

+
osPriorityNormal 
+
priority: normal (default) 

+
osPriorityAboveNormal 
+
priority: above normal 

+
osPriorityHigh 
+
priority: high 

+
osPriorityRealtime 
+
priority: realtime (highest) 

+
osPriorityError 
+
system cannot determine priority or thread has illegal priority 

+

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osThreadId osThreadCreate (osThreadDef_t * thread_def, 
void * argument 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]thread_defthread definition referenced with osThread. 
[in]argumentpointer that is passed to the thread function as start argument. 

+  

+

+
Returns:
thread ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osThreadCreate shall be consistent in every CMSIS-RTOS.

+
Start a thread function by adding it to the Active Threads list and set it to state READY. The thread function receives the argument pointer as function argument when the function is started. When the priority of the created thread function is higher than the current RUNNING thread, the created thread function starts instantly and becomes the new RUNNING thread. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osThreadId osThreadGetId (void )

+

+

+
Returns:
thread ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osThreadGetId shall be consistent in every CMSIS-RTOS.

+
Get the thread ID of the current running thread. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osPriority osThreadGetPriority (osThreadId thread_id)

+

+

+
Parameters:

+  
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 

+  

+

+
Returns:
current priority value of the thread function. 

+
Note:
MUST REMAIN UNCHANGED: osThreadGetPriority shall be consistent in every CMSIS-RTOS.

+
Get the priority of an active thread. In case of a failure the value osPriorityError is returned. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osThreadSetPriority (osThreadId thread_id, 
osPriority priority 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]prioritynew priority value for the thread function. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osThreadSetPriority shall be consistent in every CMSIS-RTOS.

+
Change the priority of an active thread.

+
Status and Error Codes

+

+
    
+
  • osOK: the prioirty of the specified thread has been successfully changed.
    • 
+
  • osErrorParameter: thread_id is incorrect.
    • 
+
  • osErrorValue: incorrect priority value.
    • 
+
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • 
+
  • osErrorISR: osThreadSetPriority cannot be called from interrupt service routines. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osThreadTerminate (osThreadId thread_id)

+

+

+
Parameters:

+  
+    
+  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osThreadTerminate shall be consistent in every CMSIS-RTOS.

+
Remove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.

+
Note:
In case that osThreadTerminate terminates the currently running task, the function never returns and other threads that are in the READY state are started.

+
Status and Error Codes

+

+
    
+
  • osOK: the specified thread has been successfully terminated.
    • 
+
  • osErrorParameter: thread_id is incorrect.
    • 
+
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • 
+
  • osErrorISR: osThreadTerminate cannot be called from interrupt service routines. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osThreadYield (void )

+

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osThreadYield shall be consistent in every CMSIS-RTOS.

+
Pass control to next thread that is in state READY. If there is no other thread in the state READY, the current thread continues execution and no thread switching occurs.

+
Status and Error Codes

+

+
    
+
  • osOK: the function has been correctly executed.
    • 
+
  • osErrorISR: osThreadYield cannot be called from interrupt service routines. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html
new file mode 100644
index 0000000000..f2fee9b78d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html
@@ -0,0 +1,377 @@
+
+
+
+
+Timer Management
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Enumerations |
+Functions  

+  

+
Timer Management
  

+
CMSIS-RTOS API

+

+
+
Create and control timer and timer callback functions.  
+More...

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define osTimerDef(name, function)
 Define a Timer object.  
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition.  

+Enumerations
enum  os_timer_type { 

+  osTimerOnce =  0, 
+

+  osTimerPeriodic =  1
+

+ }

+Functions
osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer.  
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer.  
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer.  

+
Description

+
The Timer Management function group allow creating and controlling of timers and callback functions in the system. A callback function is called when a time period expires whereby both one-shot and periodic timers are possible. A timer can be started, restarted, or stopped.

+
Timers are handled in the thread osTimerThread. Callback functions run under control of this thread and may use other CMSIS-RTOS API calls.

+
The figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the callback function.

+

+Timer.png
+

+Behavior of a Periodic Timer

+
Define Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
#define osTimer( name)   &os_timer_def_##name

+

+

+
Access to the timer definition for the function osTimerCreate.

+
Parameters:

+  
+    
+  
namename of the timer object. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osTimer shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
#define osTimerDef( name, 
 function 
)

+

+

+
Define the attributes of a timer.

+
Parameters:

+  
+    
+    
+  
namename of the timer object. 
functionname of the timer call back function. 

+  

+

+
Note:
CAN BE CHANGED: The parameter to osTimerDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 

+
+

+

+
Enumeration Type Documentation

+
+

+

+      
+        
+          
+        
+      
enum os_timer_type

+

+

+
Note:
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. The os_timer_type specifies the a repeating (periodic) or one-shot timer for the function osTimerCreate. 

+
Enumerator: 

+
+
+
osTimerOnce 
+
one-shot timer 

+
osTimerPeriodic 
+
repeating timer 

+

+

+

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osTimerId osTimerCreate (osTimerDef_t * timer_def, 
os_timer_type type, 
void * argument 
)

+

+

+
Parameters:

+  
+    
+    
+    
+  
[in]timer_deftimer object referenced with osTimer. 
[in]typeosTimerOnce for one-shot or osTimerPeriodic for periodic behavior. 
[in]argumentargument to the timer call back function. 

+  

+

+
Returns:
timer ID for reference by other functions or NULL in case of error. 

+
Note:
MUST REMAIN UNCHANGED: osTimerCreate shall be consistent in every CMSIS-RTOS.

+
Create a one-shot or periodic timer and associate it with a callback function argument. The timer is in stopped until it is started with osTimerStart. 

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
osStatus osTimerStart (osTimerId timer_id, 
uint32_t millisec 
)

+

+

+
Parameters:

+  
+    
+    
+  
[in]timer_idtimer ID obtained by osTimerCreate. 
[in]millisectime delay value of the timer. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osTimerStart shall be consistent in every CMSIS-RTOS.

+
Start or restart the timer.

+
Status and Error Codes

+

+
    
+
  • osOK: the specified timer has been started or restarted.
    • 
+
  • osErrorParameter: timer_id is incorrect. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osTimerStop (osTimerId timer_id)

+

+

+
Parameters:

+  
+    
+  
[in]timer_idtimer ID obtained by osTimerCreate. 

+  

+

+
Returns:
status code that indicates the execution status of the function. 

+
Note:
MUST REMAIN UNCHANGED: osTimerStop shall be consistent in every CMSIS-RTOS.

+
Stop the timer.

+
Status and Error Codes

+

+
    
+
  • osOK: the specified timer has been stopped.
    • 
+
  • osErrorParameter: timer_id is incorrect.
    • 
+
  • osErrorResource: the timer is not started. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html
new file mode 100644
index 0000000000..100990ebbb
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html
@@ -0,0 +1,233 @@
+
+
+
+
+Generic Wait Functions
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Defines |
+Functions  

+  

+
Generic Wait Functions
  

+
CMSIS-RTOS API

+

+
+
Wait for a time period or unspecified events.  
+More...

+
+
+
+
+
+
+
+
+
+

+Defines
#define osFeature_Wait   1
 osWait function: 1=available, 0=not available  

+Functions
osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay)  
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout.  

+
Description

+
The Generic Wait function group provides means for a time delay and allow to wait for unspecified events. 

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define osFeature_Wait   1

+

+

+
A CMSIS-RTOS implementation may support the generic wait function osWait. When the value osFeature_Wait is 1 a generic wait function osWait is available. When the value osFeature_Wait is 0 no generic wait function osWait is available. 

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osDelay (uint32_t millisec)

+

+

+
Parameters:

+  
+    
+  
[in]millisectime delay value 

+  

+

+
Returns:
status code that indicates the execution status of the function.

+
Wait for a specified time period in millisec.

+
Status and Error Codes

+

+
    
+
  • osEventTimeout: the time delay is executed.
    • 
+
  • osErrorISR: osDelay cannot be called from interrupt service routines. 
    • 
+

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
osStatus osWait (uint32_t millisec)

+

+

+
Parameters:

+  
+    
+  
[in]millisectimeout value or 0 in case of no time-out 

+  

+

+
Returns:
event that contains signal, message, or mail information or error code. 

+
Note:
MUST REMAIN UNCHANGED: osWait shall be consistent in every CMSIS-RTOS.

+
Wait for any event of the type Signal, Message, Mail for a specified time period in millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a event occurs.

+
Note:
this function is optionally and may not be provided by all CMSIS-RTOS implementations.

+
Status and Error Codes

+

+
    
+
  • osEventSignal: a signal event occurred and is returned.
    • 
+
  • osEventMessage: a message event occurred and is returned.
    • 
+
  • osEventMail: a mail event occurred and is returned.
    • 
+
  • osEventTimeout: the time delay is executed.
    • 
+
  • osErrorISR: osDelay cannot be called from interrupt service routines. 
    • 
+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/index.html b/CMSIS/Documentation/RTOS/html/index.html
new file mode 100644
index 0000000000..8225cd5e15
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/index.html
@@ -0,0 +1,199 @@
+
+
+
+
+Overview
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Overview 
  

+

+

+
The CMSIS-RTOS API is a generic RTOS interface for Cortex-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.

+
    
+
  • CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
    • 
+
  • The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.
    • 
+
  • Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.
    • 
+
  • Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.
    • 
+

+
Note:
The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.

+

+API_Structure.png
+

+CMSIS-RTOS API Structure

+
 A typical CMSIS-RTOS API implementation interfaces to an existing Real-Time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:

+
    
+
  • Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.
    • 
+

+
+
    
+
  • Interrupt Service Routines (ISR) can call many CMSIS-RTOS functions. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.
    • 
+

+
    
+
  • Three different thread event types support communication between multiple threads and/or ISR:
      
+
    • Signals: are flags that may be used to signal specific conditions to a thread. Signals can be modified in an ISR or set from other threads.
      • 
+
    • Message: is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.
      • 
+
    • Mail: is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.
      • 
+
    
+
    • 
+

+
+
    
+
  • CPU time can be schedule with the following functionalities:
      
+
    • A timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.
      • 
+
    • The osDelay function puts a thread into the state WAITING for a specified period of time.
      • 
+
    • The generic osWait function waits for events that are assigned to a thread.
      • 
+
    • The osThreadYield provides co-operative thread switching and passes execution to another thread of the same priority.
      • 
+
    
+
    • 
+

+
The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).

+
In some RTOS implementations threads may execute on different processors and Mail and Message queues can therefore reside in shard memory resources.

+
The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for example:

+
    
+
  • Generic Wait function; i.e. with support of time intervals.
    • 
+
  • Support of the Cortex-M Memory Protection Unit (MPU).
    • 
+
  • Zero-copy mail queue.
    • 
+
  • Support of multi-processor systems.
    • 
+
  • Support of a DMA controller.
    • 
+
  • Deterministic context switching.
    • 
+
  • Round-robin context switching.
    • 
+
  • Deadlock avoidance, for example with priority inversion.
    • 
+
  • Zero interrupt latency by using the Cortex-M3/M4 instructions LDEX and STEX.
    • 
+

+

+
Revision History of CMSIS-RTOS API

+
+
+
+
+
+
+
+
Version Description  
V0.02 Preview Release.  
V0.03 Added: osKernelStart; starting 'main' as a thread is now an optional feature.

+ Semaphores have now the standard behavior.

+ osTimerCreate does no longer start the timer. Added: osTimerStart (replaces osTimerRestart).

+ Changed: osThreadPass is renamed to osThreadYield.   

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/installdox b/CMSIS/Documentation/RTOS/html/installdox
new file mode 100644
index 0000000000..edf5bbfe3e
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/installdox
@@ -0,0 +1,112 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet   = 0;
+
+while ( @ARGV ) {
+  $_ = shift @ARGV;
+  if ( s/^-// ) {
+    if ( /^l(.*)/ ) {
+      $v = ($1 eq "") ? shift @ARGV : $1;
+      ($v =~ /\/$/) || ($v .= "/");
+      $_ = $v;
+      if ( /(.+)\@(.+)/ ) {
+        if ( exists $subst{$1} ) {
+          $subst{$1} = $2;
+        } else {
+          print STDERR "Unknown tag file $1 given with option -l\n";
+          &usage();
+        }
+      } else {
+        print STDERR "Argument $_ is invalid for option -l\n";
+        &usage();
+      }
+    }
+    elsif ( /^q/ ) {
+      $quiet = 1;
+    }
+    elsif ( /^\?|^h/ ) {
+      &usage();
+    }
+    else {
+      print STDERR "Illegal option -$_\n";
+      &usage();
+    }
+  }
+  else {
+    push (@files, $_ );
+  }
+}
+
+foreach $sub (keys %subst)
+{
+  if ( $subst{$sub} eq "" ) 
+  {
+    print STDERR "No substitute given for tag file `$sub'\n";
+    &usage();
+  }
+  elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+  {
+    print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; 
+  }
+}
+
+if ( ! @files ) {
+  if (opendir(D,".")) {
+    foreach $file ( readdir(D) ) {
+      $match = ".html";
+      next if ( $file =~ /^\.\.?$/ );
+      ($file =~ /$match/) && (push @files, $file);
+      ($file =~ /\.svg/) && (push @files, $file);
+      ($file =~ "navtree.js") && (push @files, $file);
+    }
+    closedir(D);
+  }
+}
+
+if ( ! @files ) {
+  print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+  if ( ! $quiet ) {
+    print "Editing: $f...\n";
+  }
+  $oldf = $f;
+  $f   .= ".bak";
+  unless (rename $oldf,$f) {
+    print STDERR "Error: cannot rename file $oldf\n";
+    exit 1;
+  }
+  if (open(F,"<$f")) {
+    unless (open(G,">$oldf")) {
+      print STDERR "Error: opening file $oldf for writing\n";
+      exit 1;
+    }
+    if ($oldf ne "tree.js") {
+      while () {
+        s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+    else {
+      while () {
+        s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+  } 
+  else {
+    print STDERR "Warning file $f does not exist\n";
+  }
+  unlink $f;
+}
+
+sub usage {
+  print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+  print STDERR "Options:\n";
+  print STDERR "     -l tagfile\@linkName   tag file + URL or directory \n";
+  print STDERR "     -q                    Quiet mode\n\n";
+  exit 1;
+}
diff --git a/CMSIS/Documentation/RTOS/html/jquery.js b/CMSIS/Documentation/RTOS/html/jquery.js
new file mode 100644
index 0000000000..c052173a89
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
+(function(){var l=this,g,y=l.jQuery,p=l.$,o=l.jQuery=l.$=function(E,F){return new o.fn.init(E,F)},D=/^[^<]*(<(.|\s)+>)[^>]*$|^#([\w-]+)$/,f=/^.[^:#\[\.,]*$/;o.fn=o.prototype={init:function(E,H){E=E||document;if(E.nodeType){this[0]=E;this.length=1;this.context=E;return this}if(typeof E==="string"){var G=D.exec(E);if(G&&(G[1]||!H)){if(G[1]){E=o.clean([G[1]],H)}else{var I=document.getElementById(G[3]);if(I&&I.id!=G[3]){return o().find(E)}var F=o(I||[]);F.context=document;F.selector=E;return F}}else{return o(H).find(E)}}else{if(o.isFunction(E)){return o(document).ready(E)}}if(E.selector&&E.context){this.selector=E.selector;this.context=E.context}return this.setArray(o.isArray(E)?E:o.makeArray(E))},selector:"",jquery:"1.3.2",size:function(){return this.length},get:function(E){return E===g?Array.prototype.slice.call(this):this[E]},pushStack:function(F,H,E){var G=o(F);G.prevObject=this;G.context=this.context;if(H==="find"){G.selector=this.selector+(this.selector?" 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';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/CMSIS/Documentation/RTOS/html/modules.html b/CMSIS/Documentation/RTOS/html/modules.html
new file mode 100644
index 0000000000..d50acf22f7
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/modules.html
@@ -0,0 +1,147 @@
+
+
+
+
+Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Reference
  

+

+

+
Here is a list of all modules:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/nav_f.png b/CMSIS/Documentation/RTOS/html/nav_f.png
new file mode 100644
index 0000000000..1b07a16207
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/nav_f.png differ
diff --git a/CMSIS/Documentation/RTOS/html/nav_h.png b/CMSIS/Documentation/RTOS/html/nav_h.png
new file mode 100644
index 0000000000..01f5fa6a59
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/nav_h.png differ
diff --git a/CMSIS/Documentation/RTOS/html/navtree.css b/CMSIS/Documentation/RTOS/html/navtree.css
new file mode 100644
index 0000000000..e46ffcd6e0
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/navtree.css
@@ -0,0 +1,123 @@
+#nav-tree .children_ul {
+  margin:0;
+  padding:4px;
+}
+
+#nav-tree ul {
+  list-style:none outside none;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree li {
+  white-space:nowrap;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .plus {
+  margin:0px;
+}
+
+#nav-tree .selected {
+  background-image: url('tab_a.png');
+  background-repeat:repeat-x;
+  color: #fff;
+  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
+
+#nav-tree img {
+  margin:0px;
+  padding:0px;
+  border:0px;
+  vertical-align: middle;
+}
+
+#nav-tree a {
+  text-decoration:none;
+  padding:0px;
+  margin:0px;
+  outline:none;
+}
+
+#nav-tree .label {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .label a {
+  padding:2px;
+}
+
+#nav-tree .selected a {
+  text-decoration:none;
+  padding:2px;
+  margin:0px;
+  color:#fff;
+}
+
+#nav-tree .children_ul {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree {
+  padding: 0px 0px;
+  background-color: #FAFAFF; 
+  font-size:14px;
+  overflow:auto;
+}
+
+#doc-content {
+  overflow:auto;
+  display:block;
+  padding:0px;
+  margin:0px;
+}
+
+#side-nav {
+  padding:0 6px 0 0;
+  margin: 0px;
+  display:block;
+  position: absolute;
+  left: 0px;
+  width: 300px;
+}
+
+.ui-resizable .ui-resizable-handle {
+  display:block;
+}
+
+.ui-resizable-e {
+  background:url("ftv2splitbar.png") repeat scroll right center transparent;
+  cursor:e-resize;
+  height:100%;
+  right:0;
+  top:0;
+  width:6px;
+}
+
+.ui-resizable-handle {
+  display:none;
+  font-size:0.1px;
+  position:absolute;
+  z-index:1;
+}
+
+#nav-tree-contents {
+  margin: 6px 0px 0px 0px;
+}
+
+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/navtree.js b/CMSIS/Documentation/RTOS/html/navtree.js
new file mode 100644
index 0000000000..90d2882aa2
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/navtree.js
@@ -0,0 +1,290 @@
+var NAVTREE =
+[
+  [ "CMSIS-RTOS", "index.html", [
+    [ "Overview", "index.html", null ],
+    [ "Usage and Description", "pages.html", [
+      [ "Using a CMSIS RTOS Implementation", "_using_o_s.html", null ],
+      [ "Function Overview", "_function_overview.html", null ],
+      [ "Header File Template: cmsis_os.h", "cmsis_os_h.html", null ]
+    ] ],
+    [ "Reference", "modules.html", [
+      [ "CMSIS-RTOS API", "group___c_m_s_i_s___r_t_o_s.html", [
+        [ "Kernel Information and Control", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html", null ],
+        [ "Thread Management", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html", null ],
+        [ "Generic Wait Functions", "group___c_m_s_i_s___r_t_o_s___wait.html", null ],
+        [ "Timer Management", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html", null ],
+        [ "Signal Management", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html", null ],
+        [ "Mutex Management", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html", null ],
+        [ "Semaphore Management", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html", null ],
+        [ "Memory Pool Management", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html", null ],
+        [ "Message Queue Management", "group___c_m_s_i_s___r_t_o_s___message.html", null ],
+        [ "Mail Queue Management", "group___c_m_s_i_s___r_t_o_s___mail.html", null ],
+        [ "Generic Data Types and Definitions", "group___c_m_s_i_s___r_t_o_s___definitions.html", null ],
+        [ "Status and Error Codes", "group___c_m_s_i_s___r_t_o_s___status.html", null ]
+      ] ]
+    ] ],
+    [ "Data Structures", "annotated.html", [
+      [ "os_mailQ", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q", null ],
+      [ "osEvent", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event", null ],
+      [ "osMailQDef_t", "structos_mail_q_def__t.html", null ],
+      [ "osMessageQDef_t", "structos_message_q_def__t.html", null ],
+      [ "osMutexDef_t", "structos_mutex_def__t.html", null ],
+      [ "osPoolDef_t", "structos_pool_def__t.html", null ],
+      [ "osSemaphoreDef_t", "structos_semaphore_def__t.html", null ],
+      [ "osThreadDef_t", "structos_thread_def__t.html", null ],
+      [ "osTimerDef_t", "structos_timer_def__t.html", null ]
+    ] ],
+    [ "Data Structure Index", "classes.html", null ],
+    [ "Data Fields", "functions.html", null ],
+    [ "Files", "files.html", [
+      [ "cmsis_os.h", "cmsis__os_8h.html", null ]
+    ] ],
+    [ "Index", "globals.html", null ]
+  ] ]
+];
+
+function createIndent(o,domNode,node,level)
+{
+  if (node.parentNode && node.parentNode.parentNode)
+  {
+    createIndent(o,domNode,node.parentNode,level+1);
+  }
+  var imgNode = document.createElement("img");
+  if (level==0 && node.childrenData)
+  {
+    node.plus_img = imgNode;
+    node.expandToggle = document.createElement("a");
+    node.expandToggle.href = "javascript:void(0)";
+    node.expandToggle.onclick = function() 
+    {
+      if (node.expanded) 
+      {
+        $(node.getChildrenUL()).slideUp("fast");
+        if (node.isLast)
+        {
+          node.plus_img.src = node.relpath+"ftv2plastnode.png";
+        }
+        else
+        {
+          node.plus_img.src = node.relpath+"ftv2pnode.png";
+        }
+        node.expanded = false;
+      } 
+      else 
+      {
+        expandNode(o, node, false);
+      }
+    }
+    node.expandToggle.appendChild(imgNode);
+    domNode.appendChild(node.expandToggle);
+  }
+  else
+  {
+    domNode.appendChild(imgNode);
+  }
+  if (level==0)
+  {
+    if (node.isLast)
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2plastnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2lastnode.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+    else
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2pnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2node.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+  }
+  else
+  {
+    if (node.isLast)
+    {
+      imgNode.src = node.relpath+"ftv2blank.png";
+    }
+    else
+    {
+      imgNode.src = node.relpath+"ftv2vertline.png";
+    }
+  }
+  imgNode.border = "0";
+}
+
+function newNode(o, po, text, link, childrenData, lastNode)
+{
+  var node = new Object();
+  node.children = Array();
+  node.childrenData = childrenData;
+  node.depth = po.depth + 1;
+  node.relpath = po.relpath;
+  node.isLast = lastNode;
+
+  node.li = document.createElement("li");
+  po.getChildrenUL().appendChild(node.li);
+  node.parentNode = po;
+
+  node.itemDiv = document.createElement("div");
+  node.itemDiv.className = "item";
+
+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
+
+  createIndent(o,node.itemDiv,node,0);
+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
+
+  var a = document.createElement("a");
+  node.labelSpan.appendChild(a);
+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
+    a.href = node.relpath+link;
+  } 
+  else 
+  {
+    if (childrenData != null) 
+    {
+      a.className = "nolink";
+      a.href = "javascript:void(0)";
+      a.onclick = node.expandToggle.onclick;
+      node.expanded = false;
+    }
+  }
+
+  node.childrenUL = null;
+  node.getChildrenUL = function() 
+  {
+    if (!node.childrenUL) 
+    {
+      node.childrenUL = document.createElement("ul");
+      node.childrenUL.className = "children_ul";
+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
+    }
+    return node.childrenUL;
+  };
+
+  return node;
+}
+
+function showRoot()
+{
+  var headerHeight = $("#top").height();
+  var footerHeight = $("#nav-path").height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
+
+function expandNode(o, node, imm)
+{
+  if (node.childrenData && !node.expanded) 
+  {
+    if (!node.childrenVisited) 
+    {
+      getNode(o, node);
+    }
+    if (imm)
+    {
+      $(node.getChildrenUL()).show();
+    } 
+    else 
+    {
+      $(node.getChildrenUL()).slideDown("fast",showRoot);
+    }
+    if (node.isLast)
+    {
+      node.plus_img.src = node.relpath+"ftv2mlastnode.png";
+    }
+    else
+    {
+      node.plus_img.src = node.relpath+"ftv2mnode.png";
+    }
+    node.expanded = true;
+  }
+}
+
+function getNode(o, po)
+{
+  po.childrenVisited = true;
+  var l = po.childrenData.length-1;
+  for (var i in po.childrenData) 
+  {
+    var nodeData = po.childrenData[i];
+    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
+        i==l);
+  }
+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
+      }
+    }
+  }
+  return null;
+}
+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
+  o.node.depth = 0;
+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
+
+  o.breadcrumbs = findNavTreePage(toroot, NAVTREE);
+  if (o.breadcrumbs == null)
+  {
+    o.breadcrumbs = findNavTreePage("index.html",NAVTREE);
+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
+    var p = o.node;
+    for (var i in o.breadcrumbs) 
+    {
+      var j = o.breadcrumbs[i];
+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/CMSIS/Documentation/RTOS/html/open.png b/CMSIS/Documentation/RTOS/html/open.png
new file mode 100644
index 0000000000..7b35d2c2c3
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/open.png differ
diff --git a/CMSIS/Documentation/RTOS/html/pages.html b/CMSIS/Documentation/RTOS/html/pages.html
new file mode 100644
index 0000000000..90c9d2cac9
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/pages.html
@@ -0,0 +1,138 @@
+
+
+
+
+Usage and Description
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Usage and Description
  

+

+

+
Here is a list of all related documentation pages:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/resize.js b/CMSIS/Documentation/RTOS/html/resize.js
new file mode 100644
index 0000000000..04fa95ce97
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/resize.js
@@ -0,0 +1,81 @@
+var cookie_namespace = 'doxygen'; 
+var sidenav,navtree,content,header;
+
+function readCookie(cookie) 
+{
+  var myCookie = cookie_namespace+"_"+cookie+"=";
+  if (document.cookie) 
+  {
+    var index = document.cookie.indexOf(myCookie);
+    if (index != -1) 
+    {
+      var valStart = index + myCookie.length;
+      var valEnd = document.cookie.indexOf(";", valStart);
+      if (valEnd == -1) 
+      {
+        valEnd = document.cookie.length;
+      }
+      var val = document.cookie.substring(valStart, valEnd);
+      return val;
+    }
+  }
+  return 0;
+}
+
+function writeCookie(cookie, val, expiration) 
+{
+  if (val==undefined) return;
+  if (expiration == null) 
+  {
+    var date = new Date();
+    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week
+    expiration = date.toGMTString();
+  }
+  document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/";
+}
+ 
+function resizeWidth() 
+{
+  var windowWidth = $(window).width() + "px";
+  var sidenavWidth = $(sidenav).width();
+  content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar
+  writeCookie('width',sidenavWidth, null);
+}
+
+function restoreWidth(navWidth)
+{
+  var windowWidth = $(window).width() + "px";
+  content.css({marginLeft:parseInt(navWidth)+6+"px"});
+  sidenav.css({width:navWidth + "px"});
+}
+
+function resizeHeight() 
+{
+  var headerHeight = header.height();
+  var footerHeight = footer.height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  content.css({height:windowHeight + "px"});
+  navtree.css({height:windowHeight + "px"});
+  sidenav.css({height:windowHeight + "px",top: headerHeight+"px"});
+}
+
+function initResizable()
+{
+  header  = $("#top");
+  sidenav = $("#side-nav");
+  content = $("#doc-content");
+  navtree = $("#nav-tree");
+  footer  = $("#nav-path");
+  $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } });
+  $(window).resize(function() { resizeHeight(); });
+  var width = readCookie('width');
+  if (width) { restoreWidth(width); } else { resizeWidth(); }
+  resizeHeight();
+  var url = location.href;
+  var i=url.indexOf("#");
+  if (i>=0) window.location.hash=url.substr(i);
+  var _preventDefault = function(evt) { evt.preventDefault(); };
+  $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault);
+}
+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_63.html b/CMSIS/Documentation/RTOS/html/search/all_63.html
new file mode 100644
index 0000000000..b71fac69f4
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_63.html
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  cmsis_os.h
+ 

+

+

+ 

+  cmsis_os.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_64.html b/CMSIS/Documentation/RTOS/html/search/all_64.html
new file mode 100644
index 0000000000..17ea6062c7
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_64.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  def
+  osEvent
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_69.html b/CMSIS/Documentation/RTOS/html/search/all_69.html
new file mode 100644
index 0000000000..a924b7908d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_69.html
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  instances
+  osThreadDef_t
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_6d.html b/CMSIS/Documentation/RTOS/html/search/all_6d.html
new file mode 100644
index 0000000000..68f42683e8
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_6d.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  mail_id
+  osEvent
+ 

+

+

+ 

+  message_id
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_6f.html b/CMSIS/Documentation/RTOS/html/search/all_6f.html
new file mode 100644
index 0000000000..6a092422c3
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_6f.html
@@ -0,0 +1,662 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  os_mailQ
+ 

+

+

+ 

+  os_pthread
+  cmsis_os.h
+ 

+

+

+ 

+  os_ptimer
+  cmsis_os.h
+ 

+

+

+ 

+  os_status_reserved
+  cmsis_os.h
+ 

+

+
+

+ 

+  osCMSIS
+  cmsis_os.h
+ 

+

+

+ 

+  osCMSIS_KERNEL
+  cmsis_os.h
+ 

+

+

+ 

+  osDelay
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorISR
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorISRRecursive
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorNoMemory
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorOS
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorParameter
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorResource
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorTimeoutResource
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorValue
+  cmsis_os.h
+ 

+

+

+ 

+  osEvent
+ 

+

+

+ 

+  osEventMail
+  cmsis_os.h
+ 

+

+

+ 

+  osEventMessage
+  cmsis_os.h
+ 

+

+

+ 

+  osEventSignal
+  cmsis_os.h
+ 

+

+

+ 

+  osEventTimeout
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MailQ
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MainThread
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MessageQ
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Pool
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Semaphore
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Signals
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Wait
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelRunning
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelStart
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelSystemId
+  cmsis_os.h
+ 

+

+

+ 

+  osMailAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osMailCAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osMailCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMailFree
+  cmsis_os.h
+ 

+

+

+ 

+  osMailGet
+  cmsis_os.h
+ 

+

+

+ 

+  osMailPut
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQ
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQDef
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQDef_t
+ 

+

+

+ 

+  osMailQId
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageGet
+  cmsis_os.h
+ 

+

+

+ 

+  osMessagePut
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageQ
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageQDef
+  cmsis_os.h
+ 

+

+
+

+ 

+  osMessageQId
+  cmsis_os.h
+ 

+

+

+ 

+  osMutex
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexDef
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexDef_t
+ 

+

+

+ 

+  osMutexId
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexRelease
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexWait
+  cmsis_os.h
+ 

+

+

+ 

+  osOK
+  cmsis_os.h
+ 

+

+

+ 

+  osPool
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolCAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolDef
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolDef_t
+ 

+

+

+ 

+  osPoolFree
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolId
+  cmsis_os.h
+ 

+

+
+

+ 

+  osPriorityAboveNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityBelowNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityError
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityHigh
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityIdle
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityLow
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityRealtime
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphore
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreDef
+  cmsis_os.h
+ 

+

+
+

+ 

+  osSemaphoreId
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreRelease
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreWait
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalClear
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalGet
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalSet
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalWait
+  cmsis_os.h
+ 

+

+
+

+ 

+  osThread
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadDef
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadDef_t
+ 

+

+

+ 

+  osThreadGetId
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadGetPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadId
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadSetPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadTerminate
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadYield
+  cmsis_os.h
+ 

+

+

+ 

+  osTimer
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerDef
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerDef_t
+ 

+

+

+ 

+  osTimerId
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerOnce
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerPeriodic
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerStart
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerStop
+  cmsis_os.h
+ 

+

+

+ 

+  osWait
+  cmsis_os.h
+ 

+

+

+ 

+  osWaitForever
+  cmsis_os.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_70.html b/CMSIS/Documentation/RTOS/html/search/all_70.html
new file mode 100644
index 0000000000..760f336d26
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_70.html
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  p
+  osEvent
+ 

+

+
+

+ 

+  pool_sz
+  osPoolDef_t
+ 

+

+

+ 

+  pthread
+  osThreadDef_t
+ 

+

+

+ 

+  ptimer
+  osTimerDef_t
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_71.html b/CMSIS/Documentation/RTOS/html/search/all_71.html
new file mode 100644
index 0000000000..9923f9a026
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_71.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_73.html b/CMSIS/Documentation/RTOS/html/search/all_73.html
new file mode 100644
index 0000000000..bcddb85e5f
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_73.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  signals
+  osEvent
+ 

+

+

+ 

+  stacksize
+  osThreadDef_t
+ 

+

+

+ 

+  status
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_74.html b/CMSIS/Documentation/RTOS/html/search/all_74.html
new file mode 100644
index 0000000000..bd1c9050b3
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_74.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  tpriority
+  osThreadDef_t
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/all_76.html b/CMSIS/Documentation/RTOS/html/search/all_76.html
new file mode 100644
index 0000000000..f0a5ee248e
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/all_76.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  v
+  osEvent
+ 

+

+

+ 

+  value
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/classes_6f.html b/CMSIS/Documentation/RTOS/html/search/classes_6f.html
new file mode 100644
index 0000000000..e5e385c1d4
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/classes_6f.html
@@ -0,0 +1,65 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  os_mailQ
+ 

+

+

+ 

+  osEvent
+ 

+

+

+ 

+  osMailQDef_t
+ 

+

+
+

+ 

+  osMutexDef_t
+ 

+

+

+ 

+  osPoolDef_t
+ 

+

+
+

+ 

+  osThreadDef_t
+ 

+

+

+ 

+  osTimerDef_t
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/close.png b/CMSIS/Documentation/RTOS/html/search/close.png
new file mode 100644
index 0000000000..9342d3dfee
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/search/close.png differ
diff --git a/CMSIS/Documentation/RTOS/html/search/defines_6f.html b/CMSIS/Documentation/RTOS/html/search/defines_6f.html
new file mode 100644
index 0000000000..72be71530d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/defines_6f.html
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  osCMSIS
+  cmsis_os.h
+ 

+

+

+ 

+  osCMSIS_KERNEL
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MailQ
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MainThread
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_MessageQ
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Pool
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Semaphore
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Signals
+  cmsis_os.h
+ 

+

+

+ 

+  osFeature_Wait
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelSystemId
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQ
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQDef
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageQ
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageQDef
+  cmsis_os.h
+ 

+

+

+ 

+  osMutex
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexDef
+  cmsis_os.h
+ 

+

+

+ 

+  osPool
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolDef
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphore
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreDef
+  cmsis_os.h
+ 

+

+

+ 

+  osThread
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadDef
+  cmsis_os.h
+ 

+

+

+ 

+  osTimer
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerDef
+  cmsis_os.h
+ 

+

+

+ 

+  osWaitForever
+  cmsis_os.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/enums_6f.html b/CMSIS/Documentation/RTOS/html/search/enums_6f.html
new file mode 100644
index 0000000000..806ec82392
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/enums_6f.html
@@ -0,0 +1,47 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html b/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html
new file mode 100644
index 0000000000..3929b4d94b
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  os_status_reserved
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorISR
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorISRRecursive
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorNoMemory
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorOS
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorParameter
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorResource
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorTimeoutResource
+  cmsis_os.h
+ 

+

+

+ 

+  osErrorValue
+  cmsis_os.h
+ 

+

+

+ 

+  osEventMail
+  cmsis_os.h
+ 

+

+

+ 

+  osEventMessage
+  cmsis_os.h
+ 

+

+

+ 

+  osEventSignal
+  cmsis_os.h
+ 

+

+

+ 

+  osEventTimeout
+  cmsis_os.h
+ 

+

+

+ 

+  osOK
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityAboveNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityBelowNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityError
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityHigh
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityIdle
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityLow
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityNormal
+  cmsis_os.h
+ 

+

+

+ 

+  osPriorityRealtime
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerOnce
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerPeriodic
+  cmsis_os.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/files_63.html b/CMSIS/Documentation/RTOS/html/search/files_63.html
new file mode 100644
index 0000000000..b71fac69f4
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/files_63.html
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  cmsis_os.h
+ 

+

+

+ 

+  cmsis_os.txt
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/functions_6f.html b/CMSIS/Documentation/RTOS/html/search/functions_6f.html
new file mode 100644
index 0000000000..59c72e036b
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/functions_6f.html
@@ -0,0 +1,236 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  osDelay
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelRunning
+  cmsis_os.h
+ 

+

+

+ 

+  osKernelStart
+  cmsis_os.h
+ 

+

+

+ 

+  osMailAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osMailCAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osMailCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMailFree
+  cmsis_os.h
+ 

+

+

+ 

+  osMailGet
+  cmsis_os.h
+ 

+

+

+ 

+  osMailPut
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageGet
+  cmsis_os.h
+ 

+

+

+ 

+  osMessagePut
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexRelease
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexWait
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolCAlloc
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolFree
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreRelease
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreWait
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalClear
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalGet
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalSet
+  cmsis_os.h
+ 

+

+

+ 

+  osSignalWait
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadGetId
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadGetPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadSetPriority
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadTerminate
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadYield
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerCreate
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerStart
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerStop
+  cmsis_os.h
+ 

+

+

+ 

+  osWait
+  cmsis_os.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/mag_sel.png b/CMSIS/Documentation/RTOS/html/search/mag_sel.png
new file mode 100644
index 0000000000..81f6040a20
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/search/mag_sel.png differ
diff --git a/CMSIS/Documentation/RTOS/html/search/nomatches.html b/CMSIS/Documentation/RTOS/html/search/nomatches.html
new file mode 100644
index 0000000000..b1ded27e9a
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/nomatches.html
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+

+
No Matches

+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/search.css b/CMSIS/Documentation/RTOS/html/search/search.css
new file mode 100644
index 0000000000..1746d13fd6
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/CMSIS/Documentation/RTOS/html/search/search.js b/CMSIS/Documentation/RTOS/html/search/search.js
new file mode 100644
index 0000000000..32e7118d3e
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/search.js
@@ -0,0 +1,742 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100001000101110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000100110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "typedefs",
+  6: "enums",
+  7: "enumvalues",
+  8: "defines"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of .
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/CMSIS/Documentation/RTOS/html/search/search_l.png b/CMSIS/Documentation/RTOS/html/search/search_l.png
new file mode 100644
index 0000000000..c872f4da4a
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/search/search_l.png differ
diff --git a/CMSIS/Documentation/RTOS/html/search/search_m.png b/CMSIS/Documentation/RTOS/html/search/search_m.png
new file mode 100644
index 0000000000..b429a16ba6
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/search/search_m.png differ
diff --git a/CMSIS/Documentation/RTOS/html/search/search_r.png b/CMSIS/Documentation/RTOS/html/search/search_r.png
new file mode 100644
index 0000000000..97ee8b4396
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/search/search_r.png differ
diff --git a/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html b/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html
new file mode 100644
index 0000000000..b1372caca3
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html
@@ -0,0 +1,74 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  os_pthread
+  cmsis_os.h
+ 

+

+

+ 

+  os_ptimer
+  cmsis_os.h
+ 

+

+

+ 

+  osMailQId
+  cmsis_os.h
+ 

+

+

+ 

+  osMessageQId
+  cmsis_os.h
+ 

+

+

+ 

+  osMutexId
+  cmsis_os.h
+ 

+

+

+ 

+  osPoolId
+  cmsis_os.h
+ 

+

+

+ 

+  osSemaphoreId
+  cmsis_os.h
+ 

+

+

+ 

+  osThreadId
+  cmsis_os.h
+ 

+

+

+ 

+  osTimerId
+  cmsis_os.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_64.html b/CMSIS/Documentation/RTOS/html/search/variables_64.html
new file mode 100644
index 0000000000..17ea6062c7
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_64.html
@@ -0,0 +1,35 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  def
+  osEvent
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_69.html b/CMSIS/Documentation/RTOS/html/search/variables_69.html
new file mode 100644
index 0000000000..a924b7908d
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_69.html
@@ -0,0 +1,36 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  instances
+  osThreadDef_t
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_6d.html b/CMSIS/Documentation/RTOS/html/search/variables_6d.html
new file mode 100644
index 0000000000..68f42683e8
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_6d.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  mail_id
+  osEvent
+ 

+

+

+ 

+  message_id
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_70.html b/CMSIS/Documentation/RTOS/html/search/variables_70.html
new file mode 100644
index 0000000000..760f336d26
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_70.html
@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  p
+  osEvent
+ 

+

+
+

+ 

+  pool_sz
+  osPoolDef_t
+ 

+

+

+ 

+  pthread
+  osThreadDef_t
+ 

+

+

+ 

+  ptimer
+  osTimerDef_t
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_71.html b/CMSIS/Documentation/RTOS/html/search/variables_71.html
new file mode 100644
index 0000000000..9923f9a026
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_71.html
@@ -0,0 +1,29 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_73.html b/CMSIS/Documentation/RTOS/html/search/variables_73.html
new file mode 100644
index 0000000000..bcddb85e5f
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_73.html
@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  signals
+  osEvent
+ 

+

+

+ 

+  stacksize
+  osThreadDef_t
+ 

+

+

+ 

+  status
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_74.html b/CMSIS/Documentation/RTOS/html/search/variables_74.html
new file mode 100644
index 0000000000..bd1c9050b3
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_74.html
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  tpriority
+  osThreadDef_t
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/search/variables_76.html b/CMSIS/Documentation/RTOS/html/search/variables_76.html
new file mode 100644
index 0000000000..f0a5ee248e
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/search/variables_76.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  v
+  osEvent
+ 

+

+

+ 

+  value
+  osEvent
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html b/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html
new file mode 100644
index 0000000000..9e8b627905
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html
@@ -0,0 +1,195 @@
+
+
+
+
+osMailQDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osMailQDef_t Struct Reference
  

+

+

+
+
Definition structure for mail queue.  
+ More...

+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t queue_sz
 number of elements in the queue  
uint32_t item_sz
 size of an item  
void * pool
 memory array for mail  

+
Description

+
Note:
CAN BE CHANGED: os_mailQ_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t item_sz

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
void* pool

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t queue_sz

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html b/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html
new file mode 100644
index 0000000000..eb0a9f71b6
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html
@@ -0,0 +1,195 @@
+
+
+
+
+osMessageQDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osMessageQDef_t Struct Reference
  

+

+

+
+
Definition structure for message queue.  
+ More...

+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t queue_sz
 number of elements in the queue  
uint32_t item_sz
 size of an item  
void * pool
 memory array for messages  

+
Description

+
Note:
CAN BE CHANGED: os_messageQ_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t item_sz

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
void* pool

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t queue_sz

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html b/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html
new file mode 100644
index 0000000000..680b25dedf
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html
@@ -0,0 +1,165 @@
+
+
+
+
+osMutexDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osMutexDef_t Struct Reference
  

+

+

+
+
Mutex Definition structure contains setup information for a mutex.  
+ More...

+
+
+
+
+

+Data Fields
uint32_t dummy
 dummy value.  

+
Description

+
Note:
CAN BE CHANGED: os_mutex_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t dummy

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html b/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html
new file mode 100644
index 0000000000..da6aadef81
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html
@@ -0,0 +1,195 @@
+
+
+
+
+osPoolDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osPoolDef_t Struct Reference
  

+

+

+
+
Definition structure for memory block allocation.  
+ More...

+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t pool_sz
 number of items (elements) in the pool  
uint32_t item_sz
 size of an item  
void * pool
 pointer to memory for pool  

+
Description

+
Note:
CAN BE CHANGED: os_pool_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t item_sz

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
void* pool

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t pool_sz

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html b/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html
new file mode 100644
index 0000000000..5cbc4e6d77
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html
@@ -0,0 +1,165 @@
+
+
+
+
+osSemaphoreDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osSemaphoreDef_t Struct Reference
  

+

+

+
+
Semaphore Definition structure contains setup information for a semaphore.  
+ More...

+
+
+
+
+

+Data Fields
uint32_t dummy
 dummy value.  

+
Description

+
Note:
CAN BE CHANGED: os_semaphore_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t dummy

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html b/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html
new file mode 100644
index 0000000000..83b9709986
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html
@@ -0,0 +1,210 @@
+
+
+
+
+osThreadDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osThreadDef_t Struct Reference
  

+

+

+
+
Thread Definition structure contains startup information of a thread.  
+ More...

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
os_pthread pthread
 start address of thread function  
osPriority tpriority
 initial thread priority  
uint32_t instances
 maximum number of instances of that thread function  
uint32_t stacksize
 stack size requirements in bytes; 0 is default stack size  

+
Description

+
Note:
CAN BE CHANGED: os_thread_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t instances

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
os_pthread pthread

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t stacksize

+

+

+
+

+

+
+

+

+      
+        
+          
+        
+      
osPriority tpriority

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html b/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html
new file mode 100644
index 0000000000..b84eaf154c
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html
@@ -0,0 +1,165 @@
+
+
+
+
+osTimerDef_t Struct Reference
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-RTOS
+    Version 1.00
+   

+   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.

+  

+

+
+

+    
+

+
+
+  
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Data Fields  

+  

+
osTimerDef_t Struct Reference
  

+

+

+
+
Timer Definition structure contains timer parameters.  
+ More...

+
+
+
+
+

+Data Fields
os_ptimer ptimer
 start address of a timer function  

+
Description

+
Note:
CAN BE CHANGED: os_timer_def is implementation specific in every CMSIS-RTOS. 

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
os_ptimer ptimer

+

+

+
+

+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/RTOS/html/tab_a.png b/CMSIS/Documentation/RTOS/html/tab_a.png
new file mode 100644
index 0000000000..2d99ef23fe
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/tab_a.png differ
diff --git a/CMSIS/Documentation/RTOS/html/tab_b.png b/CMSIS/Documentation/RTOS/html/tab_b.png
new file mode 100644
index 0000000000..b2c3d2be3c
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/tab_b.png differ
diff --git a/CMSIS/Documentation/RTOS/html/tab_h.png b/CMSIS/Documentation/RTOS/html/tab_h.png
new file mode 100644
index 0000000000..c11f48f19b
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/tab_h.png differ
diff --git a/CMSIS/Documentation/RTOS/html/tab_s.png b/CMSIS/Documentation/RTOS/html/tab_s.png
new file mode 100644
index 0000000000..978943ac80
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diff --git a/CMSIS/Documentation/RTOS/html/tab_topnav.png b/CMSIS/Documentation/RTOS/html/tab_topnav.png
new file mode 100644
index 0000000000..b257b7780f
Binary files /dev/null and b/CMSIS/Documentation/RTOS/html/tab_topnav.png differ
diff --git a/CMSIS/Documentation/RTOS/html/tabs.css b/CMSIS/Documentation/RTOS/html/tabs.css
new file mode 100644
index 0000000000..ffbab509d7
--- /dev/null
+++ b/CMSIS/Documentation/RTOS/html/tabs.css
@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
+    font-size: 12px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
+}
+
+.tabs1 .tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_topnav.png');
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/CMSIS/Documentation/SVD/html/Access_SVD_DD_Manage.png b/CMSIS/Documentation/SVD/html/Access_SVD_DD_Manage.png
new file mode 100644
index 0000000000..841587ed5f
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/Access_SVD_DD_Manage.png differ
diff --git a/CMSIS/Documentation/SVD/html/Access_SVD_Vendor.png b/CMSIS/Documentation/SVD/html/Access_SVD_Vendor.png
new file mode 100644
index 0000000000..4a7fc7c484
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/Access_SVD_Vendor.png differ
diff --git a/CMSIS/Documentation/SVD/html/CMSIS-SVD_Schema_1_0.xsd b/CMSIS/Documentation/SVD/html/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 0000000000..e0ea55d50e
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,274 @@
+
+
+
+
+  
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+         
+     
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+        
+        
+        
+        
+        
+        
+        
+          
+            
+              
+                
+                  
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                      
+                        
+                          
+                            
+                              
+                                
+                                 
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                  
+                                    
+                                      
+                                      
+                                        
+                                          
+                                          
+                                          
+                                            
+                                            
+                                            
+                                          
+                                          
+                                          
+                                          
+                                          
+                                          
+                                            
+                                              
+                                                
+                                                
+                                                
+                                                  
+                                                    
+                                                      
+                                                      
+                                                      
+                                                        
+                                                        
+                                                      
+                                                    
+                                                  
+                                                
+                                              
+                                              
+                                            
+                                          
+                                        
+                                        
+                                      
+                                    
+                                    
+                                  
+                                
+                              
+                              
+                            
+                          
+                        
+                      
+                    
+                  
+                  
+                
+              
+            
+          
+        
+        
+          
+            
+              
+              
+            
+          
+        
+      
+      
+    
+  
+
diff --git a/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png b/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000000..2056b7e747
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png differ
diff --git a/CMSIS/Documentation/SVD/html/CMSIS_SVD_Schema_Gen.png b/CMSIS/Documentation/SVD/html/CMSIS_SVD_Schema_Gen.png
new file mode 100644
index 0000000000..cf7aa838c6
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/CMSIS_SVD_Schema_Gen.png differ
diff --git a/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png b/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png
new file mode 100644
index 0000000000..d62f75bfaa
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png differ
diff --git a/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png b/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png
new file mode 100644
index 0000000000..1354448621
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png differ
diff --git a/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png b/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png
new file mode 100644
index 0000000000..f14f62c22e
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png differ
diff --git a/CMSIS/Documentation/SVD/html/bc_s.png b/CMSIS/Documentation/SVD/html/bc_s.png
new file mode 100644
index 0000000000..51ba0066de
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/bc_s.png differ
diff --git a/CMSIS/Documentation/SVD/html/closed.png b/CMSIS/Documentation/SVD/html/closed.png
new file mode 100644
index 0000000000..b7d4bd9fef
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/closed.png differ
diff --git a/CMSIS/Documentation/SVD/html/cmsis.css b/CMSIS/Documentation/SVD/html/cmsis.css
new file mode 100644
index 0000000000..a5c4b8de50
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/CMSIS/Documentation/SVD/html/doxygen.png b/CMSIS/Documentation/SVD/html/doxygen.png
new file mode 100644
index 0000000000..635ed52fce
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diff --git a/CMSIS/Documentation/SVD/html/dynsections.js b/CMSIS/Documentation/SVD/html/dynsections.js
new file mode 100644
index 0000000000..bf148075e8
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/dynsections.js
@@ -0,0 +1,42 @@
+var showTriggers = new Array();
+
+function registerShow(sectId,showFunc) {
+  showTriggers[sectId] = showFunc;
+}
+
+function hasClass(ele,cls) {
+  return ele.className.match(new RegExp('(\\s|^)'+cls+'(\\s|$)'));
+}
+
+function addClass(ele,cls) {
+  if (!this.hasClass(ele,cls)) ele.className += " "+cls;
+}
+
+function removeClass(ele,cls) {
+  if (hasClass(ele,cls)) {
+    var reg = new RegExp('(\\s|^)'+cls+'(\\s|$)');
+    ele.className=ele.className.replace(reg,' ');
+  }
+}
+
+function toggleVisibility(linkObj) {
+ var base = linkObj.getAttribute('id');
+ var summary = document.getElementById(base + '-summary');
+ var content = document.getElementById(base + '-content');
+ var trigger = document.getElementById(base + '-trigger');
+ if ( hasClass(linkObj,'closed') ) {
+   summary.style.display = 'none';
+   content.style.display = 'block';
+   trigger.src = trigger.src.substring(0,trigger.src.length-10)+'open.png';
+   removeClass(linkObj,'closed');
+   addClass(linkObj,'opened');
+   if (showTriggers[base]) { showTriggers[base](); }
+ } else if ( hasClass(linkObj,'opened') ) {
+   summary.style.display = 'block';
+   content.style.display = 'none';
+   trigger.src = trigger.src.substring(0,trigger.src.length-8)+'closed.png';
+   removeClass(linkObj,'opened');
+   addClass(linkObj,'closed');
+ }
+ return false;
+}
diff --git a/CMSIS/Documentation/SVD/html/ftv2blank.png b/CMSIS/Documentation/SVD/html/ftv2blank.png
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index 0000000000..1b703dd386
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index 0000000000..3b7a29cb81
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diff --git a/CMSIS/Documentation/SVD/html/ftv2plastnode.png b/CMSIS/Documentation/SVD/html/ftv2plastnode.png
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diff --git a/CMSIS/Documentation/SVD/html/ftv2pnode.png b/CMSIS/Documentation/SVD/html/ftv2pnode.png
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diff --git a/CMSIS/Documentation/SVD/html/ftv2vertline.png b/CMSIS/Documentation/SVD/html/ftv2vertline.png
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diff --git a/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html b/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html
new file mode 100644
index 0000000000..aee5b81ed8
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html
@@ -0,0 +1,182 @@
+
+
+
+
+Cluster Level (New)
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Cluster Level (New)
  

+
SVD Extension in Version 1.1

+

+
Cluster adds a new and optional sub-level to the CMSIS SVD registers level. A cluster describes a sequence of registers within a peripheral. A cluster has an base offset relative to the base address of the peripheral. All registers within a cluster specify their address offset relative to the cluster base address. Register and cluster sections can occur in an arbitrary order. This feature, targeted at the generation of device header files, is useful to create a C data structure within the peripheral structure type, rather than describing all registers of a peripheral in a flat structure.

+

+
+<registers> 
    <cluster derivedFrom=identifierType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>dimIndexType</dimIndex>
+        <!-- end of dimElementGroup --> 
+    
+        <name>identifierType</name>
+        <description>xs:string</description>
+    
+        <headerStructName>identifierType</headerStructName>
+        <alternateCluster>identifierType</alternateCluster>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
        <register>
+            ...
+        </register>
+    </cluster>
+    ...
+    <register>
+        ...
+    </register>
+    <cluster>
+        ...
+    </cluster>
+     
+<registers> 
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of the cluster from which to inherit the data. Elements being specified underneath will override the inherited values. 

+Remarks: When deriving a cluster, it is mandatory to specify at least the name, the description, and the addressOffset. 		registerType 0..1  
Element Name Description Type Occurrence  
See dimElementGroup for details.  
dimIncrement The value defines the number of elements in an array of clusters.  scaledNonNegativeInteger  1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring clusters of the cluster array in the address map. scaledNonNegativeInteger  1..1   
dimIndex Specifies the substrings that replaces the [%s] placeholder within the cluster name. By default, the index is a decimal value starting with 0 for the first cluster element.  dimIndexType  0..1   
name String that identifies the cluster. Register names are required to be unique within the scope of a peripheral. Specify [%s] for generating an array in the device header file. identifierType  1..1   
description String describing the details of the register. xs:string  0..1   
alternateCluster  This tag needs to specify the name of the original description of the register sequence if this cluster provides an alternative description. Otherwise the SVDConv will issue errors. identifierType 0..1   
headerStructName  This tag specifies the struct type name in the device header file. If not specified, then the name of the cluster will be used. identifierType 0..1   
addressOffset Value defining the cluster address relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1   

+

+Example:

+
<cluster>
+    <dim>4</dim>
+        <dimIncrement>8</dimIncrement>
+        <dimIndex>0-3</dimIndex>
+    <name>TX[%s]</name>
+    <description>Grouping of Transfer data and address</description>
+    <addressOffset>0x40</addressOffset>
+    <register>
+            <name>TX_DATA</name>
+        ...
+            <addressOffset>0x0</addressOffset>
+        ...
+    </register>
+    <register>
+            <name>TX_ADDR</name>
+        ...
+            <addressOffset>0x4</addressOffset>
+        ...
+    </register>
+</cluster>
+
The example above describes an array of type TX with 4 elements. TX is a cluster of two consecutive registers with 4 elements. The device header file looks like this:

+
typedef struct {
+    ...
+    struct {
+       __IO uint32_t  TX_DATA;
+       __IO uint32_t  TX_ADDR;
+    } TX[4];
+    ...
+} ..._Type;
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html
new file mode 100644
index 0000000000..ccc93af270
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html
@@ -0,0 +1,152 @@
+
+
+
+
+CPU Section (New)
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
CPU Section (New)
  

+
SVD Extension in Version 1.1

+

+
The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.

+
+<cpu>
+    <name>cpuNameType<name>
+    <revision>revisionType<revision>
+    <endian>endianType<endian>
+    <mpuPresent>xs:boolean<mpuPresent>
+    <fpuPresent>xs:boolean<fpuPresent>
+    <nvicPrioBits>scaledNonNegativeInteger<nvicPrioBits>
+    <vendorSystickConfig>xs:boolean<vendorSystickConfig>
+</cpu>
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
name The predefined tokens are:
    
+
  • CM0: ARM Cortex-M0
    • 
+
  • CM0PLUS: ARM Cortex-M0+
    • 
+
  • CM3: ARM Cortex-M3
    • 
+
  • CM4: ARM Cortex-M4
    • 
+
  • SC000: ARM Secure Core SC000
    • 
+
  • SC300: ARM Secure Core SC300
    • 
+
  • other: other processor architectures  
    • 
+

+		cpuNameType  1..1   
revisionType  Defines the HW revision of the processor. The defined version format is rNpM (N,M = [0 - 9]).  revisionType 1..1   
endian  Defines the endianess of the processor being one of:
    
+
  • little: little endian memory (least significant byte gets allocated at the lowest address).
    • 
+
  • big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
    • 
+
  • selectable: little and big endian are configurable for the device and become active after the next reset.
    • 
+
  • other: the endianess is neither little nor big endian.  
    • 
+

+		endianType  1..1   
mpuPresent  Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0. boolean  1..1   
fpuPresent  Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0. boolean  1..1   
nvicPrioBits  Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. scaledNonNegativeInteger  1..1   
vendorSystickConfig Indicates whether the processor implements a vendor-specific System Tick Timer. If false, then the ARM defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0. boolean  1..1   

+

+Example:

+
...
+<cpu>
+    <name>CM4</name> 
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig> 
+</cpu>  
+...
+
This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html b/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html
new file mode 100644
index 0000000000..b7d27f4cd6
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html
@@ -0,0 +1,154 @@
+
+
+
+
+Extensions to the Device Section
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Extensions to the Device Section
  

+
SVD Extension in Version 1.1

+

+
A number of elements have been added to the device section. These elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

+
+<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+    <vendor>stringType</vendor>
+    <vendorID>stringType</vendorID>
+    <name>identifierType</name>
+    <series>stringType</series>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <licenseText>xs:string</licenseText>
+    <cpu>cpuType</cpu>
+    <headerSystemFilename>identifierType</headerSystemFilename>
+    <headerDefinitionsPrefix>identifierType</headerDefinitionsPrefix>
+
+    ...
+</device>
+
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
vendor This specifies the vendor of the device using the full name. stringType  0..1   
vendorID This specifies the vendor of the device using the vendor abbreviation that does not contain any spaces or special characters. This information shall be used for defining the directory. stringType  0..1   
series This element specifies the name of the device series. stringType  0..1   
licenseText The content of this tag will be copied into the header section of the generated device header file and shall contain the legal disclaimer. New lines can be inserted by using "\n". This section is mandatory if the SVD file shall be used for generating the device header file. stringType  0..1    
headerSystemFilename This tag specifies the file name (without extension) of the device-specific system include file (system_<device>.h; See CMSIS-Core description). This tag is used by the header file generator for customizing the include statement referencing the CMSIS system file within the CMSIS device header file. By default, the filename is "<kbd>system_<i>device:name</i>.h". In cases where a device series shares a single system header file, the name of the series shall be used instead of the individual device name. identifierType  0..1   
headerDefinitionsPrefix The element specifies the string being prepended to all type definition names generated in the CMSIS-Core device header file. This is used if the silicon vendor's software requires vendor-specific types in order to avoid name clashes with other definied types. identifierType  0..1   

+

+Example:

+
...
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+    <vendor>Advanced RISC Machines</vendor>
+    <vendorID>ARM</vendorID>
+    ...
+    <series>ARMCM3</series>
+    ...
+    <licenseText>
+    ARM Limited (ARM) is supplying this software for use with Cortex-M \n
+    processor based microcontrollers.  This file can be freely distributed \n
+    within development tools that are supporting such ARM based processors. \n
+    \n
+    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n
+    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \n
+    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \n
+    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+    </licenseText>
+    ...
+    <headerSystemFilename>system_ARMCM4</headeSystemFilename>
+    <headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix>
+    ...
+</device>       
+...
+
This example describes a device from the vendor Advanced RISC Machines using ARM as short name. The device belongs to the device family identified by ARMCM4. The legal disclaimer in the header files generated from this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the generated device header file is named system_ARMCM4.h and all type definitions will be prepended with ARM_. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html b/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html
new file mode 100644
index 0000000000..db637accbf
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html
@@ -0,0 +1,125 @@
+
+
+
+
+dimElementGroup
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
dimElementGroup
  

+
Element Groups

+

+
The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index-specific substring defined in <dimIndex>. The <dimIncrement> specifies the address offset between two registers. The elements below can be used to generate an array of registers.

+
+
+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
dim The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1   
dimIndex Specifies the substrings that replaces the s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1   

+

+Examples:

+
...
+<register>
+    <dim>6</dim> 
+    <dimIncrement>4</dimIncrement> 
+    <dimIndex>A,B,C,D,E,Z</dimIndex> 
+    <name>GPIO_%s_CTRL</name> 
+...
+</register>
+
The code above generates: => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL

+
...
+<register>
+    <dim>4</dim> 
+    <dimIncrement>4</dimIncrement> 
+    <dimIndex>3-6</dimIndex> 
+    <name>IRQ%s</name> 
+...
+</register>
+
The example above generates: => IRQ3, IRQ4, IRQ5, IRQ6 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__elem__type__gr.html b/CMSIS/Documentation/SVD/html/group__elem__type__gr.html
new file mode 100644
index 0000000000..d66187a82e
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__elem__type__gr.html
@@ -0,0 +1,102 @@
+
+
+
+
+Element Groups
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
Element Groups
  

+

+

+
+
+
+
+

+Modules
 dimElementGroup
 registerPropertiesGroup

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html b/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html
new file mode 100644
index 0000000000..94dc75ea64
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html
@@ -0,0 +1,121 @@
+
+
+
+
+Extensions to the Peripheral Section
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Extensions to the Peripheral Section
  

+
SVD Extension in Version 1.1

+

+
The following elements have been added to the peripheral section. All new elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
alternatePeripheral All address blocks in the memory space of a device are assigned to a unique peripheral by default. If there are multiple peripherals describing the same address blocks, this needs to be specified explicitly. A peripheral redefining an address block needs to specify the name of the peripheral that is listed first in the description. If no alternate peripheral is specified, then the SVDConv utility will generate errors. identifierType  0..1   
headerStructName The header file generator uses the name of a peripheral as the base name for the C structure type. If this element is specfied, then this string is used instead of the peripheral name. This is particularly useful when multiple peripherals get derived from a peripheral description and a generic type name shall be used. identifierType  0..1   

+

+Example:

+
<peripheral>
+  <name>Timer1</name>
+  <version>1.0</version>
+  <description>Timer 1 is a standard timer ... </description>
+  <baseAddress>0x40002000</baseAddress>
+  ...
+</peripheral>
+<peripheral>
+  <name>Timer1_Alt</name>
+  <version>1.0</version>
+  <description>Alternate Timer 1 is a special timer execution mode ... </description>
+  <baseAddress>0x40002000</baseAddress>
+  <alternatePeripheral>Timer1</alternatePeripheral>
+  ...
+</peripheral>
+
Two timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html b/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html
new file mode 100644
index 0000000000..e1b22728c4
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html
@@ -0,0 +1,116 @@
+
+
+
+
+registerPropertiesGroup
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
registerPropertiesGroup
  

+
Element Groups

+

+
Register properties can be set on device, peripheral, and register level. Element values defined on a lower level overwrite element values defined on a more general level. For example, the register-level.<size> will overwrite peripheral-level.<size>. Elements that have not been defined on a more general level, must be defined at register level at the latest.

+
+
+
+
+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
size Defines the default bit-width of any register contained in the device (implicit inheritance). This element can be redefined on any lower level of the description using the size element there.  scaledNonNegativeInteger  0..1   
access  Defines the default access rights for all registers. Access rights can be redefined on any lower level of the description using the access element there. 

+ 

+ The predefined tokens are:
    
+
  • read-only: read access is permitted. Write operations have an undefined result.
    • 
+
  • write-only: write access is permitted. Read operations have an undefined result.
    • 
+
  • read-write: both read and write accesses are permitted. Writes affect the state of the register and reads return a value related to the register.
    • 
+
  • writeOnce: only the first write after reset has an effect on the register. Read operations deliver undefined results.
    • 
+
  • read-writeOnce: Read operations deliver a result related to the register content. Only the first write access to this register after a reset will have an effect on the register content.  
    • 
+

+		accessType 0..1   
resetValue  Defines the default value for all registers at RESET. The default register value can be redefined on any lower level using the resetValue element there. The actual reset value is calculated from the resetValue and the resetMask. The mask is used to specify bits with an undefined reset value. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. These bit positions are set to one. Bit positions with an undefined reset value are set to zero. scaledNonNegativeInteger 0..1   

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html b/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html
new file mode 100644
index 0000000000..65a0520fd9
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html
@@ -0,0 +1,151 @@
+
+
+
+
+Extensions to the Register Section
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Extensions to the Register Section
  

+
SVD Extension in Version 1.1

+

+
The following elements have been added to the register section. All new elements are optional.

+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
alternateRegister This tag can reference a register that has been defined above to current location in the description and that describes the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is intentional. The register name needs to be unique within the scope of the current peripheral. A register description is defined either for a unique address location or could be a redefinition of an already described address. In the latter case, the register can be either marked alternateRegister and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through the tag alternateGroup (specified in version 1.0). identifierType  0..1   
dataType It can be useful to assign a specific native C datatype to a register. This helps avoiding type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then dataType can be set to "uint32_t *". The following simple data types are predefined:
    
+
  • uint8_t: unsigned byte
    • 
+
  • uint16_t: unsigned half word
    • 
+
  • uint32_t: unsigned word
    • 
+
  • uint64_t: unsigned double word
    • 
+
  • int8_t: signed byte
    • 
+
  • int16_t: signed half word
    • 
+
  • int32_t: signed world
    • 
+
  • int64_t: signed double word
    • 
+
  • uint8_t *: pointer to unsigned byte
    • 
+
  • uint16_t *: pointer to unsigned half word
    • 
+
  • uint32_t *: pointer to unsigned word
    • 
+
  • uint64_t *: pointer to unsigned double word
    • 
+
  • int8_t *: pointer to signed byte
    • 
+
  • int16_t *: pointer to signed half word
    • 
+
  • int32_t *: pointer to signed world
    • 
+
  • int64_t *: pointer to signed double word 
    • 
+

+		dataTypeType  0..1   

+

+Example:

+
...
+<register>
+    <name>TIM_MODEA</name>
+    <description>In mode A this register acts as a reload value</description>
+    <addressOffset>0xC</addressOffset>
+</register>
+<register>
+    <name>TIM_MODEB</name>
+    <description>In mode B this register acts as the compare value</description>
+    <alternateRegister>TIM_MODEA</alternateRegister>
+    <addressOffset>0xC</addressOffset>
+</register>     
+<register>
+    <name>DMA_DATA</name>
+    <description>This register contains the address of the data being transferred</description>
+    <dataType>uint32_t *</dataType>
+    <addressOffset>0xf0</addressOffset>
+</register>     
+...
+
This example describes two registers, TIM_MODEA and TIM_MODEB. Both have the same address offset. Based on the configured operation model being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. The code generated for the device header file is:

+
typedef struct {
+  union {
+    __IO   uint32_t TIM_MODEA;
+    __IO   uint32_t TIM_MODEB;
+        };
+  __IO uint32_t * DMA_DATA; 
+  ...
+} <peripheral:name>_Type;
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html b/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html
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+++ b/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html
@@ -0,0 +1,603 @@
+
+
+
+
+CMSIS-SVD Schema File Ver. 1.1 (draft)
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
CMSIS-SVD Schema File Ver. 1.1 (draft)
  

+

+

+
<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @note    Copyright (C) 2011-2012 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @date: 12.03.2012
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+  This is a draft for CMSIS-SVD version 1.1
+  For backward compatibility all additional tags have been made optional.
+  Extensions may be mandatory for successful device header file generation
+  Other changes are related to some restructuring of the schema.
+  
+  Note that the memory section has been removed since this would limit the
+  reuse of descriptions for a series of devices.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.1">
+  <!-- stringType requires a none empty string of a least one character length -->
+  <xs:simpleType name="stringType">
+    <xs:restriction base="xs:string">
+      <xs:minLength value="1"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
+  <xs:simpleType name="cpuNameType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="CM0"/>
+      <xs:enumeration value="CM0PLUS"/>
+      <xs:enumeration value="CM0+"/>
+      <xs:enumeration value="SC000"/>
+      <xs:enumeration value="CM3"/>
+      <xs:enumeration value="SC300"/>
+      <xs:enumeration value="CM4"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->
+  <xs:simpleType name="revisionType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="r[0-9]p[0-9]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
+  <xs:simpleType name="endianType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="little"/>
+      <xs:enumeration value="big"/>
+      <xs:enumeration value="selectable"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->
+  <xs:simpleType name="dataTypeType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="uint8_t"/>
+      <xs:enumeration value="uint16_t"/>
+      <xs:enumeration value="uint32_t"/>
+      <xs:enumeration value="uint64_t"/>
+      <xs:enumeration value="int8_t"/>
+      <xs:enumeration value="int16_t"/>
+      <xs:enumeration value="int32_t"/>
+      <xs:enumeration value="int64_t"/>
+      <xs:enumeration value="uint8_t *"/>
+      <xs:enumeration value="uint16_t *"/>
+      <xs:enumeration value="uint32_t *"/>
+      <xs:enumeration value="uint64_t *"/>
+      <xs:enumeration value="int8_t *"/>
+      <xs:enumeration value="int16_t *"/>
+      <xs:enumeration value="int32_t *"/>
+      <xs:enumeration value="int64_t *"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels -->
+  <xs:simpleType name="nvicPrioBitsType">
+    <xs:restriction base="xs:integer">
+      <xs:minInclusive value="2"/>
+      <xs:maxInclusive value="8"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="identifierType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="enumerationNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[_A-Za-z0-9]*"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format -->
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- accessType specfies the pre-defined tokens for the available accesses -->
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- readAction type specifies the pre-defined tokens for read side effects -->
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+  <!-- addressBlockType specifies the elements to describe an address block -->
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="stringType"/>
+      <xs:element name="description" type="xs:string" minOccurs="0"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- register properties group specifies register size, access permission and reset value 
+       this is used in multiple locations. Settings are inherited downstream. -->  
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+       by specifying the least significant and the most significant bit position -->
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
+       by specifying the least significant bit position and the bitWidth of the field -->
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+  <!-- dimElementGroup specifies the number of array elements (dim), the address offset
+       between to consecutive array elements and an a comma seperated list of strings 
+       being used for identifying each element in the array -->
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:complexType name="cpuType">
+    <xs:sequence>
+      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->
+      <xs:element name="name" type="cpuNameType"/>
+      <!-- V1.1: ARM defined revision of the cpu -->
+      <xs:element name="revision" type="revisionType"/>
+      <!-- V1.1: Endian specifies the endianess of the processor/device -->
+      <xs:element name="endian" type="endianType"/>
+      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
+      <xs:element name="mpuPresent" type="xs:boolean"/>
+      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->
+      <xs:element name="fpuPresent" type="xs:boolean"/>
+      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller
+                   for defining the priority level = # priority levels -->
+      <xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/>
+      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device 
+                   instead of the ARM specified SysTickTimer -->
+      <xs:element name="vendorSystickConfig" type="xs:boolean"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="enumeratedValuesType">
+    <xs:sequence>
+      <!-- name specfies a reference to this enumeratedValues section for reuse purposes
+           this name does not appear in the System Viewer nor the Header File. -->
+      <xs:element name="name" type="enumerationNameType" minOccurs="0"/>
+      <!-- usage specifies whether this enumeration is to be used for read or write or 
+                                                       (read and write) accesses -->
+      <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+      <!-- enumeratedValue derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+        <xs:complexType>
+          <xs:sequence>
+            <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->
+            <xs:element name="name" type="enumerationNameType"/>
+            <!-- description contains the details about the semantics/behavior specified by this value -->
+            <xs:element name="description" type="stringType" minOccurs="0"/>
+            <xs:choice>
+              <xs:element name="value" type="enumeratedValueDataType"/>
+              <!-- isDefault specifies the name and description for all values that are not
+                   specifically described individually -->
+              <xs:element name="isDefault" type="xs:boolean"/>
+            </xs:choice>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldType">
+    <xs:sequence>
+      <!-- name specifies a field's name. The System Viewer and the device header file will
+           use the name of the field as identifier -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- description contains reference manual level information about the function and 
+           options of a field -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- alternative specifications of the bit position of the field within the register -->
+      <xs:choice minOccurs="1" maxOccurs="1">
+        <!-- bit field described by lsb followed by msb tag -->
+        <xs:group ref="bitRangeLsbMsbStyle"/>
+        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->
+        <xs:group ref="bitRangeOffsetWidthStyle"/>
+        <!-- bit field described by [<msb>:<lsb>] -->
+        <xs:element name="bitRange" type="bitRangeType"/>
+      </xs:choice>
+      <!-- access describes the predefined permissions for the field. -->
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <!-- predefined description of write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeContstraint specifies the subrange of allowed values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAction specifies the read side effects. -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- enumeratedValues derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValues" type="enumeratedValuesType" minOccurs="0" maxOccurs="2">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldsType">
+    <xs:sequence>
+      <!-- field derivedFrom=<identifierType> -->
+      <xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="registerType">
+    <xs:sequence>
+      <xs:group    ref="dimElementGroup" minOccurs="0"/>
+      <!-- name specifies the name of the register. The register name is used by System Viewer and
+                                     device header file generator to represent a register -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.
+                                     The use of this tag is discouraged because it does not allow consistency between
+                                     the System View and the device header file. -->
+      <xs:element name="displayName" type="stringType" minOccurs="0"/>
+      <!-- description contains a reference manual level description about the register and it's purpose -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <xs:choice>
+        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
+                                       This is useful if a register has a different description per mode but a single name -->
+        <xs:element name="alternateGroup" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is
+                                       already fully described. In this case the register name must be unique within the peripheral -->
+        <xs:element name="alternateRegister" type="identifierType" minOccurs="0"/>
+      </xs:choice>
+      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                                     reset value. These default values are inherited to all fields contained in this register -->
+      <xs:group    ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->
+      <xs:element name="dataType" type="dataTypeType" minOccurs="0"/>
+      <!-- modifiedWriteValues specifies the write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeConstraint specifies the subset of allowed write values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAcction specifies the read side effects -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- fields section contains all fields that belong to this register -->
+      <xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->
+  <xs:complexType name="clusterType">
+    <xs:sequence>
+      <xs:group   ref="dimElementGroup" minOccurs="0"/>
+      <xs:element name="name" type="identifierType"/>
+      <xs:element name="description" type="xs:string"/>
+      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
+                 already fully described. In this case the cluster name must be unique within the peripheral -->
+      <xs:element name="alternateCluster" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef
+                 used in the device header generation instead of the cluster name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="register" type="registerType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- the registers section can have an arbitrary list of cluster and register sections -->
+  <xs:complexType name="registersType">
+    <xs:choice minOccurs="1" maxOccurs="unbounded">
+      <xs:element name="cluster" type="clusterType"/>
+      <xs:element name="register" type="registerType"/>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="peripheralType">
+    <xs:sequence>
+      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->
+      <xs:element name="name" type="xs:Name"/>
+      <!-- version specifies the version of the peripheral descriptions -->
+      <xs:element name="version" type="stringType" minOccurs="0"/>
+      <!-- description provides a high level functional description of the peripheral -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
+           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->
+      <xs:element name="alternatePeripheral" type="identifierType" minOccurs="0"/>
+      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
+      <xs:element name="groupName" type="xs:Name" minOccurs="0"/>
+      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
+      <xs:element name="prependToName" type="identifierType" minOccurs="0"/>
+      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+                         file will sho the registers in a C-Struct of the peripheral without the postfix -->
+      <xs:element name="appendToName" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
+                         used in the device header generation instead of the peripheral name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+                         if the condition is evaluated to true, the peripheral display will be disabled -->
+      <xs:element name="disableCondition" type="stringType" minOccurs="0"/>
+      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
+                         to specify a baseAddress. -->
+      <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                         reset value. These default values are inherited to all registers contained in this peripheral -->
+      <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
+                         at least one address block -->
+      <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
+      <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
+                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        registers section is not allowed -->
+      <xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+  
+  <!-- ==================================================== -->
+  <!-- The top level element of a description is the device -->
+  <!-- ==================================================== -->
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <!-- V1.1: Vendor Name -->
+        <xs:element name="vendor" type="stringType" minOccurs="0"/>
+        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->
+        <xs:element name="vendorID" type="identifierType" minOccurs="0"/>
+        <!-- name specifies the device name being described -->
+        <xs:element name="name" type="identifierType"/>
+        <!-- V1.1: series specifies the device series or family name -->
+        <xs:element name="series" type="stringType" minOccurs="0"/>
+        <!-- version specifies the version of the device description -->
+        <xs:element name="version" type="stringType"/>
+        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->
+        <xs:element name="description" type="stringType"/>
+        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->
+        <xs:element name="licenseText" type="stringType" minOccurs="0"/>
+        <!-- V1.1: cpu specifies the details of the processor included in the device -->
+        <xs:element name="cpu" type="cpuType" minOccurs="0"/>
+        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
+             This tag is used by the header file generator for customizing the include statement referencing the
+             CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
+             In cases a device series shares a single system header file, the name of the series shall be used 
+             instead of the individual device name. -->
+        <xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
+             generated device header file -->
+        <xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/>
+        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
+             This sets the maximum size of a single register that can be defined for an address space -->
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+             reset value -->
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+
+        <!-- peripherals is containing all peripherals -->
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+
+        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.1"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__schema__gr.html b/CMSIS/Documentation/SVD/html/group__schema__gr.html
new file mode 100644
index 0000000000..5715fe071b
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__schema__gr.html
@@ -0,0 +1,368 @@
+
+
+
+
+CMSIS-SVD Schema File Ver. 1.0
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
CMSIS-SVD Schema File Ver. 1.0
  

+

+

+
<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @date: 07.12.2011
+  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
+  
+  <xs:simpleType name="registerNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="xs:string"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <xs:element name="name" type="xs:string"/>
+        <xs:element name="version" type="xs:string"/>
+        <xs:element name="description" type="xs:string"/>
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+                <xs:complexType>
+                  <xs:sequence>
+                    <xs:element name="name" type="xs:Name"/>
+                    <xs:element name="version" type="xs:string" minOccurs="0"/>
+                    <xs:element name="description" type="xs:string" minOccurs="0"/>
+                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
+                    <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+                    <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
+                      <xs:complexType>
+                        <xs:sequence>
+                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+                            <xs:complexType>
+                              <xs:sequence>
+                                <xs:group ref="dimElementGroup" minOccurs="0"/>
+                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+                                <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
+                                  <xs:complexType>
+                                    <xs:sequence>
+                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+                                      <xs:complexType>
+                                        <xs:sequence>
+                                          <xs:element name="name" type="xs:string"/>
+                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                          <xs:choice>
+                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+                                          </xs:choice>
+                                          <xs:element name="access" type="accessType" minOccurs="0"/>
+                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+                                            <xs:complexType>
+                                              <xs:sequence>
+                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
+                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+                                                  <xs:complexType>
+                                                    <xs:sequence>
+                                                      <xs:element name="name" type="xs:string"/>
+                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                                      <xs:choice>
+                                                        <xs:element name="value" type="enumeratedValueDataType"/>
+                                                        <xs:element name="isDefault" type="xs:boolean"/>
+                                                      </xs:choice>
+                                                    </xs:sequence>
+                                                  </xs:complexType>
+                                                </xs:element>
+                                              </xs:sequence>
+                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                            </xs:complexType>
+                                          </xs:element>
+                                        </xs:sequence>
+                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                      </xs:complexType>
+                                    </xs:element>
+                                    </xs:sequence>
+                                  </xs:complexType>
+                                </xs:element>
+                              </xs:sequence>
+                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                            </xs:complexType>
+                          </xs:element>
+                        </xs:sequence>
+                      </xs:complexType>
+                    </xs:element>
+                  </xs:sequence>
+                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                </xs:complexType>
+              </xs:element>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html b/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html
new file mode 100644
index 0000000000..0c91e2f6bc
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html
@@ -0,0 +1,107 @@
+
+
+
+
+SVD Extension in Version 1.1
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
SVD Extension in Version 1.1
  

+

+

+
+
+
+
+
+
+
+

+Modules
 Extensions to the Device Section
 CPU Section (New)
 Extensions to the Peripheral Section
 Cluster Level (New)
 Extensions to the Register Section

+
Description

+
From a schema perspective, CMSIS-SVD Version 1.1 is fully backward compatible to version 1.0. Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. It is expected that over time all CMSIS-SVD descriptions will comply with version 1.1. Version 1.1 has not been finalized yet and is therefore currently marked draft. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd___format__gr.html b/CMSIS/Documentation/SVD/html/group__svd___format__gr.html
new file mode 100644
index 0000000000..f1a07149ac
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd___format__gr.html
@@ -0,0 +1,139 @@
+
+
+
+
+SVD File Schema Levels
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+Modules  

+  

+
SVD File Schema Levels
  

+

+

+
+
+
+
+
+
+
+

+Modules
 Device Level
 Peripherals Level
 Registers Level
 Fields Level
 Enumerated Values Level

+
Description

+
This section specifies the SVD file format Version 1.0. Each subsection defines one level of hierarchy and lists all mandatory and optional language elements as well as their type. A brief example description snippet demonstrates the usage of the elements. 

+
Note:
    
+
  • The sequence of elements in CMSIS-SVD is mandatory.
    • 
+
  • Optional elements are highlighted in green.
    • 
+
  • Mandatory elements are highlighted in blue. Optional sections can contain mandatory elements, which must be specified when the optional section is used. In this case the mandatory elements are also highlighted in blue.
    • 
+

+

+

+Names

+
All name tags must comply with the ANSI C identifier naming restrictions (identifierType). In particular they must not contain any spaces or special characters. This is necessary to support the generation of device header files thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS compliant target software.

+

+Constants

+
Number constants shall be entered in hexadecimal, decimal, or binary format. 

+
    
+
  • The Hexadecimal format is indicated by a leading "0x". 
    • 
+
  • The Binary format is indicated by a leading "#". 
    • 
+
  • All other formats are interpreted as decimal numbers. 
    • 
+
  • The value tag in enumeratedValue accepts do not care bits represented by "x".
    • 
+

+

+Comments

+
Comments have the standard XML format. 

+
    
+
  • Start a comment with "<!--". 
    • 
+
  • End a comment with "-->".
    • 
+

+

+Empty Tags

+
    
+
  • Single tags are not supported (for example, <name>).
    • 
+
  • The tag content must not consist of an empty string (instead, omit optional tags).
    • 
+

+
Remarks:
The CMSIS-SVD Schema File Ver. 1.0 and schema_1_1_gr are provided alongside this document. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html b/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html
new file mode 100644
index 0000000000..4542279aa1
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html
@@ -0,0 +1,177 @@
+
+
+
+
+Device Level
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Device Level
  

+
SVD File Schema Levels

+

+
The element device provides the outermost frame of the description.

+
    
+
  • Only one device section is allowed per file. All other elements like peripherals, registers, fields, enumerated values, and vendor extensions are described within this scope.
    • 
+
  • A device contains one or more peripherals.
    • 
+
  • Optional elements like size, access, resetValue, and resetMask defined on this level are used as default values throughout the device description, unless they get redefined at a lower level. 
    • 
+

+

+
+<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
    <name>identifierType</name>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>
+    <width>scaledNonNegativeInteger</width>
+
+    <!-- registerPropertiesGroup -->
+    <size>scaledNonNegativeInteger</size>
+    <access>accessType</access>
+    <resetValue>scaledNonNegativeInteger</resetValue>
+    <resetMask>scaledNonNegativeInteger</resetMask>
+    <!-- end of registerPropertiesGroup -->
+
+    <peripherals>
+        ...
+    </peripherals>
+
+    <vendorExtensions>
+        ...
+    </vendorExtensions>
</device>
+
+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
Attribute Name Description Type Occurrence  
xmlns:xs Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: "http://www.w3.org/2001/XMLSchema-instance". xs:decimal 1..1  
xmlns:xs Specifies the file path and file name of the CMSIS-SVD Schema. For example, CMSIS-SVD_Schema_1_0.xsd. xs:string 1..1  
schemaVersion Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.0).  xs:decimal 1..1  
Element Name Description Type Occurrence  
name The name string is used to identify the device or device series. Device names are required to be unique. xs:string  1..1   
version  The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version.   xs:string  1..1  
description  String for describing main features of a device (for example CPU, clock frequency, peripheral overview). xs:string  1..1   
addressUnitBits  Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable).  scaledNonNegativeInteger  1..1   
width  Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. scaledNonNegativeInteger  1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1   
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
peripherals  Next level of description. see Peripherals Level for details.   1..1   
vendorExtensions  The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section.  xs:anyType (restriction)  0..1   

+

+Example:

+
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+  <name>ARM_Cortex_M3</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0</resetValue>
+  <resetMask>0xffffffff</resetMask>
+
+  <peripherals>
+    ...
+  </peripherals>
+</device>
+
The device description above is at version 0.1 and uniquely identifies the device by the name "ARM_Cortex_M3". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html b/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html
new file mode 100644
index 0000000000..0908c1b44d
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html
@@ -0,0 +1,197 @@
+
+
+
+
+Enumerated Values Level
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Enumerated Values Level
  

+
SVD File Schema Levels

+

+
Enumerated Values
 The concept of enumerated values creates a map between unsigned integers and an identifier string. In addition, a description string can be associated with each entry in the map.

+
+        0 <-> disabled -> "the clock source clk0 is turned off"
+        1 <-> enabled  -> "the clock source clk1 is running"
+	
 This information is used for generating an enum in the device header file. The debugger may use this information to display the identifier string as well as the description. Just like symbolic constants making source code more readable, the system view in the debugger becomes more instructive. The detailed description can provide reference manual level details within the debugger.

+

+
+
+<enumeratedValues derivedFrom="xs:Name">
+
+    <name>identifierType</name>
+    <usage>usageType</usage>
+
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+    ...
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+</enumeratedValues>
+
+

+
+
+
+
+
+
+
+
+
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+
+
Attribute Name Description Type Occurrence  
derivedFrom Makes a copy from a previously defined enumeratedValues section. No modifications are allowed. An enumeratedValues entry is referenced by its name. If the name is not unique throughout the description, it needs to be further qualified by specifying the associated field, register, and peripheral as required. For example: 
+	field:                           clk.dis_en_enum
+	register + field:                ctrl.clk.dis_en_enum
+	peripheral + register + field:   timer0.ctrl.clk.dis_en_enum
+
  		xs:Name 0..1  
Element Name Description Type Occurrence  
name Identifier for the whole enumeration section. xs:Name 0..1  
usage Possible values are read, write, or read-write. This allows specifying two different enumerated values depending whether it is to be used for a read or a write access. If not specified, the default value read-write is used. enumUsageType 0..1  
enumeratedValue Describes a single entry in the enumeration. The number of required items depends on the bit width of the associated field. See section below for details.   1..*  

+
Enumerated Value
 
An enumeratedValue defines a map between an unsigned integer and a human readable string. 

+ 
+
+<enumeratedValue>
    <name>identifierType</name>
+    <description>xs:string</description>
    <choice>
+        <value>scaledNonNegativeInteger</value>
+        <isDefault>xs:boolean</isDefault>
+    </choice>
</enumeratedValue>
+
+

+
+
+
+
+
+
+
+
+
+
+
+
+
Element Name Description Type Occurrence  
name String describing the semantics of the value. Can be displayed instead of the value. identifierType 0..1  
description Extended string describing the value. xs:string 0..1  
choice of 1..1  
value Defines the constant of the bit-field that the name corresponds to. scaledNonNegativeInteger 0..1  
isDefault Defines the name and description for all other values that are not listed explicitly. xs:boolean 0..1  

+

+Example:

+
<enumeratedValues>
+
+    <name>TimerIntSelect</name>
+    <usage>read-write</usage>
+
+    <enumeratedValue>
+        <name>disabled</name>
+        <description>The clock source clk0 is turned off.</description>
+        <value>0</value>
+    </enumeratedValue>
+
+    <enumeratedValue>
+        <name>reserved</name>
+        <description>Reserved values. Do not use.</description>
+        <isDefault>true</isDefault>
+    </enumeratedValue>
+
+</enumeratedValues>
+
 
<enumeratedValues>
+
+    <name>TimerIntSelect</name>
+    <usage>read-write</usage>
+
+    <enumeratedValue>
+        <name>disabled</name>
+        <description>Timer does not generate interrupts.</description>
+        <value>0</value>
+    </enumeratedValue>
+
+    <enumeratedValue>
+        <name>enabled</name>
+        <description>Timer generates interrupts.</description>
+        <isDefault>true</isDefault>
+    </enumeratedValue>
+
+</enumeratedValues>
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html b/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html
new file mode 100644
index 0000000000..342960dec7
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html
@@ -0,0 +1,215 @@
+
+
+
+
+Fields Level
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Fields Level
  

+
SVD File Schema Levels

+

+
All fields of a register are enclosed between the <fields> opening and closing tags

+
A bit-field has a name that is unique within the register. The position and size within the register is either described by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or the lsb and the bit-width of the field. A field may define an enumeratedValue in order to make the display more intuitive to read. 

+ 

+<fields>
    <field derivedFrom="xs:Name">
        <name>xs:Name</name>
+        <description>xs:string</description>
        <choice>
+             <!-- bitRangeLsbMsbStyle --> 
+            <bitOffset>scaledNonNegativeInteger<bitOffset>
+            <bitWidth>scaledNonNegativeInteger</bitWidth>
+            or
+             <!-- bitRangeOffsetWidthStyle --> 
+            <lsb>scaledNonNegativeInteger</lsb> 
+            <msb>scaledNonNegativeInteger</msb>
+            or
+             <!-- bitRangePattern --> 
+            <bitRange>pattern</bitRange>
+        </choice>
+        
+        <access>accessType</access>
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
        <enumeratedValues>
+            ...
+        </enumeratedValues>
    </field>
+    ...
+    <field>
+       ...
+    </field>
+    
+<fields>
+
+

+
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+
Attribute Name Description Type Occurrence  
derivedFrom The field is cloned from a previously defined field with a unique name. xs:Name 0..1  
Element Name Description Type Occurrence  
name Name string used to identify the field. Field names must be unique within a register. xs:string  1..1   
description String describing the details of the register.  xs:string  0..1   
Choice of Three options exist to describe the field's bit-range. The options are to be used mutually exclusive: 1..1  
1. bitRangeLsbMsbStyle   
bitOffset Value defining the position of the least significant bit of the field within the register it belongs to. scaledNonNegativeInteger 1..1   
bitWidth  Value defining the bit-width of the bitfield within the register it belongs to.  scaledNonNegativeInteger 0..1   
2. bitRangeOffsetWidthStyle  
lsb  Value defining the bit position of the least significant bit within the register it belongs to. scaledNonNegativeInteger 1..1   
msb  Value defining the bit position of the most significant bit within the register it belongs to.  scaledNonNegativeInteger 1..1  
3. bitRangePattern  
bitRange  A string in the format: "[<msb>:<lsb>]" bitRangeType  0..1   
access Predefined strings can be used to define the allowed access types for this field: read-only, write-only, read-write,  writeOnce, and read-writeOnce. Can be omitted if it matches the access permission set for the parent register.  accessType 0..1   
modifiedWriteValues Describe the manipulation of data written to a field. If not specified, the value written to the field is the value stored in the field. The other options are bitwise operations: 
    
+
  • oneToClear: write data bit of one shall clear (set to zero) the corresponding bit in the field. 
    • 
+
  • oneToSet: write data bit of one shall set (set to one) the corresponding bit in the field. 
    • 
+
  • oneToToggle: write data bit of one shall toggle (invert) the corresponding bit in the field. 
    • 
+
  • zeroToClear: write data bit of zero shall clear (set to zero) the corresponding bit in the field. 
    • 
+
  • zeroToSet: write data bit of zero shall set (set to one) the corresponding bit in the field. 
    • 
+
  • zeroToToggle: write data bit of zero shall toggle (invert) the corresponding bit in the field. 
    • 
+
  • clear: after a write operation all bits in the field are cleared (set to zero). 
    • 
+
  • set: after a write operation all bits in the field are set (set to one). 
    • 
+
  • modify: after a write operation all bit in the field may be modified (default).  
    • 
+

+		modifiedWriteValuesType 0..1   
writeConstraint Three options exist to set write-constraints: 0..1  
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1  
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1  
3. range Consists of the following two elements:   0..1  
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1  
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1  
readAction If set, it specifies the side effect following a read operation. If not set, the field is not modified after a read. The defined side effects are: 
    
+
  • clear: The field is cleared (set to zero) following a read operation. 
    • 
+
  • set: The field is set (set to ones) following a read operation. 
    • 
+
  • modify: The field is modified in some way after a read operation. 
    • 
+
  • modifyExternal: One or more dependent resources other than the current field are immediately affected by a read operation (it is recommended that the field description specifies these dependencies). Debuggers are not expected to read this field location unless explicitly instructed by the user. 
    • 
+

+		readActionType 0..1 register  
enumeratedValues Next lower level of description. See section Enumerated Values Level for details.   0..2  

+

+Example:

+
...
+<field>
+  <name>TimerCtrl0_IntSel</name>
+  <description>Select interrupt line that is triggered by timer overflow.</description>
+  <bitOffset>1</bitOffset>
+  <bitWidth>3</bitWidth>
+  <access>read-write</access>
+  <resetValue>0x0</resetValue>
+  <modifiedWriteValues>oneToSet</modifiedWriteValues>
+  <writeConstraint>
+    <range>
+      <minimum>0</minimum>
+      <maximum>5</maximum>
+    </range>
+  </writeConstraint>
+  <readAction>clear</readAction>
+ 
+  <enumeratedValues>
+    ...
+  </enumeratedValues>
+</field>
+...
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html b/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html
new file mode 100644
index 0000000000..40bf80f150
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html
@@ -0,0 +1,223 @@
+
+
+
+
+Peripherals Level
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Peripherals Level
  

+
SVD File Schema Levels

+

+
All peripherals of a device are enclosed within the tag <peripherals>. At least one peripheral has to be defined. Each peripheral is enclosed in the tag <peripheral>.

+
    
+
  • Each peripheral describes all registers belonging to that peripheral.
    • 
+
  • The address range allocated by a peripheral is defined through one or more address blocks.
    • 
+
  • An address block and register addresses are specified relative to the base address of a peripheral. The address block information can be used for constructing a memory map for the device peripherals.
    • 
+

+
Remarks:
The memory map does not contain any information about RAM, ROM, or FLASH memory.

+

+
+ <peripherals> 
    <peripheral derivedFrom="<em>identifierType</em>">
        <name>identifierType</name>
+        <version>xs:string</version>
+        <description>xs:string</description>
+    
+        <groupName>identifierType</groupName>
+        <prependToName>identifierType</prependToName>
+        <appendToName>identifierType</appendToName>
+        <disableCondition>xs:string</disableCondition>
+    
+        <baseAddress>scaledNonNegativeInteger</baseAddress>
+    
+         <!-- registerPropertiesGroup -->
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+         <!-- end of registerPropertiesGroup -->
+    
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+        ...
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+    
+        <interrupt>
+            <name>identifierType</name>
+            <value>scaledNonNegativeInteger</value>
+        </interrupt>
        <registers>
+            ...
+        </registers>
    </peripheral>
+    ...
+    <peripheral>
+       ...
+    </peripheral>
+    
+</peripherals>
+
+

+
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Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of a peripheral from which this peripheral will be derived. Values are inherit. Elements specified underneath will override inherited values.  xs:Name  0..1  
Element Name Description Type Occurrence  
name  The name string is used to identify the peripheral. Peripheral names are required to be unique for a device. The name needs to be an ANSI C identifier to allow header file generation.  xs:Name  1..1   
version  The string specifies the version of this peripheral description.  xs:string  0..1   
description  The string provides an overview of the purpose and functionality of the peripheral. xs:string  0..1   
groupName  xs:string  0..1   
prependToName  All register names of this peripheral have their names prefixed with this string. xs:string  0..1   
appendToName  All register names of this peripheral have their names suffixed with this string. xs:string  0..1   
disableCondition  Is a C-language compliant logical expression returning a TRUE or FALSE result. If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed. 

+ 

+ Only constants and references to other registers contained in the description are allowed: <peripheral>-><register>-><field>, for example, (System->ClockControl->apbEnable == 0). The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |]. 
Attention:
Use this feature only in cases where accesses from the debugger to registers of un-clocked peripherals result in severe debugging failures. SVD is intended to provide static information and does not include any run-time computation or functions. Such capabilities can be added by the tools, and is beyond the scope of this description language. 

+		xs:string  0..1   
baseAddress  Lowest address reserved or used by the peripheral. scaledNonNegativeInteger  1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1  
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
addressBlock Specifies an address range uniquely mapped to this peripheral. A peripheral must have at least one address block, but may allocate multiple distinct address ranges. If a peripheral is derived form another peripheral, the addressBlock is not mandatory.  addressBlockType 1..*  
offset Specifies the start address of an address block relative to the peripheral baseAddress.  scaledNonNegativeInteger  1..1  
size Specifies the number of addressUnitBits being covered by this address block. The end address of an address block results from the sum of baseAddress, offset, and (size - 1).  scaledNonNegativeInteger  1..1  
usage The following predefined values can be used: registers,  buffer, or reserved.  scaledNonNegativeInteger  1..1  
interrupt  A peripheral can have multiple associated interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers. interruptType  0..*   
name  The string represents the interrupt name. XS:string  1..1   
value  Is the enumeration index value associated to the interrupt. xs:integer  1..1   
registers  See Registers Level for details.    0..1   

+

+Example:

+
...
+<peripheral>
+  <name>Timer0</name>
+  <version>1.0.32</version>
+  <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+  <baseAddress>0x40000000</baseAddress>
+  <addressBlock>
+    <offset>0x0</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+  </addressBlock>
+  <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+  <registers>
+    ...
+  </registers>
+</peripheral>
+
+<peripheral derivedFrom="Timer0">
+  <name>Timer1</name>
+  <baseAddress>0x40000400</baseAddress>
+</peripheral>
+...
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html b/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html
new file mode 100644
index 0000000000..4a26175c51
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html
@@ -0,0 +1,234 @@
+
+
+
+
+Registers Level
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Registers Level
  

+
SVD File Schema Levels

+

+
All registers of a peripheral are enclosed between the <registers> opening and closing tags.

+
The description of registers is the most essential part of the SVD description. The register's name, detailed description, and the address-offset relative to the peripheral base address are the mandatory elements. If the size, access, reset value, and reset mask have not been specified on the device or peripheral level, or if the default values need to be redefined locally, these fields become mandatory.

+
A register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics. In schema-terms the fields section is optional, however, from a specification perspective, fields are mandatory when they are described in the device documentation.

+
The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index specific substring define in <dimIndex>. The <dimIncrement> specifies the address offset between two registers.

+

+
+<registers> 
    <register derivedFrom=registerNameType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>xs:string</dimIndex>
+        <!-- end of dimElementGroup --> 
+   
+        <name>identifierType</name>
+    
+        <displayName>xs:string</displayName>
+    
+        <description>xs:string</description>
+    
+        <alternateGroup>xs:Name</alternateGroup>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
+    
+        <!-- registerPropertiesGroup --> 
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+        <!-- end of registerPropertiesGroup --> 
+    
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
        <fields>
+            ...
+        </fields>
+    
+    </register>
+    ...
+    <register>
+        ...
+    </register>
+    
+<registers> 
+

+
+
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Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of the register from which to inherit the data. Elements being specified underneath will override the inherited values. 

+Remarks: When deriving a register, it is mandatory to specify at least the name, the description, and the addressOffset. 		xs:Name 0..1  
Element Name Description Type Occurrence  
See dimElementGroup for details.  
dimIncrement The value defines the number of elements in an array of registers.  scaledNonNegativeInteger  1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger  1..1   
dimIndex Specifies the substrings that replaces the s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register.  dimIndexType  0..1   
name Name string used to identify the register. Register names are required to be unique within the scope of a peripheral.  registerNameType  1..1   
displayName When specified, the string is being used by a graphical frontend to visualize the register. Otherwise the name element is displayed. The displayName may contain special characters and white spaces. The place holder s can be used and is replaced by the dimIndex substring.  xs:string  0..1   
description String describing the details of the register. xs:string  0..1   
alternateGroup  Specifies a group name associated with all alternate register that have the same name. At the same time, it indicates that there is a register definition allocating the same absolute address in the address space. xs:Name  0..1   
addressOffset Value defining the address of the register relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1   
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
modifiedWriteValues Element to describe the manipulation of data written to a register. If not specified, the value written to the field is the value stored in the field. The other options define bitwise operations: 
    
+
  • oneToClear: write data bits of one shall clear (set to zero) the corresponding bit in the register. 
    • 
+
  • oneToSet: write data bits of one shall set (set to one) the corresponding bit in the register. 
    • 
+
  • oneToToggle: write data bits of one shall toggle (invert) the corresponding bit in the register. 
    • 
+
  • zeroToClear: write data bits of zero shall clear (set to zero) the corresponding bit in the register. 
    • 
+
  • zeroToSet: write data bits of zero shall set (set to one) the corresponding bit in the register. 
    • 
+
  • zeroToToggle: write data bits of zero shall toggle (invert) the corresponding bit in the register. 
    • 
+
  • clear: after a write operation all bits in the field are cleared (set to zero). 
    • 
+
  • set: after a write operation all bits in the field are set (set to one). 
    • 
+
  • modify: after a write operation all bit in the field may be modified (default).  
    • 
+

+		modifiedWriteValuesType 0..1   
writeConstraint Three options exist to set write-constraints: 0..1  
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1  
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1  
3. range Consists of the following two elements:   0..1  
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1  
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1  
readAction  If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are: 
    
+
  • clear: The register is cleared (set to zero) following a read operation. 
    • 
+
  • set: The register is set (set to ones) following a read operation. 
    • 
+
  • modify: The register is modified in some way after a read operation. 
    • 
+
  • modifyExternal: One or more dependent resources other than the current register are immediately affected by a read operation (it is recommended that the register description specifies these dependencies). Debuggers are not expected to read this register location unless explicitly instructed by the user. 
    • 
+

+		readActionType 
0..1  

+

+
fields  Next lower level of description (see Fields Level for details). Not all registers are further divided into fields, therefore, this level is optional. In case a register is subdivided into bit fields, it should be reflected in the description. The device header file can only contain bit access macros and bit-field structures if this information is contained in the description.   0..1   

+

+Example:

+
...
+<register>
+  <name>TimerCtrl0</name>
+  <description>Timer Control Register</description>
+  <addressOffset>0x0</addressOffset>
+  <access>read-write</access>
+  <resetValue>0x00008001</resetValue>
+  <resetMask>0x0000ffff</resetMask>
+  <size>32</size>
+  <fields>
+    ...
+  </fields>
+</register>
+
+<register derivedFrom="TimerCtrl0">
+  <name>TimerCtrl1</name>
+  <description>Derived Timer</description>
+  <addressOffset>0x4</addressOffset>
+</register>
+...
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/index.html b/CMSIS/Documentation/SVD/html/index.html
new file mode 100644
index 0000000000..813b480d97
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/index.html
@@ -0,0 +1,153 @@
+
+
+
+
+System View Description
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
System View Description 
  

+

+

+
This chapter contains the introduction and specification of the CMSIS System View Description format (CMSIS-SVD). The introduction section outlines the objectives and benefits CMSIS-SVD.

+
Introduction

+
CMSIS-SVD formalizes the description of the programmer's view for the system contained in ARM Cortex-M processor-based microcontrollers, in particular the memory mapped registers of the peripherals. The detail contained in system view descriptions is comparable to what is found in device reference manuals published by silicon vendors. The information ranges from a high level functional description of a peripheral all the way down to the definition and purpose of an individual bit field in a memory mapped register. CMSIS-SVD files are developed and maintained by the silicon vendors. Silicon vendors manage their descriptions in a central, web-based Device Database and the CMSIS-SVD files are downloadable via a public web interface once they have been released by the silicon vendor. Tool vendors use these descriptions for providing device-specific debug views of peripherals in their debugger. Last but not least CMSIS compliant device header files are generated from CMSIS-SVD files.

+
CMSIS-SVD Benefits

+
    
+
  • The benefits for the Software Developer:
      
+
    • Consistency between device header file and what is being displayed by the debugger.
      • 
+
    • Detailed information about peripherals, registers, fields, and bit values from within the debugger, without the need to reference device documentation.
      • 
+
    • Public access via a web interface to new and updated descriptions as they become available from silicon vendors.
      • 
+
    • Improved software development efficiency.
      • 
+
    
+
    • 
+

+
    
+
  • The benefits for the Silicon Vendor:
      
+
    • A tool vendor independent file format enables early device support by a wide range of toolchains with limited effort.
      • 
+
    • The XML-based format helps ease the integration into in-house design flows.
      • 
+
    • Automated generation of CMSIS compliant device header files.
      • 
+
    • Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance via the web-based Device Database.
      • 
+
    
+
    • 
+

+
    
+
  • The benefits for the Tool Vendor:
      
+
    • Unified file format across silicon vendors helps the efficiency of supporting a wide range of new devices in a timely manner.
      • 
+
    • Silicon vendors provide early review access to individuals ahead of the publishing date.
      • 
+
    • Updated descriptions are available over the web simplifying the maintenance of device support.
      • 
+
    
+
    • 
+

+
The Web Infrastructure

+

+CMSIS_SVD_WEB_DATABASE.png
+

+CMSIS-SVD Management Processes

+
 The diagram illustrates the management process steps for uploading, validating, reviewing, publishing, and downloading CMSIS-SVD files.

+
    
+
  • Managing Files: A CMSIS-SVD file is uploaded by a silicon vendor via the web interface (Device Database). The system performs a check against the CMSIS-SVD Schema and runs the SVDConv consistency checker. Only if both checks have been successful the file will be stored in the SVD Storage. Files can be added, replaced and deleted.
    • 
+

+
    
+
  • Managing Devices: The silicon vendor creates an entry for each of his devices in the database by defining a name and associating it with a CMSIS-SVD file from the SVD Storage. The publishing date set forth for a device is used by the system to determine when this device becomes visible in the public device database. Prior to the publishing date, the silicon vendor can grant review access to individuals for an individual device. Reviewers get notified by e-mail about a device being made available for review.
    • 
+

+
    
+
  • Public Download: Public access to the silicon vendor specific CMSIS-SVD download pages is provided from cmsis.arm.com or www.arm.com/cmsis. Select the CMSIS-SVD tab and select the Silicon Vendor of interest from the list. For the public download of the CMSIS-SVD files of published devices it is mandatory to:
      
+
    • Be logged in on the ARM web site.
      • 
+
    • Have accepted a silicon vendor specific End Users License Agreement (EULA).
      • 
+
    
+
    • 
+

+
More information about the web infrastructure can be found in the CMSIS-SVD Web Interface User Guide

+
Language Outline

+
+
Language Specification

+
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/jquery.js b/CMSIS/Documentation/SVD/html/jquery.js
new file mode 100644
index 0000000000..c052173a89
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/CMSIS/Documentation/SVD/html/modules.html b/CMSIS/Documentation/SVD/html/modules.html
new file mode 100644
index 0000000000..cf331916d5
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/modules.html
@@ -0,0 +1,119 @@
+
+
+
+
+Reference
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Reference
  

+

+

+
Here is a list of all modules:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/nav_f.png b/CMSIS/Documentation/SVD/html/nav_f.png
new file mode 100644
index 0000000000..1b07a16207
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/nav_f.png differ
diff --git a/CMSIS/Documentation/SVD/html/nav_h.png b/CMSIS/Documentation/SVD/html/nav_h.png
new file mode 100644
index 0000000000..01f5fa6a59
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/nav_h.png differ
diff --git a/CMSIS/Documentation/SVD/html/navtree.css b/CMSIS/Documentation/SVD/html/navtree.css
new file mode 100644
index 0000000000..e46ffcd6e0
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/navtree.css
@@ -0,0 +1,123 @@
+#nav-tree .children_ul {
+  margin:0;
+  padding:4px;
+}
+
+#nav-tree ul {
+  list-style:none outside none;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree li {
+  white-space:nowrap;
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .plus {
+  margin:0px;
+}
+
+#nav-tree .selected {
+  background-image: url('tab_a.png');
+  background-repeat:repeat-x;
+  color: #fff;
+  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
+
+#nav-tree img {
+  margin:0px;
+  padding:0px;
+  border:0px;
+  vertical-align: middle;
+}
+
+#nav-tree a {
+  text-decoration:none;
+  padding:0px;
+  margin:0px;
+  outline:none;
+}
+
+#nav-tree .label {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .label a {
+  padding:2px;
+}
+
+#nav-tree .selected a {
+  text-decoration:none;
+  padding:2px;
+  margin:0px;
+  color:#fff;
+}
+
+#nav-tree .children_ul {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
+
+#nav-tree {
+  padding: 0px 0px;
+  background-color: #FAFAFF; 
+  font-size:14px;
+  overflow:auto;
+}
+
+#doc-content {
+  overflow:auto;
+  display:block;
+  padding:0px;
+  margin:0px;
+}
+
+#side-nav {
+  padding:0 6px 0 0;
+  margin: 0px;
+  display:block;
+  position: absolute;
+  left: 0px;
+  width: 300px;
+}
+
+.ui-resizable .ui-resizable-handle {
+  display:block;
+}
+
+.ui-resizable-e {
+  background:url("ftv2splitbar.png") repeat scroll right center transparent;
+  cursor:e-resize;
+  height:100%;
+  right:0;
+  top:0;
+  width:6px;
+}
+
+.ui-resizable-handle {
+  display:none;
+  font-size:0.1px;
+  position:absolute;
+  z-index:1;
+}
+
+#nav-tree-contents {
+  margin: 6px 0px 0px 0px;
+}
+
+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/navtree.js b/CMSIS/Documentation/SVD/html/navtree.js
new file mode 100644
index 0000000000..18ba9923d6
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/navtree.js
@@ -0,0 +1,285 @@
+var NAVTREE =
+[
+  [ "CMSIS-SVD", "index.html", [
+    [ "System View Description", "index.html", [
+      [ "CMSIS-SVD Web Interface User Guide", "svd_web_pg.html", [
+        [ "Public Download Area", "svd_web_public_pg.html", null ],
+        [ "Restricted Management Area", "svd_web_restricted_pg.html", null ]
+      ] ],
+      [ "SVD File Description", "svd__outline_pg.html", null ]
+    ] ],
+    [ "Usage and Description", "pages.html", [
+      [ "SVD File Validation", "svd_validate_file_pg.html", null ],
+      [ "SVD File Usage", "svd__usage_pg.html", null ],
+      [ "SVD File Example", "svd__example_pg.html", null ]
+    ] ],
+    [ "Reference", "modules.html", [
+      [ "SVD File Schema Levels", "group__svd___format__gr.html", [
+        [ "Device Level", "group__svd__xml__device__gr.html", null ],
+        [ "Peripherals Level", "group__svd__xml__peripherals__gr.html", null ],
+        [ "Registers Level", "group__svd__xml__registers__gr.html", null ],
+        [ "Fields Level", "group__svd__xml__fields__gr.html", null ],
+        [ "Enumerated Values Level", "group__svd__xml__enum__gr.html", null ]
+      ] ],
+      [ "Element Groups", "group__elem__type__gr.html", [
+        [ "dimElementGroup", "group__dim_element_group__gr.html", null ],
+        [ "registerPropertiesGroup", "group__register_properties_group__gr.html", null ]
+      ] ],
+      [ "SVD Extension in Version 1.1", "group__svd___format__1__1__gr.html", [
+        [ "Extensions to the Device Section", "group__device_section_extensions__gr.html", null ],
+        [ "CPU Section (New)", "group__cpu_section__gr.html", null ],
+        [ "Extensions to the Peripheral Section", "group__peripheral_section_extensions__gr.html", null ],
+        [ "Cluster Level (New)", "group__cluster_level__gr.html", null ],
+        [ "Extensions to the Register Section", "group__register_section_extensions__gr.html", null ]
+      ] ],
+      [ "CMSIS-SVD Schema File Ver. 1.0", "group__schema__gr.html", null ],
+      [ "CMSIS-SVD Schema File Ver. 1.1 (draft)", "group__schema__1__1__gr.html", null ]
+    ] ]
+  ] ]
+];
+
+function createIndent(o,domNode,node,level)
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+  if (node.parentNode && node.parentNode.parentNode)
+  {
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+  }
+  var imgNode = document.createElement("img");
+  if (level==0 && node.childrenData)
+  {
+    node.plus_img = imgNode;
+    node.expandToggle = document.createElement("a");
+    node.expandToggle.href = "javascript:void(0)";
+    node.expandToggle.onclick = function() 
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+      if (node.expanded) 
+      {
+        $(node.getChildrenUL()).slideUp("fast");
+        if (node.isLast)
+        {
+          node.plus_img.src = node.relpath+"ftv2plastnode.png";
+        }
+        else
+        {
+          node.plus_img.src = node.relpath+"ftv2pnode.png";
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+        node.expanded = false;
+      } 
+      else 
+      {
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+    }
+    node.expandToggle.appendChild(imgNode);
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+  {
+    if (node.isLast)
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2plastnode.png";
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+      else
+      {
+        imgNode.src = node.relpath+"ftv2lastnode.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+    else
+    {
+      if (node.childrenData)
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+        imgNode.src = node.relpath+"ftv2node.png";
+        domNode.appendChild(imgNode);
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+  node.li = document.createElement("li");
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+  node.itemDiv = document.createElement("div");
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+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
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+  createIndent(o,node.itemDiv,node,0);
+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
+
+  var a = document.createElement("a");
+  node.labelSpan.appendChild(a);
+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
+    a.href = node.relpath+link;
+  } 
+  else 
+  {
+    if (childrenData != null) 
+    {
+      a.className = "nolink";
+      a.href = "javascript:void(0)";
+      a.onclick = node.expandToggle.onclick;
+      node.expanded = false;
+    }
+  }
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+  node.childrenUL = null;
+  node.getChildrenUL = function() 
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+      node.childrenUL = document.createElement("ul");
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+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
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+    return node.childrenUL;
+  };
+
+  return node;
+}
+
+function showRoot()
+{
+  var headerHeight = $("#top").height();
+  var footerHeight = $("#nav-path").height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
+
+function expandNode(o, node, imm)
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+    {
+      getNode(o, node);
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+    if (imm)
+    {
+      $(node.getChildrenUL()).show();
+    } 
+    else 
+    {
+      $(node.getChildrenUL()).slideDown("fast",showRoot);
+    }
+    if (node.isLast)
+    {
+      node.plus_img.src = node.relpath+"ftv2mlastnode.png";
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+    else
+    {
+      node.plus_img.src = node.relpath+"ftv2mnode.png";
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+    node.expanded = true;
+  }
+}
+
+function getNode(o, po)
+{
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+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
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+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
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+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
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+  if (o.breadcrumbs == null)
+  {
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+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
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+    for (var i in o.breadcrumbs) 
+    {
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+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/CMSIS/Documentation/SVD/html/open.png b/CMSIS/Documentation/SVD/html/open.png
new file mode 100644
index 0000000000..7b35d2c2c3
Binary files /dev/null and b/CMSIS/Documentation/SVD/html/open.png differ
diff --git a/CMSIS/Documentation/SVD/html/pages.html b/CMSIS/Documentation/SVD/html/pages.html
new file mode 100644
index 0000000000..288b35e0c9
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/pages.html
@@ -0,0 +1,102 @@
+
+
+
+
+Usage and Description
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Usage and Description
  

+

+

+
Here is a list of all related documentation pages:

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/resize.js b/CMSIS/Documentation/SVD/html/resize.js
new file mode 100644
index 0000000000..04fa95ce97
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/resize.js
@@ -0,0 +1,81 @@
+var cookie_namespace = 'doxygen'; 
+var sidenav,navtree,content,header;
+
+function readCookie(cookie) 
+{
+  var myCookie = cookie_namespace+"_"+cookie+"=";
+  if (document.cookie) 
+  {
+    var index = document.cookie.indexOf(myCookie);
+    if (index != -1) 
+    {
+      var valStart = index + myCookie.length;
+      var valEnd = document.cookie.indexOf(";", valStart);
+      if (valEnd == -1) 
+      {
+        valEnd = document.cookie.length;
+      }
+      var val = document.cookie.substring(valStart, valEnd);
+      return val;
+    }
+  }
+  return 0;
+}
+
+function writeCookie(cookie, val, expiration) 
+{
+  if (val==undefined) return;
+  if (expiration == null) 
+  {
+    var date = new Date();
+    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week
+    expiration = date.toGMTString();
+  }
+  document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/";
+}
+ 
+function resizeWidth() 
+{
+  var windowWidth = $(window).width() + "px";
+  var sidenavWidth = $(sidenav).width();
+  content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar
+  writeCookie('width',sidenavWidth, null);
+}
+
+function restoreWidth(navWidth)
+{
+  var windowWidth = $(window).width() + "px";
+  content.css({marginLeft:parseInt(navWidth)+6+"px"});
+  sidenav.css({width:navWidth + "px"});
+}
+
+function resizeHeight() 
+{
+  var headerHeight = header.height();
+  var footerHeight = footer.height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  content.css({height:windowHeight + "px"});
+  navtree.css({height:windowHeight + "px"});
+  sidenav.css({height:windowHeight + "px",top: headerHeight+"px"});
+}
+
+function initResizable()
+{
+  header  = $("#top");
+  sidenav = $("#side-nav");
+  content = $("#doc-content");
+  navtree = $("#nav-tree");
+  footer  = $("#nav-path");
+  $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } });
+  $(window).resize(function() { resizeHeight(); });
+  var width = readCookie('width');
+  if (width) { restoreWidth(width); } else { resizeWidth(); }
+  resizeHeight();
+  var url = location.href;
+  var i=url.indexOf("#");
+  if (i>=0) window.location.hash=url.substr(i);
+  var _preventDefault = function(evt) { evt.preventDefault(); };
+  $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault);
+}
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd__example_pg.html b/CMSIS/Documentation/SVD/html/svd__example_pg.html
new file mode 100644
index 0000000000..c81cae46de
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/svd__example_pg.html
@@ -0,0 +1,833 @@
+
+
+
+
+SVD File Example
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
SVD File Example 
  

+

+

+
<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+  Copyright (C) 2012 ARM Limited. All rights reserved.
+
+  Purpose: System Viewer Description (SVD) Example (Schema Version 1.0)
+           This is a description of a none-existent and incomplete device
+           for demonstration purposes only.
+ -->
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>ARMCM3xxx</name>                                          <!-- name of part or part series -->
+  <version>1.0</version>                                          <!-- version of this description -->
+  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
+  <width>32</width>                                               <!-- bus width is 32 bits -->
+  <!-- default settings implicitly inherited by subsequent sections -->
+  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
+                                                                       and register that do not define "size" themselves -->
+  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
+  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
+  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->
+
+  <peripherals>
+    <!-- Timer 0 -->
+    <peripheral>
+      <name>TIMER0</name>
+      <version>1.0</version>
+      <description>32 Timer / Counter, counting up or down from different sources</description>
+      <groupName>TIMER</groupName>
+      <baseAddress>0x40010000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+
+      <interrupt>
+        <name>TIMER0</name>
+        <value>0</value>
+      </interrupt>
+
+      <registers>
+      <!-- CR: Control Register -->
+        <register>
+          <name>CR</name>
+          <description>Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x1337F7F</resetMask>
+
+          <fields>
+            <!-- EN: Enable -->
+            <field>
+              <name>EN</name>
+              <description>Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Timer is disabled and does not operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer is enabled and can operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Reset -->
+            <field>
+              <name>RST</name>
+              <description>Reset Timer</description>
+              <bitRange>[1:1]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Reserved</name>
+                  <description>Write as ZERO if necessary</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reset_Timer</name>
+                  <description>Reset the Timer</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNT: Counting Direction -->
+            <field>
+              <name>CNT</name>
+              <description>Counting direction</description>
+              <bitRange>[3:2]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Count_UP</name>
+                  <description>Timer Counts UO and wraps, if no STOP condition is set</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Count_DOWN</name>
+                  <description>Timer Counts DOWN and wraps, if no STOP condition is set</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Toggle</name>
+                  <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Operation Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Continous</name>
+                  <description>Timer runs continously</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register and stops</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- PSC: Use Prescaler -->
+            <field>
+              <name>PSC</name>
+              <description>Use Prescaler</description>
+              <bitRange>[7:7]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Prescaler is not used</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Prescaler is used as divider</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNTSRC: Timer / Counter Soruce Divider -->
+            <field>
+              <name>CNTSRC</name>
+              <description>Timer / Counter Source Divider</description>
+              <bitRange>[11:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CAP_SRC</name>
+                  <description>Capture Source is used directly</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div2</name>
+                  <description>Capture Source is divided by 2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div4</name>
+                  <description>Capture Source is divided by 4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div8</name>
+                  <description>Capture Source is divided by 8</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div16</name>
+                  <description>Capture Source is divided by 16</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div32</name>
+                  <description>Capture Source is divided by 32</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div64</name>
+                  <description>Capture Source is divided by 64</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div128</name>
+                  <description>Capture Source is divided by 128</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div256</name>
+                  <description>Capture Source is divided by 256</description>
+                  <value>8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPSRC: Timer / COunter Capture Source -->
+            <field>
+              <name>CAPSRC</name>
+              <description>Timer / Counter Capture Source</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CClk</name>
+                  <description>Core Clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_0</name>
+                  <description>GPIO A, PIN 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_1</name>
+                  <description>GPIO A, PIN 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_2</name>
+                  <description>GPIO A, PIN 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_3</name>
+                  <description>GPIO A, PIN 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_4</name>
+                  <description>GPIO A, PIN 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_5</name>
+                  <description>GPIO A, PIN 5</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_6</name>
+                  <description>GPIO A, PIN 6</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_7</name>
+                  <description>GPIO A, PIN 7</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_0</name>
+                  <description>GPIO B, PIN 0</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_1</name>
+                  <description>GPIO B, PIN 1</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_2</name>
+                  <description>GPIO B, PIN 2</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_3</name>
+                  <description>GPIO B, PIN 3</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_0</name>
+                  <description>GPIO C, PIN 0</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_5</name>
+                  <description>GPIO C, PIN 1</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_6</name>
+                  <description>GPIO C, PIN 2</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPEDGE: Capture Edge -->
+            <field>
+              <name>CAPEDGE</name>
+              <description>Capture Edge, select which Edge should result in a counter increment or decrement</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Only rising edges result in a counter increment or decrement</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Only falling edges  result in a counter increment or decrement</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Rising and falling edges result in a counter increment or decrement</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- TRGEXT: Triggers an other Peripheral -->
+            <field>
+              <name>TRGEXT</name>
+              <description>Triggers an other Peripheral</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No Trigger is emitted</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA1</name>
+                  <description>DMA Controller 1 is triggered, dependant on MODE</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA2</name>
+                  <description>DMA Controller 2 is triggered, dependant on MODE</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UART</name>
+                  <description>UART is triggered, dependant on MODE</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- Reload: Selects Reload Register n -->
+            <field>
+              <name>RELOAD</name>
+              <description>Select RELOAD Register n to reload Timer on condition</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Selects Reload Register number 0</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Selects Reload Register number 1</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Selects Reload Register number 2</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Selects Reload Register number 3</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- IDR: Inc or dec Reload Register Selection -->
+            <field>
+              <name>IDR</name>
+              <description>Selects, if Reload Register number is incremented, decremented or not modified</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>KEEP</name>
+                  <description>Reload Register number does not change automatically</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INCREMENT</name>
+                  <description>Reload Register number is incremented on each match</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DECREMENT</name>
+                  <description>Reload Register number is decremented on each match</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- START: Starts / Stops the Timer/Counter -->
+            <field>
+              <name>S</name>
+              <description>Starts and Stops the Timer / Counter</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Timer / Counter is stopped</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Timer / Counter is started</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- SR: Status Register -->
+        <register>
+          <name>SR</name>
+          <description>Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xD701</resetMask>
+
+          <fields>
+            <!-- RUN: Shows if Timer is running -->
+            <field>
+              <name>RUN</name>
+              <description>Shows if Timer is running or not</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Stopped</name>
+                  <description>Timer is not running</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Running</name>
+                  <description>Timer is running</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MATCH: Shows if a Match was hit -->
+            <field>
+              <name>MATCH</name>
+              <description>Shows if the MATCH was hit</description>
+              <bitRange>[8:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Match</name>
+                  <description>The MATCH condition was not hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Match_Hit</name>
+                  <description>The MATCH condition was hit</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- UN: Shows if an underflow occured -->
+            <field>
+              <name>UN</name>
+              <description>Shows if an underflow occured. This flag is sticky</description>
+              <bitRange>[9:9]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Underflow</name>
+                  <description>No underflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>A minimum of one underflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- OV: Shows if an overflow occured -->
+            <field>
+              <name>OV</name>
+              <description>Shows if an overflow occured. This flag is sticky</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Overflow</name>
+                  <description>No overflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow_occured</name>
+                  <description>A minimum of one overflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Shows if Timer is in RESET state -->
+            <field>
+              <name>RST</name>
+              <description>Shows if Timer is in RESET state</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Ready</name>
+                  <description>Timer is not in RESET state and can operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>In_Reset</name>
+                  <description>Timer is in RESET state and can not operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RELOAD: Shows the currently active Reload Register -->
+            <field>
+              <name>RELOAD</name>
+              <description>Shows the currently active RELOAD Register</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Reload Register number 0 is active</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Reload Register number 1 is active</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Reload Register number 2 is active</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Reload Register number 3 is active</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- INT: Interrupt Register -->
+        <register>
+          <name>INT</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x0771</resetMask>
+
+          <fields>
+            <!-- EN: Interrupt Enable -->
+            <field>
+              <name>EN</name>
+              <description>Interrupt Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Timer does not generate Interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer triggers the TIMERn Interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Interrupt Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Match</name>
+                  <description>Timer generates an Interrupt when the MATCH condition is hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>Timer generates an Interrupt when it underflows</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow</name>
+                  <description>Timer generates an Interrupt when it overflows</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- COUNT: Counter Register -->
+        <register>
+          <name>COUNT</name>
+          <description>The Counter Register reflects the actual Value of the Timer/Counter</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+        <!-- MATCH: Match Register -->
+        <register>
+          <name>MATCH</name>
+          <description>The Match Register stores the compare Value for the MATCH condition</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Read Register -->
+        <register>
+          <name>PRESCALE_RD</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Write Register -->
+        <register>
+          <name>PRESCALE_WR</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+
+        <!-- RELOAD: Array of Reload Register with 4 elements-->
+        <register>
+          <dim>4</dim>
+          <dimIncrement>4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>RELOAD[%s]</name>
+          <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+
+    <!-- Timer 1 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER1</name>
+      <baseAddress>0x40010100</baseAddress>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>4</value>
+      </interrupt>
+    </peripheral>
+
+    <!-- Timer 2 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER2</name>
+      <baseAddress>0x40010200</baseAddress>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>6</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
+
 

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd__outline_pg.html b/CMSIS/Documentation/SVD/html/svd__outline_pg.html
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+
+
+
+
+SVD File Description
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
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+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
SVD File Description 
  

+

+

+
The CMSIS-SVD format is based on XML. The specification of the System View Description format was influenced by IP-XACT, a design description format used in, for example, IP stitching and IP reuse. Due to the much wider scope and complexity of IP-XACT it was decided to specify a separate format, which is focused and tailored toward the description of the programmer's view of a device only.

+
CMSIS-SVD XML Hierarchy

+

+CMSIS_SVD_Schema_Gen.png
+

+CMSIS-SVD Hierarchy Levels

+
 One CMSIS-SVD file contains the description of a single device. A device consists of a processor and at least one peripheral. Each peripheral contains at least one register. A register may consist of one or more fields. The range of values for a field may be further described with enumerated values.

+
    
+
  • Device Level: The top level of a System View Description is the device. On this level, information is captured that is specific to the device as a whole. For example, the device name, description, or version. The minimal addressable unit as well as the bit-width of the data bus are required by the debugger to perform the correct target accesses.
    
+ 
    
+Default values for register attributes like register size, reset value, and access permissions can be set for the whole device on this level and are implicitly inherited by the lower levels of the description. If however specified on a lower level, the default setting from a higher level will get overruled.
    • 
+

+
    
+
  • Peripherals Level: A peripheral is a named collection of registers. A peripheral is mapped to a defined base address within the device's address space. A peripheral allocates one or more exclusive address blocks relative to its base address, such that all described registers fit into the allocated address blocks. Allocated addresses without an associated register description are automatically considered reserved. The peripheral can be assigned to a group of peripherals and may be associated with one or more interrupts.
    • 
+

+
    
+
  • Registers Level: A register is a named, programmable resource that belongs to a peripheral. Registers are mapped to a defined address in the address space of the device. An address is specified relative to the peripheral base address. The description of a register documents the purpose and function of the resource. A debugger requires information about the permitted access to a resource as well as side effects triggered by read and write accesses respectively.
    • 
+

+
    
+
  • Fields Level: Registers may be partitioned into chunks of bits of distinct functionality. A chunk is referred to as field. The field names within a single register must be unique. Only architecturally defined fields shall be described. Any bits not being explicitly described are treated as reserved. They are not displayed in the System Viewer and are padded in the bit fields of the device header file. The case-insensitive field named "reserved" is treated as a keyword and each field with this name is ignored.
    • 
+

+
    
+
  • Enumerated Values Level: An enumeration maps an unsigned integer constant to a descriptive identifier and, optionally, to a description string. Enumerations are used in C to enhance the readability of source code. Similarly, it can be used by debuggers to provide more instructive information to the programmer, avoiding a lookup in the device documentation.
    • 
+

+
    
+
  • Vendor Extensions: The CMSIS-SVD format includes a section named vendorExtensions positioned after the closing tag peripherals. This allows silicon vendors and tool partners to innovate and expand the description beyond the current specification.
    • 
+

+
Multiple Instantiation

+
CMSIS-SVD supports the reuse of whole sections of the description. The attribute derivedFrom for the peripheral-, register-, and field-section specifies the source of the section to be copied from. Individual tags can be used to redefine specific elements within a copied section. In case the name of the description source is not unique, the name needs to be qualified hierarchically until the element composite name becomes unique. Hierarchies are separated by a dot. For example, <peripheral name>.<register name>.<field name>.

+
Peripheral Grouping

+
Peripherals that provide similar functionality (Simple Timer, Complex Timer) can be grouped with the element groupName. All peripherals associated with the same group name are collectively listed under this group in the order they have been specified in the file. Collecting similar or related peripherals into peripheral groups helps structuring the list of peripherals in the debugger.

+
Descriptions

+
On each level, the tag description provides verbose information about the respective element. The description field plays an important part in improving the software development productivity as it gives instant access to information that otherwise would need to be looked up in the device documentation. 

+

+

+  
+
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+
diff --git a/CMSIS/Documentation/SVD/html/svd__usage_pg.html b/CMSIS/Documentation/SVD/html/svd__usage_pg.html
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+
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+SVD File Usage
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
SVD File Usage 
  

+

+

+
System Views 

+ There are a number of tool vendors who are supporting the CMSIS-SVD format with their products. Refer to the tools documentation to find out how to use CMSIS-SVD descriptions with the debugger of your choice. You can download the latest versions of available CMSIS-SVD files from the Public Download Area on the ARM web. 

+

+
Device Header File Generation (<device_name>.h): 

+ SVDConv generates CMSIS compliant device header files from a CMSIS-SVD description. Note that CMSIS device header files are developed and maintained by the silicon vendors. Therefore the expectation is that this conversion is only of interest to these parties. 

+ In a first step, a consistency check of the description is performed. In a second step, the device header file is generated. The device header file is generated into the current directory and the file name is determined by the tag name on the device level from CMSIS-SVD input file. 

+
  SVDConv.exe myDevice.xml --generate=header 
+
 

+

+
    
+
  • Additional options: 
    
+ This option generates bit fields in the device header file for each field description contained in the CMSIS-SVD input file. 
        --fields=struct
+
     
    
+ This option generates position and mask C-Macros for each field description contained in the CMSIS-SVD input file. 
        --fields=macro
+
     
    • 
+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html b/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html
new file mode 100644
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+
+
+
+
+SVD File Validation
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
SVD File Validation 
  

+

+

+
The quality of the available descriptions is key to the success of the CMSIS-SVD format. Aspects of quality are:

+
    
+
  • Syntactical and structural compliance with the specified CMSIS-SVD format.
    • 
+
  • Consistency and correctness.
    • 
+
  • Completeness.
    • 
+
  • Level of detail.
    • 
+

+
Automated checks are done on two levels:

+
    
+
  1. The CMSIS-SVD Schema File: The schema file specifies the syntax and structure of an XML-based format. XML tools use the schema file for checking the syntactical and structural correctness of an XML file that claims compliance with a certain format. The schema file CMSIS-SVD_Schema_1_0.xsd can be found in the folder SVD of the CMSIS distribution. 
    
+
    
+
    2. 
+
  2. SVD Conversion Utility: ARM provides the SVD Utility (SVDConv.exe) tool to check the semantics and consistency of the data contained in a CMSIS-SVD file. SVDConv is a command-line tool included in the CMSIS distribution. It is located in the SVD folder side by side with the CMSIS-SVD schema file. The SVDConv shall be used for checking CMSIS-SVD descriptions as well as for generating CMSIS-compliant device header files. 
    
+
    
+
      
+
    • Usage Information: 
      
+ SVDConv provides usage information at the command line when invoked without arguments. 
       SVDConv.exe 
+
       
      
+
      
+
      • 
+
    • Consistency Check: 
      
+ SVDConv is performing a consistency of the CMSIS-SVD file passed as the first command-line argument. The checks go beyond syntactical tests as they can be performed using the CMSIS-SVD schema file in combination with XML validation tools. Errors and warnings are printed to the command line. 
      
+ 
        SVDConv.exe myDevice.xml 
+
       
      
+
      
+ 
      • 
+
    
+
    3. 
+

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd_web_pg.html b/CMSIS/Documentation/SVD/html/svd_web_pg.html
new file mode 100644
index 0000000000..4f51d29528
--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/svd_web_pg.html
@@ -0,0 +1,104 @@
+
+
+
+
+CMSIS-SVD Web Interface User Guide
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
CMSIS-SVD Web Interface User Guide 
  

+

+

+
The CMSIS Web Interface provides functionalities for downloading and managing the CMSIS-SVD files.

+
+
In any case, the ARM web page requires login credentials to grant access to the content.

+
+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd_web_public_pg.html b/CMSIS/Documentation/SVD/html/svd_web_public_pg.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/svd_web_public_pg.html
@@ -0,0 +1,131 @@
+
+
+
+
+Public Download Area
+
+
+
+
+
+
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+
+
+
+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Public Download Area 
  

+

+

+
Public access to the Device Database is provided from cmsis.arm.com. For the public download of the CMSIS-SVD files of published devices it is mandatory to:

+
    
+
  • Be logged in on the ARM web site.
    • 
+
  • Have accepted a silicon vendor specific End Users License Agreement (EULA).
    • 
+

+

+Logging in

+
    
+
  • Use your credentials to Login.
    • 
+

+

+Opening the CMSIS-SVD Download page

+

+Access_SVD_Vendor.png
+

+Access Silicon Vendor Device Database

+
    
+
  • Access the CMSIS webpage at cmsis.arm.com.
    • 
+
  • Select the "CMSIS-SVD" tab.
    • 
+
  • Click on a Silicon Vendor's name for getting redirected to the respective vendor device database.
    • 
+

+

+Accepting the Silicon Vendor's License terms

+
On your first visit to a vendor database page you will be asked to review and accept the vendor-specific "End User License Agreement" (EULA). If you do not accept the EULA, you will see the list of devices and associated CMSIS-SVD files, but you will not be able to download any of the files. Note, in case the EULA has changed, you will be asked to review and accept the EULA again.

+

+Downloading CMSIS-SVD files

+

+CMSIS_SVD_Vendor_DD.png
+

+Download Device Database Files

+
    
+
  • Select one, multiple, or all devices from the table.
    • 
+
  • Click the "download" button.
    • 
+

+
You will be asked to open or save the zip archive file containing the files. If you have selected multiple devices, the file contents.txt included in the archive will list the mapping between devices and CMSIS-SVD files. Multiple devices can share the same CMSIS-SVD file. 

+

+

+  
+
+
+
+
diff --git a/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html b/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html
new file mode 100644
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--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html
@@ -0,0 +1,157 @@
+
+
+
+
+Restricted Management Area
+
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+
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+
+

+
+

+
+ 
+ 
+  
+  
+  
+  
+  
+  
+ 
+ 
+

+   
CMSIS-SVD
+    Version 1.10
+   

+   
CMSIS System View Description

+  

+

+
+

+    
+

+
+
+  
+

+

+  
+  

+  

+

+
+

+

+  

+
Restricted Management Area 
  

+

+

+
Access to the CMSIS-SVD device database management system is restricted to:

+
    
+
  • Silicon Vendors.
    • 
+
  • Companies who have signed an agreement with ARM about using the CMSIS-SVD device database.
    • 
+
  • ARM Cortex-M based microcontroller devices.
    • 
+

+

+Signing the agreement

+
    
+
  • The Silicon Vendor contacts the ARM sales representative or sends an email to cmsis@arm.com requesting to contribute to the CMSIS-SVD Database.
    • 
+
  • An agreement needs to be signed between the Silicon Vendor and ARM defining the terms of use and specifying the representatives authorized for managing the files and devices.
    • 
+
  • The login e-mail addresses for www.arm.com get listed in the contract. The representatives need to ensure that their login already exists.
    • 
+
  • As part of exercising the contract the representatives will be given CMSIS-SVD Upload permissions in the system.
    • 
+

+

+Logging in

+
    
+
  • Use your credentials to Login.
    • 
+

+

+Opening the CMSIS-SVD Device Database page

+

+Access_SVD_DD_Manage.png
+

+Management Access to Device Database

+
    
+
  • Access the CMSIS web page at cmsis.arm.com.
    • 
+
  • Click the button "Device Database" 
    Note:
    If you do not see this button, you are either not logged in or you have not been granted CMSIS-SVD Upload permissions.
    
+
    • 
+

+

+Managing the Device Database

+
The database lists microcontroller devices and their associated CMSIS-SVD files and, optionally, resource files. Multiple devices may share the same CMSIS-SVD and the optional resource file. For this reason, files and devices are managed separately. Files need to be uploaded and have to pass the check against the CMSIS-SVD Schema as well as the plausibility and consistency check by the SVDConv utility before they can be used to define a device. The SVDConv checking is scheduled. Therefore, it can take up to 15 minutes before the file status gets updated.

+

+Manage_SVD_DD.png
+

+Manage Device Database Entries

+
    
+
  • a) Manage Files
      
+
    • Add file: Select the CMSIS-SVD file and start the upload process. The schema check will run immediately after the file upload is complete. If the check fails the file will not be stored and you are asked to upload a corrected file. The SVDConv check for this file is automatically scheduled and will take place within 15 minutes. The status of the file will be updated and reports errors and warnings in a text file that can be downloaded (click on error/warning respectively).
      • 
+
    • Delete file: Files can only be deleted if they are not associated with a device otherwise the system will list the devices the file is still associated with.
      • 
+
    • Replace file: Replace files allows you to update a file without the need to edit the device definition.
      • 
+
    
+
    • 
+

+
    
+
  • b) Manage Devices 
    
+ New devices can be added or existing devices can be edited. A device defines:
      
+
    • Name of device
      • 
+
    • Filename CMSIS-SVD
      • 
+
    • Filename Resource zip archive
      • 
+
    • Reviewer List
      • 
+
    • Publishing Date 
      
+ A checkbox is in front of each device to enable and disable a device. A disabled device will not show in the vendor-specific download area.
      • 
+
    
+
    • 
+

+
    
+
  • c) Review Devices 
    
+ Ask you reviewer for the login email address being used for the login on the ARM web. Add this email address into the field, one email address per line. You can add some text to the e-mail body however the email template already contains all relevant information like the device name as well as a link to the device database. 
    • 
+

+

+

+  
+
+
+
+
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--- /dev/null
+++ b/CMSIS/Documentation/SVD/html/tabs.css
@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
+    font-size: 12px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
+}
+
+.tabs1 .tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_topnav.png');
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/CMSIS/Include/arm_common_tables.h b/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..5fd6ff4af9
--- /dev/null
+++ b/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,38 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef[6144];
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/CMSIS/Include/arm_math.h b/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..ebaf6b21b1
--- /dev/null
+++ b/CMSIS/Include/arm_math.h
@@ -0,0 +1,7557 @@
+/* ----------------------------------------------------------------------   
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.   
+ *   
+ * $Date:        15. February 2012  
+ * $Revision: 	V1.1.0  
+ *   
+ * Project: 	    CMSIS DSP Library   
+ * Title:	     	arm_math.h
+ *   
+ * Description:	 Public header file for CMSIS DSP Library
+ *   
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *  
+ * Version 1.1.0 2012/02/15 
+ *    Updated with more optimizations, bug fixes and minor API changes.  
+ *  
+ * Version 1.0.10 2011/7/15 
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.  
+ *   
+ * Version 1.0.3 2010/11/29  
+ *    Re-organized the CMSIS folders and updated documentation.   
+ *    
+ * Version 1.0.2 2010/11/11   
+ *    Documentation updated.    
+ *   
+ * Version 1.0.1 2010/10/05    
+ *    Production release and review comments incorporated.   
+ *   
+ * Version 1.0.0 2010/09/20    
+ *    Production release and review comments incorporated.   
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   *
+   * This user manual describes the CMSIS DSP software library, 
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:  
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values. 
+   *
+   * Pre-processor Macros 
+   * 
+   * Each library project have differant pre-processor macros. 
+   * 
+   * - UNALIGNED_SUPPORT_DISABLE: 
+   * 
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access    
+   * 
+   * - ARM_MATH_BIG_ENDIAN: 
+   * 
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. 
+   * 
+   * - ARM_MATH_MATRIX_CHECK: 
+   * 
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices 
+   * 
+   * - ARM_MATH_ROUNDING: 
+   * 
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target.
+   * 
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   *
+   * Toolchain Support
+   *
+   * The library has been developed and tested with MDK-ARM version 4.23. 
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Using the Library
+   *
+   * The library installer contains prebuilt versions of the libraries in the Lib folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
+   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * ARM_MATH_CM0 depending on the target processor in the application.
+   *
+   * Examples
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Building the Library
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * Copyright Notice
+   *
+   * Copyright (C) 2010 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 

+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size numRows X numCols
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * 
+ *     pData[i*numCols + j]
+ * 

+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 

+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * 
+ *     ARM_MATH_SIZE_MISMATCH
+ * 

+ * Otherwise the functions return
+ * 
+ *     ARM_MATH_SUCCESS
+ * 

+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * 
+ *     ARM_MATH_MATRIX_CHECK
+ * 

+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined  (__GNUC__)
+  #define __SIMD32(addr)         (*( int32_t **) & (addr))
+  #define  _SIMD32_OFFSET(addr)  (*( int32_t * )   (addr))
+#else
+  #define __SIMD32(addr)         (*(__packed                    int32_t **) & (addr))
+  #define  _SIMD32_OFFSET(addr)  (*(__packed                    int32_t * )   (addr))
+#endif 
+
+  #define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
+
+  __STATIC_INLINE  uint32_t __CLZ(q31_t data);
+
+
+  __STATIC_INLINE uint32_t __CLZ(q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+   */
+
+  __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+   */
+  __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0)
+
+  __STATIC_INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  __STATIC_INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * numTaps is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Radix-2 Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+
+
+  /*----------------------------------------------------------------------
+   *		Internal functions prototypes FFT function
+   ----------------------------------------------------------------------*/
+
+  /**
+   * @brief  Core function for the floating-point CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the floating-point CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]      onebyfftLen      value of 1/fftLen.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+   * @param[in]      fftSize      length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+   * @param[in]      *pBitRevTab  points to the bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q31 CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the f32 FFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix2_butterfly_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q31 CFFT butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q15 CFFT butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q15 CFFT Inverse butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef       	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q31 CFFT Inverse butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the f32 IFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]		 onebyfftLen	  1/fftLenfth
+   * @return none.
+   */
+
+  void arm_radix2_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+                                                                /**
+   * @brief  Core function for the Q31 CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q15 CFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+
+  /**
+   * @brief  Core function for the Q15 CIFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q15 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q31 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief  Initialization function for the floating-point RFFT/RIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLenReal     length of the FFT.
+   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**  
+ * @brief Convolution of floating-point sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+  
+  /**   
+   * @brief Convolution of Q15 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**  
+ * @brief Convolution of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**   
+   * @brief Convolution of Q7 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**   
+   * @brief Partial convolution of Q15 sequences.   
+   * @param[in]       *pSrcA points to the first input sequence.   
+   * @param[in]       srcALen length of the first input sequence.   
+   * @param[in]       *pSrcB points to the second input sequence.   
+   * @param[in]       srcBLen length of the second input sequence.   
+   * @param[out]      *pDst points to the block of output data   
+   * @param[in]       firstIndex is the first output sample to start with.   
+   * @param[in]       numPoints is the number of output points to be computed.   
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**   
+   * @brief Partial convolution of Q7 sequences   
+   * @param[in]       *pSrcA points to the first input sequence.   
+   * @param[in]       srcALen length of the first input sequence.   
+   * @param[in]       *pSrcB points to the second input sequence.   
+   * @param[in]       srcBLen length of the second input sequence.   
+   * @param[out]      *pDst points to the block of output data   
+   * @param[in]       firstIndex is the first output sample to start with.   
+   * @param[in]       numPoints is the number of output points to be computed.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
+   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**   
+   * @brief Correlation of Q15 sequences   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @return none.   
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**   
+   * @brief Correlation of Q7 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cos output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cosine output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * S points to an instance of the PID control data structure.  in
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  

+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   * 
+   * \par 
+   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.  
+   * The proportional value determines the reaction to the current error, 
+   * the integral value determines the reaction based on the sum of recent errors, 
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure 
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
+   * A separate instance structure must be defined for each PID Controller. 
+   * There are separate instance structure declarations for each of the 3 supported data types. 
+   * 
+   * \par Reset Functions 
+   * There is also an associated reset function for each data type which clears the state array. 
+   *
+   * \par Initialization Functions 
+   * There is also an associated initialization function for each data type. 
+   * The initialization function performs the following operations: 
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.   
+   * 
+   * \par 
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   *
+   * \par Fixed-Point Behavior 
+   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
+   * Refer to the function specific documentation below for usage guidelines. 
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using an internal 64-bit accumulator. 
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
+   * Thus, if the accumulator result overflows it wraps around rather than clip. 
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   */
+
+  __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using a 64-bit internal accumulator. 
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+    /* Implementation of PID controller */
+
+#ifdef ARM_MATH_CM0
+
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+#else
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+#endif
+
+#ifdef ARM_MATH_CM0
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#else
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+   * When Ialpha is superposed with Ia as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+   * can be calculated using only Ia and Ib.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where Ia and Ib are the instantaneous stator phases and
+   * pIalpha and pIbeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   * 
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where pIa and pIb are the instantaneous stator phases and
+   * Ialpha and Ibeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   */
+
+
+  __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version 
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents 
+   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where Ialpha and Ibeta are the stator vector components,  
+   * pId and pIq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version 
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where pIalpha and pIbeta are the stator vector components,  
+   * Id and Iq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version 
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par 
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 

+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * S points to an instance of the Linear Interpolate function data structure.
+   * x is the input sample value. The functions returns the output value.
+   * 
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
+   * if x is below input range and returns last value of table if x is above range.  
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (x - S->x1) / xSpacing;
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if(i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12. 
+   *
+   */
+
+
+  __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 

+   * where x1 is the current estimate,
+   * x0 is the previous estimate and
+   * f'(x0) is the derivative of f() evaluated at x0.
+   * For the square root function, the algorithm reduces to:
+   * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 

+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+
+  __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//    #if __FPU_USED
+    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+    #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+        *pOut = __builtin_sqrtf(in);
+    #else
+        *pOut = sqrtf(in);
+    #endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return none. 
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * Algorithm
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 

+   *
+   * \par
+   * where numRows specifies the number of rows in the table;
+   * numCols specifies the number of columns in the table;
+   * and pData points to an array of size numRows*numCols values.
+   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+   *
+   * \par
+   * Let (x, y) specify the desired interpolation point.  Then define:
+   * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 

+   * \par
+   * The interpolated output point is computed as:
+   * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 

+   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/CMSIS/Include/core_cm0.h b/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..0d7cfd85e2
--- /dev/null
+++ b/CMSIS/Include/core_cm0.h
@@ -0,0 +1,667 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     13. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_cm0plus.h b/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..cf92fb7fef
--- /dev/null
+++ b/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x01)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0+ system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts   */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_cm3.h b/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..db1716ad95
--- /dev/null
+++ b/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1612 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_cm4.h b/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..024302e4a6
--- /dev/null
+++ b/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1757 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+#include                /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_cm4_simd.h b/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000..b5140073fb
--- /dev/null
+++ b/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,649 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include 
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include 
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_cmFunc.h b/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..adb07b5d34
--- /dev/null
+++ b/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/CMSIS/Include/core_cmInstr.h b/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..624c175fd5
--- /dev/null
+++ b/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+  return(op1);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/CMSIS/Include/core_sc000.h b/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..9d874b754e
--- /dev/null
+++ b/CMSIS/Include/core_sc000.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for SC000 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Include/core_sc300.h b/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..1dd2f12626
--- /dev/null
+++ b/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1583 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include                       /* standard types definitions                      */
+#include                 /* Core Instruction Access                         */
+#include                  /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
+    function SysTick_Config is not included. In this case, the file device.h
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/CMSIS/Lib/ARM/arm_cortexM0b_math.lib b/CMSIS/Lib/ARM/arm_cortexM0b_math.lib
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diff --git a/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a b/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a
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diff --git a/CMSIS/README.txt b/CMSIS/README.txt
new file mode 100644
index 0000000000..6d032a06ea
--- /dev/null
+++ b/CMSIS/README.txt
@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2012 ARM Limited. All rights reserved.  
+* 
+* Date:        07 March 2012  
+* Revision:    V3.01 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.
diff --git a/CMSIS/RTOS/cmsis_os.h b/CMSIS/RTOS/cmsis_os.h
new file mode 100644
index 0000000000..290c315b37
--- /dev/null
+++ b/CMSIS/RTOS/cmsis_os.h
@@ -0,0 +1,717 @@
+/* ----------------------------------------------------------------------  
+ * Copyright (C) 2012 ARM Limited. All rights reserved.  
+ *  
+ * $Date:        5. March 2012
+ * $Revision:    V0.03
+ *  
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h template header file
+ *  
+ * Version 0.02
+ *    Initial Proposal Phase 
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behaviour
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield 
+ * -------------------------------------------------------------------- */ 
+
+/**
+\page cmsis_os_h Header File Template: cmsis_os.h
+
+The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
+Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
+its implementation.
+
+The file cmsis_os.h contains:
+ - CMSIS-RTOS API function definitions
+ - struct definitions for parameters and return types
+ - status and priority values used by CMSIS-RTOS API functions
+ - macros for defining threads and other kernel objects
+
+
+Name conventions and header file modifications
+
+All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
+Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
+All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
+ 
+Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. 
+These definitions can be specific to the underlying RTOS kernel.
+
+Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
+compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
+
+
+Function calls from interrupt service routines
+
+The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
+  - \ref osSignalSet
+  - \ref osSemaphoreRelease
+  - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
+  - \ref osMessagePut, \ref osMessageGet
+  - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
+
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called 
+from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
+
+Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
+If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
+
+
+Define and reference object definitions
+
+With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file
+that is used troughtout a project as shown below:
+
+Header File
+\code
+#include                                          // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);                      
+\endcode
+
+
+This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is 
+present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
+used throughout the whole project.
+
+Example
+\code
+#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+\endcode
+
+\code
+#define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+\endcode
+
+*/
+ 
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version
+#define osCMSIS           0x00003      ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
+#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    30      ///< maximum count for SemaphoreInit function
+#define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
+                                    
+#include 
+#include 
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high 
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus; 
+
+
+/// Timer type value for the timer definition
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer 
+  osTimerPeriodic         =     1        ///< repeating timer 
+} os_timer_type; 
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument); 
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument); 
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_thread_def  {
+  os_pthread               pthread;    ///< start address of thread function
+  osPriority             tpriority;    ///< initial thread priority
+  uint32_t               instances;    ///< maximum number of instances of that thread function
+  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_mutex_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_semaphore_def  {
+  uint32_t                   dummy;    ///< dummy value.
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item 
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item 
+  void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef const struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item 
+  void                       *pool;    ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event. 
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. 
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value 
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags 
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate 
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate 
+  } def;                               ///< event definition
+} osEvent;
+
+
+//  ==== Kernel Control Functions ====
+
+/// Start the RTOS Kernel with executing the specified thread.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. 
+osStatus osKernelStart (osThreadDef_t *thread_def, void *argument);
+   
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. 
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+
+//  ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         instances    number of possible thread instances.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz)  \
+extern osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#define osThreadDef(name, priority, instances, stacksz)  \
+osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz)  }
+#endif
+
+/// Access a Thread defintion.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.  
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+
+//  ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay)
+/// \param[in]     millisec      time delay value 
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout
+/// \param[in] millisec          timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+
+#endif  // Generic Wait available
+
+
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function)  \
+osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+
+//  ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signal);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signal);
+
+/// Get Signal Flags status of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalGet (osThreadId thread_id);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+//  ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name)  \
+osMutexDef_t os_mutex_def_##name = { 0 }
+#endif
+
+/// Access a Mutex defintion.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+
+//  ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name)  \
+osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphore.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphore.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+#endif     // Semaphore available
+ 
+//  ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of objects (elements) in the memory pool.
+/// \param         type          data type of a single object (element).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero 
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif   // Memory Pool Management available
+
+
+//  ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type)   \
+osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type)  }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif     // Message Queues available
+
+
+//  ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+
+/// \brief Create a Mail Queue Definition
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof (type) }
+#endif
+     
+/// \brief Access a Mail Queue Definition
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the 
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can shall filled with mail or NULL in case error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+                            
+#endif  // Mail Queues available
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  // _CMSIS_OS_H
diff --git a/CMSIS/SVD/ARM_Sample.svd b/CMSIS/SVD/ARM_Sample.svd
new file mode 100644
index 0000000000..d0860b2707
--- /dev/null
+++ b/CMSIS/SVD/ARM_Sample.svd
@@ -0,0 +1,739 @@
+
+
+
+
+
+ 
+
+  ARMCM3xxx                                          
+  1.0                                          
+  ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. 
+  8                            
+  32                                               
+  
+  32                                                 
+  read-write                                     
+  0x00000000                             
+  0xFFFFFFFF                               
+
+  
+    
+    
+      TIMER0
+      1.0
+      32 Timer / Counter, counting up or down from different sources
+      TIMER
+      0x40010000
+      32
+      read-write
+
+      
+        0
+        0x100
+        registers
+      
+
+      
+        TIMER0
+        0
+      
+
+      
+      
+        
+          CR
+          Control Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0x1337F7F
+
+          
+            
+            
+              EN
+              Enable
+              [0:0]
+              read-write
+              
+                
+                  Disable
+                  Timer is disabled and does not operate
+                  0
+                
+                
+                  Enable
+                  Timer is enabled and can operate
+                  1
+                
+              
+            
+
+            
+            
+              RST
+              Reset Timer
+              [1:1]
+              write-only
+              
+                
+                  Reserved
+                  Write as ZERO if necessary
+                  0
+                
+                
+                  Reset_Timer
+                  Reset the Timer
+                  1
+                
+              
+            
+
+            
+            
+              CNT
+              Counting direction
+              [3:2]
+              read-write
+              
+                
+                  Count_UP
+                  Timer Counts UO and wraps, if no STOP condition is set
+                  0
+                
+                
+                  Count_DOWN
+                  Timer Counts DOWN and wraps, if no STOP condition is set
+                  1
+                
+                
+                  Toggle
+                  Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set
+                  2
+                
+              
+            
+
+            
+            
+              MODE
+              Operation Mode
+              [6:4]
+              read-write
+              
+                
+                  Continous
+                  Timer runs continously
+                  0
+                
+                
+                  Single_ZERO_MAX
+                  Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops
+                  1
+                
+                
+                  Single_MATCH
+                  Timer counts to the Value of MATCH Register and stops
+                  2
+                
+                
+                  Reload_ZERO_MAX
+                  Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues
+                  3
+                
+                
+                  Reload_MATCH
+                  Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues
+                  4
+                
+              
+            
+
+            
+            
+              PSC
+              Use Prescaler
+              [7:7]
+              read-write
+              
+                
+                  Disabled
+                  Prescaler is not used
+                  0
+                
+                
+                  Enabled
+                  Prescaler is used as divider
+                  1
+                
+              
+            
+
+            
+            
+              CNTSRC
+              Timer / Counter Source Divider
+              [11:8]
+              read-write
+              
+                
+                  CAP_SRC
+                  Capture Source is used directly
+                  0
+                
+                
+                  CAP_SRC_div2
+                  Capture Source is divided by 2
+                  1
+                
+                
+                  CAP_SRC_div4
+                  Capture Source is divided by 4
+                  2
+                
+                
+                  CAP_SRC_div8
+                  Capture Source is divided by 8
+                  3
+                
+                
+                  CAP_SRC_div16
+                  Capture Source is divided by 16
+                  4
+                
+                
+                  CAP_SRC_div32
+                  Capture Source is divided by 32
+                  5
+                
+                
+                  CAP_SRC_div64
+                  Capture Source is divided by 64
+                  6
+                
+                
+                  CAP_SRC_div128
+                  Capture Source is divided by 128
+                  7
+                
+                
+                  CAP_SRC_div256
+                  Capture Source is divided by 256
+                  8
+                
+              
+            
+
+            
+            
+              CAPSRC
+              Timer / Counter Capture Source
+              [15:12]
+              read-write
+              
+                
+                  CClk
+                  Core Clock
+                  0
+                
+                
+                  GPIOA_0
+                  GPIO A, PIN 0
+                  1
+                
+                
+                  GPIOA_1
+                  GPIO A, PIN 1
+                  2
+                
+                
+                  GPIOA_2
+                  GPIO A, PIN 2
+                  3
+                
+                
+                  GPIOA_3
+                  GPIO A, PIN 3
+                  4
+                
+                
+                  GPIOA_4
+                  GPIO A, PIN 4
+                  5
+                
+                
+                  GPIOA_5
+                  GPIO A, PIN 5
+                  6
+                
+                
+                  GPIOA_6
+                  GPIO A, PIN 6
+                  7
+                
+                
+                  GPIOA_7
+                  GPIO A, PIN 7
+                  8
+                
+                
+                  GPIOB_0
+                  GPIO B, PIN 0
+                  9
+                
+                
+                  GPIOB_1
+                  GPIO B, PIN 1
+                  10
+                
+                
+                  GPIOB_2
+                  GPIO B, PIN 2
+                  11
+                
+                
+                  GPIOB_3
+                  GPIO B, PIN 3
+                  12
+                
+                
+                  GPIOC_0
+                  GPIO C, PIN 0
+                  13
+                
+                
+                  GPIOC_5
+                  GPIO C, PIN 1
+                  14
+                
+                
+                  GPIOC_6
+                  GPIO C, PIN 2
+                  15
+                
+              
+            
+
+            
+            
+              CAPEDGE
+              Capture Edge, select which Edge should result in a counter increment or decrement
+              [17:16]
+              read-write
+              
+                
+                  RISING
+                  Only rising edges result in a counter increment or decrement
+                  0
+                
+                
+                  FALLING
+                  Only falling edges  result in a counter increment or decrement
+                  1
+                
+                
+                  BOTH
+                  Rising and falling edges result in a counter increment or decrement
+                  2
+                
+              
+            
+
+            
+            
+              TRGEXT
+              Triggers an other Peripheral
+              [21:20]
+              read-write
+              
+                
+                  NONE
+                  No Trigger is emitted
+                  0
+                
+                
+                  DMA1
+                  DMA Controller 1 is triggered, dependant on MODE
+                  1
+                
+                
+                  DMA2
+                  DMA Controller 2 is triggered, dependant on MODE
+                  2
+                
+                
+                  UART
+                  UART is triggered, dependant on MODE
+                  3
+                
+              
+            
+
+            
+            
+              RELOAD
+              Select RELOAD Register n to reload Timer on condition
+              [25:24]
+              read-write
+              
+                
+                  RELOAD0
+                  Selects Reload Register number 0
+                  0
+                
+                
+                  RELOAD1
+                  Selects Reload Register number 1
+                  1
+                
+                
+                  RELOAD2
+                  Selects Reload Register number 2
+                  2
+                
+                
+                  RELOAD3
+                  Selects Reload Register number 3
+                  3
+                
+              
+            
+
+            
+            
+              IDR
+              Selects, if Reload Register number is incremented, decremented or not modified
+              [27:26]
+              read-write
+              
+                
+                  KEEP
+                  Reload Register number does not change automatically
+                  0
+                
+                
+                  INCREMENT
+                  Reload Register number is incremented on each match
+                  1
+                
+                
+                  DECREMENT
+                  Reload Register number is decremented on each match
+                  2
+                
+              
+            
+
+            
+            
+              S
+              Starts and Stops the Timer / Counter
+              [31:31]
+              read-write
+              
+                
+                  STOP
+                  Timer / Counter is stopped
+                  0
+                
+                
+                  START
+                  Timer / Counter is started
+                  1
+                
+              
+            
+          
+        
+
+        
+        
+          SR
+          Status Register
+          0x04
+          16
+          read-write
+          0x00000000
+          0xD701
+
+          
+            
+            
+              RUN
+              Shows if Timer is running or not
+              [0:0]
+              read-only
+              
+                
+                  Stopped
+                  Timer is not running
+                  0
+                
+                
+                  Running
+                  Timer is running
+                  1
+                
+              
+            
+
+            
+            
+              MATCH
+              Shows if the MATCH was hit
+              [8:8]
+              read-write
+              
+                
+                  No_Match
+                  The MATCH condition was not hit
+                  0
+                
+                
+                  Match_Hit
+                  The MATCH condition was hit
+                  1
+                
+              
+            
+
+            
+            
+              UN
+              Shows if an underflow occured. This flag is sticky
+              [9:9]
+              read-write
+              
+                
+                  No_Underflow
+                  No underflow occured since last clear
+                  0
+                
+                
+                  Underflow
+                  A minimum of one underflow occured since last clear
+                  1
+                
+              
+            
+
+            
+            
+              OV
+              Shows if an overflow occured. This flag is sticky
+              [10:10]
+              read-write
+              
+                
+                  No_Overflow
+                  No overflow occured since last clear
+                  0
+                
+                
+                  Overflow_occured
+                  A minimum of one overflow occured since last clear
+                  1
+                
+              
+            
+
+            
+            
+              RST
+              Shows if Timer is in RESET state
+              [12:12]
+              read-only
+              
+                
+                  Ready
+                  Timer is not in RESET state and can operate
+                  0
+                
+                
+                  In_Reset
+                  Timer is in RESET state and can not operate
+                  1
+                
+              
+            
+
+            
+            
+              RELOAD
+              Shows the currently active RELOAD Register
+              [15:14]
+              read-only
+              
+                
+                  RELOAD0
+                  Reload Register number 0 is active
+                  0
+                
+                
+                  RELOAD1
+                  Reload Register number 1 is active
+                  1
+                
+                
+                  RELOAD2
+                  Reload Register number 2 is active
+                  2
+                
+                
+                  RELOAD3
+                  Reload Register number 3 is active
+                  3
+                
+              
+            
+          
+        
+
+        
+        
+          INT
+          Interrupt Register
+          0x10
+          16
+          read-write
+          0x00000000
+          0x0771
+
+          
+            
+            
+              EN
+              Interrupt Enable
+              [0:0]
+              read-write
+              
+                
+                  Disabled
+                  Timer does not generate Interrupts
+                  0
+                
+                
+                  Enable
+                  Timer triggers the TIMERn Interrupt
+                  1
+                
+              
+            
+
+            
+            
+              MODE
+              Interrupt Mode, selects on which condition the Timer should generate an Interrupt
+              [6:4]
+              read-write
+              
+                
+                  Match
+                  Timer generates an Interrupt when the MATCH condition is hit
+                  0
+                
+                
+                  Underflow
+                  Timer generates an Interrupt when it underflows
+                  1
+                
+                
+                  Overflow
+                  Timer generates an Interrupt when it overflows
+                  2
+                
+              
+            
+          
+        
+
+        
+        
+          COUNT
+          The Counter Register reflects the actual Value of the Timer/Counter
+          0x20
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+
+        
+        
+          MATCH
+          The Match Register stores the compare Value for the MATCH condition
+          0x24
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+        
+        
+        
+          PRESCALE_RD
+          The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value
+          0x28
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+        
+        
+        
+        
+          PRESCALE_WR
+          The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value
+          0x28
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+        
+
+
+        
+        
+          4
+          4
+          0,1,2,3
+          RELOAD[%s]
+          The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.
+          0x50
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+      
+    
+
+    
+    
+      TIMER1
+      0x40010100
+      
+        TIMER1
+        4
+      
+    
+
+    
+    
+      TIMER2
+      0x40010200
+      
+        TIMER2
+        6
+      
+    
+  
+
diff --git a/CMSIS/SVD/ARM_Sample_1_1.svd b/CMSIS/SVD/ARM_Sample_1_1.svd
new file mode 100644
index 0000000000..1f77a28fc4
--- /dev/null
+++ b/CMSIS/SVD/ARM_Sample_1_1.svd
@@ -0,0 +1,763 @@
+
+
+
+
+
+ 
+
+  ARM Ltd.                                       
+  ARM                                        
+  ARMCM3xxx                                          
+  ARMCM3                                         
+  1.2                                          
+  ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. 
+                                                     
+    ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+    processor based microcontroller, but can be equally used for other\n
+    suitable  processor architectures. This file can be freely distributed.\n
+    Modifications to this file shall be clearly marked.\n
+    \n
+    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+  
+                                                             
+    CM3
+    r1p0
+    little
+    true
+    false
+    3
+    false
+  
+  8                            
+  32                                               
+  
+  32                                                 
+  read-write                                     
+  0x00000000                             
+  0xFFFFFFFF                               
+
+  
+    
+    
+      TIMER0
+      1.0
+      32 Timer / Counter, counting up or down from different sources
+      TIMER
+      0x40010000
+      32
+      read-write
+
+      
+        0
+        0x100
+        registers
+      
+
+      
+        TIMER0
+        0
+      
+
+      
+      
+        
+          CR
+          Control Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0x1337F7F
+
+          
+            
+            
+              EN
+              Enable
+              [0:0]
+              read-write
+              
+                
+                  Disable
+                  Timer is disabled and does not operate
+                  0
+                
+                
+                  Enable
+                  Timer is enabled and can operate
+                  1
+                
+              
+            
+
+            
+            
+              RST
+              Reset Timer
+              [1:1]
+              write-only
+              
+                
+                  Reserved
+                  Write as ZERO if necessary
+                  0
+                
+                
+                  Reset_Timer
+                  Reset the Timer
+                  1
+                
+              
+            
+
+            
+            
+              CNT
+              Counting direction
+              [3:2]
+              read-write
+              
+                
+                  Count_UP
+                  Timer Counts UO and wraps, if no STOP condition is set
+                  0
+                
+                
+                  Count_DOWN
+                  Timer Counts DOWN and wraps, if no STOP condition is set
+                  1
+                
+                
+                  Toggle
+                  Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set
+                  2
+                
+              
+            
+
+            
+            
+              MODE
+              Operation Mode
+              [6:4]
+              read-write
+              
+                
+                  Continous
+                  Timer runs continously
+                  0
+                
+                
+                  Single_ZERO_MAX
+                  Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops
+                  1
+                
+                
+                  Single_MATCH
+                  Timer counts to the Value of MATCH Register and stops
+                  2
+                
+                
+                  Reload_ZERO_MAX
+                  Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues
+                  3
+                
+                
+                  Reload_MATCH
+                  Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues
+                  4
+                
+              
+            
+
+            
+            
+              PSC
+              Use Prescaler
+              [7:7]
+              read-write
+              
+                
+                  Disabled
+                  Prescaler is not used
+                  0
+                
+                
+                  Enabled
+                  Prescaler is used as divider
+                  1
+                
+              
+            
+
+            
+            
+              CNTSRC
+              Timer / Counter Source Divider
+              [11:8]
+              read-write
+              
+                
+                  CAP_SRC
+                  Capture Source is used directly
+                  0
+                
+                
+                  CAP_SRC_div2
+                  Capture Source is divided by 2
+                  1
+                
+                
+                  CAP_SRC_div4
+                  Capture Source is divided by 4
+                  2
+                
+                
+                  CAP_SRC_div8
+                  Capture Source is divided by 8
+                  3
+                
+                
+                  CAP_SRC_div16
+                  Capture Source is divided by 16
+                  4
+                
+                
+                  CAP_SRC_div32
+                  Capture Source is divided by 32
+                  5
+                
+                
+                  CAP_SRC_div64
+                  Capture Source is divided by 64
+                  6
+                
+                
+                  CAP_SRC_div128
+                  Capture Source is divided by 128
+                  7
+                
+                
+                  CAP_SRC_div256
+                  Capture Source is divided by 256
+                  8
+                
+              
+            
+
+            
+            
+              CAPSRC
+              Timer / Counter Capture Source
+              [15:12]
+              read-write
+              
+                
+                  CClk
+                  Core Clock
+                  0
+                
+                
+                  GPIOA_0
+                  GPIO A, PIN 0
+                  1
+                
+                
+                  GPIOA_1
+                  GPIO A, PIN 1
+                  2
+                
+                
+                  GPIOA_2
+                  GPIO A, PIN 2
+                  3
+                
+                
+                  GPIOA_3
+                  GPIO A, PIN 3
+                  4
+                
+                
+                  GPIOA_4
+                  GPIO A, PIN 4
+                  5
+                
+                
+                  GPIOA_5
+                  GPIO A, PIN 5
+                  6
+                
+                
+                  GPIOA_6
+                  GPIO A, PIN 6
+                  7
+                
+                
+                  GPIOA_7
+                  GPIO A, PIN 7
+                  8
+                
+                
+                  GPIOB_0
+                  GPIO B, PIN 0
+                  9
+                
+                
+                  GPIOB_1
+                  GPIO B, PIN 1
+                  10
+                
+                
+                  GPIOB_2
+                  GPIO B, PIN 2
+                  11
+                
+                
+                  GPIOB_3
+                  GPIO B, PIN 3
+                  12
+                
+                
+                  GPIOC_0
+                  GPIO C, PIN 0
+                  13
+                
+                
+                  GPIOC_5
+                  GPIO C, PIN 1
+                  14
+                
+                
+                  GPIOC_6
+                  GPIO C, PIN 2
+                  15
+                
+              
+            
+
+            
+            
+              CAPEDGE
+              Capture Edge, select which Edge should result in a counter increment or decrement
+              [17:16]
+              read-write
+              
+                
+                  RISING
+                  Only rising edges result in a counter increment or decrement
+                  0
+                
+                
+                  FALLING
+                  Only falling edges  result in a counter increment or decrement
+                  1
+                
+                
+                  BOTH
+                  Rising and falling edges result in a counter increment or decrement
+                  2
+                
+              
+            
+
+            
+            
+              TRGEXT
+              Triggers an other Peripheral
+              [21:20]
+              read-write
+              
+                
+                  NONE
+                  No Trigger is emitted
+                  0
+                
+                
+                  DMA1
+                  DMA Controller 1 is triggered, dependant on MODE
+                  1
+                
+                
+                  DMA2
+                  DMA Controller 2 is triggered, dependant on MODE
+                  2
+                
+                
+                  UART
+                  UART is triggered, dependant on MODE
+                  3
+                
+              
+            
+
+            
+            
+              RELOAD
+              Select RELOAD Register n to reload Timer on condition
+              [25:24]
+              read-write
+              
+                
+                  RELOAD0
+                  Selects Reload Register number 0
+                  0
+                
+                
+                  RELOAD1
+                  Selects Reload Register number 1
+                  1
+                
+                
+                  RELOAD2
+                  Selects Reload Register number 2
+                  2
+                
+                
+                  RELOAD3
+                  Selects Reload Register number 3
+                  3
+                
+              
+            
+
+            
+            
+              IDR
+              Selects, if Reload Register number is incremented, decremented or not modified
+              [27:26]
+              read-write
+              
+                
+                  KEEP
+                  Reload Register number does not change automatically
+                  0
+                
+                
+                  INCREMENT
+                  Reload Register number is incremented on each match
+                  1
+                
+                
+                  DECREMENT
+                  Reload Register number is decremented on each match
+                  2
+                
+              
+            
+
+            
+            
+              S
+              Starts and Stops the Timer / Counter
+              [31:31]
+              read-write
+              
+                
+                  STOP
+                  Timer / Counter is stopped
+                  0
+                
+                
+                  START
+                  Timer / Counter is started
+                  1
+                
+              
+            
+          
+        
+
+        
+        
+          SR
+          Status Register
+          0x04
+          16
+          read-write
+          0x00000000
+          0xD701
+
+          
+            
+            
+              RUN
+              Shows if Timer is running or not
+              [0:0]
+              read-only
+              
+                
+                  Stopped
+                  Timer is not running
+                  0
+                
+                
+                  Running
+                  Timer is running
+                  1
+                
+              
+            
+
+            
+            
+              MATCH
+              Shows if the MATCH was hit
+              [8:8]
+              read-write
+              
+                
+                  No_Match
+                  The MATCH condition was not hit
+                  0
+                
+                
+                  Match_Hit
+                  The MATCH condition was hit
+                  1
+                
+              
+            
+
+            
+            
+              UN
+              Shows if an underflow occured. This flag is sticky
+              [9:9]
+              read-write
+              
+                
+                  No_Underflow
+                  No underflow occured since last clear
+                  0
+                
+                
+                  Underflow
+                  A minimum of one underflow occured since last clear
+                  1
+                
+              
+            
+
+            
+            
+              OV
+              Shows if an overflow occured. This flag is sticky
+              [10:10]
+              read-write
+              
+                
+                  No_Overflow
+                  No overflow occured since last clear
+                  0
+                
+                
+                  Overflow_occured
+                  A minimum of one overflow occured since last clear
+                  1
+                
+              
+            
+
+            
+            
+              RST
+              Shows if Timer is in RESET state
+              [12:12]
+              read-only
+              
+                
+                  Ready
+                  Timer is not in RESET state and can operate
+                  0
+                
+                
+                  In_Reset
+                  Timer is in RESET state and can not operate
+                  1
+                
+              
+            
+
+            
+            
+              RELOAD
+              Shows the currently active RELOAD Register
+              [15:14]
+              read-only
+              
+                
+                  RELOAD0
+                  Reload Register number 0 is active
+                  0
+                
+                
+                  RELOAD1
+                  Reload Register number 1 is active
+                  1
+                
+                
+                  RELOAD2
+                  Reload Register number 2 is active
+                  2
+                
+                
+                  RELOAD3
+                  Reload Register number 3 is active
+                  3
+                
+              
+            
+          
+        
+
+        
+        
+          INT
+          Interrupt Register
+          0x10
+          16
+          read-write
+          0x00000000
+          0x0771
+
+          
+            
+            
+              EN
+              Interrupt Enable
+              [0:0]
+              read-write
+              
+                
+                  Disabled
+                  Timer does not generate Interrupts
+                  0
+                
+                
+                  Enable
+                  Timer triggers the TIMERn Interrupt
+                  1
+                
+              
+            
+
+            
+            
+              MODE
+              Interrupt Mode, selects on which condition the Timer should generate an Interrupt
+              [6:4]
+              read-write
+              
+                
+                  Match
+                  Timer generates an Interrupt when the MATCH condition is hit
+                  0
+                
+                
+                  Underflow
+                  Timer generates an Interrupt when it underflows
+                  1
+                
+                
+                  Overflow
+                  Timer generates an Interrupt when it overflows
+                  2
+                
+              
+            
+          
+        
+
+        
+        
+          COUNT
+          The Counter Register reflects the actual Value of the Timer/Counter
+          0x20
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+
+        
+        
+          MATCH
+          The Match Register stores the compare Value for the MATCH condition
+          0x24
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+        
+        
+        
+          PRESCALE_RD
+          The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value
+          0x28
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+        
+        
+        
+        
+          PRESCALE_WR
+          The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value
+          0x28
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+        
+
+
+        
+        
+          4
+          4
+          0,1,2,3
+          RELOAD[%s]
+          The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.
+          0x50
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+      
+    
+
+    
+    
+      TIMER1
+      0x40010100
+      
+        TIMER1
+        4
+      
+    
+
+    
+    
+      TIMER2
+      0x40010200
+      
+        TIMER2
+        6
+      
+    
+  
+
diff --git a/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd b/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 0000000000..e0ea55d50e
--- /dev/null
+++ b/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,274 @@
+
+
+
+
+  
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+         
+     
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+        
+        
+        
+        
+        
+        
+        
+          
+            
+              
+                
+                  
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                      
+                        
+                          
+                            
+                              
+                                
+                                 
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                  
+                                    
+                                      
+                                      
+                                        
+                                          
+                                          
+                                          
+                                            
+                                            
+                                            
+                                          
+                                          
+                                          
+                                          
+                                          
+                                          
+                                            
+                                              
+                                                
+                                                
+                                                
+                                                  
+                                                    
+                                                      
+                                                      
+                                                      
+                                                        
+                                                        
+                                                      
+                                                    
+                                                  
+                                                
+                                              
+                                              
+                                            
+                                          
+                                        
+                                        
+                                      
+                                    
+                                    
+                                  
+                                
+                              
+                              
+                            
+                          
+                        
+                      
+                    
+                  
+                  
+                
+              
+            
+          
+        
+        
+          
+            
+              
+              
+            
+          
+        
+      
+      
+    
+  
+
diff --git a/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd b/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd
new file mode 100644
index 0000000000..e3d431a813
--- /dev/null
+++ b/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd
@@ -0,0 +1,509 @@
+
+
+
+
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+    
+  
+  
+  
+  
+    
+      
+    
+  
+  
+  
+  
+    
+      
+    
+  
+
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+      
+    
+  
+  
+  
+    
+      
+    
+  
+  
+  
+    
+      
+      
+      
+        
+          
+            
+            
+          
+        
+      
+    
+  
+  
+  
+    
+      
+      
+      
+        
+          
+            
+            
+            
+          
+        
+      
+    
+  
+  
+  
+    
+      
+      
+      
+    
+  
+    
+  
+    
+      
+      
+      
+      
+    
+  
+  
+  
+    
+      
+      
+    
+  
+  
+  
+    
+      
+         
+     
+  
+  
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+        
+          
+            
+            
+            
+            
+            
+              
+              
+              
+            
+          
+        
+      
+    
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+        
+        
+        
+        
+        
+        
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+        
+        
+        
+        
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+  
+
+  
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+  
+
+  
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+  
+  
+  
+  
+  
+  
+    
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+
+        
+        
+          
+            
+              
+            
+          
+        
+
+        
+        
+          
+            
+              
+              
+            
+          
+        
+      
+      
+    
+  
+
diff --git a/CMSIS/SVD/SVDConv.exe b/CMSIS/SVD/SVDConv.exe
new file mode 100644
index 0000000000..6008adc23f
Binary files /dev/null and b/CMSIS/SVD/SVDConv.exe differ
diff --git a/CMSIS/index.html b/CMSIS/index.html
new file mode 100644
index 0000000000..3d57a19190
--- /dev/null
+++ b/CMSIS/index.html
@@ -0,0 +1,14 @@
+
+
+
+Redirect to the CMSIS main page after 0 seconds
+
+
+
+
+
+
+If the automatic redirection is failing, click open CMSIS Documentation.
+
+
+
diff --git a/apps/examples/math_demo/Makefile b/apps/examples/math_demo/Makefile
new file mode 100644
index 0000000000..a1105899a7
--- /dev/null
+++ b/apps/examples/math_demo/Makefile
@@ -0,0 +1,42 @@
+############################################################################
+#
+#   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name PX4 nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+#
+# Basic example application
+#
+
+APPNAME		 = math_demo
+PRIORITY	 = SCHED_PRIORITY_DEFAULT
+STACKSIZE	 = 8192
+
+include $(APPDIR)/mk/app.mk
diff --git a/apps/examples/math_demo/math_demo.cpp b/apps/examples/math_demo/math_demo.cpp
new file mode 100644
index 0000000000..4df082877d
--- /dev/null
+++ b/apps/examples/math_demo/math_demo.cpp
@@ -0,0 +1,110 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *   Author: @author Example User 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file math_demo.cpp
+ * Demonstration of math library
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * Management function.
+ */
+extern "C" __EXPORT int math_demo_main(int argc, char *argv[]);
+
+/**
+ * Test function
+ */
+void test();
+
+/**
+ * Print the correct usage.
+ */
+static void usage(const char *reason);
+
+static void
+usage(const char *reason)
+{
+    if (reason)
+        fprintf(stderr, "%s\n", reason);
+    fprintf(stderr, "usage: math_demo {test}\n\n");
+    exit(1);
+}
+
+/**
+ * The deamon app only briefly exists to start
+ * the background job. The stack size assigned in the
+ * Makefile does only apply to this management task.
+ * 
+ * The actual stack size should be set in the call
+ * to task_create().
+ */
+int math_demo_main(int argc, char *argv[])
+{
+
+    if (argc < 1)
+        usage("missing command");
+
+    if (!strcmp(argv[1], "test")) {
+        test();
+        exit(0);
+    }
+
+    usage("unrecognized command");
+    exit(1);
+}
+
+void test()
+{
+    printf("beginning math lib test\n");
+    using namespace math;
+    vectorTest();
+    matrixTest();
+    vector3Test();
+    eulerAnglesTest();
+    quaternionTest();
+    dcmTest();
+}
diff --git a/apps/systemlib/math/Dcm.cpp b/apps/systemlib/math/Dcm.cpp
new file mode 100644
index 0000000000..1e9c4ee6d0
--- /dev/null
+++ b/apps/systemlib/math/Dcm.cpp
@@ -0,0 +1,136 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Dcm.cpp
+ *
+ * math direction cosine matrix
+ */
+
+#include 
+
+#include "Dcm.hpp"
+#include "Quaternion.hpp"
+#include "EulerAngles.hpp"
+#include "Vector3.hpp"
+
+namespace math
+{
+
+Dcm::Dcm() :
+    Matrix(Matrix::identity(3))
+{
+}
+
+Dcm::Dcm(const float * data) :
+    Matrix(3,3,data)
+{
+}
+
+Dcm::Dcm(const Quaternion & q) :
+    Matrix(3,3)
+{
+    Dcm & dcm = *this;
+    float a = q.getA();
+    float b = q.getB();
+    float c = q.getC();
+    float d = q.getD();
+    float aSq = a*a;
+    float bSq = b*b;
+    float cSq = c*c;
+    float dSq = d*d;
+    dcm(0,0) = aSq + bSq - cSq - dSq;
+    dcm(0,1) = 2*(b*c - a*d);
+    dcm(0,2) = 2*(a*c + b*d);
+    dcm(1,0) = 2*(b*c + a*d);
+    dcm(1,1) = aSq - bSq + cSq - dSq;
+    dcm(1,2) = 2*(c*d - a*b);
+    dcm(2,0) = 2*(b*d - a*c);
+    dcm(2,1) = 2*(a*b + c*d);
+    dcm(2,2) = aSq - bSq - cSq + dSq;
+}
+
+Dcm::Dcm(const EulerAngles & euler) :
+    Matrix(3,3)
+{
+    Dcm & dcm = *this;
+    float cosPhi = cosf(euler.getPhi());
+    float sinPhi = sinf(euler.getPhi());
+    float cosThe = cosf(euler.getTheta());
+    float sinThe = sinf(euler.getTheta());
+    float cosPsi = cosf(euler.getPsi());
+    float sinPsi = sinf(euler.getPsi());
+
+    dcm(0,0) = cosThe*cosPsi;
+    dcm(0,1) = -cosPhi*sinPsi + sinPhi*sinThe*cosPsi;
+    dcm(0,2) = sinPhi*sinPsi + cosPhi*sinThe*cosPsi;
+
+    dcm(1,0) = cosThe*sinPsi;
+    dcm(1,1) = cosPhi*cosPsi + sinPhi*sinThe*sinPsi;
+    dcm(1,2) = -sinPhi*cosPsi + cosPhi*sinThe*sinPsi;
+
+    dcm(2,0) = -sinThe;
+    dcm(2,1) = sinPhi*cosThe;
+    dcm(2,2) = cosPhi*cosThe;
+}
+
+Dcm::Dcm(const Dcm & right) :
+    Matrix(right)
+{
+}
+
+Dcm::~Dcm()
+{
+}
+
+int __EXPORT dcmTest()
+{
+    printf("Test DCM\t\t: ");
+    Vector3 vB(1,2,3);
+    ASSERT(matrixEqual(Dcm(Quaternion(1,0,0,0)),
+                    Matrix::identity(3)));
+    ASSERT(matrixEqual(Dcm(EulerAngles(0,0,0)),
+                    Matrix::identity(3)));
+    ASSERT(vectorEqual(Vector3(-2,1,3),
+        Dcm(EulerAngles(0,0,M_PI_2_F))*vB));
+    ASSERT(vectorEqual(Vector3(3,2,-1),
+        Dcm(EulerAngles(0,M_PI_2_F,0))*vB));
+    ASSERT(vectorEqual(Vector3(1,-3,2),
+        Dcm(EulerAngles(M_PI_2_F,0,0))*vB));
+    ASSERT(vectorEqual(Vector3(3,2,-1),
+        Dcm(EulerAngles(
+                M_PI_2_F,M_PI_2_F,M_PI_2_F))*vB));
+    printf("PASS\n");
+    return 0;
+}
+} // namespace math
diff --git a/apps/systemlib/math/Dcm.hpp b/apps/systemlib/math/Dcm.hpp
new file mode 100644
index 0000000000..658d902faa
--- /dev/null
+++ b/apps/systemlib/math/Dcm.hpp
@@ -0,0 +1,95 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Dcm.hpp
+ *
+ * math direction cosine matrix
+ */
+
+//#pragma once
+
+#include "Vector.hpp"
+#include "Matrix.hpp"
+
+namespace math {
+
+class Quaternion;
+class EulerAngles;
+
+/**
+ * This is a Tait Bryan, Body 3-2-1 sequence.
+ * (yaw)-(pitch)-(roll)
+ * The Dcm transforms a vector in the body frame
+ * to the navigation frame, typically represented
+ * as C_nb. C_bn can be obtained through use 
+ * of the transpose() method.
+ */
+class __EXPORT Dcm : public Matrix
+{
+public:
+    /**
+     * default ctor
+     */
+    Dcm();
+
+    /**
+     * data ctor
+     */
+    Dcm(const float * data);
+
+    /**
+     * quaternion ctor
+     */
+    Dcm(const Quaternion & q);
+
+    /**
+     * euler angles ctor
+     */
+    Dcm(const EulerAngles & euler);
+
+    /**
+     * copy ctor (deep)
+     */
+    Dcm(const Dcm & right);
+
+    /**
+     * dtor
+     */
+    virtual ~Dcm();
+};
+
+int __EXPORT dcmTest();
+
+} // math
+
diff --git a/apps/systemlib/math/EulerAngles.cpp b/apps/systemlib/math/EulerAngles.cpp
new file mode 100644
index 0000000000..b530f172d8
--- /dev/null
+++ b/apps/systemlib/math/EulerAngles.cpp
@@ -0,0 +1,124 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Vector.cpp
+ *
+ * math vector
+ */
+
+#include 
+
+#include "EulerAngles.hpp"
+#include "Quaternion.hpp"
+#include "Dcm.hpp"
+#include "Vector3.hpp"
+
+namespace math
+{
+
+EulerAngles::EulerAngles() :
+    Vector(3)
+{
+    setPhi(0.0f);
+    setTheta(0.0f);
+    setPsi(0.0f);
+}
+
+EulerAngles::EulerAngles(float phi, float theta, float psi) :
+    Vector(3)
+{
+    setPhi(phi);
+    setTheta(theta);
+    setPsi(psi);
+}
+
+EulerAngles::EulerAngles(const Quaternion & q) :
+    Vector(3)
+{
+    (*this) = EulerAngles(Dcm(q));
+}
+
+EulerAngles::EulerAngles(const Dcm & dcm) :
+    Vector(3)
+{
+    setTheta(asinf(-dcm(2,0))); 
+    if (fabsf(getTheta() - M_PI_2_F) < 1.0e-3f)
+    {
+        setPhi(0.0f);
+        setPsi(atan2f(dcm(1,2) - dcm(0,1),
+            dcm(0,2) + dcm(1,1)) + getPhi());
+    }
+    else if (fabsf(getTheta() + M_PI_2_F) < 1.0e-3f)
+    {
+        setPhi(0.0f);
+        setPsi(atan2f(dcm(1,2) - dcm(0,1),
+            dcm(0,2) + dcm(1,1)) - getPhi());
+    }
+    else
+    {
+        setPhi(atan2f(dcm(2,1),dcm(2,2)));
+        setPsi(atan2f(dcm(1,0),dcm(0,0)));
+    }
+}
+
+EulerAngles::~EulerAngles()
+{
+}
+
+int __EXPORT eulerAnglesTest()
+{
+    printf("Test EulerAngles\t: ");
+    EulerAngles euler(1,2,3);
+
+    // test ctor
+    ASSERT(vectorEqual(Vector3(1,2,3),euler));
+    ASSERT(equal(euler.getPhi(),1));
+    ASSERT(equal(euler.getTheta(),2));
+    ASSERT(equal(euler.getPsi(),3));
+
+    // test dcm ctor
+
+    // test assignment
+    euler.setPhi(4);
+    ASSERT(equal(euler.getPhi(),4));
+    euler.setTheta(5);
+    ASSERT(equal(euler.getTheta(),5));
+    euler.setPsi(6);
+    ASSERT(equal(euler.getPsi(),6));
+    
+    printf("PASS\n");
+    return 0;
+}
+
+} // namespace math
diff --git a/apps/systemlib/math/EulerAngles.hpp b/apps/systemlib/math/EulerAngles.hpp
new file mode 100644
index 0000000000..59e5500ad0
--- /dev/null
+++ b/apps/systemlib/math/EulerAngles.hpp
@@ -0,0 +1,73 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Vector.h
+ *
+ * math vector
+ */
+
+#pragma once
+
+#include "Vector.hpp"
+
+namespace math {
+
+class Quaternion;
+class Dcm;
+
+class __EXPORT EulerAngles : public Vector
+{
+public:
+    EulerAngles();
+    EulerAngles(float phi, float theta, float psi);
+    EulerAngles(const Quaternion & q);
+    EulerAngles(const Dcm & dcm);
+    virtual ~EulerAngles();
+
+    // alias
+    void setPhi(float phi) { (*this)(0) = phi; }
+    void setTheta(float theta) { (*this)(1) = theta; }
+    void setPsi(float psi) { (*this)(2) = psi; }
+
+    // const accessors
+    const float & getPhi() const { return (*this)(0); }
+    const float & getTheta() const { return (*this)(1); }
+    const float & getPsi() const { return (*this)(2); }
+
+};
+
+int __EXPORT eulerAnglesTest();
+
+} // math
+
diff --git a/apps/systemlib/math/Matrix.cpp b/apps/systemlib/math/Matrix.cpp
new file mode 100644
index 0000000000..08796da89b
--- /dev/null
+++ b/apps/systemlib/math/Matrix.cpp
@@ -0,0 +1,180 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Matrix.cpp
+ *
+ * matrix code
+ */
+
+#include 
+#include 
+
+#include "Matrix.hpp"
+
+namespace math
+{
+
+static const float data_testA[] = 
+    {1,2,3,
+     4,5,6};
+static Matrix testA(2,3,data_testA);
+
+static const float data_testB[] = 
+    {0,1,3,
+     7,-1,2};
+static Matrix testB(2,3,data_testB);
+
+static const float data_testC[] = 
+    {0,1,
+     2,1,
+     3,2};
+static Matrix testC(3,2,data_testC);
+
+static const float data_testD[] = 
+    {0,1,2,
+     2,1,4,
+     5,2,0};
+static Matrix testD(3,3,data_testD);
+
+static const float data_testE[] = 
+    {1,-1,2,
+     0,2,3,
+     2,-1,1};
+static Matrix testE(3,3,data_testE);
+
+static const float data_testF[] = 
+    {3.777e006f, 2.915e007f, 0.000e000f,
+     2.938e007f, 2.267e008f, 0.000e000f,
+     0.000e000f, 0.000e000f, 6.033e008f};
+static Matrix testF(3,3,data_testF);
+
+int __EXPORT matrixTest()
+{
+    matrixAddTest();
+    matrixSubTest();
+    matrixMultTest();
+    matrixInvTest();
+    matrixDivTest();
+    return 0;
+}
+
+int matrixAddTest()
+{
+    printf("Test Matrix Add\t\t: ");
+    Matrix r = testA + testB;
+    float data_test[] =
+        { 1.0f, 3.0f, 6.0f,
+         11.0f, 4.0f, 8.0f};
+    ASSERT(matrixEqual(Matrix(2,3,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+int matrixSubTest()
+{
+    printf("Test Matrix Sub\t\t: ");
+    Matrix r = testA - testB;
+    float data_test[] =
+        { 1.0f, 1.0f, 0.0f,
+         -3.0f, 6.0f, 4.0f};
+    ASSERT(matrixEqual(Matrix(2,3,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+int matrixMultTest()
+{
+    printf("Test Matrix Mult\t: ");
+    Matrix r = testC * testB;
+    float data_test[] =
+        { 7.0f, -1.0f,  2.0f,
+          7.0f,  1.0f,  8.0f,
+         14.0f,  1.0f, 13.0f};
+    ASSERT(matrixEqual(Matrix(3,3,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+int matrixInvTest()
+{
+    printf("Test Matrix Inv\t\t: ");
+    Matrix origF = testF;
+    Matrix r = testF.inverse();
+    float data_test[] =
+        { -0.0012518f,  0.0001610f, 0.0000000f,
+           0.0001622f, -0.0000209f, 0.0000000f,
+           0.0000000f,  0.0000000f, 1.6580e-9f};
+    ASSERT(matrixEqual(Matrix(3,3,data_test),r));
+    // make sure F in unchanged
+    ASSERT(matrixEqual(origF,testF));
+    printf("PASS\n");
+    return 0;
+}
+
+int matrixDivTest()
+{
+    printf("Test Matrix Div\t\t: ");
+    Matrix r = testD / testE;
+    float data_test[] = {
+         0.2222222f, 0.5555556f, -0.1111111f,
+               0.0f,       1.0f,         1.0,
+        -4.1111111f, 1.2222222f,  4.5555556f};
+    ASSERT(matrixEqual(Matrix(3,3,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+bool matrixEqual(const Matrix & a, const Matrix & b, float eps)
+{
+    if (a.getRows() != b.getRows()) {
+        printf("row number not equal a: %d, b:%d\n", a.getRows(), b.getRows());
+        return false;
+    } else if (a.getCols() != b.getCols()) {
+        printf("column number not equal a: %d, b:%d\n", a.getCols(), b.getCols());
+        return false;
+    }
+    bool ret = true;
+    for (size_t i=0;i
+
+
+#include "Quaternion.hpp"
+#include "Dcm.hpp"
+#include "EulerAngles.hpp"
+
+namespace math
+{
+
+Quaternion::Quaternion() :
+    Vector(4)
+{
+    setA(1.0f);
+    setB(0.0f);
+    setC(0.0f);
+    setD(0.0f);
+}
+
+Quaternion::Quaternion(float a, float b,
+        float c, float d) :
+    Vector(4)
+{
+    setA(a);
+    setB(b);
+    setC(c);
+    setD(d);
+}
+
+Quaternion::Quaternion(const float * data) :
+    Vector(4,data)
+{
+}
+
+Quaternion::Quaternion(const Vector & v) :
+    Vector(v)
+{
+}
+
+Quaternion::Quaternion(const Dcm & dcm) :
+    Vector(4)
+{
+    setA(0.5f*sqrtf(1 + dcm(0,0) + 
+            dcm(1,1) + dcm(2,2)));
+    setB((dcm(2,1) - dcm(1,2))/
+            (4*getA()));
+    setC((dcm(0,2) - dcm(2,0))/
+        (4*getA()));
+    setD((dcm(1,0) - dcm(0,1))/
+        (4*getA()));
+}
+
+Quaternion::Quaternion(const EulerAngles & euler) :
+    Vector(4)
+{
+    float cosPhi_2 = cosf(euler.getPhi()/2.0f);
+    float cosTheta_2 = cosf(euler.getTheta()/2.0f);
+    float cosPsi_2 = cosf(euler.getPsi()/2.0f);
+    float sinPhi_2 = sinf(euler.getPhi()/2.0f);
+    float sinTheta_2 = sinf(euler.getTheta()/2.0f);
+    float sinPsi_2 = sinf(euler.getPsi()/2.0f);
+    setA(cosPhi_2*cosTheta_2*cosPsi_2 + 
+        sinPhi_2*sinTheta_2*sinPsi_2);
+    setB(sinPhi_2*cosTheta_2*cosPsi_2 -
+        cosPhi_2*sinTheta_2*sinPsi_2);
+    setC(cosPhi_2*sinTheta_2*cosPsi_2 +
+        sinPhi_2*cosTheta_2*sinPsi_2);
+    setD(cosPhi_2*cosTheta_2*sinPsi_2 +
+        sinPhi_2*sinTheta_2*cosPsi_2);
+}
+
+Quaternion::Quaternion(const Quaternion & right) :
+    Vector(right)
+{
+}
+
+Quaternion::~Quaternion()
+{
+}
+
+Vector Quaternion::derivative(const Vector & w)
+{
+#ifdef QUATERNION_ASSERT
+    ASSERT(w.getRows()==3);
+#endif
+    float dataQ[] = 
+    {getA(), -getB(), -getC(), -getD(),
+     getB(),  getA(), -getD(),  getC(),
+     getC(),  getD(),  getA(), -getB(),
+     getD(), -getC(),  getB(),  getA()};
+    Vector v(4);
+    v(0) = 0.0f;
+    v(1) = w(0);
+    v(2) = w(1);
+    v(3) = w(2);
+    Matrix Q(4,4,dataQ);
+    return Q*v*0.5f; 
+}
+
+int __EXPORT quaternionTest()
+{
+    printf("Test Quaternion\t\t: ");
+    // test default ctor
+    Quaternion q;
+    ASSERT(equal(q.getA(),1));  
+    ASSERT(equal(q.getB(),0));  
+    ASSERT(equal(q.getC(),0));  
+    ASSERT(equal(q.getD(),0));  
+    // test float ctor
+    q = Quaternion(0,1,0,0);
+    ASSERT(equal(q.getA(),0));  
+    ASSERT(equal(q.getB(),1));  
+    ASSERT(equal(q.getC(),0));  
+    ASSERT(equal(q.getD(),0));  
+    // test euler ctor
+    q = Quaternion(EulerAngles(0,0,0));
+    ASSERT(equal(q.getA(),1));  
+    ASSERT(equal(q.getB(),0));  
+    ASSERT(equal(q.getC(),0));  
+    ASSERT(equal(q.getD(),0));     
+    // test dcm ctor
+    q = Quaternion(Dcm());
+    ASSERT(equal(q.getA(),1));  
+    ASSERT(equal(q.getB(),0));  
+    ASSERT(equal(q.getC(),0));  
+    ASSERT(equal(q.getD(),0));     
+    // TODO test derivative
+    // test accessors
+    q.setA(0.1);
+    q.setB(0.2);
+    q.setC(0.3);
+    q.setD(0.4);
+    ASSERT(equal(q.getA(),0.1));  
+    ASSERT(equal(q.getB(),0.2));  
+    ASSERT(equal(q.getC(),0.3));  
+    ASSERT(equal(q.getD(),0.4));  
+    printf("PASS\n");
+    return 0;
+}
+
+} // namespace math
diff --git a/apps/systemlib/math/Quaternion.hpp b/apps/systemlib/math/Quaternion.hpp
new file mode 100644
index 0000000000..334b0dd036
--- /dev/null
+++ b/apps/systemlib/math/Quaternion.hpp
@@ -0,0 +1,114 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Quaternion.hpp
+ *
+ * math quaternion lib
+ */
+
+//#pragma once
+
+#include "Vector.hpp"
+#include "Matrix.hpp"
+
+namespace math {
+
+class Dcm;
+class EulerAngles;
+
+class __EXPORT Quaternion : public Vector
+{
+public:
+
+    /**
+     * default ctor
+     */
+    Quaternion();
+
+    /**
+     * ctor from floats
+     */
+    Quaternion(float a, float b, float c, float d);
+
+    /**
+     * ctor from data
+     */
+    Quaternion(const float * data);
+
+    /**
+     * ctor from Vector
+     */
+    Quaternion(const Vector & v);
+
+    /**
+     * ctor from EulerAngles
+     */
+    Quaternion(const EulerAngles & euler);
+
+    /**
+     * ctor from Dcm
+     */
+    Quaternion(const Dcm & dcm);
+
+    /**
+     * deep copy ctor
+     */
+    Quaternion(const Quaternion & right);
+
+    /**
+     * dtor
+     */
+    virtual ~Quaternion();
+    
+    /**
+     * derivative
+     */
+    Vector derivative(const Vector & w);
+
+    /**
+     * accessors
+     */
+    void setA(float a) { (*this)(0) = a; }
+    void setB(float b) { (*this)(1) = b; }
+    void setC(float c) { (*this)(2) = c; }
+    void setD(float d) { (*this)(3) = d; }
+    const float & getA() const { return (*this)(0); }
+    const float & getB() const { return (*this)(1); }
+    const float & getC() const { return (*this)(2); }
+    const float & getD() const { return (*this)(3); }
+};
+
+int __EXPORT quaternionTest();
+} // math
+
diff --git a/apps/systemlib/math/Vector.cpp b/apps/systemlib/math/Vector.cpp
new file mode 100644
index 0000000000..5bdbc91689
--- /dev/null
+++ b/apps/systemlib/math/Vector.cpp
@@ -0,0 +1,99 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Vector.cpp
+ *
+ * math vector
+ */
+
+#include 
+
+#include "Vector.hpp"
+
+namespace math
+{
+
+static const float data_testA[] = {1,3};
+static const float data_testB[] = {4,1};
+
+static Vector testA(2,data_testA);
+static Vector testB(2,data_testB);
+
+int __EXPORT vectorTest()
+{
+    vectorAddTest();
+    vectorSubTest();
+    return 0;
+}
+
+int vectorAddTest()
+{
+    printf("Test Vector Add\t\t: ");
+    Vector r = testA + testB;
+    float data_test[] = {5.0f, 4.0f};
+    ASSERT(vectorEqual(Vector(2,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+int vectorSubTest()
+{
+    printf("Test Vector Sub\t\t: ");
+    Vector r(2);
+    r = testA - testB;
+    float data_test[] = {-3.0f, 2.0f};
+    ASSERT(vectorEqual(Vector(2,data_test),r));
+    printf("PASS\n");
+    return 0;
+}
+
+bool vectorEqual(const Vector & a, const Vector & b, float eps)
+{
+    if (a.getRows() != b.getRows()) {
+        printf("row number not equal a: %d, b:%d\n", a.getRows(), b.getRows());
+        return false;
+    }
+    bool ret = true;
+    for (size_t i=0;i
+
+#include "Vector3.hpp"
+
+namespace math
+{
+
+Vector3::Vector3() :
+    Vector(3)
+{
+}
+
+Vector3::Vector3(const Vector & right) :
+    Vector(right)
+{
+#ifdef VECTOR_ASSERT
+    ASSERT(right.getRows()==3);
+#endif
+}
+
+Vector3::Vector3(float x, float y, float z) :
+    Vector(3)
+{
+    setX(x);
+    setY(y);
+    setZ(z);
+}
+
+Vector3::Vector3(const float * data) :
+    Vector(3,data)
+{
+}
+
+Vector3::~Vector3()
+{
+}
+
+Vector3 Vector3::cross(const Vector3 & b)
+{
+    Vector3 & a = *this;
+    Vector3 result;
+    result(0) = a(1)*b(2) - a(2)*b(1);
+    result(1) = a(2)*b(0) - a(0)*b(2);
+    result(2) = a(0)*b(1) - a(1)*b(0);
+    return result;
+}
+
+int __EXPORT vector3Test()
+{
+    printf("Test Vector3\t\t: ");
+    // test float ctor
+    Vector3 v(1,2,3);
+    ASSERT(equal(v(0),1)); 
+    ASSERT(equal(v(1),2)); 
+    ASSERT(equal(v(2),3)); 
+    printf("PASS\n");
+    return 0;
+}
+
+} // namespace math
diff --git a/apps/systemlib/math/Vector3.hpp b/apps/systemlib/math/Vector3.hpp
new file mode 100644
index 0000000000..48dfd5b22e
--- /dev/null
+++ b/apps/systemlib/math/Vector3.hpp
@@ -0,0 +1,71 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Vector3.hpp
+ *
+ * math 3 vector
+ */
+
+#pragma once
+
+#include "Vector.hpp"
+
+namespace math
+{
+
+class __EXPORT Vector3 :
+    public Vector
+{
+public:
+    Vector3();
+    Vector3(const Vector & right);
+    Vector3(float x, float y, float z);
+    Vector3(const float * data);
+    virtual ~Vector3();
+    Vector3 cross(const Vector3 & b);
+
+    /**
+     * accessors
+     */
+    void setX(float x) { (*this)(0) = x; }
+    void setY(float y) { (*this)(1) = y; }
+    void setZ(float z) { (*this)(2) = z; }
+    const float & getX() const { return (*this)(0); }
+    const float & getY() const { return (*this)(1); }
+    const float & getZ() const { return (*this)(2); }
+};
+
+int __EXPORT vector3Test();
+} // math
+
diff --git a/apps/systemlib/math/arm/Matrix.cpp b/apps/systemlib/math/arm/Matrix.cpp
new file mode 100644
index 0000000000..21661622ab
--- /dev/null
+++ b/apps/systemlib/math/arm/Matrix.cpp
@@ -0,0 +1,40 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Matrix.cpp
+ *
+ * matrix code
+ */
+
+#include "Matrix.hpp"
diff --git a/apps/systemlib/math/arm/Matrix.hpp b/apps/systemlib/math/arm/Matrix.hpp
new file mode 100644
index 0000000000..a949808723
--- /dev/null
+++ b/apps/systemlib/math/arm/Matrix.hpp
@@ -0,0 +1,312 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Matrix.h
+ *
+ * matrix code
+ */
+
+#pragma once
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+// arm specific
+#include "arm_math.h"
+
+namespace math
+{
+
+class __EXPORT Matrix {
+public:
+    // constructor
+    Matrix(size_t rows, size_t cols) :
+        _matrix()
+    {
+        arm_mat_init_f32(&_matrix,
+            rows, cols,
+            (float*)calloc(rows*cols,sizeof(float)));
+    }
+    Matrix(size_t rows, size_t cols, const float * data) :
+        _matrix()
+    {
+        arm_mat_init_f32(&_matrix,
+            rows, cols,
+            (float*)malloc(rows*cols*sizeof(float)));
+        memcpy(getData(),data,getSize());
+    }
+    // deconstructor
+    virtual ~Matrix()
+    {
+        delete [] _matrix.pData;
+    }
+    // copy constructor (deep)
+    Matrix(const Matrix & right) :
+        _matrix()
+    {
+        arm_mat_init_f32(&_matrix,
+            right.getRows(), right.getCols(),
+            (float*)malloc(right.getRows()*
+                right.getCols()*sizeof(float)));
+        memcpy(getData(),right.getData(),
+                getSize());
+    }
+    // assignment
+    inline Matrix & operator=(const Matrix & right)
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getRows()==right.getRows());
+        ASSERT(getCols()==right.getCols());
+#endif
+        if (this != &right)
+        {
+            memcpy(getData(),right.getData(),
+                        right.getSize());
+        }
+        return *this;
+    }
+    // element accessors
+    inline float & operator()(size_t i, size_t j)
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(i 1e-30f)
+                    return false;
+            }
+        }
+        return true;
+    }
+    // scalar ops
+    inline Matrix operator+(float right) const
+    {
+        Matrix result(getRows(), getCols());
+        arm_offset_f32((float *)getData(),right,
+                (float *)result.getData(),getRows()*getCols());
+        return result;
+    }
+    inline Matrix operator-(float right) const
+    {
+        Matrix result(getRows(), getCols());
+        arm_offset_f32((float *)getData(),-right,
+                (float *)result.getData(),getRows()*getCols());
+        return result;
+    }
+    inline Matrix operator*(float right) const
+    {
+        Matrix result(getRows(), getCols());
+        arm_mat_scale_f32(&_matrix,right,
+                &(result._matrix));
+        return result;
+    }
+    inline Matrix operator/(float right) const
+    {
+        Matrix result(getRows(), getCols());
+        arm_mat_scale_f32(&_matrix,1.0f/right,
+                &(result._matrix));
+        return result;
+    }
+    // vector ops
+    inline Vector operator*(const Vector & right) const
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getCols()==right.getRows());
+#endif
+        Matrix resultMat = (*this)*
+            Matrix(right.getRows(),1,right.getData());
+        return Vector(getRows(),resultMat.getData());
+    }
+    // matrix ops
+    inline Matrix operator+(const Matrix & right) const
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getRows()==right.getRows());
+        ASSERT(getCols()==right.getCols());
+#endif
+        Matrix result(getRows(), getCols());
+        arm_mat_add_f32(&_matrix, &(right._matrix),
+                &(result._matrix));
+        return result;
+    }
+    inline Matrix operator-(const Matrix & right) const
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getRows()==right.getRows());
+        ASSERT(getCols()==right.getCols());
+#endif
+        Matrix result(getRows(), getCols());
+        arm_mat_sub_f32(&_matrix, &(right._matrix),
+                &(result._matrix));
+        return result;
+    }
+    inline Matrix operator*(const Matrix & right) const
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getCols()==right.getRows());
+#endif
+        Matrix result(getRows(), right.getCols());
+        arm_mat_mult_f32(&_matrix, &(right._matrix),
+                &(result._matrix));
+        return result;
+    }
+    inline Matrix operator/(const Matrix & right) const
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(right.getRows()==right.getCols());
+        ASSERT(getCols()==right.getCols());
+#endif
+        return (*this)*right.inverse();
+    }
+    // other functions
+    inline Matrix transpose() const
+    {
+        Matrix result(getCols(),getRows());
+        arm_mat_trans_f32(&_matrix, &(result._matrix));
+        return result;
+    }
+    inline void swapRows(size_t a, size_t b)
+    {
+        if (a==b) return;
+        for(size_t j=0;j
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+// arm specific
+#include "arm_math.h"
+
+namespace math
+{
+
+class __EXPORT Vector {
+public:
+    // constructor
+    Vector(size_t rows) :
+        _rows(rows),
+        _data((float*)calloc(rows,sizeof(float)))
+    {
+    }
+    Vector(size_t rows, const float * data) :
+        _rows(rows),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),data,getSize());
+    }
+    // deconstructor
+    virtual ~Vector()
+    {
+        delete [] getData();
+    }
+    // copy constructor (deep)
+    Vector(const Vector & right) :
+        _rows(right.getRows()),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),right.getData(),
+                    right.getSize());
+    }
+    // assignment
+    inline Vector & operator=(const Vector & right)
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(getRows()==right.getRows());
+#endif
+        if (this != &right)
+        {
+            memcpy(getData(),right.getData(),
+                        right.getSize());
+        }
+        return *this;
+    }
+    // element accessors
+    inline float& operator()(size_t i)
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(i 1e-30f)
+                return false;
+        }
+        return true;
+    }
+    // scalar ops
+    inline Vector operator+(float right) const
+    {
+        Vector result(getRows());
+        arm_offset_f32((float*)getData(),
+                right, result.getData(),
+                getRows());
+        return result;
+    }
+    inline Vector operator-(float right) const
+    {
+        Vector result(getRows());
+        arm_offset_f32((float*)getData(),
+                -right, result.getData(),
+                getRows());
+        return result;
+    }
+    inline Vector operator*(float right) const
+    {
+        Vector result(getRows());
+        arm_scale_f32((float*)getData(),
+                right, result.getData(),
+                getRows());
+        return result;
+    }
+    inline Vector operator/(float right) const
+    {
+        Vector result(getRows());
+        arm_scale_f32((float*)getData(),
+                1.0f/right, result.getData(),
+                getRows());
+        return result;
+    }
+    // vector ops
+    inline Vector operator+(const Vector & right) const
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(getRows()==right.getRows());
+#endif
+        Vector result(getRows());
+        arm_add_f32((float*)getData(),
+                (float*)right.getData(),
+                result.getData(),
+                getRows());
+        return result;
+    }
+    inline Vector operator-(const Vector & right) const
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(getRows()==right.getRows());
+#endif
+        Vector result(getRows());
+        arm_sub_f32((float*)getData(),
+                (float*)right.getData(),
+                result.getData(),
+                getRows());
+        return result;
+    }
+    // other functions
+    inline float dot(const Vector & right)
+    {
+        float result = 0;
+        arm_dot_prod_f32((float*)getData(),
+                (float*)right.getData(),
+                getRows(),
+                &result);
+        return result;
+    }
+    inline float norm()
+    {
+        return sqrtf(dot(*this));
+    }
+    inline Vector unit()
+    {
+        return (*this)/norm();
+    }
+    inline static Vector zero(size_t rows)
+    {
+        Vector result(rows);
+        // calloc returns zeroed memory
+        return result;
+    }
+    inline void setAll(const float & val)
+    {
+        for (size_t i=0;i
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+namespace math
+{
+
+class __EXPORT Matrix {
+public:
+    // constructor
+    Matrix(size_t rows, size_t cols) :
+        _rows(rows),
+        _cols(cols),
+        _data((float*)calloc(rows*cols,sizeof(float)))
+    {
+    }
+    Matrix(size_t rows, size_t cols, const float * data) :
+        _rows(rows),
+        _cols(cols),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),data,getSize());
+    }
+    // deconstructor
+    virtual ~Matrix()
+    {
+        delete [] getData();
+    }
+    // copy constructor (deep)
+    Matrix(const Matrix & right) :
+        _rows(right.getRows()),
+        _cols(right.getCols()),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),right.getData(),
+                    right.getSize());
+    }
+    // assignment
+    inline Matrix & operator=(const Matrix & right)
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(getRows()==right.getRows());
+        ASSERT(getCols()==right.getCols());
+#endif
+        if (this != &right)
+        {
+            memcpy(getData(),right.getData(),
+                        right.getSize());
+        }
+        return *this;
+    }
+    // element accessors
+    inline float & operator()(size_t i, size_t j)
+    {
+#ifdef MATRIX_ASSERT
+        ASSERT(i 1e-30f)
+                    return false;
+            }
+        }
+        return true;
+    }
+    // scalar ops
+    inline Matrix operator+(const float & right) const
+    {
+        Matrix result(getRows(), getCols());
+        for (size_t i=0; i1e-8f) {
+                        //printf("swapped %d\n",i);
+                        U.swapRows(i,n);
+                        P.swapRows(i,n);
+                    }
+                }
+            }
+#ifdef MATRIX_ASSERT
+            //printf("A:\n"); A.print();
+            //printf("U:\n"); U.print();
+            //printf("P:\n"); P.print();
+            //fflush(stdout);
+            ASSERT(fabsf(U(n,n))>1e-8f);
+#endif
+            // failsafe, return zero matrix
+            if (fabsf(U(n,n))<1e-8f)
+            {
+                return Matrix::zero(n);
+            }
+
+            // for all rows below diagonal
+            for (size_t i=(n+1); i
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+namespace math
+{
+
+class __EXPORT Vector {
+public:
+    // constructor
+    Vector(size_t rows) :
+        _rows(rows),
+        _data((float*)calloc(rows,sizeof(float)))
+    {
+    }
+    Vector(size_t rows, const float * data) :
+        _rows(rows),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),data,getSize());
+    }
+    // deconstructor
+    virtual ~Vector()
+    {
+        delete [] getData();
+    }
+    // copy constructor (deep)
+    Vector(const Vector & right) :
+        _rows(right.getRows()),
+        _data((float*)malloc(getSize()))
+    {
+        memcpy(getData(),right.getData(),
+                    right.getSize());
+    }
+    // assignment
+    inline Vector & operator=(const Vector & right)
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(getRows()==right.getRows());
+#endif
+        if (this != &right)
+        {
+            memcpy(getData(),right.getData(),
+                        right.getSize());
+        }
+        return *this;
+    }
+    // element accessors
+    inline float& operator()(size_t i)
+    {
+#ifdef VECTOR_ASSERT
+        ASSERT(i 1e-30f)
+                return false;
+        }
+        return true;
+    }
+    // scalar ops
+    inline Vector operator+(const float & right) const
+    {
+        Vector result(getRows());
+        for (size_t i=0; i