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STM32 ADC driver update

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4208 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2011-12-20 23:44:21 +00:00
parent 468bf27b12
commit 67609317a5
4 changed files with 314 additions and 114 deletions
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nuttx/TODO
+12 -2
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@@ -1,4 +1,4 @@
NuttX TODO List (Last updated December 3, 2011)
NuttX TODO List (Last updated December 20, 2011)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements.
nuttx/
(5) Task/Scheduler (sched/)
(6) Task/Scheduler (sched/)
(1) On-demand paging (sched/)
(1) Memory Managment (mm/)
(2) Signals (sched/, arch/)
@@ -87,6 +87,16 @@ o Task/Scheduler (sched/)
Priority: Medium, required for standard compliance (but makes the
code bigger)
Title: TICKLESS OS
Description: On a side note, I have thought about a tick-less timer for the OS
for a long time. Basically we could replace the periodic system
timer interrupt with a one-shot interval timer programmed for the
next interesting event time. That is one way to both reduce the
timer interrupt overhead and also to increase the accuracy of
delays.
Status: Open
Priority: Low
o On-demand paging (sched/)
^^^^^^^^^^^^^^^^^^^^^^^^^
nuttx/arch/arm/src/stm32/stm32_adc.c
+243 -93
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File diff suppressed because it is too large Load Diff
nuttx/arch/arm/src/stm32/stm32_adc.h
+21 -18
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@@ -168,27 +168,27 @@
#if defined(CONFIG_STM32_TIM1_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM1_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32_TIM2_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM2_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32_TIM3_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM3_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM4_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM5_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM5_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32_TIM8_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM8_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
#else
# undef ADC1_HAVE_TIMER
#endif
@@ -206,27 +206,27 @@
#if defined(CONFIG_STM32_TIM1_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM1_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32_TIM2_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM2_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32_TIM3_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM3_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM4_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM5_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM5_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32_TIM8_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM8_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
#else
# undef ADC2_HAVE_TIMER
#endif
@@ -244,27 +244,27 @@
#if defined(CONFIG_STM32_TIM1_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM1_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32_TIM2_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM2_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32_TIM3_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM3_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM4_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM5_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM5_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32_TIM8_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM8_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
#else
# undef ADC3_HAVE_TIMER
#endif
@@ -281,6 +281,9 @@
#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER)
# define ADC_HAVE_TIMER 1
# if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FORCEPOWER)
# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)"
# endif
#else
# undef ADC_HAVE_TIMER
#endif
nuttx/drivers/mtd/m25px.c
+38 -1
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@@ -67,7 +67,10 @@
# define CONFIG_MP25P_SPIMODE SPIDEV_MODE0
#endif
/* Various manufacturers may have produced the parts */
/* Various manufacturers may have produced the parts. 0x20 is the manufacturer ID
* for the STMicro MP25x serial FLASH. If, for example, you are using the a Macronix
* International MX25 serial FLASH, the correct manufacturer ID would be 0xc2.
*/
#ifndef CONFIG_MP25P_MANUFACTURER
# define CONFIG_MP25P_MANUFACTURER 0x20
@@ -317,6 +320,34 @@ static void m25p_waitwritecomplete(struct m25p_dev_s *priv)
{
uint8_t status;
/* Are we the only device on the bus? */
#ifdef CONFIG_SPI_OWNBUS
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, M25P_RDSR);
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, M25P_DUMMY);
}
while ((status & M25P_SR_WIP) != 0);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
#else
/* Loop as long as the memory is busy with a write cycle */
do
@@ -337,6 +368,11 @@ static void m25p_waitwritecomplete(struct m25p_dev_s *priv)
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
/* Given that writing could take up to few tens of milliseconds, and erasing
* could take more. The following short delay in the "busy" case will allow
* other peripherals to access the SPI bus.
*/
if ((status & M25P_SR_WIP) != 0)
{
m25p_unlock(priv->dev);
@@ -345,6 +381,7 @@ static void m25p_waitwritecomplete(struct m25p_dev_s *priv)
}
}
while ((status & M25P_SR_WIP) != 0);
#endif
fvdbg("Complete\n");
}