diff --git a/boards/ark/fmu-v6x/nuttx-config/include/board.h b/boards/ark/fmu-v6x/nuttx-config/include/board.h
index c3aa8d36850..fa82671a826 100644
--- a/boards/ark/fmu-v6x/nuttx-config/include/board.h
+++ b/boards/ark/fmu-v6x/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/cuav/nora/nuttx-config/include/board.h b/boards/cuav/nora/nuttx-config/include/board.h
index ad4b16fbd51..9aaf12fcdaf 100644
--- a/boards/cuav/nora/nuttx-config/include/board.h
+++ b/boards/cuav/nora/nuttx-config/include/board.h
@@ -192,7 +192,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/cuav/x7pro/nuttx-config/include/board.h b/boards/cuav/x7pro/nuttx-config/include/board.h
index ad4b16fbd51..9aaf12fcdaf 100644
--- a/boards/cuav/x7pro/nuttx-config/include/board.h
+++ b/boards/cuav/x7pro/nuttx-config/include/board.h
@@ -192,7 +192,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/cubepilot/cubeorange/nuttx-config/include/board.h b/boards/cubepilot/cubeorange/nuttx-config/include/board.h
index 3a4abd0235e..5827b1bc81d 100644
--- a/boards/cubepilot/cubeorange/nuttx-config/include/board.h
+++ b/boards/cubepilot/cubeorange/nuttx-config/include/board.h
@@ -192,7 +192,7 @@
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 
 /* FLASH wait states */
 #define BOARD_FLASH_WAITSTATES 2
diff --git a/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h b/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h
index 00a886d0860..d650c616911 100644
--- a/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h
+++ b/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h
@@ -193,7 +193,7 @@
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 
 /* FLASH wait states */
 #define BOARD_FLASH_WAITSTATES 2
diff --git a/boards/holybro/durandal-v1/nuttx-config/include/board.h b/boards/holybro/durandal-v1/nuttx-config/include/board.h
index 2a475b7b49a..e1f43bf7b9c 100644
--- a/boards/holybro/durandal-v1/nuttx-config/include/board.h
+++ b/boards/holybro/durandal-v1/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/holybro/kakuteh7/nuttx-config/include/board.h b/boards/holybro/kakuteh7/nuttx-config/include/board.h
index 83245ff925a..4d3ed5eb476 100644
--- a/boards/holybro/kakuteh7/nuttx-config/include/board.h
+++ b/boards/holybro/kakuteh7/nuttx-config/include/board.h
@@ -245,7 +245,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/holybro/kakuteh7mini/nuttx-config/include/board.h b/boards/holybro/kakuteh7mini/nuttx-config/include/board.h
index 83245ff925a..4d3ed5eb476 100644
--- a/boards/holybro/kakuteh7mini/nuttx-config/include/board.h
+++ b/boards/holybro/kakuteh7mini/nuttx-config/include/board.h
@@ -245,7 +245,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/holybro/kakuteh7v2/nuttx-config/include/board.h b/boards/holybro/kakuteh7v2/nuttx-config/include/board.h
index 83245ff925a..4d3ed5eb476 100644
--- a/boards/holybro/kakuteh7v2/nuttx-config/include/board.h
+++ b/boards/holybro/kakuteh7v2/nuttx-config/include/board.h
@@ -245,7 +245,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/matek/h743-mini/nuttx-config/include/board.h b/boards/matek/h743-mini/nuttx-config/include/board.h
index 4bf2b6e45e0..f8afe3e6b87 100644
--- a/boards/matek/h743-mini/nuttx-config/include/board.h
+++ b/boards/matek/h743-mini/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 clock source */
 
diff --git a/boards/matek/h743-slim/nuttx-config/include/board.h b/boards/matek/h743-slim/nuttx-config/include/board.h
index 4bf2b6e45e0..f8afe3e6b87 100644
--- a/boards/matek/h743-slim/nuttx-config/include/board.h
+++ b/boards/matek/h743-slim/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 clock source */
 
diff --git a/boards/matek/h743/nuttx-config/include/board.h b/boards/matek/h743/nuttx-config/include/board.h
index 4bf2b6e45e0..f8afe3e6b87 100644
--- a/boards/matek/h743/nuttx-config/include/board.h
+++ b/boards/matek/h743/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 clock source */
 
diff --git a/boards/modalai/fc-v2/nuttx-config/include/board.h b/boards/modalai/fc-v2/nuttx-config/include/board.h
index 34a8d2c2af7..b196e7a68c7 100644
--- a/boards/modalai/fc-v2/nuttx-config/include/board.h
+++ b/boards/modalai/fc-v2/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h b/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h
index 9b1ae6342d3..d5ffa2c5848 100644
--- a/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h
+++ b/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h
@@ -192,7 +192,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h
index 9b1ae6342d3..d5ffa2c5848 100644
--- a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h
+++ b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h
@@ -192,7 +192,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h
index 78a0048760b..cdbd3dd3e62 100644
--- a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h
+++ b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h
@@ -191,7 +191,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/mro/pixracerpro/nuttx-config/include/board.h b/boards/mro/pixracerpro/nuttx-config/include/board.h
index 2377d529f46..5edda931dc1 100644
--- a/boards/mro/pixracerpro/nuttx-config/include/board.h
+++ b/boards/mro/pixracerpro/nuttx-config/include/board.h
@@ -191,7 +191,7 @@
 #define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2  /* SPI45 clock source */
 #define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2    /* SPI6 clock source */
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3    /* USB 1 and 2 clock source */
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/px4/fmu-v6c/nuttx-config/include/board.h b/boards/px4/fmu-v6c/nuttx-config/include/board.h
index 8042d466a7b..1951031cb82 100644
--- a/boards/px4/fmu-v6c/nuttx-config/include/board.h
+++ b/boards/px4/fmu-v6c/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/px4/fmu-v6u/nuttx-config/include/board.h b/boards/px4/fmu-v6u/nuttx-config/include/board.h
index a82a7bf098a..826c5df337b 100644
--- a/boards/px4/fmu-v6u/nuttx-config/include/board.h
+++ b/boards/px4/fmu-v6u/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* CAN FD clock source */
 #define STM32_FDCANCLK               STM32_HSE_FREQUENCY
diff --git a/boards/px4/fmu-v6x/nuttx-config/include/board.h b/boards/px4/fmu-v6x/nuttx-config/include/board.h
index eb3004183b0..5057ed713ec 100644
--- a/boards/px4/fmu-v6x/nuttx-config/include/board.h
+++ b/boards/px4/fmu-v6x/nuttx-config/include/board.h
@@ -248,7 +248,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* FDCAN 1 2 clock source */
 
diff --git a/boards/siyi/n7/nuttx-config/include/board.h b/boards/siyi/n7/nuttx-config/include/board.h
index d6b690c2932..1df145ed26d 100644
--- a/boards/siyi/n7/nuttx-config/include/board.h
+++ b/boards/siyi/n7/nuttx-config/include/board.h
@@ -222,7 +222,7 @@
 
 #define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3		/* USB 1 and 2 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2		/* ADC 1 2 3 clock source */
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2		/* ADC 1 2 3 clock source */
 
 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
 
diff --git a/boards/spracing/h7extreme/nuttx-config/include/board.h b/boards/spracing/h7extreme/nuttx-config/include/board.h
index 91edb4e650c..117edb76a74 100644
--- a/boards/spracing/h7extreme/nuttx-config/include/board.h
+++ b/boards/spracing/h7extreme/nuttx-config/include/board.h
@@ -241,7 +241,7 @@
 
 /* ADC 1 2 3 clock source */
 
-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
 
 /* QSPI clock source */
 #define STM32_RCC_D1CCIPR_QSPISEL    RCC_D1CCIPR_QSPISEL_PLL2
diff --git a/boards/spracing/h7extreme/src/rcc.c b/boards/spracing/h7extreme/src/rcc.c
index 9fc05848163..cd4299b880e 100644
--- a/boards/spracing/h7extreme/src/rcc.c
+++ b/boards/spracing/h7extreme/src/rcc.c
@@ -503,10 +503,10 @@ __ramfunc__ void stm32_board_clockconfig(void)
 
 		/* Configure ADC source clock */
 
-#if defined(STM32_RCC_D3CCIPR_ADCSEL)
+#if defined(STM32_RCC_D3CCIPR_ADCSRC)
 		regval = getreg32(STM32_RCC_D3CCIPR);
 		regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
-		regval |= STM32_RCC_D3CCIPR_ADCSEL;
+		regval |= STM32_RCC_D3CCIPR_ADCSRC;
 		putreg32(regval, STM32_RCC_D3CCIPR);
 #endif