|
diff --git a/nuttx/arch/arm/include/lpc43xx/irq.h b/nuttx/arch/arm/include/lpc43xx/irq.h
index 08fce71d1d..f2c899a442 100644
--- a/nuttx/arch/arm/include/lpc43xx/irq.h
+++ b/nuttx/arch/arm/include/lpc43xx/irq.h
@@ -116,8 +116,8 @@
#define LPC43M4_IRQ_PININT5 (LPC43_IRQ_EXTINT+37) /* GPIO pin interrupt 5 */
#define LPC43M4_IRQ_PININT6 (LPC43_IRQ_EXTINT+38) /* GPIO pin interrupt 6 */
#define LPC43M4_IRQ_PININT7 (LPC43_IRQ_EXTINT+39) /* GPIO pin interrupt 7 */
-#define LPC43M4_IRQ_GINT0 (LPC43_IRQ_EXTINT+40) /* GPIO global interrupt 0 */
-#define LPC43M4_IRQ_GINT1 (LPC43_IRQ_EXTINT+41) /* GPIO global interrupt 1 */
+#define LPC43M4_IRQ_GINT0 (LPC43_IRQ_EXTINT+40) /* GPIO group interrupt 0 */
+#define LPC43M4_IRQ_GINT1 (LPC43_IRQ_EXTINT+41) /* GPIO group interrupt 1 */
#define LPC43M4_IRQ_EVENTROUTER (LPC43_IRQ_EXTINT+42) /* Event router interrupt */
#define LPC43M4_IRQ_CAN1 (LPC43_IRQ_EXTINT+43) /* C_CAN1 interrupt */
#define LPC43M4_IRQ_ATIMER (LPC43_IRQ_EXTINT+46) /* ATIMER Alarm timer interrupt */
@@ -129,96 +129,11 @@
#define LPC43M4_IRQ_NEXTINT (53)
#define LPC43M4_IRQ_NIRQS (LPC43_IRQ_EXTINT+LPC43M4_IRQ_NEXTINT)
-/* Cortex-M4 GPIO interrupts. The LPC43xx supports several interrupts on ports 0 and 2
- * (only). We go through some special efforts to keep the number of IRQs to a minimum in
- * this sparse interrupt case.
- *
- * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
- * 14 interrupts on Port 2: p2.0 - p2.13
- * --
- * 42
- */
-
-#ifdef CONFIG_GPIO_IRQ
-# warning "REVISIT"
-# define LPC43M4_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */
-# define LPC43M4_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
-
- /* Set 1: 12 interrupts p0.0-p0.11 */
-
-# define LPC43M4_VALID_GPIOINT0L (0x00000ffful)
-# define LPC43M4_VALID_SHIFT0L (0)
-# define LPC43M4_VALID_FIRST0L (LPC43_IRQ_EXTINT+LPC43M4_IRQ_NEXTINT)
-
-# define LPC43M4_IRQ_P0p0 (LPC43M4_VALID_FIRST0L+0)
-# define LPC43M4_IRQ_P0p1 (LPC43M4_VALID_FIRST0L+1)
-# define LPC43M4_IRQ_P0p2 (LPC43M4_VALID_FIRST0L+2)
-# define LPC43M4_IRQ_P0p3 (LPC43M4_VALID_FIRST0L+3)
-# define LPC43M4_IRQ_P0p4 (LPC43M4_VALID_FIRST0L+4)
-# define LPC43M4_IRQ_P0p5 (LPC43M4_VALID_FIRST0L+5)
-# define LPC43M4_IRQ_P0p6 (LPC43M4_VALID_FIRST0L+6)
-# define LPC43M4_IRQ_P0p7 (LPC43M4_VALID_FIRST0L+7)
-# define LPC43M4_IRQ_P0p8 (LPC43M4_VALID_FIRST0L+8)
-# define LPC43M4_IRQ_P0p9 (LPC43M4_VALID_FIRST0L+9)
-# define LPC43M4_IRQ_P0p10 (LPC43M4_VALID_FIRST0L+10)
-# define LPC43M4_IRQ_P0p11 (LPC43M4_VALID_FIRST0L+11)
-# define LPC43M4_VALID_NIRQS0L (12)
-
- /* Set 2: 16 interrupts p0.15-p0.30 */
-
-# define LPC43M4_VALID_GPIOINT0H (0x7fff8000ull)
-# define LPC43M4_VALID_SHIFT0H (15)
-# define LPC43M4_VALID_FIRST0H (LPC43M4_VALID_FIRST0L+LPC43M4_VALID_NIRQS0L)
-
-# define LPC43M4_IRQ_P0p15 (LPC43M4_VALID_FIRST0H+0)
-# define LPC43M4_IRQ_P0p16 (LPC43M4_VALID_FIRST0H+1)
-# define LPC43M4_IRQ_P0p17 (LPC43M4_VALID_FIRST0H+2)
-# define LPC43M4_IRQ_P0p18 (LPC43M4_VALID_FIRST0H+3)
-# define LPC43M4_IRQ_P0p19 (LPC43M4_VALID_FIRST0H+4)
-# define LPC43M4_IRQ_P0p20 (LPC43M4_VALID_FIRST0H+5)
-# define LPC43M4_IRQ_P0p21 (LPC43M4_VALID_FIRST0H+6)
-# define LPC43M4_IRQ_P0p22 (LPC43M4_VALID_FIRST0H+7)
-# define LPC43M4_IRQ_P0p23 (LPC43M4_VALID_FIRST0H+8)
-# define LPC43M4_IRQ_P0p24 (LPC43M4_VALID_FIRST0H+9)
-# define LPC43M4_IRQ_P0p25 (LPC43M4_VALID_FIRST0H+10)
-# define LPC43M4_IRQ_P0p26 (LPC43M4_VALID_FIRST0H+11)
-# define LPC43M4_IRQ_P0p27 (LPC43M4_VALID_FIRST0H+12)
-# define LPC43M4_IRQ_P0p28 (LPC43M4_VALID_FIRST0H+13)
-# define LPC43M4_IRQ_P0p29 (LPC43M4_VALID_FIRST0H+14)
-# define LPC43M4_IRQ_P0p30 (LPC43M4_VALID_FIRST0H+15)
-# define LPC43M4_VALID_NIRQS0H (16)
-
- /* Set 3: 14 interrupts p2.0-p2.13 */
-
-# define LPC43M4_VALID_GPIOINT2 (0x00003ffful)
-# define LPC43M4_VALID_SHIFT2 (0)
-# define LPC43M4_VALID_FIRST2 (LPC43M4_VALID_FIRST0H+LPC43M4_VALID_NIRQS0H)
-
-# define LPC43M4_IRQ_P2p0 (LPC43M4_VALID_FIRST2+0)
-# define LPC43M4_IRQ_P2p1 (LPC43M4_VALID_FIRST2+1)
-# define LPC43M4_IRQ_P2p2 (LPC43M4_VALID_FIRST2+2)
-# define LPC43M4_IRQ_P2p3 (LPC43M4_VALID_FIRST2+3)
-# define LPC43M4_IRQ_P2p4 (LPC43M4_VALID_FIRST2+4)
-# define LPC43M4_IRQ_P2p5 (LPC43M4_VALID_FIRST2+5)
-# define LPC43M4_IRQ_P2p6 (LPC43M4_VALID_FIRST2+6)
-# define LPC43M4_IRQ_P2p7 (LPC43M4_VALID_FIRST2+7)
-# define LPC43M4_IRQ_P2p8 (LPC43M4_VALID_FIRST2+8)
-# define LPC43M4_IRQ_P2p9 (LPC43M4_VALID_FIRST2+9)
-# define LPC43M4_IRQ_P2p10 (LPC43M4_VALID_FIRST2+10)
-# define LPC43M4_IRQ_P2p11 (LPC43M4_VALID_FIRST2+11)
-# define LPC43M4_IRQ_P2p12 (LPC43M4_VALID_FIRST2+12)
-# define LPC43M4_IRQ_P2p13 (LPC43M4_VALID_FIRST2+13)
-# define LPC43M4_VALID_NIRQS2 (14)
-# define LPC43M4_NGPIOAIRQS (LPC43M4_VALID_NIRQS0L+LPC43M4_VALID_NIRQS0H+LPC43M4_VALID_NIRQS2)
-#else
-# define LPC43M4_NGPIOAIRQS (0)
-#endif
-
/* Total number of IRQ numbers (This will need to be revisited if/when the Cortex-M0 is
- * supported
+ * supported)
*/
-#define NR_IRQS (LPC43_IRQ_EXTINT+LPC43M4_IRQ_NEXTINT+LPC43M4_NGPIOAIRQS)
+#define NR_IRQS LPC43M4_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
@@ -263,21 +178,12 @@
#define LPC43M0_IRQ_NEXTINT (30)
#define LPC43M0_IRQ_NIRQS (LPC43_IRQ_EXTINT+LPC43M0_IRQ_NEXTINT)
-/* Cortex-M0 GPIO interrupts */
-
-#ifdef CONFIG_GPIO_IRQ
-# warning "REVISIT"
-# define LPC43M0_NGPIOAIRQS (0)
-#else
-# define LPC43M0_NGPIOAIRQS (0)
-#endif
-
/* Total number of IRQ numbers (This will need to be revisited if/when the Cortex-M0 is
* supported)
*/
#if 0
-#define NR_IRQS (LPC43_IRQ_EXTINT+LPC43M0_IRQ_NEXTINT+LPC43M0_NGPIOAIRQS)
+#define NR_IRQS LPC43M0_IRQ_NIRQS
#endif
/********************************************************************************************
diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs
index 071a9dd9e9..ee8b647c9a 100644
--- a/nuttx/arch/arm/src/lpc43xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc43xx/Make.defs
@@ -74,6 +74,10 @@ ifeq ($(CONFIG_LPC43_GPDMA),y)
CHIP_CSRCS += lpc43_gpdma.c
endif
+ifeq ($(CONFIG_GPIO_IRQ),y)
+CHIP_CSRCS += lpc43_gpioint.c
+endif
+
ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c
endif
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
index 05a214765d..036da2697c 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
@@ -248,14 +248,14 @@ static inline void lpc43_pll1enable(void)
}
/****************************************************************************
- * Name: lpc32_m4clkselect
+ * Name: lpc43_m4clkselect
*
* Description:
* Select PLL1 output as the Cortex-M4 source clock.
*
****************************************************************************/
-static inline void lpc32_m4clkselect(void)
+static inline void lpc43_m4clkselect(void)
{
uint32_t regval;
@@ -295,5 +295,5 @@ void lpc43_clockconfig(void)
/* Set up PLL1 output as the M4 clock */
- lpc32_m4clkselect();
+ lpc43_m4clkselect();
}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c b/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c
index 94237ab09c..00e8ebc42a 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/lpc43/lpc43_pinconfig.c
+ * arch/arm/src/lpc43/lpc43_pin_config.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -63,7 +63,7 @@
* Public Functions
****************************************************************************/
/****************************************************************************
- * Function: lpc43_dumppinconfig
+ * Function: lpc43_pin_dump
*
* Description:
* Dump all pin configuration registers associated with the provided pin
@@ -71,21 +71,21 @@
*
****************************************************************************/
-int lpc43_dumppinconfig(uint32_t pinconf, const char *msg)
+int lpc43_pin_dump(uint32_t pinconf, const char *msg)
{
#warning "Missing logic"
return -ENOSYS;
}
/********************************************************************************************
- * Function: lpc43_dumpgpio
+ * Function: lpc43_gpio_dump
*
* Description:
* Dump all pin configuration registers associated with the provided base address
*
********************************************************************************************/
-int lpc43_dumpgpio(uint16_t gpiocfg, const char *msg)
+int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg)
{
#warning "Missing logic"
return -ENOSYS;
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
index 36983b8eca..d1f3ec8599 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -42,8 +42,10 @@
#include
#include
+#include
-#include "lpc43_pinconfig.h"
+#include "up_arch.h"
+#include "lpc43_gpio.h"
/****************************************************************************
* Pre-processor Definitions
@@ -53,33 +55,159 @@
* Private Data
****************************************************************************/
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
/****************************************************************************
* Private Functions
****************************************************************************/
+/****************************************************************************
+ * Name: lpc43_configinput
+ *
+ * Description:
+ * Configure a GPIO pin as an input (or pre-configured the pin for an
+ * interrupt).
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_configinput(uint16_t gpiocfg,
+ unsigned int port, unsigned int pin)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+
+ /* Make sure that the pin is *not* configured as an interrupt */
+
+#ifdef CONFIG_GPIO_IRQ
+ (void)lpc43_gpioint_unconfig(gpiocfg)
+#endif
+
+ /* Then configure the pin as a normal input by clearing the corresponding
+ * bit in the GPIO DIR register for the port.
+ */
+
+ regaddr = LPC43_GPIO_DIR(port);
+ regval = getreg32(regaddr);
+ regval &= ~GPIO_DIR(pin);
+ putreg32(regval, regaddr);
+
+ /* To be able to read the signal on the GPIO input, the input
+ * buffer must be enabled in the syscon block for the corresponding pin.
+ * This should have been done when the pin was configured as a GPIO.
+ */
+}
+
+/****************************************************************************
+ * Name: lpc43_configoutput
+ *
+ * Description:
+ * Configure a GPIO pin as an output.
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_configoutput(uint16_t gpiocfg,
+ unsigned int port, unsigned int pin)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+
+ /* Make sure that the pin is *not* configured as an interrupt */
+
+#ifdef CONFIG_GPIO_IRQ
+ (void)lpc43_gpioint_unconfig(gpiocfg)
+#endif
+
+ /* Then configure the pin as an output by setting the corresponding
+ * bit in the GPIO DIR register for the port.
+ */
+
+ regaddr = LPC43_GPIO_DIR(port);
+ regval = getreg32(regaddr);
+ regval |= GPIO_DIR(pin);
+ putreg32(regval, regaddr);
+
+ /* Set the initial value of the output */
+
+ lpc43_gpio_write(gpiocfg, GPIO_IS_ONE(gpiocfg));
+
+ /* To be able to read the signal on the GPIO input, the input
+ * buffer must be enabled in the syscon block for the corresponding pin.
+ * This should have been done when the pin was configured as a GPIO.
+ */
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: lpc43_gpioconfig
+ * Name: lpc43_gpio_config
*
* Description:
- * Configure a GPIO based on bit-encoded description of the pin.
+ * Configure a GPIO based on bit-encoded description of the pin. NOTE:
+ * The pin *must* have first been configured for GPIO usage with a
+ * corresponding call to lpc43_pin_config().
*
* Returned Value:
* OK on success; A negated errno value on failure.
*
****************************************************************************/
-int lpc43_gpioconfig(uint16_t gpiocfg)
+int lpc43_gpio_config(uint16_t gpiocfg)
{
-#warning "Missing logic"
- return -ENOSYS;
+ unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ irqstate_t flags;
+ int ret = OK;
+
+ DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+ /* Handle the GPIO configuration by the basic mode of the pin */
+
+ flags = irqsave();
+ switch (gpiocfg & GPIO_PORT_MASK)
+ {
+ case GPIO_MODE_INPUT:
+ lpc43_configinput(gpiocfg, port, pin);
+ break;
+
+ case GPIO_MODE_OUTPUT:
+ lpc43_configoutput(gpiocfg, port, pin);
+ break;
+
+ case GPIO_MODE_INTERRUPT:
+ lpc43_configinput(gpiocfg, port, pin);
+#ifdef CONFIG_GPIO_IRQ
+ ret = lpc43_gpiointconfig(gpiocfg, port, pin);
+#endif
+ break;
+
+ default :
+ sdbg("ERROR: Unrecognized pin mode: %04x\n", gpiocfg);
+ ret = -EINVAL;
+ break;
+ }
+
+ irqrestore(flags);
+ return ret;
}
/****************************************************************************
- * Name: lpc43_gpiowrite
+ * Name: lpc43_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
@@ -89,13 +217,20 @@ int lpc43_gpioconfig(uint16_t gpiocfg)
*
****************************************************************************/
-void lpc43_gpiowrite(uint16_t gpiocfg, bool value)
+void lpc43_gpio_write(uint16_t gpiocfg, bool value)
{
-#warning "Missing logic"
+ unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+
+ DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+ /* Write the value (0 or 1). To the pin byte register */
+
+ putreg8((uint8_t)value, LPC43_GPIO_B(port, pin));
}
/****************************************************************************
- * Name: lpc43_gpioread
+ * Name: lpc43_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
@@ -105,10 +240,16 @@ void lpc43_gpiowrite(uint16_t gpiocfg, bool value)
*
****************************************************************************/
-bool lpc43_gpioread(uint16_t gpiocfg)
+bool lpc43_gpio_read(uint16_t gpiocfg)
{
-#warning "Missing logic"
- return false;
+ unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+
+ DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+ /* Get the value of the pin from the pin byte register */
+
+ return (getreg8(LPC43_GPIO_B(port, pin)) & GPIO_B) != 0;
}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
index d7615efa00..d3522197f7 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -51,6 +51,9 @@
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
+
+/* Max number of GPIO ports and the maximum number of pins per port */
+
#define NUM_GPIO_PORTS 8
#define NUM_GPIO_PINS 32
@@ -80,9 +83,9 @@
# define GPIO_MODE_OUTPUT (2 << GPIO_MODE_SHIFT)
# define GPIO_MODE_INTERRUPT (3 << GPIO_MODE_SHIFT)
-#define GPIO_IS_OUTPUT(p) ((p) & GPIO_MODE_MASK) == GPIO_MODE_INPUT)
-#define GPIO_IS_INPUT(p) ((p) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT)
-#define GPIO_IS_INTERRUPT(p) ((p) & GPIO_MODE_MASK) == GPIO_MODE_INTERRUPT)
+#define GPIO_IS_OUTPUT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_INPUT)
+#define GPIO_IS_INPUT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT)
+#define GPIO_IS_INTERRUPT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_INTERRUPT)
/* Initial value (for GPIO outputs only)
*
@@ -95,6 +98,9 @@
#define GPIO_VALUE_ONE (1 << 12) /* Bit 12: 1=High */
#define GPIO_VALUE_ZERO (0) /* Bit 12: 0=Low */
+#define GPIO_IS_ONE(p) (((p) & GPIO_VALUE_ONE) != 0)
+#define GPIO_IS_ZERO(p) (((p) & GPIO_VALUE_ONE) == 0)
+
/* Group Interrupt Selection (valid only for interrupt GPIO pins):
*
* 1111 1100 0000 0000
@@ -105,15 +111,15 @@
#define GPIO_GRPINT_SHIFT (11) /* Bits 11-12: Group interrupt selection */
#define GPIO_GRPINT_MASK (3 << GPIO_GRPINT_SHIFT)
-# define GPIO_GRPINT_NONE (0 << GPIO_GRPINT_SHIFT) /* 00 Not a member of a group */
+# define GPIO_GRPINT_NOGROUP (0 << GPIO_GRPINT_SHIFT) /* 00 Not a member of a group */
# define GPIO_GRPINT_GROUP0 (2 << GPIO_GRPINT_SHIFT) /* 10 Member of group 0 */
# define GPIO_GRPINT_GROUP1 (3 << GPIO_GRPINT_SHIFT) /* 11 Member of group 1 */
#define _GPIO_GRPINT (1 << (GPIO_GRPINT_SHIFT+1)) /* Bit 12: 1=Member of a group */
#define _GPIO_GRPNO (1 << GPIO_GRPINT_SHIFT) /* Bit 11: Group number */
-#define GPIO_IS_GRPINT(p) ((p) & _GPIO_GRPINT) != 0)
-#define GPIO_GRPPNO(p) ((p) & _GPIO_GRPNO) >> GPIO_GRPINT_SHIFT)
+#define GPIO_IS_GRPINT(p) (((p) & _GPIO_GRPINT) != 0)
+#define GPIO_GRPPNO(p) (((p) & _GPIO_GRPNO) >> GPIO_GRPINT_SHIFT)
/* Group Interrupt Polarity (valid only for interrupt GPIO group interrupts ):
*
@@ -149,10 +155,10 @@
#define _GPIO_ACTIVE_HI (1 << GPIO_INT_SHIFT)
#define _GPIO_EDGE (1 << (GPIO_INT_SHIFT+1))
-#define GPIO_IS_ACTIVE_HI(p) ((p) & _GPIO_ACTIVE_HI) != 0)
-#define GPIO_IS_ACTIVE_LOW(p) ((p) & _GPIO_ACTIVE_HI) == 0)
-#define GPIO_IS_EDGE(p) ((p) & _GPIO_EDGE) != 0)
-#define GPIO_IS_LEVEL(p) ((p) & _GPIO_EDGE) == 0)
+#define GPIO_IS_ACTIVE_HI(p) (((p) & _GPIO_ACTIVE_HI) != 0)
+#define GPIO_IS_ACTIVE_LOW(p) (((p) & _GPIO_ACTIVE_HI) == 0)
+#define GPIO_IS_EDGE(p) (((p) & _GPIO_EDGE) != 0)
+#define GPIO_IS_LEVEL(p) (((p) & _GPIO_EDGE) == 0)
/* GPIO Port Number:
*
@@ -162,16 +168,16 @@
* .... GPII .... ....
*/
-#define GPIO_PORT_SHIFT (4) /* Bits 4-6: Port number */
-#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
-# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
-# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
-# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
-# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
-# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
-# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
-# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT)
-# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT)
+#define GPIO_PORT_SHIFT (4) /* Bits 4-6: Port number */
+#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
+# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
+# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
+# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
+# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
+# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
+# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
+# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT)
+# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT)
/* GPIO Pin Number:
*
@@ -181,40 +187,40 @@
* .... .... ...B BBBB
*/
-#define GPIO_PIN_SHIFT (0) /* Bits 0-5: Pin number */
-#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
-# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
-# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
-# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
-# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
-# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
-# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
-# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
-# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
-# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
-# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
-# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
-# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
-# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
-# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
-# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
-# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
-# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
-# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
-# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
-# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
-# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
-# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
-# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
-# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
-# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
-# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
-# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
-# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
-# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
-# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
-# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
-# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
+#define GPIO_PIN_SHIFT (0) /* Bits 0-5: Pin number */
+#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
+# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
+# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
+# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
+# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
+# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
+# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
+# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
+# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
+# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
+# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
+# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
+# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
+# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
+# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
+# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
+# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
+# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
+# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
+# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
+# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
+# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
+# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
+# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
+# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
+# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
+# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
+# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
+# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
+# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
+# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
+# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
+# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
/********************************************************************************************
* Public Types
@@ -232,29 +238,26 @@ extern "C" {
#define EXTERN extern
#endif
-/* Base addresses for each GPIO block */
-
-EXTERN const uint32_t g_gpiobase[NUM_GPIO_PORTS];
-
/********************************************************************************************
* Public Functions
********************************************************************************************/
/********************************************************************************************
- * Name: lpc43_gpioconfig
+ * Name: lpc43_gpio_config
*
* Description:
- * Configure a GPIO based on bit-encoded description of the pin.
+ * Configure a GPIO based on bit-encoded description of the pin. NOTE: The pin *must*
+ * have first been configured for GPIO usage with a corresponding call to lpc43_pin_config.
*
* Returned Value:
* OK on success; A negated errno value on failure.
*
********************************************************************************************/
-EXTERN int lpc43_gpioconfig(uint16_t gpiocfg);
+EXTERN int lpc43_gpio_config(uint16_t gpiocfg);
/********************************************************************************************
- * Name: lpc43_gpiowrite
+ * Name: lpc43_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
@@ -264,10 +267,10 @@ EXTERN int lpc43_gpioconfig(uint16_t gpiocfg);
*
********************************************************************************************/
-EXTERN void lpc43_gpiowrite(uint16_t gpiocfg, bool value);
+EXTERN void lpc43_gpio_write(uint16_t gpiocfg, bool value);
/********************************************************************************************
- * Name: lpc43_gpioread
+ * Name: lpc43_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
@@ -277,31 +280,10 @@ EXTERN void lpc43_gpiowrite(uint16_t gpiocfg, bool value);
*
********************************************************************************************/
-EXTERN bool lpc43_gpioread(uint16_t gpiocfg);
+EXTERN bool lpc43_gpio_read(uint16_t gpiocfg);
/********************************************************************************************
- * Name: lpc43_gpioattach
- *
- * Description:
- * Attach and enable a GPIO interrupts on the selected GPIO pin, receiving the
- * interrupt with the selected interrupt handler. The GPIO interrupt may be
- * disabled by providing a NULL value for the interrupt handler function pointer.
- *
- * Parameters:
- * - gpiocfg: GPIO pin identification
- * - func: Interrupt handler
- *
- * Returns:
- * The previous value of the interrupt handler function pointer. This value may,
- * for example, be used to restore the previous handler when multiple handlers are
- * used.
- *
- ********************************************************************************************/
-
-EXTERN xcpt_t lpc43_gpioattach(uint16_t gpiocfg, xcpt_t func);
-
-/********************************************************************************************
- * Function: lpc43_dumpgpio
+ * Function: lpc43_gpio_dump
*
* Description:
* Dump all pin configuration registers associated with the provided base address
@@ -309,9 +291,9 @@ EXTERN xcpt_t lpc43_gpioattach(uint16_t gpiocfg, xcpt_t func);
********************************************************************************************/
#ifdef CONFIG_DEBUG
-EXTERN int lpc43_dumpgpio(uint16_t gpiocfg, const char *msg);
+EXTERN int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg);
#else
-# define lpc43_dumpgpio(p,m)
+# define lpc43_gpio_dump(p,m)
#endif
#undef EXTERN
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c
new file mode 100644
index 0000000000..9861514861
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * arch/arm/src/lpc43/lpc43_gpioint.c
+ *
+ * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/* GPIO pin interrupts
+ *
+ * From all available GPIO pins, up to eight pins can be selected in the system
+ * control block to serve as external interrupt pins. The external interrupt pins
+ * are connected to eight individual interrupts in the NVIC and are created based
+ * on rising or falling edges or on the input level on the pin.
+ *
+ * GPIO group interrupt
+ *
+ * For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
+ * (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
+ * enabled to generate interrupts and what the active polarities of each of those
+ * inputs are. The GPIO grouped interrupt registers also select whether the interrupt
+ * output will be level or edge triggered and whether it will be based on the OR or
+ * the AND of all of the enabled inputs.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+#include
+#include
+
+#include "lpc43_gpioint.h"
+
+#ifdef CONFIG_GPIO_IRQ
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_gpioint_initialize
+ *
+ * Description:
+ * Initialize logic to interrupting GPIO pins GPIO pins
+ *
+ ****************************************************************************/
+
+void lpc43_gpioint_initialize(void)
+{
+#warning "Missing logic"
+}
+
+/****************************************************************************
+ * Name: lpc43_gpioint_config
+ *
+ * Description:
+ * Configure a GPIO pin as an interrupt source (after it has been
+ * configured as an input).
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_config(uint16_t gpiocfg)
+{
+#warning "Missing logic"
+ return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc43_gpiointconfig
+ *
+ * Description:
+ * Un-configure a GPIO pin as an interrupt source.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_unconfig(uint16_t gpiocfg)
+{
+#warning "Missing logic"
+ return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc43_gpioint_enable
+ *
+ * Description:
+ * Enable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+void lpc43_gpioint_enable(int irq)
+{
+#warning "Missing logic"
+}
+
+/****************************************************************************
+ * Name: lpc43_gpioint_disable
+ *
+ * Description:
+ * Disable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+void lpc43_gpioint_disable(int irq)
+{
+#warning "Missing logic"
+}
+
+#endif /* CONFIG_GPIO_IRQ */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h
new file mode 100644
index 0000000000..1d9b2a8263
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -0,0 +1,139 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpioint.h
+ *
+ * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+/* GPIO pin interrupts
+ *
+ * From all available GPIO pins, up to eight pins can be selected in the system
+ * control block to serve as external interrupt pins. The external interrupt pins
+ * are connected to eight individual interrupts in the NVIC and are created based
+ * on rising or falling edges or on the input level on the pin.
+ *
+ * GPIO group interrupt
+ *
+ * For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
+ * (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
+ * enabled to generate interrupts and what the active polarities of each of those
+ * inputs are. The GPIO grouped interrupt registers also select whether the interrupt
+ * output will be level or edge triggered and whether it will be based on the OR or
+ * the AND of all of the enabled inputs.
+ */
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+#include "chip/lpc43_gpio.h"
+
+#ifdef CONFIG_GPIO_IRQ
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc43_gpioint_initialize
+ *
+ * Description:
+ * Initialize logic to interrupting GPIO pins GPIO pins
+ *
+ ************************************************************************************/
+
+EXTERN void lpc43_gpioint_initialize(void);
+
+/****************************************************************************
+ * Name: lpc43_gpioint_config
+ *
+ * Description:
+ * Configure a GPIO pin as an interrupt source (after it has been
+ * configured as an input).
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_gpioint_config(uint16_t gpiocfg);
+
+/****************************************************************************
+ * Name: lpc43_gpiointconfig
+ *
+ * Description:
+ * Un-configure a GPIO pin as an interrupt source.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_gpioint_unconfig(uint16_t gpiocfg);
+
+/************************************************************************************
+ * Name: lpc43_gpioint_enable
+ *
+ * Description:
+ * Zero on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+EXTERN int lpc43_gpioint_enable(int irq);
+
+/************************************************************************************
+ * Name: lpc43_gpioint_disable
+ *
+ * Description:
+ * Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+EXTERN void lpc43_gpioint_disable(int irq);
+
+#endif /* CONFIG_GPIO_IRQ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c
index 22471ce1e9..c6c94af882 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -357,12 +357,10 @@ void up_irqinitialize(void)
lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS);
- /* Initialize logic to support a second level of interrupt decoding for
- * GPIO pins.
- */
+ /* Initialize logic to interrupting GPIO pins GPIO pins */
#ifdef CONFIG_GPIO_IRQ
- lpc43_gpioirqinitialize();
+ lpc43_gpioint_initialize();
#endif
/* And finally, enable interrupts */
@@ -400,7 +398,7 @@ void up_disable_irq(int irq)
{
/* Maybe it is a (derived) GPIO IRQ */
- lpc43_gpioirqdisable(irq);
+ lpc43_gpioint_disable(irq);
}
#endif
lpc43_dumpnvic("disable", irq);
@@ -433,7 +431,7 @@ void up_enable_irq(int irq)
{
/* Maybe it is a (derived) GPIO IRQ */
- lpc43_gpioirqenable(irq);
+ lpc43_gpioint_enable(irq);
}
#endif
lpc43_dumpnvic("enable", irq);
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_lowputc.c b/nuttx/arch/arm/src/lpc43xx/lpc43_lowputc.c
index 2e45f9855c..e865be11d2 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_lowputc.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_lowputc.c
@@ -365,25 +365,25 @@ void lpc43_lowsetup(void)
*/
#if defined(CONFIG_USART0_SERIAL_CONSOLE)
- lpc43_pinconfig(PINCONF_U0_TXD);
- lpc43_pinconfig(PINCONF_U0_RXD);
+ lpc43_pin_config(PINCONF_U0_TXD);
+ lpc43_pin_config(PINCONF_U0_RXD);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
- lpc43_pinconfig(PINCONF_U1_TXD);
- lpc43_pinconfig(PINCONF_U1_RXD);
+ lpc43_pin_config(PINCONF_U1_TXD);
+ lpc43_pin_config(PINCONF_U1_RXD);
#ifdef CONFIG_UART1_FLOWCONTROL
- lpc43_pinconfig(PINCONF_U1_CTS);
- lpc43_pinconfig(PINCONF_U1_DCD);
- lpc43_pinconfig(PINCONF_U1_DSR);
- lpc43_pinconfig(PINCONF_U1_DTR);
- lpc43_pinconfig(PINCONF_U1_RI);
- lpc43_pinconfig(PINCONF_U1_RTS);
+ lpc43_pin_config(PINCONF_U1_CTS);
+ lpc43_pin_config(PINCONF_U1_DCD);
+ lpc43_pin_config(PINCONF_U1_DSR);
+ lpc43_pin_config(PINCONF_U1_DTR);
+ lpc43_pin_config(PINCONF_U1_RI);
+ lpc43_pin_config(PINCONF_U1_RTS);
#endif
#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
- lpc43_pinconfig(PINCONF_U2_TXD);
- lpc43_pinconfig(PINCONF_U2_RXD);
+ lpc43_pin_config(PINCONF_U2_TXD);
+ lpc43_pin_config(PINCONF_U2_RXD);
#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
- lpc43_pinconfig(PINCONF_U3_TXD);
- lpc43_pinconfig(PINCONF_U3_RXD);
+ lpc43_pin_config(PINCONF_U3_TXD);
+ lpc43_pin_config(PINCONF_U3_RXD);
#endif
/* Configure the console (only) */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
index d41d6f5884..69456d12b8 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/lpc43/lpc43_pinconfig.c
+ * arch/arm/src/lpc43/lpc43_pin_config.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -62,7 +62,7 @@
****************************************************************************/
/****************************************************************************
- * Name: lpc43_pinconfig
+ * Name: lpc43_pin_config
*
* Description:
* Configure a pin based on bit-encoded description of the pin.
@@ -75,7 +75,7 @@
*
****************************************************************************/
-int lpc43_pinconfig(uint32_t pinconf)
+int lpc43_pin_config(uint32_t pinconf)
{
#warning "Missing logic"
return -ENOSYS;
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index 27769f4b4a..1de93a78df 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -254,7 +254,7 @@ extern "C" {
********************************************************************************************/
/********************************************************************************************
- * Name: lpc43_pinconfig
+ * Name: lpc43_pin_config
*
* Description:
* Configure a pin based on bit-encoded description of the pin.
@@ -267,10 +267,10 @@ extern "C" {
*
********************************************************************************************/
-EXTERN int lpc43_pinconfig(uint32_t pinconf);
+EXTERN int lpc43_pin_config(uint32_t pinconf);
/********************************************************************************************
- * Function: lpc43_dumppinconfig
+ * Function: lpc43_pin_dump
*
* Description:
* Dump all pin configuration registers associated with the provided pin configuration
@@ -278,9 +278,9 @@ EXTERN int lpc43_pinconfig(uint32_t pinconf);
********************************************************************************************/
#ifdef CONFIG_DEBUG
-EXTERN int lpc43_dumppinconfig(uint32_t pinconf, const char *msg);
+EXTERN int lpc43_pin_dump(uint32_t pinconf, const char *msg);
#else
-# define lpc43_dumppinconfig(p,m)
+# define lpc43_pin_dump(p,m)
#endif
#undef EXTERN
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h
index 7af965947d..28c8338269 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h
@@ -42,7 +42,7 @@
#include
#include
-#include "chip/lpc32_spi.h"
+#include "chip/lpc43_spi.h"
#ifdef CONFIG_LPC43_SPI
diff --git a/nuttx/configs/lpc4330-xplorer/src/up_autoleds.c b/nuttx/configs/lpc4330-xplorer/src/up_autoleds.c
index 89b2a10202..b19e334591 100644
--- a/nuttx/configs/lpc4330-xplorer/src/up_autoleds.c
+++ b/nuttx/configs/lpc4330-xplorer/src/up_autoleds.c
@@ -124,8 +124,8 @@
#ifdef LED_VERBOSE
static void led_dumppins(FAR const char *msg)
{
- lpc43_dumppinconfig(PINCONFIG_LED1, msg);
- lpc43_dumpgpio(GPIO_LED2, msg);
+ lpc43_pin_dump(PINCONFIG_LED1, msg);
+ lpc43_gpio_dump(GPIO_LED2, msg);
}
#else
# define led_dumppins(m)
@@ -147,11 +147,11 @@ void up_ledinit(void)
/* Configure LED pins as GPIOs, then configure GPIOs as outputs */
- lpc43_pinconfig(PINCONFIG_LED1);
- lpc43_gpioconfig(GPIO_LED1);
+ lpc43_pin_config(PINCONFIG_LED1);
+ lpc43_gpio_config(GPIO_LED1);
- lpc43_pinconfig(PINCONFIG_LED2);
- lpc43_gpioconfig(GPIO_LED2);
+ lpc43_pin_config(PINCONFIG_LED2);
+ lpc43_gpio_config(GPIO_LED2);
led_dumppins("up_ledinit() Exit");
}
@@ -166,17 +166,17 @@ void up_ledon(int led)
{
default:
case 0:
- lpc43_gpiowrite(GPIO_LED1, true); /* LED1 OFF */
- lpc43_gpiowrite(GPIO_LED2, true); /* LED2 OFF */
+ lpc43_gpio_write(GPIO_LED1, true); /* LED1 OFF */
+ lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */
break;
case 1:
- lpc43_gpiowrite(GPIO_LED1, false); /* LED1 ON */
- lpc43_gpiowrite(GPIO_LED2, true); /* LED2 OFF */
+ lpc43_gpio_write(GPIO_LED1, false); /* LED1 ON */
+ lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */
break;
case 2:
- lpc43_gpiowrite(GPIO_LED2, false); /* LED2 ON */
+ lpc43_gpio_write(GPIO_LED2, false); /* LED2 ON */
break;
}
}
@@ -195,7 +195,7 @@ void up_ledoff(int led)
break;
case 2:
- lpc43_gpiowrite(GPIO_LED2, true); /* LED2 OFF */
+ lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */
break;
}
}
diff --git a/nuttx/configs/lpc4330-xplorer/src/up_buttons.c b/nuttx/configs/lpc4330-xplorer/src/up_buttons.c
index cd3e1583fe..841f52b23f 100644
--- a/nuttx/configs/lpc4330-xplorer/src/up_buttons.c
+++ b/nuttx/configs/lpc4330-xplorer/src/up_buttons.c
@@ -142,7 +142,7 @@ uint8_t up_buttons(void)
{
/* A LOW value means that the key is pressed. */
- bool released = lpc43_gpioread(g_buttoncfg[i]);
+ bool released = lpc43_gpio_read(g_buttoncfg[i]);
/* Accumulate the set of depressed (not released) keys */
diff --git a/nuttx/configs/lpc4330-xplorer/src/up_userleds.c b/nuttx/configs/lpc4330-xplorer/src/up_userleds.c
index 0f7ccee505..e7b4b11894 100644
--- a/nuttx/configs/lpc4330-xplorer/src/up_userleds.c
+++ b/nuttx/configs/lpc4330-xplorer/src/up_userleds.c
@@ -102,8 +102,8 @@
#ifdef LED_VERBOSE
static void led_dumppins(FAR const char *msg)
{
- lpc43_dumppinconfig(PINCONFIG_LED1, msg);
- lpc43_dumpgpio(GPIO_LED2, msg);
+ lpc43_pin_dump(PINCONFIG_LED1, msg);
+ lpc43_gpio_dump(GPIO_LED2, msg);
}
#else
# define led_dumppins(m)
@@ -125,11 +125,11 @@ void lpc43_ledinit(void)
/* Configure LED pins as GPIOs, then configure GPIOs as outputs */
- lpc43_pinconfig(PINCONFIG_LED1);
- lpc43_gpioconfig(GPIO_LED1);
+ lpc43_pin_config(PINCONFIG_LED1);
+ lpc43_gpio_config(GPIO_LED1);
- lpc43_pinconfig(PINCONFIG_LED2);
- lpc43_gpioconfig(GPIO_LED2);
+ lpc43_pin_config(PINCONFIG_LED2);
+ lpc43_gpio_config(GPIO_LED2);
led_dumppins("lpc43_ledinit() Exit");
}
@@ -141,7 +141,7 @@ void lpc43_ledinit(void)
void lpc43_setled(int led, bool ledon)
{
uint16_t gpiocfg = (led == BOARD_LED1 ? BOARD_LED1 : BOARD_LED2);
- lpc43_gpiowrite(GPIO_LED1, !ledon);
+ lpc43_gpio_write(GPIO_LED1, !ledon);
}
/****************************************************************************
@@ -150,8 +150,8 @@ void lpc43_setled(int led, bool ledon)
void lpc43_setleds(uint8_t ledset)
{
- lpc43_gpiowrite(BOARD_LED1, (ledset & BOARD_LED1_BIT) == 0);
- lpc43_gpiowrite(BOARD_LED2, (ledset & BOARD_LED2_BIT) == 0);
+ lpc43_gpio_write(BOARD_LED1, (ledset & BOARD_LED1_BIT) == 0);
+ lpc43_gpio_write(BOARD_LED2, (ledset & BOARD_LED2_BIT) == 0);
}
#endif /* !CONFIG_ARCH_LEDS */
|