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/**
 * @file InvenSense_MPU6000_registers.hpp
 *
 * Invensense MPU6000 registers.
 *
 */

#pragma once

// TODO: move to a central header
static constexpr uint8_t Bit0 = (1 << 0);
static constexpr uint8_t Bit1 = (1 << 1);
static constexpr uint8_t Bit2 = (1 << 2);
static constexpr uint8_t Bit3 = (1 << 3);
static constexpr uint8_t Bit4 = (1 << 4);
static constexpr uint8_t Bit5 = (1 << 5);
static constexpr uint8_t Bit6 = (1 << 6);
static constexpr uint8_t Bit7 = (1 << 7);

namespace InvenSense_MPU6000
{
static constexpr uint32_t SPI_SPEED = 20 * 1000 * 1000;
static constexpr uint8_t DIR_READ = 0x80;

static constexpr uint8_t WHOAMI = 0x68;

enum class Register : uint8_t {
	CONFIG        = 0x1A,
	GYRO_CONFIG   = 0x1B,
	ACCEL_CONFIG  = 0x1C,

	FIFO_EN       = 0x23,

	INT_STATUS    = 0x3A,

	INT_ENABLE    = 0x38,

	TEMP_OUT_H    = 0x41,
	TEMP_OUT_L    = 0x42,

	USER_CTRL     = 0x6A,
	PWR_MGMT_1    = 0x6B,

	FIFO_COUNTH   = 0x72,
	FIFO_COUNTL   = 0x73,
	FIFO_R_W      = 0x74,
	WHO_AM_I      = 0x75,
};

// CONFIG
enum CONFIG_BIT : uint8_t {
	DLPF_CFG_BYPASS_DLPF = 7, // Reserved
};

// GYRO_CONFIG
enum GYRO_CONFIG_BIT : uint8_t {
	// FS_SEL [4:3]
	FS_SEL_250_DPS	= 0,           // 0b00000
	FS_SEL_500_DPS	= Bit3,        // 0b01000
	FS_SEL_1000_DPS	= Bit4,        // 0b10000
	FS_SEL_2000_DPS	= Bit4 | Bit3, // 0b11000
};

// ACCEL_CONFIG
enum ACCEL_CONFIG_BIT : uint8_t {
	// AFS_SEL [4:3]
	AFS_SEL_2G  = 0,           // 0b00000
	AFS_SEL_4G  = Bit3,        // 0b01000
	AFS_SEL_8G  = Bit4,        // 0b10000
	AFS_SEL_16G = Bit4 | Bit3, // 0b11000
};

// FIFO_EN
enum FIFO_EN_BIT : uint8_t {
	TEMP_FIFO_EN  = Bit7,
	XG_FIFO_EN    = Bit6,
	YG_FIFO_EN    = Bit5,
	ZG_FIFO_EN    = Bit4,
	ACCEL_FIFO_EN = Bit3,
};

// INT_ENABLE
enum INT_ENABLE_BIT : uint8_t {
	FIFO_OFLOW_EN   = Bit4,
	DATA_RDY_INT_EN = Bit0
};

// INT_STATUS
enum INT_STATUS_BIT : uint8_t {
	FIFO_OFLOW_INT = Bit4,
	DATA_RDY_INT   = Bit0,
};

// USER_CTRL
enum USER_CTRL_BIT : uint8_t {
	FIFO_EN    = Bit6,
	FIFO_RESET = Bit2,
};

// PWR_MGMT_1
enum PWR_MGMT_1_BIT : uint8_t {
	DEVICE_RESET = Bit7,

	CLKSEL_2   = Bit2,
	CLKSEL_1   = Bit1,
	CLKSEL_0   = Bit0,
};


namespace FIFO
{
static constexpr size_t SIZE = 1024;

// FIFO_DATA layout when FIFO_EN has {X, Y, Z}G_FIFO_EN and ACCEL set
struct DATA {
	uint8_t ACCEL_XOUT_H;
	uint8_t ACCEL_XOUT_L;
	uint8_t ACCEL_YOUT_H;
	uint8_t ACCEL_YOUT_L;
	uint8_t ACCEL_ZOUT_H;
	uint8_t ACCEL_ZOUT_L;
	uint8_t GYRO_XOUT_H;
	uint8_t GYRO_XOUT_L;
	uint8_t GYRO_YOUT_H;
	uint8_t GYRO_YOUT_L;
	uint8_t GYRO_ZOUT_H;
	uint8_t GYRO_ZOUT_L;
};
}

} // namespace InvenSense_MPU6000
