diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 4213d94e..583fce2c 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h index 723ecf2e..e52d9edb 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h index 97f2039c..56bbc4af 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h index 2a75009b..067342fd 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index 20414e69..4031cf11 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -73,9 +73,13 @@ typedef enum HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -231,7 +235,9 @@ typedef struct CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ @@ -253,16 +259,19 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ /** * @} */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index f16233d3..720948e5 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index bf89fb9e..d60a6cd2 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h index 48746b10..c24cf6c1 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h index 2dec53bc..714800be 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h index 0794fd5b..55d1f1ce 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h index b3a03178..bfd16328 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h index 48aa3d6c..c2841231 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index f4f27e8d..a961f3ef 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h index 556fff5f..96ab6740 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index 03e9e269..f6de7348 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h index 5a02706c..e7144805 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index 59360e10..b32a012b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h index b7f79bb8..d57bf4b7 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index af6b3e8c..a2def24c 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index 9720d0a4..f7e3fb24 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h index 57237261..c1d9b855 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 7ba34c05..2be1ff33 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h index 806d85da..92bf0f21 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index 25dc7d12..0c8fa996 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index de90e681..bd1dc7d8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.5.0 + * @brief STM32F4xx HAL Driver version number V1.7.1 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -272,7 +272,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) HAL_SYSTICK_Config(SystemCoreClock/1000U); /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); /* Return function status */ return HAL_OK; diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index 8ec31085..3be6a015 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c index e6a15f86..27708fc2 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 737f611b..d1c9c41b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: * + Initialization and de-initialization functions @@ -578,15 +578,21 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Process locked */ __HAL_LOCK(hcan); - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } /* Select one empty transmit mailbox */ @@ -636,7 +642,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check End of transmission flag */ @@ -648,24 +654,33 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ __HAL_UNLOCK(hcan); - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); return HAL_TIMEOUT; } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -701,6 +716,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { + /* Process Locked */ + __HAL_LOCK(hcan); /* Select one empty transmit mailbox */ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) @@ -738,39 +755,49 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | ((uint32_t)hcan->pTxMsg->Data[4U])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - + /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ + Last error and Error Interrupts */ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | CAN_IT_EPV | CAN_IT_BOF | CAN_IT_LEC | CAN_IT_ERR | CAN_IT_TME); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { @@ -795,24 +822,70 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { uint32_t tickstart = 0U; - + CanRxMsgTypeDef* pRxMsg = NULL; + /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } } - + /* Get tick */ tickstart = HAL_GetTick(); @@ -831,35 +904,45 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u } } } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); /* Get the FIFONumber */ - hcan->pRxMsg->FIFONumber = FIFONumber; + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) { @@ -871,18 +954,45 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Release FIFO1 */ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -899,53 +1009,98 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u */ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { - uint32_t tmp = 0U; - /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - tmp = hcan->State; - if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX)) - { - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); - } - - } - else + /* Check if CAN state is not busy for RX FIFO0 */ + if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { return HAL_BUSY; } - + + /* Check if CAN state is not busy for RX FIFO1 */ + if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if(FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + /* Return function status */ return HAL_OK; } @@ -968,7 +1123,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) /* Request Sleep mode */ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - + /* Sleep mode status */ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) { @@ -978,8 +1133,8 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) /* Return function status */ return HAL_ERROR; } - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ @@ -993,13 +1148,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_TIMEOUT; } } - + /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hcan); - + /* Return function status */ return HAL_OK; } @@ -1066,7 +1221,32 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + /* Check Overrun flag for FIFO1 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); + + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + /* Check End of transmission flag */ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) { @@ -1075,11 +1255,27 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); if(tmp1 || tmp2 || tmp3) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); + tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); + tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); + /* Check Transmit success */ + if(tmp1 || tmp2 || tmp3) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); } } - + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); /* Check End of reception flag for FIFO0 */ @@ -1088,7 +1284,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); } - + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); /* Check End of reception flag for FIFO1 */ @@ -1097,7 +1293,10 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); } - + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); @@ -1176,6 +1375,29 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) hcan->Instance->MSR = CAN_MSR_ERRI; /* Set the CAN state ready to be able to start again the process */ hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME); + /* Call Error callback function */ HAL_CAN_ErrorCallback(hcan); } @@ -1231,8 +1453,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * + * @brief CAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -1286,25 +1508,31 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_BUSY_TX) { /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ + and Error Interrupts */ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | CAN_IT_EPV | CAN_IT_BOF | CAN_IT_LEC | CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - + /* Transmission complete callback */ HAL_CAN_TxCpltCallback(hcan); @@ -1321,52 +1549,66 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + uint32_t tmp1 = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) { - hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; /* Get the FIFONumber */ - hcan->pRxMsg->FIFONumber = FIFONumber; + pRxMsg->FIFONumber = FIFONumber; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); /* Get the data field */ - hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + tmp1 = hcan->State; + if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) { /* Disable Error warning, Error passive, Bus-off, Last error code and Error Interrupts */ @@ -1376,16 +1618,43 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum CAN_IT_LEC | CAN_IT_ERR); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Receive complete callback */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index 3d1a13c7..9a7d1c91 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c index 22f8d7d5..ca14c5aa 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c index a71f54e6..2c839a34 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c index f5224959..977c76c9 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c index 78b9009b..8c56ce05 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c index 5640f0b0..1b19e62d 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief FLASH RAMFUNC module driver. * This file provides a FLASH firmware functions which should be * executed from internal SRAM diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c index d0d9a07f..aeaafea8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 4cdf830e..c524f970 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 19dcd108..db3e04fa 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index ee54ec8f..18e5cc20 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c index d1024b34..a1d353f1 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -537,7 +537,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) /** * @brief Enters in Under-Drive STOP mode. * - * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. * * @note This mode can be selected only when the Under-Drive is already active * @@ -576,8 +576,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - + /* Check the parameters */ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); @@ -591,18 +590,6 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* Enable the Under-drive */ __HAL_PWR_UNDERDRIVE_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for UnderDrive mode is ready */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) - { - if((HAL_GetTick() - tickstart) > PWR_UDERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg1 = PWR->CR; /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index 06f3e9e6..af8ea2f8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index 08c48b6b..ab7691ce 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 039b5de0..4774dc2e 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index daa1cfa8..03d699b5 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index b0834f06..7294400a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 09c192e0..7491fee6 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 + * @version V1.7.1 + * @date 14-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/Inc/FreeRTOSConfig.h b/Inc/FreeRTOSConfig.h index 4e9dc4e9..8258f86c 100644 --- a/Inc/FreeRTOSConfig.h +++ b/Inc/FreeRTOSConfig.h @@ -104,10 +104,10 @@ #define configMINIMAL_STACK_SIZE ((uint16_t)128) #define configTOTAL_HEAP_SIZE ((size_t)15360) #define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 diff --git a/Inc/adc.h b/Inc/adc.h index e488f0ae..d0b13264 100644 --- a/Inc/adc.h +++ b/Inc/adc.h @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the ADC instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -64,7 +69,7 @@ extern ADC_HandleTypeDef hadc3; /* USER CODE END Private defines */ -extern void Error_Handler(void); +extern void _Error_Handler(char *, int); void MX_ADC1_Init(void); void MX_ADC2_Init(void); diff --git a/Inc/can.h b/Inc/can.h index d05d4c1b..0e221f20 100644 --- a/Inc/can.h +++ b/Inc/can.h @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the CAN instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -62,7 +67,7 @@ extern CAN_HandleTypeDef hcan1; /* USER CODE END Private defines */ -extern void Error_Handler(void); +extern void _Error_Handler(char *, int); void MX_CAN1_Init(void); diff --git a/Inc/gpio.h b/Inc/gpio.h index c8eac048..8a1da672 100644 --- a/Inc/gpio.h +++ b/Inc/gpio.h @@ -4,6 +4,11 @@ * Description : This file contains all the functions prototypes for * the gpio ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Inc/main.h b/Inc/main.h index c8d127cb..461a458e 100644 --- a/Inc/main.h +++ b/Inc/main.h @@ -3,6 +3,11 @@ * File Name : main.h * Description : This file contains the common defines of the application ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -151,6 +156,10 @@ /* USER CODE END Private defines */ +void _Error_Handler(char *, int); + +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) + /** * @} */ diff --git a/Inc/spi.h b/Inc/spi.h index 60ec8f26..0b8f223c 100644 --- a/Inc/spi.h +++ b/Inc/spi.h @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the SPI instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -62,7 +67,7 @@ extern SPI_HandleTypeDef hspi3; /* USER CODE END Private defines */ -extern void Error_Handler(void); +extern void _Error_Handler(char *, int); void MX_SPI3_Init(void); diff --git a/Inc/tim.h b/Inc/tim.h index b11fa712..db2d0262 100644 --- a/Inc/tim.h +++ b/Inc/tim.h @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the TIM instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -66,7 +71,7 @@ extern TIM_HandleTypeDef htim8; /* USER CODE END Private defines */ -extern void Error_Handler(void); +extern void _Error_Handler(char *, int); void MX_TIM1_Init(void); void MX_TIM2_Init(void); diff --git a/Inc/usb_device.h b/Inc/usb_device.h index 7939ca48..1381880c 100644 --- a/Inc/usb_device.h +++ b/Inc/usb_device.h @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : Header for usb_device file. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Inc/usbd_cdc_if.h b/Inc/usbd_cdc_if.h index 17fe53d8..7faf73af 100644 --- a/Inc/usbd_cdc_if.h +++ b/Inc/usbd_cdc_if.h @@ -3,6 +3,11 @@ * @file : usbd_cdc_if.h * @brief : Header for usbd_cdc_if file. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Inc/usbd_conf.h b/Inc/usbd_conf.h index cb8fd179..4a69d7b9 100644 --- a/Inc/usbd_conf.h +++ b/Inc/usbd_conf.h @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : Header for usbd_conf file. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -81,8 +86,6 @@ #define USBD_LPM_ENABLED 0 /*---------- -----------*/ #define USBD_SELF_POWERED 1 -/*---------- -----------*/ -#define USBD_CDC_INTERVAL 1000 /****************************************/ /* #define for FS and HS identification */ diff --git a/Inc/usbd_desc.h b/Inc/usbd_desc.h index 1fb50263..dd3d6753 100644 --- a/Inc/usbd_desc.h +++ b/Inc/usbd_desc.h @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : Header for usbd_desc file. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index 366733f2..7ff30e9d 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -57,7 +57,7 @@ ****************************************************************************** * @file cmsis_os.c * @author MCD Application Team - * @date 30-September-2016 + * @date 03-March-2017 * @brief CMSIS-RTOS API implementation for FreeRTOS V9.0.0 ****************************************************************************** * @attention @@ -99,6 +99,47 @@ #include #include "cmsis_os.h" +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + #include "cmsis_armcc.h" + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + + + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include +#endif + extern void xPortSysTickHandler(void); /* Convert from CMSIS type osPriority to FreeRTOS priority number */ @@ -498,32 +539,31 @@ osStatus result = osOK; * @brief Set the specified Signal Flags of an active thread. * @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. * @param signals specifies the signal flags of the thread that should be set. -* @retval osOK if successful, osErrorOS if failed . +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. * @note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. */ int32_t osSignalSet (osThreadId thread_id, int32_t signal) { #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulPreviousNotificationValue = 0; if (inHandlerMode()) { - if(xTaskNotifyFromISR( thread_id, (uint32_t)signal, eSetBits, &xHigherPriorityTaskWoken ) != pdPASS ) - return osErrorOS; - + if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS ) + return 0x80000000; + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); } - else if(xTaskNotify( thread_id, (uint32_t)signal, eSetBits) != pdPASS ) - { - return osErrorOS; - } + else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS ) + return 0x80000000; - return osOK; + return ulPreviousNotificationValue; #else (void) thread_id; (void) signal; - return osErrorOS; /* Task Notification not supported */ + return 0x80000000; /* Task Notification not supported */ #endif } @@ -1245,7 +1285,7 @@ void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) void *p = osMailAlloc(queue_id, millisec); if (p) { - for (i = 0; i < sizeof(queue_id->queue_def->item_sz); i++) { + for (i = 0; i < queue_id->queue_def->item_sz; i++) { ((uint8_t *)p)[i] = 0; } } diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 8c4f20f5..c83e14eb 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -57,7 +57,7 @@ ****************************************************************************** * @file cmsis_os.h * @author MCD Application Team - * @date 30-September-2016 + * @date 03-March-2017 * @brief Header of cmsis_os.c * A new set of APIs are added in addition to existing ones, these APIs * are specific to FreeRTOS. @@ -96,25 +96,7 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ - - #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline -#endif - -#include -#include -#include "core_cmFunc.h" + */ #include "FreeRTOS.h" #include "task.h" diff --git a/Odrive.ioc b/Odrive.ioc index 1cdb9778..f6804fe3 100755 --- a/Odrive.ioc +++ b/Odrive.ioc @@ -1,5 +1,4 @@ #MicroXplorer Configuration settings - do not modify -ADC1.AutoInjectedConv=DISABLE ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5 ADC1.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_0 ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 @@ -13,10 +12,9 @@ ADC1.ExternalTrigConv=ADC_SOFTWARE_START ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE ADC1.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1.ExternalTrigInjecConvEdge=ADC_EXTERNALTRIGINJECCONVEDGE_RISING -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjectedConvMode,ExternalTrigInjecConvEdge,ExternalTrigInjecConv,ExternalTrigConv,AutoInjectedConv,InjectedDiscontinuousConvMode +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjectedConvMode,ExternalTrigInjecConvEdge,ExternalTrigInjecConv,ExternalTrigConv ADC1.InjNumberOfConversion=1 ADC1.InjectedConvMode=None -ADC1.InjectedDiscontinuousConvMode=DISABLE ADC1.InjectedOffset-1\#ChannelInjectedConversion=0 ADC1.NbrOfConversion=1 ADC1.NbrOfConversionFlag=1 @@ -27,7 +25,6 @@ ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC1.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_3CYCLES ADC1.ScanConvMode=DISABLE ADC1.master=1 -ADC2.AutoInjectedConv=DISABLE ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_13 ADC2.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_10 ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 @@ -41,10 +38,9 @@ ADC2.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T8_TRGO ADC2.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_RISING ADC2.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC2.ExternalTrigInjecConvEdge=ADC_EXTERNALTRIGINJECCONVEDGE_RISING -ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,InjNumberOfConversion,EnableAnalogWatchDog,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,ExternalTrigInjecConvEdge,ExternalTrigConvEdge,InjectedConvMode,ExternalTrigInjecConv,ExternalTrigConv,AutoInjectedConv,InjectedDiscontinuousConvMode +ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,InjNumberOfConversion,EnableAnalogWatchDog,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,ExternalTrigInjecConvEdge,ExternalTrigConvEdge,InjectedConvMode,ExternalTrigInjecConv,ExternalTrigConv ADC2.InjNumberOfConversion=1 ADC2.InjectedConvMode=None -ADC2.InjectedDiscontinuousConvMode=DISABLE ADC2.InjectedOffset-1\#ChannelInjectedConversion=0 ADC2.NbrOfConversion=1 ADC2.NbrOfConversionFlag=1 @@ -54,7 +50,6 @@ ADC2.Resolution=ADC_RESOLUTION_12B ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC2.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_3CYCLES ADC2.ScanConvMode=DISABLE -ADC3.AutoInjectedConv=DISABLE ADC3.Channel-7\#ChannelRegularConversion=ADC_CHANNEL_12 ADC3.Channel-8\#ChannelInjectedConversion=ADC_CHANNEL_11 ADC3.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 @@ -68,10 +63,9 @@ ADC3.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T8_TRGO ADC3.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_RISING ADC3.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC3.ExternalTrigInjecConvEdge=ADC_EXTERNALTRIGINJECCONVEDGE_RISING -ADC3.IPParameters=Rank-7\#ChannelRegularConversion,Channel-7\#ChannelRegularConversion,SamplingTime-7\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-8\#ChannelInjectedConversion,Channel-8\#ChannelInjectedConversion,SamplingTime-8\#ChannelInjectedConversion,InjectedOffset-8\#ChannelInjectedConversion,ExternalTrigInjecConvEdge,InjectedConvMode,ExternalTrigInjecConv,ExternalTrigConv,AutoInjectedConv,InjectedDiscontinuousConvMode +ADC3.IPParameters=Rank-7\#ChannelRegularConversion,Channel-7\#ChannelRegularConversion,SamplingTime-7\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-8\#ChannelInjectedConversion,Channel-8\#ChannelInjectedConversion,SamplingTime-8\#ChannelInjectedConversion,InjectedOffset-8\#ChannelInjectedConversion,ExternalTrigInjecConvEdge,InjectedConvMode,ExternalTrigInjecConv,ExternalTrigConv ADC3.InjNumberOfConversion=1 ADC3.InjectedConvMode=None -ADC3.InjectedDiscontinuousConvMode=DISABLE ADC3.InjectedOffset-8\#ChannelInjectedConversion=0 ADC3.NbrOfConversion=1 ADC3.NbrOfConversionFlag=1 @@ -85,9 +79,8 @@ CAN1.CalculateTimeBit=1142 CAN1.CalculateTimeQuantum=380.95238095238096 CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit FREERTOS.INCLUDE_vTaskDelayUntil=1 -FREERTOS.IPParameters=Tasks01,INCLUDE_vTaskDelayUntil,configUSE_ALTERNATIVE_API +FREERTOS.IPParameters=Tasks01,INCLUDE_vTaskDelayUntil FREERTOS.Tasks01=defaultTask,-3,256,StartDefaultTask,Default -FREERTOS.configUSE_ALTERNATIVE_API=0 File.Version=6 KeepUserPlacement=false Mcu.Family=STM32F4 @@ -169,8 +162,8 @@ Mcu.Pin9=PA0-WKUP Mcu.PinsNb=56 Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,10192;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,20 Mcu.UserName=STM32F405RGTx -MxCube.Version=4.20.0 -MxDb.Version=DB.4.0.200 +MxCube.Version=4.22.0 +MxDb.Version=DB.4.0.220 NVIC.ADC_IRQn=true\:5\:0\:false\:true\:true\:1\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false @@ -351,7 +344,6 @@ PC9.Signal=GPIO_Output PCC.Checker=false PCC.Line=STM32F405/415 PCC.MCU=STM32F405RGTx -PCC.MXVersion=4.20.0 PCC.PartNumber=STM32F405RGTx PCC.Seq0=0 PCC.Series=STM32F4 @@ -366,6 +358,7 @@ PH0-OSC_IN.Mode=HSE-External-Oscillator PH0-OSC_IN.Signal=RCC_OSC_IN PH1-OSC_OUT.Mode=HSE-External-Oscillator PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=2 @@ -375,7 +368,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F405RGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.15.0 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.16.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x3C00 @@ -401,54 +394,27 @@ RCC.APB2CLKDivider=RCC_HCLK_DIV2 RCC.APB2Freq_Value=84000000 RCC.APB2TimCLKDivider=1 RCC.APB2TimFreq_Value=84000000 -RCC.ClockTypeHCLK=RCC_CLOCKTYPE_HCLK -RCC.ClockTypePCLK1=RCC_CLOCKTYPE_PCLK1 -RCC.ClockTypePCLK2=RCC_CLOCKTYPE_PCLK2 -RCC.ClockTypeSysClk=RCC_CLOCKTYPE_SYSCLK RCC.CortexFreq_Value=168000000 -RCC.EnableExtClockForI2S=false -RCC.EnableHSE=true -RCC.EnableHSERTCDevisor=false -RCC.EnableLSE=false -RCC.EnableLSERTC=false RCC.EthernetFreq_Value=168000000 -RCC.ExtClockEnable=false RCC.FCLKCortexFreq_Value=168000000 RCC.FamilyName=M RCC.HCLKFreq_Value=168000000 -RCC.HSEState=RCC_HSE_ON RCC.HSE_VALUE=8000000 -RCC.HSIState=RCC_HSI_OFF RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=192000000 -RCC.I2SEnable=false -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimCLKDivider,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimCLKDivider,APB2TimFreq_Value,ClockTypeHCLK,ClockTypePCLK1,ClockTypePCLK2,ClockTypeSysClk,CortexFreq_Value,EnableExtClockForI2S,EnableHSE,EnableHSERTCDevisor,EnableLSE,EnableLSERTC,EthernetFreq_Value,ExtClockEnable,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSEState,HSE_VALUE,HSIState,HSI_VALUE,I2SClocksFreq_Value,I2SEnable,IWDGEnable,LSE_VALUE,LSIState,LSI_VALUE,MCO1OutPutEnable,MCO2OutPutEnable,MCO2PinFreq_Value,OscillatorTypeHSE,OscillatorTypeLSI,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSource,PLLSourceVirtual,PLLState,RNGEnable,RTCEnable,RTCFreq_Value,RTCHSEDivFreq_Value,SDIOEnable,SYSCLKFreq_VALUE,SYSCLKSource,USBFSEnable,USBHSEnable,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S -RCC.IWDGEnable=false +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimCLKDivider,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimCLKDivider,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S RCC.LSE_VALUE=32768 -RCC.LSIState=RCC_LSI_OFF RCC.LSI_VALUE=32000 -RCC.MCO1OutPutEnable=false -RCC.MCO2OutPutEnable=false RCC.MCO2PinFreq_Value=168000000 -RCC.OscillatorTypeHSE=RCC_OSCILLATORTYPE_HSE -RCC.OscillatorTypeLSI= RCC.PLLCLKFreq_Value=168000000 RCC.PLLM=4 RCC.PLLN=168 RCC.PLLQ=7 RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLSource=RCC_PLLSOURCE_HSE -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.PLLState=RCC_PLL_ON -RCC.RNGEnable=false -RCC.RTCEnable=false RCC.RTCFreq_Value=32000 RCC.RTCHSEDivFreq_Value=4000000 -RCC.SDIOEnable=false RCC.SYSCLKFreq_VALUE=168000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.USBFSEnable=true -RCC.USBHSEnable=false RCC.VCOI2SOutputFreq_Value=384000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=336000000 @@ -522,12 +488,11 @@ SH.S_TIM8_CH3.0=TIM8_CH3,PWM Generation3 CH3 CH3N SH.S_TIM8_CH3.ConfNb=1 SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 SPI3.CLKPhase=SPI_PHASE_2EDGE -SPI3.CRCPolynomial=10 SPI3.CalculateBaudRate=2.625 MBits/s SPI3.DataSize=SPI_DATASIZE_16BIT SPI3.Direction=SPI_DIRECTION_2LINES SPI3.FirstBit=SPI_FIRSTBIT_MSB -SPI3.IPParameters=Mode,CalculateBaudRate,BaudRatePrescaler,DataSize,FirstBit,CLKPhase,VirtualType,Direction,CRCPolynomial +SPI3.IPParameters=Mode,CalculateBaudRate,BaudRatePrescaler,DataSize,FirstBit,CLKPhase,VirtualType,Direction SPI3.Mode=SPI_MODE_MASTER SPI3.VirtualType=VM_MASTER TIM1.Channel-Output\ Compare4\ No\ Output=TIM_CHANNEL_4 @@ -536,12 +501,10 @@ TIM1.Channel-PWM\ Generation2\ CH2\ CH2N=TIM_CHANNEL_2 TIM1.Channel-PWM\ Generation3\ CH3\ CH3N=TIM_CHANNEL_3 TIM1.CounterMode=TIM_COUNTERMODE_CENTERALIGNED3 TIM1.DeadTime=TIM_1_8_DEADTIME_CLOCKS -TIM1.DefaultOCFastMode-Output\ Compare4\ No\ Output=TIM_OCFAST_DISABLE -TIM1.IPParameters=Channel-PWM Generation2 CH2 CH2N,Channel-PWM Generation3 CH3 CH3N,OCNPolarity_1,OCNPolarity_2,OCNPolarity_3,CounterMode,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Period,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N,DefaultOCFastMode-Output Compare4 No Output,OCNIdleState_4 +TIM1.IPParameters=Channel-PWM Generation2 CH2 CH2N,Channel-PWM Generation3 CH3 CH3N,OCNPolarity_1,OCNPolarity_2,OCNPolarity_3,CounterMode,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Period,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N TIM1.OCMode_PWM-PWM\ Generation1\ CH1\ CH1N=TIM_OCMODE_PWM2 TIM1.OCMode_PWM-PWM\ Generation2\ CH2\ CH2N=TIM_OCMODE_PWM2 TIM1.OCMode_PWM-PWM\ Generation3\ CH3\ CH3N=TIM_OCMODE_PWM2 -TIM1.OCNIdleState_4=TIM_OCNIDLESTATE_RESET TIM1.OCNPolarity_1=TIM_OCNPOLARITY_HIGH TIM1.OCNPolarity_2=TIM_OCNPOLARITY_HIGH TIM1.OCNPolarity_3=TIM_OCNPOLARITY_HIGH @@ -587,18 +550,16 @@ TIM8.OffStateRunMode=TIM_OSSR_ENABLE TIM8.Period=TIM_1_8_PERIOD_CLOCKS TIM8.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE USB_DEVICE.CLASS_NAME_FS=CDC -USB_DEVICE.IPParameters=VirtualMode-CDC_FS,VirtualModeFS,CLASS_NAME_FS,MANUFACTURER_STRING-CDC_FS,PRODUCT_STRING_CDC_FS,VID-CDC_FS,PID_CDC_FS,SERIALNUMBER_STRING_CDC_FS,USBD_HandleTypeDef_FS +USB_DEVICE.IPParameters=VirtualMode-CDC_FS,VirtualModeFS,CLASS_NAME_FS,MANUFACTURER_STRING-CDC_FS,PRODUCT_STRING_CDC_FS,VID-CDC_FS,PID_CDC_FS,SERIALNUMBER_STRING_CDC_FS USB_DEVICE.MANUFACTURER_STRING-CDC_FS=ODrive USB_DEVICE.PID_CDC_FS=0x0D31 USB_DEVICE.PRODUCT_STRING_CDC_FS=ODrive rev 3.1 USB_DEVICE.SERIALNUMBER_STRING_CDC_FS=000000000001 -USB_DEVICE.USBD_HandleTypeDef_FS=hUsbDevice_OTG_FS USB_DEVICE.VID-CDC_FS=0x1209 USB_DEVICE.VirtualMode-CDC_FS=Cdc USB_DEVICE.VirtualModeFS=Cdc_FS -USB_OTG_FS.IPParameters=VirtualMode,vbus_sensing_enable,phy_itface +USB_OTG_FS.IPParameters=VirtualMode,vbus_sensing_enable USB_OTG_FS.VirtualMode=Device_Only -USB_OTG_FS.phy_itface=PCD_PHY_EMBEDDED USB_OTG_FS.vbus_sensing_enable=DISABLE VP_FREERTOS_VS_ENABLE.Mode=Enabled VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE diff --git a/Src/adc.c b/Src/adc.c index 7da5b6aa..1d06f4e3 100644 --- a/Src/adc.c +++ b/Src/adc.c @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the ADC instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -77,7 +82,7 @@ void MX_ADC1_Init(void) hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; if (HAL_ADC_Init(&hadc1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. @@ -87,7 +92,7 @@ void MX_ADC1_Init(void) sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time @@ -103,7 +108,7 @@ void MX_ADC1_Init(void) sConfigInjected.InjectedOffset = 0; if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -129,7 +134,7 @@ void MX_ADC2_Init(void) hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; if (HAL_ADC_Init(&hadc2) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. @@ -139,7 +144,7 @@ void MX_ADC2_Init(void) sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time @@ -155,7 +160,7 @@ void MX_ADC2_Init(void) sConfigInjected.InjectedOffset = 0; if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -181,7 +186,7 @@ void MX_ADC3_Init(void) hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; if (HAL_ADC_Init(&hadc3) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. @@ -191,7 +196,7 @@ void MX_ADC3_Init(void) sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time @@ -207,7 +212,7 @@ void MX_ADC3_Init(void) sConfigInjected.InjectedOffset = 0; if (HAL_ADCEx_InjectedConfigChannel(&hadc3, &sConfigInjected) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -221,7 +226,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ - /* Peripheral clock enable */ + /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); /**ADC1 GPIO Configuration @@ -260,7 +265,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) /* USER CODE BEGIN ADC2_MspInit 0 */ /* USER CODE END ADC2_MspInit 0 */ - /* Peripheral clock enable */ + /* ADC2 clock enable */ __HAL_RCC_ADC2_CLK_ENABLE(); /**ADC2 GPIO Configuration @@ -299,7 +304,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) /* USER CODE BEGIN ADC3_MspInit 0 */ /* USER CODE END ADC3_MspInit 0 */ - /* Peripheral clock enable */ + /* ADC3 clock enable */ __HAL_RCC_ADC3_CLK_ENABLE(); /**ADC3 GPIO Configuration @@ -351,7 +356,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) HAL_GPIO_DeInit(GPIOA, VBUS_S_Pin|M1_TEMP_Pin|AUX_I_Pin|GPIO_4_Pin |GPIO_3_Pin|GPIO_2_Pin|AUX_V_Pin); - /* Peripheral interrupt Deinit*/ + /* ADC1 interrupt Deinit */ /* USER CODE BEGIN ADC1:ADC_IRQn disable */ /** * Uncomment the line below to disable the "ADC_IRQn" interrupt @@ -393,7 +398,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) HAL_GPIO_DeInit(GPIOA, VBUS_S_Pin|M1_TEMP_Pin|AUX_I_Pin|GPIO_4_Pin |GPIO_3_Pin|GPIO_2_Pin|AUX_V_Pin); - /* Peripheral interrupt Deinit*/ + /* ADC2 interrupt Deinit */ /* USER CODE BEGIN ADC2:ADC_IRQn disable */ /** * Uncomment the line below to disable the "ADC_IRQn" interrupt @@ -422,7 +427,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) */ HAL_GPIO_DeInit(GPIOC, M0_IB_Pin|M0_IC_Pin|M1_IC_Pin|M1_IB_Pin); - /* Peripheral interrupt Deinit*/ + /* ADC3 interrupt Deinit */ /* USER CODE BEGIN ADC3:ADC_IRQn disable */ /** * Uncomment the line below to disable the "ADC_IRQn" interrupt diff --git a/Src/can.c b/Src/can.c index 52091b30..6462e5d4 100644 --- a/Src/can.c +++ b/Src/can.c @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the CAN instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -71,7 +76,7 @@ void MX_CAN1_Init(void) hcan1.Init.TXFP = DISABLE; if (HAL_CAN_Init(&hcan1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -85,7 +90,7 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) /* USER CODE BEGIN CAN1_MspInit 0 */ /* USER CODE END CAN1_MspInit 0 */ - /* Peripheral clock enable */ + /* CAN1 clock enable */ __HAL_RCC_CAN1_CLK_ENABLE(); /**CAN1 GPIO Configuration @@ -122,10 +127,10 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle) */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); - } /* USER CODE BEGIN CAN1_MspDeInit 1 */ /* USER CODE END CAN1_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ diff --git a/Src/freertos.c b/Src/freertos.c index 0db19c50..c445cdd6 100644 --- a/Src/freertos.c +++ b/Src/freertos.c @@ -3,6 +3,11 @@ * File Name : freertos.c * Description : Code for freertos applications ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -46,7 +51,7 @@ #include "task.h" #include "cmsis_os.h" -/* USER CODE BEGIN Includes */ +/* USER CODE BEGIN Includes */ #include "freertos_vars.h" #include "low_level.h" #include "version.h" diff --git a/Src/gpio.c b/Src/gpio.c index a14d7230..6f088d7d 100644 --- a/Src/gpio.c +++ b/Src/gpio.c @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of all used GPIO pins. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Src/main.c b/Src/main.c index 5e854c47..aff09ebc 100644 --- a/Src/main.c +++ b/Src/main.c @@ -3,6 +3,11 @@ * File Name : main.c * Description : Main program body ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -64,7 +69,6 @@ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); -void Error_Handler(void); void MX_FREERTOS_Init(void); static void MX_NVIC_Init(void); @@ -89,9 +93,17 @@ int main(void) /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + /* Configure the system clock */ SystemClock_Config(); + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_ADC1_Init(); @@ -163,7 +175,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLQ = 7; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Initializes the CPU, AHB and APB busses clocks @@ -177,7 +189,7 @@ void SystemClock_Config(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } /**Configure the Systick interrupt time @@ -210,14 +222,14 @@ static void MX_NVIC_Init(void) * @param None * @retval None */ -void Error_Handler(void) +void _Error_Handler(char * file, int line) { - /* USER CODE BEGIN Error_Handler */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ while(1) { } - /* USER CODE END Error_Handler */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT diff --git a/Src/spi.c b/Src/spi.c index 48c7c4ae..c41b3e0e 100644 --- a/Src/spi.c +++ b/Src/spi.c @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the SPI instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -71,7 +76,7 @@ void MX_SPI3_Init(void) hspi3.Init.CRCPolynomial = 10; if (HAL_SPI_Init(&hspi3) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -85,7 +90,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) /* USER CODE BEGIN SPI3_MspInit 0 */ /* USER CODE END SPI3_MspInit 0 */ - /* Peripheral clock enable */ + /* SPI3 clock enable */ __HAL_RCC_SPI3_CLK_ENABLE(); /**SPI3 GPIO Configuration @@ -124,10 +129,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12); - } /* USER CODE BEGIN SPI3_MspDeInit 1 */ /* USER CODE END SPI3_MspDeInit 1 */ + } } /* USER CODE BEGIN 1 */ diff --git a/Src/stm32f4xx_hal_msp.c b/Src/stm32f4xx_hal_msp.c index 54983c5f..d3a01499 100644 --- a/Src/stm32f4xx_hal_msp.c +++ b/Src/stm32f4xx_hal_msp.c @@ -4,6 +4,11 @@ * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -44,7 +49,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" -extern void Error_Handler(void); +extern void _Error_Handler(char *, int); /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ diff --git a/Src/tim.c b/Src/tim.c index 7199b66d..5131b240 100644 --- a/Src/tim.c +++ b/Src/tim.c @@ -4,6 +4,11 @@ * Description : This file provides code for the configuration * of the TIM instances. ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -91,30 +96,30 @@ void MX_TIM1_Init(void) htim1.Init.RepetitionCounter = 0; if (HAL_TIM_Base_Init(&htim1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_OC_Init(&htim1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sConfigOC.OCMode = TIM_OCMODE_PWM2; @@ -126,23 +131,23 @@ void MX_TIM1_Init(void) sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sConfigOC.OCMode = TIM_OCMODE_TIMING; if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; @@ -154,7 +159,7 @@ void MX_TIM1_Init(void) sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } HAL_TIM_MspPostInit(&htim1); @@ -173,14 +178,14 @@ void MX_TIM2_Init(void) htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sConfigOC.OCMode = TIM_OCMODE_PWM2; @@ -189,14 +194,14 @@ void MX_TIM2_Init(void) sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sConfigOC.Pulse = TIM_APB1_PERIOD_CLOCKS+1; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } HAL_TIM_MspPostInit(&htim2); @@ -224,14 +229,14 @@ void MX_TIM3_Init(void) sConfig.IC2Filter = 4; if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -257,14 +262,14 @@ void MX_TIM4_Init(void) sConfig.IC2Filter = 4; if (HAL_TIM_Encoder_Init(&htim4, &sConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } } @@ -283,14 +288,14 @@ void MX_TIM8_Init(void) htim8.Init.RepetitionCounter = 0; if (HAL_TIM_PWM_Init(&htim8) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sConfigOC.OCMode = TIM_OCMODE_PWM2; @@ -302,17 +307,17 @@ void MX_TIM8_Init(void) sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE; @@ -324,7 +329,7 @@ void MX_TIM8_Init(void) sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } HAL_TIM_MspPostInit(&htim8); @@ -339,7 +344,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ - /* Peripheral clock enable */ + /* TIM1 clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); /* USER CODE BEGIN TIM1_MspInit 1 */ @@ -355,7 +360,7 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ - /* Peripheral clock enable */ + /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); /* USER CODE BEGIN TIM2_MspInit 1 */ @@ -366,7 +371,7 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) /* USER CODE BEGIN TIM8_MspInit 0 */ /* USER CODE END TIM8_MspInit 0 */ - /* Peripheral clock enable */ + /* TIM8 clock enable */ __HAL_RCC_TIM8_CLK_ENABLE(); /* USER CODE BEGIN TIM8_MspInit 1 */ @@ -383,7 +388,7 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ - /* Peripheral clock enable */ + /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); /**TIM3 GPIO Configuration @@ -406,7 +411,7 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) /* USER CODE BEGIN TIM4_MspInit 0 */ /* USER CODE END TIM4_MspInit 0 */ - /* Peripheral clock enable */ + /* TIM4 clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); /**TIM4 GPIO Configuration @@ -533,10 +538,10 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM1_CLK_DISABLE(); - } /* USER CODE BEGIN TIM1_MspDeInit 1 */ /* USER CODE END TIM1_MspDeInit 1 */ + } } void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) diff --git a/Src/usb_device.c b/Src/usb_device.c index d8fb706d..300c3573 100644 --- a/Src/usb_device.c +++ b/Src/usb_device.c @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : This file implements the USB Device ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Src/usbd_cdc_if.c b/Src/usbd_cdc_if.c index 4f06cc58..6ecc7119 100644 --- a/Src/usbd_cdc_if.c +++ b/Src/usbd_cdc_if.c @@ -3,6 +3,11 @@ * @file : usbd_cdc_if.c * @brief : ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. diff --git a/Src/usbd_conf.c b/Src/usbd_conf.c index 0b471eea..39a6d803 100644 --- a/Src/usbd_conf.c +++ b/Src/usbd_conf.c @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : This file implements the board support package for the USB device library ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. @@ -48,7 +53,7 @@ #include "usbd_core.h" PCD_HandleTypeDef hpcd_USB_OTG_FS; -void Error_Handler(void); +void _Error_Handler(char * file, int line); /* External functions --------------------------------------------------------*/ void SystemClock_Config(void); @@ -300,7 +305,7 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev) hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) { - Error_Handler(); + _Error_Handler(__FILE__, __LINE__); } HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); diff --git a/Src/usbd_desc.c b/Src/usbd_desc.c index 725c96fe..1e8f425f 100644 --- a/Src/usbd_desc.c +++ b/Src/usbd_desc.c @@ -4,6 +4,11 @@ * @version : v1.0_Cube * @brief : This file implements the USB Device descriptors ****************************************************************************** + * This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved.