From c15dba8c4707e01db8b07f0dca968bec8eb16202 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 25 Sep 2018 23:39:11 -0700 Subject: [PATCH 001/106] try fixing the odd div behaviour --- docs/getting-started.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/docs/getting-started.md b/docs/getting-started.md index f4035948..c0e0dc7d 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -162,7 +162,6 @@ You can read more about `odrivetool` [here](odrivetool.md). ### 1. Set the limits:
Wait, how do I set these?
- In the previous step we started `odrivetool`. In there, you can assign variables directly by name. For instance, to set the current limit of M0 to 10A you would type: `odrv0.axis0.motor.config.current_lim = 10` Enter @@ -173,12 +172,12 @@ For instance, to set the current limit of M0 to 10A you would type: `odrv0.axis0 The default current limit, for safety reasons, is set to 10A. This is quite weak, but good for making sure the drive is stable. Once you have tuned the oDrive, you can increase this to 75A to increase performance. Note that above 75A, you must change the current amplifier gains. You do this by requesting a different current range. i.e. for 90A on M0: `odrv0.axis0.motor.config.requested_current_range = 90` [A], then save the configuration and reboot as the gains are written out to the DRV (MOSFET driver) only during startup. *Note: The motor current and the current drawn from the power supply is not the same in general. You should not look at the power supply current to see what is going on with the motor current.* -
Ok, so tell me how it actually works then...
The current in the motor is only connected to the current in the power supply _sometimes_ and other times it just cycles out of one phase and back in the other. This is what the modulation magnitude is (sometimes people call this duty cycle, but that's a bit confusing because we use SVM not straight PWM). When the modulation magnitude is 0, the average voltage seen across the motor phases is 0, and the motor current is never connected to the power supply. When the magnitude is 100%, it is always connected, and at 50% it's connected half the time, and cycled in just the motor half the time. The largest effect on modulation magnitude is speed. There are other smaller factors, but in general: if the motor is still it's not unreasonable to have 50A in the motor from 5A on the power supply. When the motor is spinning close to top speed, the power supply current and the motor current will be somewhat close to each other. -
+
+ #### Velocity limit `odrv0.axis0.controller.config.vel_limit` [counts/s]. The motor will be limited to this speed. Again the default value is quite slow. @@ -194,7 +193,6 @@ This is the number of **magnet poles** in the rotor, **divided by two**. To find If you can't see them, try sliding a magnet around the rotor, and counting how many times it stops. This will be the number of **pole pairs**. If you use a magnetic piece of metal instead of a magnet, you will get the number of **magnet poles**. `odrv0.axis0.motor.config.motor_type` This is the type of motor being used. Currently two types of motors are supported: High-current motors (`MOTOR_TYPE_HIGH_CURRENT`) and gimbal motors (`MOTOR_TYPE_GIMBAL`). -
Which motor_type to choose?
If you're using a regular hobby brushless motor like [this](https://hobbyking.com/en_us/turnigy-aerodrive-sk3-5065-236kv-brushless-outrunner-motor.html) one, you should set `motor_mode` to `MOTOR_TYPE_HIGH_CURRENT`. For low-current gimbal motors like [this](https://hobbyking.com/en_us/turnigy-hd-5208-brushless-gimbal-motor-bldc.html) one, you should choose `MOTOR_TYPE_GIMBAL`. Do not use `MOTOR_TYPE_GIMBAL` on a motor that is not a gimbal motor, as it may overheat the motor or the ODrive. @@ -203,7 +201,6 @@ If you're using a regular hobby brushless motor like [this](https://hobbyking.co If 100's of mA of current noise is "small" for you, you can choose `MOTOR_TYPE_HIGH_CURRENT`. If 100's of mA of current noise is "large" for you, and you do not intend to spin the motor very fast (Ω * L << R), and the motor is fairly large resistance (1 ohm or larger), you can chose `MOTOR_TYPE_GIMBAL`. If 100's of mA current noise is "large" for you, _and_ you intend to spin the motor fast, then you need to replace the shunt resistors on the ODrive. -

*Note: When using gimbal motors,* `current_lim` *and* `calibration_current` *actually mean "voltage limit" and "calibration voltage", since we don't use current feedback. This means that if you set it to 10, it means 10V, despite the name of the parameter.* From 71160b5c937f0bd71499357a6d263b072a7cd3c9 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 25 Sep 2018 23:58:37 -0700 Subject: [PATCH 002/106] chagne style of 4th lvl header --- docs/getting-started.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/getting-started.md b/docs/getting-started.md index c0e0dc7d..65182418 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -132,10 +132,10 @@ Try step 5 again ``` ## Firmware -#### ODrive v3.5 and later +**ODrive v3.5 and later** Your board should come preflashed with firmware. If you run into problems, follow the instructions [here](odrivetool.md#device-firmware-update) on the DFU procedure before you continue. -#### ODrive v3.4 and earlier +**ODrive v3.4 and earlier** Your board does **not** come preflashed with any firmware. Follow the instructions [here](odrivetool.md#device-firmware-update) on the STP Link procedure before you continue. ## Start `odrivetool` @@ -167,7 +167,7 @@ In the previous step we started `odrivetool`. In there, you can assign variables For instance, to set the current limit of M0 to 10A you would type: `odrv0.axis0.motor.config.current_lim = 10` Enter -#### Current limit +**Current limit** `odrv0.axis0.motor.config.current_lim` [A]. The default current limit, for safety reasons, is set to 10A. This is quite weak, but good for making sure the drive is stable. Once you have tuned the oDrive, you can increase this to 75A to increase performance. Note that above 75A, you must change the current amplifier gains. You do this by requesting a different current range. i.e. for 90A on M0: `odrv0.axis0.motor.config.requested_current_range = 90` [A], then save the configuration and reboot as the gains are written out to the DRV (MOSFET driver) only during startup. @@ -178,10 +178,10 @@ The current in the motor is only connected to the current in the power supply _s The largest effect on modulation magnitude is speed. There are other smaller factors, but in general: if the motor is still it's not unreasonable to have 50A in the motor from 5A on the power supply. When the motor is spinning close to top speed, the power supply current and the motor current will be somewhat close to each other. -#### Velocity limit +**Velocity limit** `odrv0.axis0.controller.config.vel_limit` [counts/s]. The motor will be limited to this speed. Again the default value is quite slow. -#### Calibration current +**Calibration current** You can change `odrv0.axis0.motor.config.calibration_current` [A] to the largest value you feel comfortable leaving running through the motor continuously when the motor is stationary. If you are using a small motor (i.e. 15A current rated) you may need to reduce `calibration_current` to a value smaller than the default. ### 2. Set other hardware parameters @@ -205,10 +205,10 @@ If 100's of mA current noise is "large" for you, _and_ you intend to spin the mo *Note: When using gimbal motors,* `current_lim` *and* `calibration_current` *actually mean "voltage limit" and "calibration voltage", since we don't use current feedback. This means that if you set it to 10, it means 10V, despite the name of the parameter.* -#### If using encoder +**If using encoder** `odrv0.axis0.encoder.config.cpr`: Encoder Count Per Revolution [CPR] This is 4x the Pulse Per Revolution (PPR) value. Usually this is indicated in the datasheet of your encoder. -#### If not using encoder +**If not using encoder** * If you wish to run in sensorless mode, please see [Setting up sensorless](commands.md#setting-up-sensorless). * If you are using hall sensor feedback, please see the [hoverboard motor example](hoverboard.md). @@ -245,10 +245,10 @@ Let's get motor 0 up and running. The procedure for motor 1 is exactly the same, ### Other control modes The ODrive also supports velocity control and current (torque) control. -#### Velocity control +**Velocity control** Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`. You can now control the velocity with `odrv0.axis0.controller.vel_setpoint = 5000` [count/s]. -#### Current control +**Current control** Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_CURRENT_CONTROL`. You can now control the current with `odrv0.axis0.controller.current_setpoint = 3` [A]. From 0c7724cdbd2373a65a3ab8cd83522d5f1f5bf5df Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 26 Sep 2018 00:04:18 -0700 Subject: [PATCH 003/106] chagne style of 4th lvl header --- docs/getting-started.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/getting-started.md b/docs/getting-started.md index 65182418..f175fb43 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -132,10 +132,10 @@ Try step 5 again ``` ## Firmware -**ODrive v3.5 and later** +**ODrive v3.5 and later**
Your board should come preflashed with firmware. If you run into problems, follow the instructions [here](odrivetool.md#device-firmware-update) on the DFU procedure before you continue. -**ODrive v3.4 and earlier** +**ODrive v3.4 and earlier**
Your board does **not** come preflashed with any firmware. Follow the instructions [here](odrivetool.md#device-firmware-update) on the STP Link procedure before you continue. ## Start `odrivetool` @@ -167,7 +167,7 @@ In the previous step we started `odrivetool`. In there, you can assign variables For instance, to set the current limit of M0 to 10A you would type: `odrv0.axis0.motor.config.current_lim = 10` Enter -**Current limit** +**Current limit**
`odrv0.axis0.motor.config.current_lim` [A]. The default current limit, for safety reasons, is set to 10A. This is quite weak, but good for making sure the drive is stable. Once you have tuned the oDrive, you can increase this to 75A to increase performance. Note that above 75A, you must change the current amplifier gains. You do this by requesting a different current range. i.e. for 90A on M0: `odrv0.axis0.motor.config.requested_current_range = 90` [A], then save the configuration and reboot as the gains are written out to the DRV (MOSFET driver) only during startup. @@ -178,10 +178,10 @@ The current in the motor is only connected to the current in the power supply _s The largest effect on modulation magnitude is speed. There are other smaller factors, but in general: if the motor is still it's not unreasonable to have 50A in the motor from 5A on the power supply. When the motor is spinning close to top speed, the power supply current and the motor current will be somewhat close to each other. -**Velocity limit** +**Velocity limit**
`odrv0.axis0.controller.config.vel_limit` [counts/s]. The motor will be limited to this speed. Again the default value is quite slow. -**Calibration current** +**Calibration current**
You can change `odrv0.axis0.motor.config.calibration_current` [A] to the largest value you feel comfortable leaving running through the motor continuously when the motor is stationary. If you are using a small motor (i.e. 15A current rated) you may need to reduce `calibration_current` to a value smaller than the default. ### 2. Set other hardware parameters @@ -205,10 +205,10 @@ If 100's of mA current noise is "large" for you, _and_ you intend to spin the mo *Note: When using gimbal motors,* `current_lim` *and* `calibration_current` *actually mean "voltage limit" and "calibration voltage", since we don't use current feedback. This means that if you set it to 10, it means 10V, despite the name of the parameter.* -**If using encoder** +**If using encoder**
`odrv0.axis0.encoder.config.cpr`: Encoder Count Per Revolution [CPR] This is 4x the Pulse Per Revolution (PPR) value. Usually this is indicated in the datasheet of your encoder. -**If not using encoder** +**If not using encoder**
* If you wish to run in sensorless mode, please see [Setting up sensorless](commands.md#setting-up-sensorless). * If you are using hall sensor feedback, please see the [hoverboard motor example](hoverboard.md). @@ -245,10 +245,10 @@ Let's get motor 0 up and running. The procedure for motor 1 is exactly the same, ### Other control modes The ODrive also supports velocity control and current (torque) control. -**Velocity control** +**Velocity control**
Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`. You can now control the velocity with `odrv0.axis0.controller.vel_setpoint = 5000` [count/s]. -**Current control** +**Current control**
Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_CURRENT_CONTROL`. You can now control the current with `odrv0.axis0.controller.current_setpoint = 3` [A]. From 3f7637b5677b3c372799b810913e0651b34689b0 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 26 Sep 2018 15:12:01 -0700 Subject: [PATCH 004/106] chagne style of 4th lvl header --- docs/getting-started.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/getting-started.md b/docs/getting-started.md index f175fb43..dd5362ff 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -181,6 +181,7 @@ The largest effect on modulation magnitude is speed. There are other smaller fac **Velocity limit**
`odrv0.axis0.controller.config.vel_limit` [counts/s]. The motor will be limited to this speed. Again the default value is quite slow. + **Calibration current**
You can change `odrv0.axis0.motor.config.calibration_current` [A] to the largest value you feel comfortable leaving running through the motor continuously when the motor is stationary. If you are using a small motor (i.e. 15A current rated) you may need to reduce `calibration_current` to a value smaller than the default. @@ -208,6 +209,7 @@ If 100's of mA current noise is "large" for you, _and_ you intend to spin the mo **If using encoder**
`odrv0.axis0.encoder.config.cpr`: Encoder Count Per Revolution [CPR] This is 4x the Pulse Per Revolution (PPR) value. Usually this is indicated in the datasheet of your encoder. + **If not using encoder**
* If you wish to run in sensorless mode, please see [Setting up sensorless](commands.md#setting-up-sensorless). * If you are using hall sensor feedback, please see the [hoverboard motor example](hoverboard.md). @@ -245,9 +247,11 @@ Let's get motor 0 up and running. The procedure for motor 1 is exactly the same, ### Other control modes The ODrive also supports velocity control and current (torque) control. + **Velocity control**
Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`. You can now control the velocity with `odrv0.axis0.controller.vel_setpoint = 5000` [count/s]. + **Current control**
Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_CURRENT_CONTROL`. You can now control the current with `odrv0.axis0.controller.current_setpoint = 3` [A]. From 68ddd5f07fa1e3cb9521209fd654a539183c26f2 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 26 Sep 2018 16:59:33 -0700 Subject: [PATCH 005/106] Update troubleshooting.md --- docs/troubleshooting.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/troubleshooting.md b/docs/troubleshooting.md index b6d36720..756f2b62 100644 --- a/docs/troubleshooting.md +++ b/docs/troubleshooting.md @@ -66,7 +66,12 @@ Out[2]: 1.408751450071577e-05 In [3]: odrv0.axis0.motor.config.phase_resistance Out[3]: 0.029788672924041748 ``` -Some motors will have a considerably different phase resistance and inductance than this. For example, gimbal motors, some small motors (e.g. < 10A peak current). If you think this applies to you try increasing `odrv0.axis0.motor.config.resistance_calib_max_voltage` from its default value of 1 using odrive tool and repeat the motor calibration process. If your motor has a small peak current draw (e.g. < 20A) you can also try decreasing `odrv0.axis0.motor.config.calibration_current` from its default value of 10A. +Some motors will have a considerably different phase resistance and inductance than this. For example, gimbal motors, some small motors (e.g. < 10A peak current). If you think this applies to you try increasing `odrv0.axis0.motor.config.resistance_calib_max_voltage` from its default value of 1 using odrivetool and repeat the motor calibration process. If your motor has a small peak current draw (e.g. < 20A) you can also try decreasing `odrv0.axis0.motor.config.calibration_current` from its default value of 10A. + +In general, you need +```text +resistance_calib_max_voltage > calibration_current * phase_resistance`. +``` * `ERROR_DRV_FAULT = 0x0008` From 671d2cced247f452afaa42acc0ad7aa5f7391c35 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 29 Sep 2018 14:07:09 -0700 Subject: [PATCH 006/106] Update hoverboard.md --- docs/hoverboard.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/docs/hoverboard.md b/docs/hoverboard.md index 5cf64332..5ad40184 100644 --- a/docs/hoverboard.md +++ b/docs/hoverboard.md @@ -5,6 +5,20 @@ Each step is acompanied by some explanation so hopefully you can carry over some [![IMAGE ALT TEXT HERE](https://img.youtube.com/vi/ponx_U4xhoM/0.jpg)](https://www.youtube.com/watch?v=ponx_U4xhoM)
Click above to play video. +### Hoverboard motor wiring +Hoverboard motors come with three motor phases (usually colored yellow, blue, green) which are thicker, and a set of 5 thinner wires for the hall sensor feedback (usually colored red, yellow, blue, green, black). + +You may wire the motor phases in any order into a motor connector on the ODrive, as we will calibrate the phase alignment later anyway. Wire the hall feedback into the ODrive J2 conenctor (make sure that the motor channel number matches) as follows: + +| Hall wire | J2 signal | +|-----------|-----------| +| Red | 5V | +| Yellow | A | +| Blue | B | +| Green | Z | +| Black | GND | + + ### Hoverboard motor configuration Standard 6.5 inch hoverboard hub motors have 30 permanent magnet poles, and thus 15 pole pairs. If you have a different motor you need to count the magnets or have a reliable datasheet for this information. ```txt From b8e449b138ec5f439e5168cf078ddf7328ee5089 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 29 Sep 2018 23:59:26 -0700 Subject: [PATCH 007/106] Update encoders.md --- docs/encoders.md | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/docs/encoders.md b/docs/encoders.md index 8735575f..04cf9663 100644 --- a/docs/encoders.md +++ b/docs/encoders.md @@ -1,15 +1,7 @@ # Encoders ## Known and Supported Encoders -Contributions to this table highly encouraged! - -Encoder|Manufacturer|Output|Index|Max CPR|Max RPM|Voltage|Supported|Price|Link|Datasheet -:--|:--|:--|:-:|:-:|:-:|:-:|:--|:--|:--|:-- -AMT102|CUI|Quadrature|Yes|8192 (2048 * 4)|-|5V|Yes|-|-|- -AMT203|CUI|Quadrature + Absolute|Yes|4096 (1024 * 4)|-|5V|Quadrature Only|-|-|- -AS5047P|AMS|Quadrature + Absolute|Yes|4096 (1024 * 4)|28k|3.3V or 5V|Quadrature Only|-|-|- -E6B2-CWZ6C|Omron|Quadrature|Yes|8000 (2000 * 4)|-|5-24V|Yes|-|-|[Datasheet](http://www.ia.omron.com/products/family/487/) -J733|-|Quadrature|No|2400 (600 * 4)|-|5-24V|Yes|-|-|- +Check out the [ODrive Encoder Guide](https://docs.google.com/spreadsheets/d/1OBDwYrBb5zUPZLrhL98ezZbg94tUsZcdTuwiVNgVqpU). ## Encoder Calibration From 73b8521827080750ea3c7e984877a6a3d85ed05c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 30 Sep 2018 12:54:40 -0700 Subject: [PATCH 008/106] Update Gemfile.lock --- docs/Gemfile.lock | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/Gemfile.lock b/docs/Gemfile.lock index feb6c6f6..20e81d61 100644 --- a/docs/Gemfile.lock +++ b/docs/Gemfile.lock @@ -25,13 +25,13 @@ GEM execjs (2.7.0) faraday (0.14.0) multipart-post (>= 1.2, < 3) - ffi (1.9.23) + ffi (1.9.24) forwardable-extended (2.6.0) gemoji (3.0.0) github-pages (181) activesupport (= 4.2.9) github-pages-health-check (= 1.4.0) - jekyll (= 3.7.3) + jekyll (= 3.7.4) jekyll-avatar (= 0.5.0) jekyll-coffeescript (= 1.1.1) jekyll-commonmark-ghpages (= 0.1.5) @@ -85,7 +85,7 @@ GEM http_parser.rb (0.6.0) i18n (0.9.5) concurrent-ruby (~> 1.0) - jekyll (3.7.3) + jekyll (3.7.4) addressable (~> 2.4) colorator (~> 1.0) em-websocket (~> 0.5) @@ -134,7 +134,7 @@ GEM jekyll (~> 3.3) jekyll-remote-theme (0.2.3) jekyll (~> 3.5) - rubyzip (>= 1.2.1, < 3.0) + rubyzip (>= 1.2.2, < 3.0) typhoeus (>= 0.7, < 2.0) jekyll-sass-converter (1.5.2) sass (~> 3.4) From 8e8b7787ea46ae7158b946a87700b7ed7cfec246 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 30 Sep 2018 20:31:50 -0700 Subject: [PATCH 009/106] Update getting-started.md --- docs/getting-started.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/getting-started.md b/docs/getting-started.md index dd5362ff..ad0c7956 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -24,7 +24,7 @@ permalink: / ### You will need: * One or two [brushless motors](https://docs.google.com/spreadsheets/d/12vzz7XVEK6YNIOqH0jAz51F5VUpc-lJEs3mmkWP1H4Y). It is fine, even recommended, to start testing with just a single motor and encoder. -* One or two [quadrature incremental encoder(s)](encoders) +* One or two [encoder(s)](https://docs.google.com/spreadsheets/d/1OBDwYrBb5zUPZLrhL98ezZbg94tUsZcdTuwiVNgVqpU) * A power resistor. A good starting point would be the 50W resistor included with your ODrive.
Do I really need a power resistor? What values to choose?
From 1c39a6078defdf4e5b5805fa21339d9b780f1e4b Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Thu, 4 Oct 2018 18:57:31 -0700 Subject: [PATCH 010/106] Update troubleshooting.md --- docs/troubleshooting.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/troubleshooting.md b/docs/troubleshooting.md index 756f2b62..c05c7f92 100644 --- a/docs/troubleshooting.md +++ b/docs/troubleshooting.md @@ -38,7 +38,7 @@ The axis error may say that some other component has failed. Say it reports `ERR * `ERROR_INVALID_STATE = 0x01` -Typically returned along with another error. Resolve that error and then reboot using `odrv0.reboot()` or remoivng power, waiting 5 seconds and restoring power to return to normal operating. +You tried to run a state before you are allowed to. Typically you tried to run encoder calibration or closed loop control before the motor was calibrated, or you tried to run closed loop control before the encoder was calibrated. * `ERROR_DC_BUS_UNDER_VOLTAGE = 0x02` From 2c5b4f93a15b6a31359245202c166fc1d4848f74 Mon Sep 17 00:00:00 2001 From: je310 Date: Fri, 5 Oct 2018 12:43:43 +0100 Subject: [PATCH 011/106] Update axis.hpp Added direction in the comments for the error codes to go look at the relevant hpp. When skimming the help documentation one assumes you arrive at an unhelpful error, such as ERROR_MOTOR_FAILED, when there is more information to be had. --- Firmware/MotorControl/axis.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 111f9e26..d78cb54f 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -49,9 +49,9 @@ public: ERROR_CURRENT_MEASUREMENT_TIMEOUT = 0x08, ERROR_BRAKE_RESISTOR_DISARMED = 0x10, // Date: Fri, 5 Oct 2018 20:28:55 -0700 Subject: [PATCH 012/106] add component guide links to sidebar --- docs/_data/index.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/_data/index.yaml b/docs/_data/index.yaml index 786c5559..fabd32ee 100644 --- a/docs/_data/index.yaml +++ b/docs/_data/index.yaml @@ -27,3 +27,9 @@ sections: url: configuring-vscode - title: Configuring Eclipse url: configuring-eclipse + - title: Component Guides + docs: + - title: Motor Guide + url: https://docs.google.com/spreadsheets/d/12vzz7XVEK6YNIOqH0jAz51F5VUpc-lJEs3mmkWP1H4Y + - title: Encoder Guide + url: https://docs.google.com/spreadsheets/d/1OBDwYrBb5zUPZLrhL98ezZbg94tUsZcdTuwiVNgVqpU \ No newline at end of file From 5a22821bcdca05d417299532f30ceee207d8f5d7 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 6 Oct 2018 19:33:33 -0700 Subject: [PATCH 013/106] release firmware v0.4.5 --- CHANGELOG.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index efa2966c..fda2aca8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,8 +1,9 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. -# Unreleased +# Releases +## [0.4.5] - 2018-10-06 ### Added * **Trapezoidal Trajectory Planner** * Hook to execute protocol property written callback @@ -24,7 +25,6 @@ Please add a note of your changes below this heading if you make a Pull Request. * An issue where the axis state machine would jump in and out of idle when there is an error * There is a [bug](https://github.com/ARM-software/CMSIS_5/issues/267) in the arm fast math library, which gives spikes in the output of arm_cos_f32 for input values close to -pi/2. We fixed the bug locally, and hence are using "our_arm_cos_f32". -# Releases ## [0.4.4] - 2018-09-18 ### Fixed * Serious reliability issue with USB communication where packets on Native and the CDC interface would collide with each other. From 26eb4e776506a58ee51e20f9555c23161ae73a4c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 7 Oct 2018 13:12:37 -0700 Subject: [PATCH 014/106] disable PWM straight away on motor error --- Firmware/MotorControl/motor.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Firmware/MotorControl/motor.cpp b/Firmware/MotorControl/motor.cpp index ee71c98a..230f7f64 100644 --- a/Firmware/MotorControl/motor.cpp +++ b/Firmware/MotorControl/motor.cpp @@ -136,6 +136,8 @@ bool Motor::check_DRV_fault() { void Motor::set_error(Motor::Error_t error){ error_ |= error; axis_->error_ |= Axis::ERROR_MOTOR_FAILED; + safety_critical_disarm_motor_pwm(*this); + update_brake_current(); } bool Motor::do_checks() { From 321332cb24224b1accf659f70714d1589e6617ce Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 7 Oct 2018 16:20:00 -0700 Subject: [PATCH 015/106] fix ascii float print bug --- CHANGELOG.md | 3 +++ Firmware/fibre/cpp/include/fibre/protocol.hpp | 18 ++++++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index fda2aca8..07a30ae6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,9 @@ Please add a note of your changes below this heading if you make a Pull Request. # Releases +## [0.4.6] - 2018-10-07 +### Fixed +* Broken printing of floats on ascii protocol ## [0.4.5] - 2018-10-06 ### Added diff --git a/Firmware/fibre/cpp/include/fibre/protocol.hpp b/Firmware/fibre/cpp/include/fibre/protocol.hpp index e599c0d9..4b503e68 100644 --- a/Firmware/fibre/cpp/include/fibre/protocol.hpp +++ b/Firmware/fibre/cpp/include/fibre/protocol.hpp @@ -603,6 +603,14 @@ struct format_traits_t; // static constexpr const char * fmt = "%f"; // static constexpr const char * fmtp = "%f"; // }; +template<> struct format_traits_t { using type = void; + static constexpr const char * fmt = "%lld"; + static constexpr const char * fmtp = "%lld"; +}; +template<> struct format_traits_t { using type = void; + static constexpr const char * fmt = "%llu"; + static constexpr const char * fmtp = "%llu"; +}; template<> struct format_traits_t { using type = void; static constexpr const char * fmt = "%ld"; static constexpr const char * fmtp = "%ld"; @@ -634,14 +642,12 @@ static bool to_string(const T& value, char * buffer, size_t length, int) { return true; } // Special case for float because printf promotes float to double, and we get warnings -template +template static bool to_string(const float& value, char * buffer, size_t length, int) { snprintf(buffer, length, "%f", (double)value); return true; } - - -template +template static bool to_string(const bool& value, char * buffer, size_t length, int) { buffer[0] = value ? '1' : '0'; buffer[1] = 0; @@ -657,11 +663,11 @@ static bool from_string(const char * buffer, size_t length, T* property, int) { return sscanf(buffer, format_traits_t::fmt, property) == 1; } // Special case for float because printf promotes float to double, and we get warnings -template +template static bool from_string(const char * buffer, size_t length, float* property, int) { return sscanf(buffer, "%f", property) == 1; } -template +template static bool from_string(const char * buffer, size_t length, bool* property, int) { int val; if (sscanf(buffer, "%d", &val) != 1) From a0cedaaf94ff021bdc0305309f5c417b96485f85 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 7 Oct 2018 21:09:09 -0700 Subject: [PATCH 016/106] clean up critical section use --- Firmware/MotorControl/encoder.cpp | 10 +++---- Firmware/MotorControl/low_level.cpp | 43 ++++++++--------------------- Firmware/MotorControl/low_level.h | 9 ++++++ 3 files changed, 25 insertions(+), 37 deletions(-) diff --git a/Firmware/MotorControl/encoder.cpp b/Firmware/MotorControl/encoder.cpp index b4bb288f..f8e1e530 100644 --- a/Firmware/MotorControl/encoder.cpp +++ b/Firmware/MotorControl/encoder.cpp @@ -60,8 +60,7 @@ void Encoder::enc_index_cb() { // Function that sets the current encoder count to a desired 32-bit value. void Encoder::set_linear_count(int32_t count) { // Disable interrupts to make a critical section to avoid race condition - uint32_t prim = __get_PRIMASK(); - __disable_irq(); + uint32_t prim = cpu_enter_critical(); // Update states shadow_count_ = count; @@ -69,15 +68,14 @@ void Encoder::set_linear_count(int32_t count) { //Write hardware last hw_config_.timer->Instance->CNT = count; - __set_PRIMASK(prim); + cpu_exit_critical(prim); } // Function that sets the CPR circular tracking encoder count to a desired 32-bit value. // Note that this will get mod'ed down to [0, cpr) void Encoder::set_circular_count(int32_t count, bool update_offset) { // Disable interrupts to make a critical section to avoid race condition - uint32_t prim = __get_PRIMASK(); - __disable_irq(); + uint32_t prim = cpu_enter_critical(); if (update_offset) { config_.offset += count - count_in_cpr_; @@ -88,7 +86,7 @@ void Encoder::set_circular_count(int32_t count, bool update_offset) { count_in_cpr_ = mod(count, config_.cpr); pos_cpr_ = (float)count_in_cpr_; - __set_PRIMASK(prim); + cpu_exit_critical(prim); } diff --git a/Firmware/MotorControl/low_level.cpp b/Firmware/MotorControl/low_level.cpp index ffeeeadd..d807dc33 100644 --- a/Firmware/MotorControl/low_level.cpp +++ b/Firmware/MotorControl/low_level.cpp @@ -45,25 +45,6 @@ static const int num_GPIO = sizeof(GPIOs_to_samp) / sizeof(GPIOs_to_samp[0]); static uint16_t GPIO_port_samples [2][num_GPIO]; /* CPU critical section helpers ----------------------------------------------*/ -static inline uint8_t cpu_enter_critical() { - uint8_t status_register; - asm ( - "MRS R0, PRIMASK\n\t" - "CPSID I\n\t" - "STRB R0, %[output]" - : [output] "=m" (status_register) :: "r0" - ); - return status_register; -} - -static inline void cpu_exit_critical(uint8_t status_register) { - asm ( - "ldrb r0, %[input]\n\t" - "msr PRIMASK,r0;\n\t" - ::[input] "m" (status_register) : "r0" - ); -} - /* Safety critical functions -------------------------------------------------*/ /* @@ -115,11 +96,11 @@ void low_level_fault(Motor::Error_t error) { // All calls to this function must clearly originate // from user input. void safety_critical_arm_motor_pwm(Motor& motor) { - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); if (brake_resistor_armed) { motor.armed_state_ = Motor::ARMED_STATE_WAITING_FOR_TIMINGS; } - cpu_exit_critical(sr); + cpu_exit_critical(mask); } // @brief Disarms the motor PWM. @@ -128,11 +109,11 @@ void safety_critical_arm_motor_pwm(Motor& motor) { // safety_critical_arm_motor_phases is called. // @returns true if the motor was in a state other than disarmed before bool safety_critical_disarm_motor_pwm(Motor& motor) { - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); bool was_armed = motor.armed_state_ != Motor::ARMED_STATE_DISARMED; motor.armed_state_ = Motor::ARMED_STATE_DISARMED; __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(motor.hw_config_.timer); - cpu_exit_critical(sr); + cpu_exit_critical(mask); return was_armed; } @@ -142,7 +123,7 @@ bool safety_critical_disarm_motor_pwm(Motor& motor) { // the actual PMW timings on the pins can be undefined for up to one // timer period. void safety_critical_apply_motor_pwm_timings(Motor& motor, uint16_t timings[3]) { - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); if (!brake_resistor_armed) { motor.armed_state_ = Motor::ARMED_STATE_ARMED; } @@ -168,16 +149,16 @@ void safety_critical_apply_motor_pwm_timings(Motor& motor, uint16_t timings[3]) // unknown state oh no safety_critical_disarm_motor_pwm(motor); } - cpu_exit_critical(sr); + cpu_exit_critical(mask); } // @brief Arms the brake resistor void safety_critical_arm_brake_resistor() { - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); brake_resistor_armed = true; htim2.Instance->CCR3 = 0; htim2.Instance->CCR4 = TIM_APB1_PERIOD_CLOCKS + 1; - cpu_exit_critical(sr); + cpu_exit_critical(mask); } // @brief Disarms the brake resistor and by extension @@ -185,14 +166,14 @@ void safety_critical_arm_brake_resistor() { // After calling this, the brake resistor can only be armed again // by calling safety_critical_arm_brake_resistor(). void safety_critical_disarm_brake_resistor() { - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); brake_resistor_armed = false; htim2.Instance->CCR3 = 0; htim2.Instance->CCR4 = TIM_APB1_PERIOD_CLOCKS + 1; for (size_t i = 0; i < AXIS_COUNT; ++i) { safety_critical_disarm_motor_pwm(axes[i]->motor_); } - cpu_exit_critical(sr); + cpu_exit_critical(mask); } // @brief Updates the brake resistor PWM timings unless @@ -200,7 +181,7 @@ void safety_critical_disarm_brake_resistor() { void safety_critical_apply_brake_resistor_timings(uint32_t low_off, uint32_t high_on) { if (high_on - low_off < TIM_APB1_DEADTIME_CLOCKS) low_level_fault(Motor::ERROR_BRAKE_DEADTIME_VIOLATION); - uint8_t sr = cpu_enter_critical(); + uint32_t mask = cpu_enter_critical(); if (brake_resistor_armed) { // Safe update of low and high side timings // To avoid race condition, first reset timings to safe state @@ -210,7 +191,7 @@ void safety_critical_apply_brake_resistor_timings(uint32_t low_off, uint32_t hig htim2.Instance->CCR3 = low_off; htim2.Instance->CCR4 = high_on; } - cpu_exit_critical(sr); + cpu_exit_critical(mask); } /* Function implementations --------------------------------------------------*/ diff --git a/Firmware/MotorControl/low_level.h b/Firmware/MotorControl/low_level.h index 4af6e3e0..0b594e34 100644 --- a/Firmware/MotorControl/low_level.h +++ b/Firmware/MotorControl/low_level.h @@ -53,6 +53,15 @@ void pwm_in_init(); void update_brake_current(); +inline uint32_t cpu_enter_critical() { + return __get_PRIMASK(); + __disable_irq(); +} + +inline void cpu_exit_critical(uint32_t priority_mask) { + __set_PRIMASK(priority_mask); +} + #ifdef __cplusplus } #endif From 5df64ed5131ae184f1c8b50abf9bf7590302ccb4 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 8 Oct 2018 16:00:29 -0700 Subject: [PATCH 017/106] update Changelog --- CHANGELOG.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 07a30ae6..71edf5d8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,9 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. +## Fixed +* Would ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. + # Releases ## [0.4.6] - 2018-10-07 ### Fixed From 3cc8c09339db03653c751c1cf76f6f30520305a8 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 8 Oct 2018 16:55:59 -0700 Subject: [PATCH 018/106] change a var name --- tools/odrive/dfu.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/odrive/dfu.py b/tools/odrive/dfu.py index 6283b81a..9dc5f6d9 100755 --- a/tools/odrive/dfu.py +++ b/tools/odrive/dfu.py @@ -338,8 +338,8 @@ def update_device(device, firmware, logger, cancellation_token): # Back up configuration if dfudev is None: - did_backup_config = device.user_config_loaded if hasattr(device, 'user_config_loaded') else False - if did_backup_config: + do_backup_config = device.user_config_loaded if hasattr(device, 'user_config_loaded') else False + if do_backup_config: odrive.configuration.backup_config(device, None, logger) elif not odrive.utils.yes_no_prompt("The configuration cannot be backed up because the device is already in DFU mode. The configuration may be lost after updating. Do you want to continue anyway?", True): raise OperationAbortedException() @@ -414,7 +414,7 @@ def update_device(device, firmware, logger, cancellation_token): device = odrive.find_any("usb", serial_number, cancellation_token, cancellation_token, timeout=30) - if did_backup_config: + if do_backup_config: odrive.configuration.restore_config(device, None, logger) os.remove(odrive.configuration.get_temp_config_filename(device)) From c0cfc2f3b2e13f702db6c61149b4c1239def730a Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 8 Oct 2018 01:46:24 -0700 Subject: [PATCH 019/106] generate disasembly in build --- Firmware/build.lua | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Firmware/build.lua b/Firmware/build.lua index ea792219..8962e403 100644 --- a/Firmware/build.lua +++ b/Firmware/build.lua @@ -99,6 +99,8 @@ function GCCToolchain(prefix, builddir, compiler_flags, linker_flags) } -- display the size tup.frule{inputs={output_name..'.elf'}, command=prefix..'size %f'} + -- generate disassembly + tup.frule{inputs={output_name..'.elf'}, command=prefix..'objdump %f -dSC > %o', outputs={output_name..'.asm'}} -- create *.hex and *.bin output formats tup.frule{inputs={output_name..'.elf'}, command=prefix..'objcopy -O ihex %f %o', outputs={output_name..'.hex'}} tup.frule{inputs={output_name..'.elf'}, command=prefix..'objcopy -O binary -S %f %o', outputs={output_name..'.bin'}} From c702e2f7e50653d8330543421df7ff67fad04187 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Thu, 11 Oct 2018 21:52:53 -0700 Subject: [PATCH 020/106] fix early return in critical section entry --- Firmware/MotorControl/low_level.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Firmware/MotorControl/low_level.h b/Firmware/MotorControl/low_level.h index 0b594e34..605db9ba 100644 --- a/Firmware/MotorControl/low_level.h +++ b/Firmware/MotorControl/low_level.h @@ -54,8 +54,9 @@ void pwm_in_init(); void update_brake_current(); inline uint32_t cpu_enter_critical() { - return __get_PRIMASK(); + uint32_t primask = __get_PRIMASK(); __disable_irq(); + return primask; } inline void cpu_exit_critical(uint32_t priority_mask) { From a499d087e8537e08b03f4781b98973c72ef68fe2 Mon Sep 17 00:00:00 2001 From: je310 Date: Sat, 13 Oct 2018 11:32:20 +0100 Subject: [PATCH 021/106] Update usart.c Added a comment regarding baud rate. Probably should be tied into the build system at some point such that it does not need to be changed manually. --- Firmware/Board/v3/Src/usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Src/usart.c b/Firmware/Board/v3/Src/usart.c index 52a869db..0c4bed6f 100644 --- a/Firmware/Board/v3/Src/usart.c +++ b/Firmware/Board/v3/Src/usart.c @@ -66,7 +66,7 @@ void MX_UART4_Init(void) { huart4.Instance = UART4; - huart4.Init.BaudRate = 115200; + huart4.Init.BaudRate = 115200; // Provisionally this can be changed to 921600 for faster transfers, the low power Arduinos will not keep up. huart4.Init.WordLength = UART_WORDLENGTH_8B; huart4.Init.StopBits = UART_STOPBITS_1; huart4.Init.Parity = UART_PARITY_NONE; From b41016eba3756f5f3d15802bf39bb9af8bcc7c59 Mon Sep 17 00:00:00 2001 From: tobbelobb Date: Thu, 18 Oct 2018 13:29:05 +0200 Subject: [PATCH 022/106] Update commands.md --- docs/commands.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/commands.md b/docs/commands.md index 7e7fe3da..05c28364 100644 --- a/docs/commands.md +++ b/docs/commands.md @@ -22,14 +22,14 @@ The current state of an axis is indicated by `.current_state`. The user ca 1. `AXIS_STATE_IDLE` Disable motor PWM and do nothing. 2. `AXIS_STATE_STARTUP_SEQUENCE` Run the [startup procedure](#startup-procedure). - 3. `AXIS_STATE_FULL_CALIBRATION_SEQUENCE` Run motor calibration and then encoder offset calibration (or encoder index search if `.encoder.use_index` is `True`). + 3. `AXIS_STATE_FULL_CALIBRATION_SEQUENCE` Run motor calibration and then encoder offset calibration (or encoder index search if `.encoder.config.use_index` is `True`). 4. `AXIS_STATE_MOTOR_CALIBRATION` Measure phase resistance and phase inductance of the motor. * To store the results set `.motor.config.pre_calibrated` to `True` and [save the configuration](#saving-the-configuration). After that you don't have to run the motor calibration on the next start up. * This modifies the variables `.motor.config.phase_resistance` and `.motor.config.phase_inductance`. 5. `AXIS_STATE_SENSORLESS_CONTROL` Run sensorless control. * The motor must be calibrated (`.motor.is_calibrated`) * [`.controller.control_mode`](#control-mode) must be `True`. - 6. `AXIS_STATE_ENCODER_INDEX_SEARCH` Turn the motor in one direction until the encoder index is traversed. This state can only be entered if `.encoder.config.use_index` is `True`. + 6. `AXIS_STATE_ENCODER_INDEX_SEARCH` Turn the motor in one direction until the encoder index is traversed. This state can only be entered if `.encoder.config.config.use_index` is `True`. 7. `AXIS_STATE_ENCODER_OFFSET_CALIBRATION` Turn the motor in one direction for a few seconds and then back to measure the offset between the encoder position and the electrical phase. * Can only be entered if the motor is calibrated (`.motor.is_calibrated`). * A successful encoder calibration will make the `.encoder.is_ready` go to true. From 30b950008389708e1a4e9a90ed75aaf8f4749c5e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Thu, 18 Oct 2018 22:21:28 -0700 Subject: [PATCH 023/106] Update commands.md --- docs/commands.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/commands.md b/docs/commands.md index 05c28364..32b7769d 100644 --- a/docs/commands.md +++ b/docs/commands.md @@ -29,7 +29,7 @@ The current state of an axis is indicated by `.current_state`. The user ca 5. `AXIS_STATE_SENSORLESS_CONTROL` Run sensorless control. * The motor must be calibrated (`.motor.is_calibrated`) * [`.controller.control_mode`](#control-mode) must be `True`. - 6. `AXIS_STATE_ENCODER_INDEX_SEARCH` Turn the motor in one direction until the encoder index is traversed. This state can only be entered if `.encoder.config.config.use_index` is `True`. + 6. `AXIS_STATE_ENCODER_INDEX_SEARCH` Turn the motor in one direction until the encoder index is traversed. This state can only be entered if `.encoder.config.use_index` is `True`. 7. `AXIS_STATE_ENCODER_OFFSET_CALIBRATION` Turn the motor in one direction for a few seconds and then back to measure the offset between the encoder position and the electrical phase. * Can only be entered if the motor is calibrated (`.motor.is_calibrated`). * A successful encoder calibration will make the `.encoder.is_ready` go to true. From 02740cc97b3cde3c96337914b4a8ca549d8019cb Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 20 Oct 2018 13:51:33 -0700 Subject: [PATCH 024/106] Update Gemfile.lock --- docs/Gemfile.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Gemfile.lock b/docs/Gemfile.lock index 20e81d61..1c6d972e 100644 --- a/docs/Gemfile.lock +++ b/docs/Gemfile.lock @@ -221,7 +221,7 @@ GEM ruby-enum (0.7.2) i18n ruby_dep (1.5.0) - rubyzip (1.2.1) + rubyzip (1.2.2) safe_yaml (1.0.4) sass (3.5.6) sass-listen (~> 4.0.0) From 3cb9a8d58441741ab0f92c690ec5532811f83b01 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 20 Oct 2018 18:24:25 -0700 Subject: [PATCH 025/106] rename axis.enable_step_dir to axis.step_dir_active --- CHANGELOG.md | 3 +++ Firmware/MotorControl/axis.cpp | 6 +++--- Firmware/MotorControl/axis.hpp | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 71edf5d8..742c5300 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,6 +4,9 @@ Please add a note of your changes below this heading if you make a Pull Request. ## Fixed * Would ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. +### Changed +* renamed `axis.enable_step_dir` to `axis.step_dir_active` + # Releases ## [0.4.6] - 2018-10-07 ### Fixed diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index 01892af1..0ab726ff 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -66,7 +66,7 @@ bool Axis::wait_for_current_meas() { // step/direction interface void Axis::step_cb() { - if (enable_step_dir_) { + if (step_dir_active_) { GPIO_PinState dir_pin = HAL_GPIO_ReadPin(hw_config_.dir_port, hw_config_.dir_pin); float dir = (dir_pin == GPIO_PIN_SET) ? 1.0f : -1.0f; controller_.pos_setpoint_ += dir * config_.counts_per_step; @@ -87,9 +87,9 @@ void Axis::set_step_dir_enabled(bool enable) { GPIO_subscribe(hw_config_.step_port, hw_config_.step_pin, GPIO_PULLDOWN, step_cb_wrapper, this); - enable_step_dir_ = true; + step_dir_active_ = true; } else { - enable_step_dir_ = false; + step_dir_active_ = false; // Unsubscribe from step GPIO GPIO_unsubscribe(hw_config_.step_port, hw_config_.step_pin); diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 9e3de43c..6e9b8bfc 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -167,7 +167,7 @@ public: // variables exposed on protocol Error_t error_ = ERROR_NONE; - bool enable_step_dir_ = false; // auto enabled after calibration, based on config.enable_step_dir + bool step_dir_active_ = false; // auto enabled after calibration, based on config.enable_step_dir State_t requested_state_ = AXIS_STATE_STARTUP_SEQUENCE; State_t task_chain_[10] = { AXIS_STATE_UNDEFINED }; State_t& current_state_ = task_chain_[0]; @@ -177,7 +177,7 @@ public: auto make_protocol_definitions() { return make_protocol_member_list( make_protocol_property("error", &error_), - make_protocol_property("enable_step_dir", &enable_step_dir_), + make_protocol_ro_property("step_dir_active", &step_dir_active_), make_protocol_ro_property("current_state", ¤t_state_), make_protocol_property("requested_state", &requested_state_), make_protocol_ro_property("loop_counter", &loop_counter_), From f1b261e8dd10b991f82cdbfd2bc504fbab211eb1 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 20 Oct 2018 23:57:31 -0700 Subject: [PATCH 026/106] fix huge .bin file outputs --- Firmware/Board/v3/STM32F405RGTx_FLASH.ld | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/STM32F405RGTx_FLASH.ld b/Firmware/Board/v3/STM32F405RGTx_FLASH.ld index 30acca2c..f1259a71 100644 --- a/Firmware/Board/v3/STM32F405RGTx_FLASH.ld +++ b/Firmware/Board/v3/STM32F405RGTx_FLASH.ld @@ -134,9 +134,10 @@ SECTIONS * * IMPORTANT NOTE! * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. + * the startup code needs to be modified to copy the init-values. + * Oskar: Added NOLOAD to remove this section from .bin outputs */ - .ccmram : + .ccmram (NOLOAD): { . = ALIGN(4); _sccmram = .; /* create a global symbol at ccmram start */ From 95a5e2ad2c2df8190a7a573627ab0cdaabf0689b Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 21 Oct 2018 00:03:40 -0700 Subject: [PATCH 027/106] add dfu-util instructions for Linux --- docs/odrivetool.md | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/docs/odrivetool.md b/docs/odrivetool.md index 01670257..731f8b63 100644 --- a/docs/odrivetool.md +++ b/docs/odrivetool.md @@ -123,7 +123,19 @@ You can use the DfuSe app from ST. 1. Congratulations your ODrive should now be flashed; you can now quit DfuSeDemo. 1. Turn off the power to the ODrive and set the DIP switch back to RUN mode. -#### MacOS or Linux +#### Linux +Install `dfu-util`: +```text +sudo apt install dfu-util +``` + +Force DFU mode, as per the instructions above. +In the Firmware directory, after finishing building the firmware: +```text +sudo dfu-util -a 0 -s 0x08000000 -D build/ODriveFirmware.bin +``` + +#### MacOS **This section needs more detail. Please consider adding detail if you got it to work.** You may be able to use [dfu-util](http://dfu-util.sourceforge.net/) to upgrade the firmware. You will need to convert the .hex file to a .dfu file. You may be able to do it with the python script [dfu-convert](https://github.com/plietar/dfuse-tool/blob/master/dfu-convert) or the c program [hex2dfu](https://github.com/encedo/hex2dfu). From db676cead54109f6fbe2d2a97c8eb455f6f4211b Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 21 Oct 2018 17:04:24 -0700 Subject: [PATCH 028/106] fix units comment in encoder.hpp --- Firmware/MotorControl/encoder.hpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Firmware/MotorControl/encoder.hpp b/Firmware/MotorControl/encoder.hpp index 6eca0536..27ba284b 100644 --- a/Firmware/MotorControl/encoder.hpp +++ b/Firmware/MotorControl/encoder.hpp @@ -68,12 +68,12 @@ public: int32_t shadow_count_ = 0; int32_t count_in_cpr_ = 0; float interpolation_ = 0.0f; - float phase_ = 0.0f; // [rad] - float pos_estimate_ = 0.0f; // [rad] - float pos_cpr_ = 0.0f; // [rad] - float vel_estimate_ = 0.0f; // [rad/s] - float pll_kp_ = 0.0f; // [rad/s / rad] - float pll_ki_ = 0.0f; // [(rad/s^2) / rad] + float phase_ = 0.0f; // [count] + float pos_estimate_ = 0.0f; // [count] + float pos_cpr_ = 0.0f; // [count] + float vel_estimate_ = 0.0f; // [count/s] + float pll_kp_ = 0.0f; // [count/s / count] + float pll_ki_ = 0.0f; // [(count/s^2) / count] // Updated by low_level pwm_adc_cb uint8_t hall_state_ = 0x0; // bit[0] = HallA, .., bit[2] = HallC From 066265beba3052a772685b2664507add614178de Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 21 Oct 2018 17:08:28 -0700 Subject: [PATCH 029/106] update instructions --- docs/odrivetool.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/docs/odrivetool.md b/docs/odrivetool.md index 731f8b63..18dc7b0d 100644 --- a/docs/odrivetool.md +++ b/docs/odrivetool.md @@ -137,9 +137,7 @@ sudo dfu-util -a 0 -s 0x08000000 -D build/ODriveFirmware.bin #### MacOS **This section needs more detail. Please consider adding detail if you got it to work.** -You may be able to use [dfu-util](http://dfu-util.sourceforge.net/) to upgrade the firmware. You will need to convert the .hex file to a .dfu file. You may be able to do it with the python script [dfu-convert](https://github.com/plietar/dfuse-tool/blob/master/dfu-convert) or the c program [hex2dfu](https://github.com/encedo/hex2dfu). - -You probably need to force DFU mode, as per the instructions above. +You may be able to use [dfu-util](http://dfu-util.sourceforge.net/) to upgrade the firmware. The command should be similar to the Linux instructions. ## Flashing with an STLink From 8aac095bfd9bed59bbd082a2a7addf11970fd6d0 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 22 Oct 2018 20:23:54 -0700 Subject: [PATCH 030/106] clean up SVM switch case style --- Firmware/MotorControl/utils.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/Firmware/MotorControl/utils.c b/Firmware/MotorControl/utils.c index b59af789..3278d614 100644 --- a/Firmware/MotorControl/utils.c +++ b/Firmware/MotorControl/utils.c @@ -51,9 +51,8 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tA = (1.0f - t1 - t2) * 0.5f; *tB = *tA + t1; *tC = *tB + t2; + } break; - break; - } // sextant v2-v3 case 2: { // Vector on-times @@ -64,9 +63,8 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tB = (1.0f - t2 - t3) * 0.5f; *tA = *tB + t3; *tC = *tA + t2; + } break; - break; - } // sextant v3-v4 case 3: { // Vector on-times @@ -77,9 +75,8 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tB = (1.0f - t3 - t4) * 0.5f; *tC = *tB + t3; *tA = *tC + t4; + } break; - break; - } // sextant v4-v5 case 4: { // Vector on-times @@ -90,9 +87,8 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tC = (1.0f - t4 - t5) * 0.5f; *tB = *tC + t5; *tA = *tB + t4; + } break; - break; - } // sextant v5-v6 case 5: { // Vector on-times @@ -103,9 +99,8 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tC = (1.0f - t5 - t6) * 0.5f; *tA = *tC + t5; *tB = *tA + t6; + } break; - break; - } // sextant v6-v1 case 6: { // Vector on-times @@ -116,9 +111,7 @@ int SVM(float alpha, float beta, float* tA, float* tB, float* tC) { *tA = (1.0f - t6 - t1) * 0.5f; *tC = *tA + t1; *tB = *tC + t6; - - break; - } + } break; } // if any of the results becomes NaN, result_valid will evaluate to false From b09d1e9e256e31059c6a9faf6467586fe5e5cbdc Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 22 Oct 2018 21:03:13 -0700 Subject: [PATCH 031/106] make step/dir pins configurable --- CHANGELOG.md | 3 ++ Firmware/MotorControl/axis.cpp | 37 +++++++++++++++-------- Firmware/MotorControl/axis.hpp | 21 +++++++++++-- Firmware/MotorControl/board_config_v3.h | 40 +++++++++++++++---------- Firmware/MotorControl/main.cpp | 4 ++- 5 files changed, 74 insertions(+), 31 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 742c5300..b3d59676 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,9 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. +## Added +* Make step dir gpio pins configurable. + ## Fixed * Would ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index 0ab726ff..cae62223 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -26,6 +26,8 @@ Axis::Axis(const AxisHardwareConfig_t& hw_config, controller_.axis_ = this; motor_.axis_ = this; trap_.axis_ = this; + + decode_step_dir_pins(); } static void step_cb_wrapper(void* ctx) { @@ -67,24 +69,37 @@ bool Axis::wait_for_current_meas() { // step/direction interface void Axis::step_cb() { if (step_dir_active_) { - GPIO_PinState dir_pin = HAL_GPIO_ReadPin(hw_config_.dir_port, hw_config_.dir_pin); + GPIO_PinState dir_pin = HAL_GPIO_ReadPin(dir_port_, dir_pin_); float dir = (dir_pin == GPIO_PIN_SET) ? 1.0f : -1.0f; controller_.pos_setpoint_ += dir * config_.counts_per_step; } }; -// @brief Enables or disables step/dir input -void Axis::set_step_dir_enabled(bool enable) { - if (enable) { +void Axis::load_default_step_dir_pin_config( + const AxisHardwareConfig_t& hw_config, Config_t* config) { + config->step_gpio_pin = hw_config.step_gpio_pin; + config->dir_gpio_pin = hw_config.dir_gpio_pin; +} + +void Axis::decode_step_dir_pins() { + step_port_ = get_gpio_port_by_pin(config_.step_gpio_pin); + step_pin_ = get_gpio_pin_by_pin(config_.step_gpio_pin); + dir_port_ = get_gpio_port_by_pin(config_.dir_gpio_pin); + dir_pin_ = get_gpio_pin_by_pin(config_.dir_gpio_pin); +} + +// @brief (de)activates step/dir input +void Axis::set_step_dir_active(bool active) { + if (active) { // Set up the direction GPIO as input GPIO_InitTypeDef GPIO_InitStruct; - GPIO_InitStruct.Pin = hw_config_.dir_pin; + GPIO_InitStruct.Pin = dir_pin_; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(hw_config_.dir_port, &GPIO_InitStruct); + HAL_GPIO_Init(dir_port_, &GPIO_InitStruct); // Subscribe to rising edges of the step GPIO - GPIO_subscribe(hw_config_.step_port, hw_config_.step_pin, GPIO_PULLDOWN, + GPIO_subscribe(step_port_, step_pin_, GPIO_PULLDOWN, step_cb_wrapper, this); step_dir_active_ = true; @@ -92,7 +107,7 @@ void Axis::set_step_dir_enabled(bool enable) { step_dir_active_ = false; // Unsubscribe from step GPIO - GPIO_unsubscribe(hw_config_.step_port, hw_config_.step_pin); + GPIO_unsubscribe(step_port_, step_pin_); } } @@ -167,7 +182,6 @@ bool Axis::run_sensorless_spin_up() { // Note run_sensorless_control_loop and run_closed_loop_control_loop are very similar and differ only in where we get the estimate from. bool Axis::run_sensorless_control_loop() { - set_step_dir_enabled(config_.enable_step_dir); run_control_loop([this](){ if (controller_.config_.control_mode >= Controller::CTRL_MODE_POSITION_CONTROL) return error_ |= ERROR_POS_CTRL_DURING_SENSORLESS, false; @@ -180,12 +194,11 @@ bool Axis::run_sensorless_control_loop() { return false; // set_error should update axis.error_ return true; }); - set_step_dir_enabled(false); return check_for_errors(); } bool Axis::run_closed_loop_control_loop() { - set_step_dir_enabled(config_.enable_step_dir); + set_step_dir_active(config_.enable_step_dir); run_control_loop([this](){ // Note that all estimators are updated in the loop prefix in run_control_loop float current_setpoint; @@ -195,7 +208,7 @@ bool Axis::run_closed_loop_control_loop() { return false; // set_error should update axis.error_ return true; }); - set_step_dir_enabled(false); + set_step_dir_active(false); return check_for_errors(); } diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 6e9b8bfc..d9f95ad8 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -45,9 +45,12 @@ public: bool startup_sensorless_control = false; //(ctx)->decode_step_dir_pins(); }, this), + make_protocol_property("dir_gpio_pin", &config_.dir_gpio_pin, + [](void* ctx) { static_cast(ctx)->decode_step_dir_pins(); }, this), make_protocol_property("ramp_up_time", &config_.ramp_up_time), make_protocol_property("ramp_up_distance", &config_.ramp_up_distance), make_protocol_property("spin_up_current", &config_.spin_up_current), diff --git a/Firmware/MotorControl/board_config_v3.h b/Firmware/MotorControl/board_config_v3.h index 1e170fed..afda10f6 100644 --- a/Firmware/MotorControl/board_config_v3.h +++ b/Firmware/MotorControl/board_config_v3.h @@ -21,10 +21,12 @@ typedef struct { - GPIO_TypeDef* step_port; - uint16_t step_pin; - GPIO_TypeDef* dir_port; - uint16_t dir_pin; + // GPIO_TypeDef* step_port; + // uint16_t step_pin; + // GPIO_TypeDef* dir_port; + // uint16_t dir_pin; + uint16_t step_gpio_pin; + uint16_t dir_gpio_pin; size_t thermistor_adc_ch; osPriority thread_priority; } AxisHardwareConfig_t; @@ -74,10 +76,12 @@ const size_t thermistor_num_coeffs = sizeof(thermistor_poly_coeffs)/sizeof(therm const BoardHardwareConfig_t hw_configs[2] = { { //M0 .axis_config = { - .step_port = GPIO_1_GPIO_Port, - .step_pin = GPIO_1_Pin, - .dir_port = GPIO_2_GPIO_Port, - .dir_pin = GPIO_2_Pin, + // .step_port = GPIO_1_GPIO_Port, + // .step_pin = GPIO_1_Pin, + // .dir_port = GPIO_2_GPIO_Port, + // .dir_pin = GPIO_2_Pin, + .step_gpio_pin = 1, + .dir_gpio_pin = 2, .thermistor_adc_ch = 15, .thread_priority = (osPriority)(osPriorityHigh + (osPriority)1), }, @@ -111,15 +115,19 @@ const BoardHardwareConfig_t hw_configs[2] = { { //M1 .axis_config = { #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 5 - .step_port = GPIO_7_GPIO_Port, - .step_pin = GPIO_7_Pin, - .dir_port = GPIO_8_GPIO_Port, - .dir_pin = GPIO_8_Pin, + // .step_port = GPIO_7_GPIO_Port, + // .step_pin = GPIO_7_Pin, + // .dir_port = GPIO_8_GPIO_Port, + // .dir_pin = GPIO_8_Pin, + .step_gpio_pin = 7, + .dir_gpio_pin = 8, #else - .step_port = GPIO_3_GPIO_Port, - .step_pin = GPIO_3_Pin, - .dir_port = GPIO_4_GPIO_Port, - .dir_pin = GPIO_4_Pin, + // .step_port = GPIO_3_GPIO_Port, + // .step_pin = GPIO_3_Pin, + // .dir_port = GPIO_4_GPIO_Port, + // .dir_pin = GPIO_4_Pin, + .step_gpio_pin = 3, + .dir_gpio_pin = 4, #endif #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 3 .thermistor_adc_ch = 4, diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 4550605e..738836a3 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -65,6 +65,8 @@ void load_configuration(void) { motor_configs[i] = Motor::Config_t(); trap_configs[i] = TrapezoidalTrajectory::Config_t(); axis_configs[i] = Axis::Config_t(); + // Default step/dir pins are different, so we need to explicitly load them + Axis::load_default_step_dir_pin_config(hw_configs[i].axis_config, &axis_configs[i]); } } else { user_config_loaded_ = true; @@ -179,7 +181,7 @@ int odrive_main(void) { #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 3 if (board_config.enable_uart) { axes[0]->config_.enable_step_dir = false; - axes[0]->set_step_dir_enabled(false); + axes[0]->set_step_dir_active(false); SetGPIO12toUART(); } #endif From 209839d2a796a198fa8f64f7f6f33a4130481539 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 22 Oct 2018 21:28:15 -0700 Subject: [PATCH 032/106] remve uart stepdir interlock: stepdir now takes priority --- Firmware/MotorControl/main.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 738836a3..4146850c 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -180,8 +180,6 @@ int odrive_main(void) { // TODO: make dynamically reconfigurable #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 3 if (board_config.enable_uart) { - axes[0]->config_.enable_step_dir = false; - axes[0]->set_step_dir_active(false); SetGPIO12toUART(); } #endif From ae30439d14f7519b252392cbef09242231cf140c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 22 Oct 2018 21:32:20 -0700 Subject: [PATCH 033/106] clean up commented parts --- Firmware/MotorControl/board_config_v3.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Firmware/MotorControl/board_config_v3.h b/Firmware/MotorControl/board_config_v3.h index afda10f6..7aee4881 100644 --- a/Firmware/MotorControl/board_config_v3.h +++ b/Firmware/MotorControl/board_config_v3.h @@ -21,10 +21,6 @@ typedef struct { - // GPIO_TypeDef* step_port; - // uint16_t step_pin; - // GPIO_TypeDef* dir_port; - // uint16_t dir_pin; uint16_t step_gpio_pin; uint16_t dir_gpio_pin; size_t thermistor_adc_ch; @@ -76,10 +72,6 @@ const size_t thermistor_num_coeffs = sizeof(thermistor_poly_coeffs)/sizeof(therm const BoardHardwareConfig_t hw_configs[2] = { { //M0 .axis_config = { - // .step_port = GPIO_1_GPIO_Port, - // .step_pin = GPIO_1_Pin, - // .dir_port = GPIO_2_GPIO_Port, - // .dir_pin = GPIO_2_Pin, .step_gpio_pin = 1, .dir_gpio_pin = 2, .thermistor_adc_ch = 15, @@ -115,17 +107,9 @@ const BoardHardwareConfig_t hw_configs[2] = { { //M1 .axis_config = { #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 5 - // .step_port = GPIO_7_GPIO_Port, - // .step_pin = GPIO_7_Pin, - // .dir_port = GPIO_8_GPIO_Port, - // .dir_pin = GPIO_8_Pin, .step_gpio_pin = 7, .dir_gpio_pin = 8, #else - // .step_port = GPIO_3_GPIO_Port, - // .step_pin = GPIO_3_Pin, - // .dir_port = GPIO_4_GPIO_Port, - // .dir_pin = GPIO_4_Pin, .step_gpio_pin = 3, .dir_gpio_pin = 4, #endif From 5958ae23f4be042f393a7fd3f7c059f8bd352a2e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Mon, 22 Oct 2018 21:39:57 -0700 Subject: [PATCH 034/106] update docs --- docs/interfaces.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/docs/interfaces.md b/docs/interfaces.md index ba6ccfb0..ff0ec9ac 100644 --- a/docs/interfaces.md +++ b/docs/interfaces.md @@ -32,7 +32,10 @@ The ODrive can be controlled over various ports and protocols. If you're comfort (+) on ODrive v3.4 and earlier
(*) ODrive v3.5 and later -ODrive v3.3 and onward have 5V tolerant GPIO pins. +Notes: +* ODrive v3.3 and onward have 5V tolerant GPIO pins. +* ODrive v3.5 and later have some noise supression filters on the default step/dir pins +* You can change the step/dir pins using `axis.config._gpio_pin`. ### Pin function priorities 1. PWM in, if enabled. Disabled by default. @@ -89,7 +92,7 @@ There is an Arduino library that gives some expamples on how to use the ASCII pr This is the simplest possible way of controlling the ODrive. It is also the most primitive and fragile one. So don't use it unless you must interoperate with other hardware that you don't control. Pinout: -* Step/dir signals: see [Pinout](#pinout) above. +* Step/dir signals: see [Pinout](#pinout) above. Note in that section how to reassign the pins. * GND: you must connect the grounds of the devices together. Use any GND pin on J3 of the ODrive. To enable step/dir mode for the GPIO, set `.config.enable_step_dir` to true for each axis that you wish to use this on. From 57d3836d938c246061e311aaafa6645ccc0d7ebb Mon Sep 17 00:00:00 2001 From: Unknown Date: Tue, 23 Oct 2018 21:18:33 -0400 Subject: [PATCH 035/106] Change TIM_1_8_PERIOD_CLOCKS and add RCR --- Firmware/Board/v3/Inc/main.h | 3 ++- Firmware/Board/v3/Src/tim.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 0a307122..ec9aa17d 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -67,12 +67,13 @@ /* Private define ------------------------------------------------------------*/ #define TIM_1_8_CLOCK_HZ 168000000 -#define TIM_1_8_PERIOD_CLOCKS 10192 +#define TIM_1_8_PERIOD_CLOCKS 3500 #define TIM_1_8_DEADTIME_CLOCKS 20 #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 #define configAPPLICATION_ALLOCATED_HEAP 1 +#define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 #define M0_nCS_GPIO_Port GPIOC diff --git a/Firmware/Board/v3/Src/tim.c b/Firmware/Board/v3/Src/tim.c index 7b159ea5..a909cf2a 100644 --- a/Firmware/Board/v3/Src/tim.c +++ b/Firmware/Board/v3/Src/tim.c @@ -94,7 +94,7 @@ void MX_TIM1_Init(void) htim1.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED3; htim1.Init.Period = TIM_1_8_PERIOD_CLOCKS; htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim1.Init.RepetitionCounter = 0; + htim1.Init.RepetitionCounter = TIM_1_8_RCR; if (HAL_TIM_Base_Init(&htim1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); @@ -324,7 +324,7 @@ void MX_TIM8_Init(void) htim8.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED3; htim8.Init.Period = TIM_1_8_PERIOD_CLOCKS; htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim8.Init.RepetitionCounter = 0; + htim8.Init.RepetitionCounter = TIM_1_8_RCR; if (HAL_TIM_PWM_Init(&htim8) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); From 074b04243c176062e14b7cd81e61f0733964301f Mon Sep 17 00:00:00 2001 From: Unknown Date: Tue, 23 Oct 2018 21:35:04 -0400 Subject: [PATCH 036/106] Update the current control loop speed --- Firmware/Board/v3/Inc/main.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index ec9aa17d..6dfbd301 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -169,8 +169,8 @@ //TODO: make this come automatically out of CubeMX somehow #define TIM_TIME_BASE TIM14 -#define CURRENT_MEAS_PERIOD ((float)(2*TIM_1_8_PERIOD_CLOCKS)/(float)TIM_1_8_CLOCK_HZ) -#define CURRENT_MEAS_HZ (TIM_1_8_CLOCK_HZ/(2*TIM_1_8_PERIOD_CLOCKS)) +#define CURRENT_MEAS_PERIOD ((float)(2.0f*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)/(float)TIM_1_8_CLOCK_HZ)) +#define CURRENT_MEAS_HZ ((float)(TIM_1_8_CLOCK_HZ/(2.0f*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)))) #if HW_VERSION_VOLTAGE == 48 #define VBUS_S_DIVIDER_RATIO 19.0f From b8b41867316ad2d8768ba4d658e85a42d7af570c Mon Sep 17 00:00:00 2001 From: Unknown Date: Tue, 23 Oct 2018 21:43:58 -0400 Subject: [PATCH 037/106] Make sure old board revs use the same defines --- Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h | 3 ++- Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h | 3 ++- Firmware/Board/v3/Odrive.ioc | 12 ++++++++---- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h index bd3f6305..567fe028 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h @@ -1,12 +1,13 @@ /* Private define ------------------------------------------------------------*/ #define TIM_1_8_CLOCK_HZ 168000000 -#define TIM_1_8_PERIOD_CLOCKS 10192 +#define TIM_1_8_PERIOD_CLOCKS 3500 #define TIM_1_8_DEADTIME_CLOCKS 20 #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 #define configAPPLICATION_ALLOCATED_HEAP 1 +#define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 #define M0_nCS_GPIO_Port GPIOC diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h index 19428406..5695d700 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h @@ -1,12 +1,13 @@ /* Private define ------------------------------------------------------------*/ #define TIM_1_8_CLOCK_HZ 168000000 -#define TIM_1_8_PERIOD_CLOCKS 10192 +#define TIM_1_8_PERIOD_CLOCKS 3500 #define TIM_1_8_DEADTIME_CLOCKS 20 #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 #define configAPPLICATION_ALLOCATED_HEAP 1 +#define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 #define M0_nCS_GPIO_Port GPIOC diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index fa9ca5ac..707c3f2a 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -76,7 +76,7 @@ ADC3.SamplingTime-7\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC3.SamplingTime-8\#ChannelInjectedConversion=ADC_SAMPLETIME_3CYCLES ADC3.ScanConvMode=DISABLE CAN1.AutoWakeUp=ENABLE -CAN1.CalculateTimeBit=2000 +CAN1.CalculateTimeBit=500 CAN1.CalculateTimeQuantum=166.66666666666669 CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,Prescaler,TimeSeg1,TimeSeg2,AutoWakeUp CAN1.Prescaler=7 @@ -207,7 +207,7 @@ Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP Mcu.PinsNb=56 Mcu.ThirdPartyNb=0 -Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,10192;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1 +Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx MxCube.Version=4.24.0 MxDb.Version=DB.4.0.240 @@ -450,6 +450,8 @@ ProjectManager.HeapSize=0x3C00 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false ProjectManager.PreviousToolchain=SW4STM32 ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=Odrive.ioc @@ -576,7 +578,7 @@ TIM1.Channel-PWM\ Generation2\ CH2\ CH2N=TIM_CHANNEL_2 TIM1.Channel-PWM\ Generation3\ CH3\ CH3N=TIM_CHANNEL_3 TIM1.CounterMode=TIM_COUNTERMODE_CENTERALIGNED3 TIM1.DeadTime=TIM_1_8_DEADTIME_CLOCKS -TIM1.IPParameters=Channel-PWM Generation2 CH2 CH2N,Channel-PWM Generation3 CH3 CH3N,OCNPolarity_1,OCNPolarity_2,OCNPolarity_3,CounterMode,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Period,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N +TIM1.IPParameters=Channel-PWM Generation2 CH2 CH2N,Channel-PWM Generation3 CH3 CH3N,OCNPolarity_1,OCNPolarity_2,OCNPolarity_3,CounterMode,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Period,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N,RepetitionCounter TIM1.OCMode_PWM-PWM\ Generation1\ CH1\ CH1N=TIM_OCMODE_PWM2 TIM1.OCMode_PWM-PWM\ Generation2\ CH2\ CH2N=TIM_OCMODE_PWM2 TIM1.OCMode_PWM-PWM\ Generation3\ CH3\ CH3N=TIM_OCMODE_PWM2 @@ -586,6 +588,7 @@ TIM1.OCNPolarity_3=TIM_OCNPOLARITY_HIGH TIM1.OffStateIDLEMode=TIM_OSSI_ENABLE TIM1.OffStateRunMode=TIM_OSSR_ENABLE TIM1.Period=TIM_1_8_PERIOD_CLOCKS +TIM1.RepetitionCounter=TIM_1_8_RCR TIM1.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 @@ -624,13 +627,14 @@ TIM8.Channel-PWM\ Generation2\ CH2\ CH2N=TIM_CHANNEL_2 TIM8.Channel-PWM\ Generation3\ CH3\ CH3N=TIM_CHANNEL_3 TIM8.CounterMode=TIM_COUNTERMODE_CENTERALIGNED3 TIM8.DeadTime=TIM_1_8_DEADTIME_CLOCKS -TIM8.IPParameters=Channel-PWM Generation3 CH3 CH3N,Channel-PWM Generation2 CH2 CH2N,CounterMode,Period,OffStateRunMode,OffStateIDLEMode,DeadTime,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N +TIM8.IPParameters=Channel-PWM Generation3 CH3 CH3N,Channel-PWM Generation2 CH2 CH2N,CounterMode,Period,OffStateRunMode,OffStateIDLEMode,DeadTime,OCMode_PWM-PWM Generation1 CH1 CH1N,OCMode_PWM-PWM Generation2 CH2 CH2N,OCMode_PWM-PWM Generation3 CH3 CH3N,Channel-Output Compare4 No Output,TIM_MasterOutputTrigger,Channel-PWM Generation1 CH1 CH1N,RepetitionCounter TIM8.OCMode_PWM-PWM\ Generation1\ CH1\ CH1N=TIM_OCMODE_PWM2 TIM8.OCMode_PWM-PWM\ Generation2\ CH2\ CH2N=TIM_OCMODE_PWM2 TIM8.OCMode_PWM-PWM\ Generation3\ CH3\ CH3N=TIM_OCMODE_PWM2 TIM8.OffStateIDLEMode=TIM_OSSI_ENABLE TIM8.OffStateRunMode=TIM_OSSR_ENABLE TIM8.Period=TIM_1_8_PERIOD_CLOCKS +TIM8.RepetitionCounter=TIM_1_8_RCR TIM8.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE UART4.IPParameters=VirtualMode UART4.VirtualMode=Asynchronous From a3b6c6ea3ebbe40bdf170e37cd6fe5deac334163 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 19:29:17 -0700 Subject: [PATCH 038/106] Update main.h --- Firmware/Board/v3/Inc/main.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 6dfbd301..8a2bba13 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -169,8 +169,8 @@ //TODO: make this come automatically out of CubeMX somehow #define TIM_TIME_BASE TIM14 -#define CURRENT_MEAS_PERIOD ((float)(2.0f*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)/(float)TIM_1_8_CLOCK_HZ)) -#define CURRENT_MEAS_HZ ((float)(TIM_1_8_CLOCK_HZ/(2.0f*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)))) +#define CURRENT_MEAS_PERIOD ((float)(2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)/(float)TIM_1_8_CLOCK_HZ)) +#define CURRENT_MEAS_HZ ((float)(TIM_1_8_CLOCK_HZ/(2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)))) #if HW_VERSION_VOLTAGE == 48 #define VBUS_S_DIVIDER_RATIO 19.0f From 89f00992cbac105681122aa8df6ca48d8e7ebf5c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 19:38:24 -0700 Subject: [PATCH 039/106] add the pc sampling profiler script --- Firmware/sampler.py | 124 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Firmware/sampler.py diff --git a/Firmware/sampler.py b/Firmware/sampler.py new file mode 100644 index 00000000..08dc126e --- /dev/null +++ b/Firmware/sampler.py @@ -0,0 +1,124 @@ +#!/usr/bin/python2 + +# run openocd (0.9.0) with : +# $ openocd -f stlink-v2-1.cfg -f stm32f4x.cfg &> /dev/null" +# then run +# $ python2 sampler.py path_to_myelf_with_symbols + +import sys +import time +import telnetlib +import subprocess +from bisect import bisect_right +import operator + +class OpenOCDCMSampler(object): + + def __init__(self, host='localhost', port=4444): + + self.net = telnetlib.Telnet(host, port) + self.net.read_very_eager() + + self.table = [] + self.indexes = set() + + def __del__(self): + self.net.write(b'exit\r\n') + self.net.read_until(b'exit\r\n', 1) + self.net.close() + + def getpc(self): + + self.net.write(b'mrw 0xE000101C\r\n') + res = self.net.read_until(b'\r\n\r> ', 1) + + if res: + prefix = res[0:16] + num = res[16:-5] + res = res[-15:0] + + if prefix == b'mrw 0xE000101C\r\n': + return int(num) + + return 0 + + + def initSymbols(self, elf, readelf='arm-none-eabi-readelf'): + proc = subprocess.Popen([readelf, '-s', elf], stdout=subprocess.PIPE) + for line in proc.stdout.readlines(): + field = line.split() + # for i,txt in enumerate(field): + # print("{}, {}".format(i, txt)) + try: + if field[3] == b'FUNC': + addr = int(field[1], 16) - 1 # For some reason readelf dumps the func addr off by 1 + func = field[7] + size = int(field[2]) + if addr not in self.indexes: + self.table.append((addr, func, size)) + self.indexes.add(addr) + except IndexError: + pass + + self.table.sort() + self.addrs = [ x for (x, y, z) in self.table ] + + + def func(self, pc): + + if pc == 0 or pc == 0xFFFFFFFF: + return ('', 0) + + i = bisect_right(self.addrs, pc) + if i: + addr, symb, size = self.table[i-1] + if pc >= addr and pc <= addr + size: + return (symb, addr) + + return ('', 0) + + +if __name__ == '__main__': + + sampler = OpenOCDCMSampler('localhost', 4444) + sampler.initSymbols(sys.argv[1]) + + total = 0 + countmap = { } + pcmap = { } + start = time.time() + + try: + while True: + pc = sampler.getpc() + + if pc in pcmap: + pcmap[pc] += 1 + else: + pcmap[pc] = 1 + + func, addr = sampler.func(pc) + + if not addr: + continue + + if func in countmap: + countmap[func] += 1 + total += 1 + else: + countmap[func] = 1 + total += 1 + + cur = time.time() + if cur - start > 1.0: + tmp = sorted(countmap.items(), key=operator.itemgetter(1), reverse=True) + for k, v in tmp: + # print('{:05.2f}% {}'.format((v * 100.) / total, k)) + print('{:06.2f} clocks : {}'.format((v * 8192) / total, k)) + start = cur + print('{} Samples'.format(total)) + print('') + + except KeyboardInterrupt: + pcmap = sorted(pcmap.items(), key=operator.itemgetter(1), reverse=True) + pcmap = [(hex(addr), count) for addr, count in pcmap] From afce08b3ca931c42c143f67386891f7d4a1916f0 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 22:03:14 -0700 Subject: [PATCH 040/106] Update main.h --- Firmware/Board/v3/Inc/main.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 8a2bba13..1e76830d 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -169,8 +169,8 @@ //TODO: make this come automatically out of CubeMX somehow #define TIM_TIME_BASE TIM14 -#define CURRENT_MEAS_PERIOD ((float)(2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)/(float)TIM_1_8_CLOCK_HZ)) -#define CURRENT_MEAS_HZ ((float)(TIM_1_8_CLOCK_HZ/(2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)))) +#define CURRENT_MEAS_PERIOD ( (float)2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1) / (float)TIM_1_8_CLOCK_HZ ) +#define CURRENT_MEAS_HZ ( (float)(TIM_1_8_CLOCK_HZ) / (float)(2*TIM_1_8_PERIOD_CLOCKS*(TIM_1_8_RCR+1)) ) #if HW_VERSION_VOLTAGE == 48 #define VBUS_S_DIVIDER_RATIO 19.0f From 0c7171be72f6a07c36fcf68f631e2f4b71c7f220 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 22:14:25 -0700 Subject: [PATCH 041/106] update changelog --- CHANGELOG.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 742c5300..2d918843 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,11 +1,12 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. -## Fixed -* Would ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. - ### Changed -* renamed `axis.enable_step_dir` to `axis.step_dir_active` +* Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. +* Renamed `axis.enable_step_dir` to `axis.step_dir_active` + +## Fixed +* Would get ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. # Releases ## [0.4.6] - 2018-10-07 From 0f2d0deba8654f77cb9dbca67b60a4ffe176c9bd Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:16:26 -0700 Subject: [PATCH 042/106] Run STM32CubeMX v1.21 --- .../Inc/stm32f4xx_hal_def.h | 17 +- .../Inc/stm32f4xx_hal_flash_ramfunc.h | 8 +- .../Inc/stm32f4xx_hal_i2c.h | 649 -- .../Inc/stm32f4xx_hal_i2c_ex.h | 137 - .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 4 +- .../Src/stm32f4xx_hal_flash_ramfunc.c | 16 +- .../Src/stm32f4xx_hal_i2c.c | 5494 ----------------- .../Src/stm32f4xx_hal_i2c_ex.c | 204 - Firmware/Board/v3/Inc/FreeRTOSConfig.h | 3 +- Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 7 +- Firmware/Board/v3/Inc/tim.h | 5 +- Firmware/Board/v3/Inc/usbd_cdc_if.h | 2 +- Firmware/Board/v3/Inc/usbd_conf.h | 3 +- Firmware/Board/v3/Inc/usbd_desc.h | 3 +- .../Class/CDC/Inc/usbd_cdc.h | 39 +- .../Class/CDC/Src/usbd_cdc.c | 567 +- .../Core/Inc/usbd_def.h | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 10 +- Firmware/Board/v3/Odrive.ioc | 10 +- Firmware/Board/v3/Src/can.c | 2 +- Firmware/Board/v3/Src/dma.c | 6 +- Firmware/Board/v3/Src/freertos.c | 52 +- Firmware/Board/v3/Src/main.c | 1 + Firmware/Board/v3/Src/stm32f4xx_hal_msp.c | 4 +- Firmware/Board/v3/Src/usbd_cdc_if.c | 12 +- Firmware/Board/v3/Src/usbd_conf.c | 24 +- Firmware/Board/v3/Src/usbd_desc.c | 25 +- 28 files changed, 352 insertions(+), 6960 deletions(-) delete mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h delete mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h delete mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c delete mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index 06414648..6d5e5b22 100644 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -70,6 +70,9 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) @@ -79,9 +82,7 @@ typedef enum do{ \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) + } while(0U) /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. @@ -135,7 +136,7 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) +#define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN @@ -146,7 +147,7 @@ typedef enum #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) +#define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ @@ -167,14 +168,14 @@ typedef enum Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ -#define __RAM_FUNC HAL_StatusTypeDef +#define __RAM_FUNC #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef +#define __RAM_FUNC __ramfunc #elif defined ( __GNUC__ ) /* GNU Compiler @@ -182,7 +183,7 @@ typedef enum RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) +#define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h index 500d33ad..fa7e4906 100644 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -64,10 +64,10 @@ /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 * @{ */ -__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void); -__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void); -__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void); -__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); /** * @} */ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h deleted file mode 100644 index 5452a507..00000000 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h +++ /dev/null @@ -1,649 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_I2C_H -#define __STM32F4xx_HAL_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** - * @brief I2C Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_addressing_mode */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_dual_addressing_mode */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_nostretch_mode */ - -}I2C_InitTypeDef; - -/** - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : Abort (Abort user request on going) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) - * b4 (not used) - * x : Should be set to 0 - * b3 - * 0 : Ready or Busy (No Listen mode ongoing) - * 1 : Listen (IP in Address Listen Mode) - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -}HAL_I2C_StateTypeDef; - -/** - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap : - * b7 (not used) - * x : Should be set to 0 - * b6 - * 0 : None - * 1 : Memory (HAL I2C communication is in Memory Mode) - * b5 - * 0 : None - * 1 : Slave (HAL I2C communication is in Slave Mode) - * b4 - * 0 : None - * 1 : Master (HAL I2C communication is in Master Mode) - * b3-b2-b1-b0 (not used) - * xxxx : Should be set to 0000 - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -}HAL_I2C_ModeTypeDef; - -/** - * @brief I2C handle Structure definition - */ -typedef struct -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C transfer options */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode - context for internal usage */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t Devaddress; /*!< I2C Target device address */ - - __IO uint32_t Memaddress; /*!< I2C Target memory address */ - - __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ - - __IO uint32_t EventCount; /*!< I2C Event counter */ - -}I2C_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_Error_Code I2C Error Code - * @brief I2C Error Code - * @{ - */ -#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ -#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ -#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ -#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode - * @{ - */ -#define I2C_DUTYCYCLE_2 0x00000000U -#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY -/** - * @} - */ - -/** @defgroup I2C_addressing_mode I2C addressing mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT 0x00004000U -#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) -/** - * @} - */ - -/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE 0x00000000U -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL -/** - * @} - */ - -/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE 0x00000000U -#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC -/** - * @} - */ - -/** @defgroup I2C_nostretch_mode I2C nostretch mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE 0x00000000U -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT 0x00000001U -#define I2C_MEMADD_SIZE_16BIT 0x00000010U -/** - * @} - */ - -/** @defgroup I2C_XferDirection_definition I2C XferDirection definition - * @{ - */ -#define I2C_DIRECTION_RECEIVE 0x00000000U -#define I2C_DIRECTION_TRANSMIT 0x00000001U -/** - * @} - */ - -/** @defgroup I2C_XferOptions_definition I2C XferOptions definition - * @{ - */ -#define I2C_FIRST_FRAME 0x00000001U -#define I2C_NEXT_FRAME 0x00000002U -#define I2C_FIRST_AND_LAST_FRAME 0x00000004U -#define I2C_LAST_FRAME 0x00000008U -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @{ - */ -#define I2C_IT_BUF I2C_CR2_ITBUFEN -#define I2C_IT_EVT I2C_CR2_ITEVTEN -#define I2C_IT_ERR I2C_CR2_ITERREN -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_SMBALERT 0x00018000U -#define I2C_FLAG_TIMEOUT 0x00014000U -#define I2C_FLAG_PECERR 0x00011000U -#define I2C_FLAG_OVR 0x00010800U -#define I2C_FLAG_AF 0x00010400U -#define I2C_FLAG_ARLO 0x00010200U -#define I2C_FLAG_BERR 0x00010100U -#define I2C_FLAG_TXE 0x00010080U -#define I2C_FLAG_RXNE 0x00010040U -#define I2C_FLAG_STOPF 0x00010010U -#define I2C_FLAG_ADD10 0x00010008U -#define I2C_FLAG_BTF 0x00010004U -#define I2C_FLAG_ADDR 0x00010002U -#define I2C_FLAG_SB 0x00010001U -#define I2C_FLAG_DUALF 0x00100080U -#define I2C_FLAG_SMBHOST 0x00100040U -#define I2C_FLAG_SMBDEFAULT 0x00100020U -#define I2C_FLAG_GENCALL 0x00100010U -#define I2C_FLAG_TRA 0x00100004U -#define I2C_FLAG_BUSY 0x00100002U -#define I2C_FLAG_MSL 0x00100001U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable or disable the specified I2C interrupts. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2C_IT_BUF: Buffer interrupt enable - * @arg I2C_IT_EVT: Event interrupt enable - * @arg I2C_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) - -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_BUF: Buffer interrupt enable - * @arg I2C_IT_EVT: Event interrupt enable - * @arg I2C_IT_ERR: Error interrupt enable - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag - * @arg I2C_FLAG_RXNE: Data register not empty flag - * @arg I2C_FLAG_STOPF: Stop detection flag - * @arg I2C_FLAG_ADD10: 10-bit header sent flag - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag - * Address matched flag - * @arg I2C_FLAG_SB: Start bit flag - * @arg I2C_FLAG_DUALF: Dual flag - * @arg I2C_FLAG_SMBHOST: SMBus host header - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header - * @arg I2C_FLAG_GENCALL: General call header flag - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) - -/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) - -/** @brief Clears the I2C ADDR pending flag. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg = 0x00U; \ - tmpreg = (__HANDLE__)->Instance->SR1; \ - tmpreg = (__HANDLE__)->Instance->SR2; \ - UNUSED(tmpreg); \ - } while(0) - -/** @brief Clears the I2C STOPF pending flag. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg = 0x00U; \ - tmpreg = (__HANDLE__)->Instance->SR1; \ - (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ - UNUSED(tmpreg); \ - } while(0) - -/** @brief Enable the I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) - -/** @brief Disable the I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) - -/** - * @} - */ - -/* Include I2C HAL Extension module */ -#include "stm32f4xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions *****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State, Mode and Errors functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ -#define I2C_FLAG_MASK 0x0000FFFFU -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macros I2C Private Macros - * @{ - */ - -#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) -#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) -#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) -#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) - -#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) - -#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) -#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) - -/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters - * @{ - */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ - ((CYCLE) == I2C_DUTYCYCLE_16_9)) -#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ - ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F4xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h deleted file mode 100644 index ff47d5cc..00000000 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_I2C_EX_H -#define __STM32F4xx_HAL_I2C_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2CEx_Exported_Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macros I2C Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ - STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ - STM32F413xx || STM32F423xx */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_I2C_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index bf966f9a..1d6da26b 100644 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -66,11 +66,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.3 + * @brief STM32F4xx HAL Driver version number V1.7.4 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c index fab41154..b896d072 100644 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -107,9 +107,9 @@ * @note This mode is only available for STM32F41xxx/STM32F446xx devices. * @note This mode couldn't be set while executing with the flash itself. * It should be done with specific routine executed from RAM. - * @retval None + * @retval HAL status */ -__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void) +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) { /* Enable Power ctrl clock */ __HAL_RCC_PWR_CLK_ENABLE(); @@ -124,9 +124,9 @@ __RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void) * @note This mode is only available for STM32F411xx/STM32F446xx devices. * @note This mode couldn't be set while executing with the flash itself. * It should be done with specific routine executed from RAM. - * @retval None + * @retval HAL status */ -__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void) +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) { /* Enable Power ctrl clock */ __HAL_RCC_PWR_CLK_ENABLE(); @@ -141,9 +141,9 @@ __RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void) * @note This mode is only available for STM32F41xxx/STM32F446xx devices. * @note This mode could n't be set while executing with the flash itself. * It should be done with specific routine executed from RAM. - * @retval None + * @retval HAL status */ -__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void) +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) { /* Enable Power ctrl clock */ __HAL_RCC_PWR_CLK_ENABLE(); @@ -158,9 +158,9 @@ __RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void) * @note This mode is only available for STM32F41xxx/STM32F446xx devices. * @note This mode couldn't be set while executing with the flash itself. * It should be done with specific routine executed from RAM. - * @retval None + * @retval HAL status */ -__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void) +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) { /* Enable Power ctrl clock */ __HAL_RCC_PWR_CLK_ENABLE(); diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c deleted file mode 100644 index da185200..00000000 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ /dev/null @@ -1,5494 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State, Mode and Error functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx Stream - - (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, - Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - - *** Interrupt mode IO sequential operation *** - ============================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup I2C_Private_Define - * @{ - */ -#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ -#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ -#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup I2C_Private_Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -static void I2C_ITError(I2C_HandleTypeDef *hi2c); - -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); - -static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Communication Speed - (++) Duty cycle - (++) Addressing mode - (++) Own Address 1 - (++) Dual Addressing mode - (++) Own Address 2 - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - uint32_t freqrange = 0U; - uint32_t pclk1 = 0U; - - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); - assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if(hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get PCLK1 frequency */ - pclk1 = HAL_RCC_GetPCLK1Freq(); - - /* Calculate frequency range */ - freqrange = I2C_FREQRANGE(pclk1); - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->CR2 = freqrange; - - /*---------------------------- I2Cx TRISE Configuration --------------------*/ - /* Configure I2Cx: Rise Time */ - hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); - - /*---------------------------- I2Cx CCR Configuration ----------------------*/ - /* Configure I2Cx: Speed */ - hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Configure I2Cx: Own Address1 and addressing mode */ - hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2C peripheral. - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief I2C MSP Init. - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2C MSP DeInit - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Master_Sequential_Transmit_IT() - (++) HAL_I2C_Master_Sequential_Receive_IT() - (++) HAL_I2C_Slave_Sequential_Transmit_IT() - (++) HAL_I2C_Slave_Sequential_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - (++) HAL_I2C_AbortCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - while(hi2c->XferSize > 0U) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* Wait until BTF flag is set */ - if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - if(hi2c->XferSize == 0U) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - else if(hi2c->XferSize == 1U) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - else if(hi2c->XferSize == 2U) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Enable Pos */ - hi2c->Instance->CR1 |= I2C_CR1_POS; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(hi2c->XferSize > 0U) - { - if(hi2c->XferSize <= 3U) - { - /* One byte */ - if(hi2c->XferSize == 1U) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - /* Two bytes */ - else if(hi2c->XferSize == 2U) - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - /* 3 Last bytes */ - else - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - } - else - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - } - } - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(hi2c->XferSize > 0U) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - } - - /* Wait until AF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - while(hi2c->XferSize > 0U) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - } - - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - __IO uint32_t Prev_State = 0x00U; - __IO uint32_t count = 0x00U; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Check Busy Flag only if FIRST call of Master interface */ - if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - Prev_State = hi2c->PreviousState; - - /* Generate Start */ - if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) - { - /* Generate Start condition if first transfer */ - if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) - { - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else - { - /* Generate ReStart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - __IO uint32_t count = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Check Busy Flag only if FIRST call of Master interface */ - if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) - { - /* Generate Start condition if first transfer */ - if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate ReStart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferSize = hi2c->XferCount; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferSize = hi2c->XferCount; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Disable Address Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Disable EVT and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - if(hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferM1CpltCallback = NULL; - hi2c->hdmatx->XferM1HalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); - - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - hi2c->Devaddress = DevAddress; - - if(hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferM1CpltCallback = NULL; - hi2c->hdmarx->XferM1HalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C process communication with Interrupt. - * @note This abort can be called only if state is ready - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(DevAddress); - - /* Abort Master transfer during Receive or Transmit process */ - if(hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->XferCount = 0U; - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferM1CpltCallback = NULL; - hi2c->hdmatx->XferM1HalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferM1CpltCallback = NULL; - hi2c->hdmarx->XferM1HalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - while(hi2c->XferSize > 0U) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - } - - /* Wait until BTF flag is set */ - if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - if(hi2c->XferSize == 0U) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - else if(hi2c->XferSize == 1U) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - else if(hi2c->XferSize == 2U) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Enable Pos */ - hi2c->Instance->CR1 |= I2C_CR1_POS; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(hi2c->XferSize > 0U) - { - if(hi2c->XferSize <= 3U) - { - /* One byte */ - if(hi2c->XferSize== 1U) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - /* Two bytes */ - else if(hi2c->XferSize == 2U) - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - /* 3 Last bytes */ - else - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - } - else - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferSize--; - hi2c->XferCount--; - } - } - } - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->Devaddress = DevAddress; - hi2c->Memaddress = MemAddress; - hi2c->MemaddSize = MemAddSize; - hi2c->EventCount = 0U; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->Devaddress = DevAddress; - hi2c->Memaddress = MemAddress; - hi2c->MemaddSize = MemAddSize; - hi2c->EventCount = 0U; - - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - if(hi2c->XferSize > 0U) - { - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - __IO uint32_t count = 0U; - - uint32_t tickstart = 0x00U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if(hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferM1CpltCallback = NULL; - hi2c->hdmatx->XferM1HalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0x00U; - __IO uint32_t count = 0U; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); - do - { - if(count-- == 0U) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferSize = hi2c->XferCount; - - if(hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferM1CpltCallback = NULL; - hi2c->hdmarx->XferM1HalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - if(Size == 1U) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - } - else - { - /* Enable Last DMA bit */ - hi2c->Instance->CR2 |= I2C_CR2_LAST; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); - - /* Enable DMA Request */ - hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Check if the I2C is already enabled */ - if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) - { - /* Enable I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - } - - /* Disable Pos */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - do - { - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR or AF flag are set */ - /* Get tick */ - tickstart = HAL_GetTick(); - - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - tmp3 = hi2c->State; - while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_TIMEOUT; - } - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - tmp3 = hi2c->State; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if the ADDR flag has been set */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Clear ADDR Flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Clear AF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - }while(I2C_Trials++ < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); - uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); - uint32_t itsources = READ_REG(hi2c->Instance->CR2); - - uint32_t CurrentMode = hi2c->Mode; - - /* Master or Memory mode selected */ - if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) - { - /* SB Set ----------------------------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_Master_SB(hi2c); - } - /* ADD10 Set -------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_Master_ADD10(hi2c); - } - /* ADDR Set --------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_Master_ADDR(hi2c); - } - - /* I2C in mode Transmitter -----------------------------------------------*/ - if((sr2itflags & I2C_FLAG_TRA) != RESET) - { - /* TXE set and BTF reset -----------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) - { - I2C_MasterTransmit_TXE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_MasterTransmit_BTF(hi2c); - } - } - /* I2C in mode Receiver --------------------------------------------------*/ - else - { - /* RXNE set and BTF reset -----------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) - { - I2C_MasterReceive_RXNE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_MasterReceive_BTF(hi2c); - } - } - } - /* Slave mode selected */ - else - { - /* ADDR set --------------------------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_Slave_ADDR(hi2c); - } - /* STOPF set --------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_Slave_STOPF(hi2c); - } - /* I2C in mode Transmitter -----------------------------------------------*/ - else if((sr2itflags & I2C_FLAG_TRA) != RESET) - { - /* TXE set and BTF reset -----------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) - { - I2C_SlaveTransmit_TXE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_SlaveTransmit_BTF(hi2c); - } - } - /* I2C in mode Receiver --------------------------------------------------*/ - else - { - /* RXNE set and BTF reset ----------------------------------------------*/ - if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) - { - I2C_SlaveReceive_RXNE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) - { - I2C_SlaveReceive_BTF(hi2c); - } - } - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; - uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); - uint32_t itsources = READ_REG(hi2c->Instance->CR2); - - /* I2C Bus error interrupt occurred ----------------------------------------*/ - if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ - if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* I2C Acknowledge failure error interrupt occurred ------------------------*/ - if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) - { - tmp1 = hi2c->Mode; - tmp2 = hi2c->XferCount; - tmp3 = hi2c->State; - tmp4 = hi2c->PreviousState; - if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ - ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ - ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) - { - I2C_Slave_AF(hi2c); - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ - if(hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - } - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - - /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ - if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* Call the Error Callback in case of Error detected -----------------------*/ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback can be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback can be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Return the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** - * @brief Return the I2C error code - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval I2C Error Code - */ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Handle TXE flag for Master - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - uint32_t CurrentMode = hi2c->Mode; - uint32_t CurrentXferOptions = hi2c->XferOptions; - - if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) - { - /* Call TxCpltCallback() directly if no stop mode is set */ - if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) - { - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MasterTxCpltCallback(hi2c); - } - else /* Generate Stop condition then Call TxCpltCallback() */ - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - } - else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ - ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) - { - if(hi2c->XferCount == 0U) - { - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - } - else - { - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - if(hi2c->EventCount == 0) - { - /* If Memory address size is 8Bit */ - if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); - - hi2c->EventCount += 2; - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); - - hi2c->EventCount++; - } - } - else if(hi2c->EventCount == 1) - { - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); - - hi2c->EventCount++; - } - else if(hi2c->EventCount == 2) - { - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - /* Generate Restart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - } - } - else - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - } - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Master transmitter - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentXferOptions = hi2c->XferOptions; - - if(hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - if(hi2c->XferCount != 0U) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - else - { - /* Call TxCpltCallback() directly if no stop mode is set */ - if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) - { - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MasterTxCpltCallback(hi2c); - } - else /* Generate Stop condition then Call TxCpltCallback() */ - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - } - } - return HAL_OK; -} - -/** - * @brief Handle RXNE flag for Master - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - uint32_t tmp = 0U; - - tmp = hi2c->XferCount; - if(tmp > 3U) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - if(hi2c->XferCount == 3) - { - /* Disable BUF interrupt, this help to treat correctly the last 4 bytes - on BTF subroutine */ - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - } - } - else if((tmp == 1U) || (tmp == 0U)) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Master receiver - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentXferOptions = hi2c->XferOptions; - - if(hi2c->XferCount == 4U) - { - /* Disable BUF interrupt, this help to treat correctly the last 2 bytes - on BTF subroutine if there is a reception delay between N-1 and N byte */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - else if(hi2c->XferCount == 3U) - { - /* Disable BUF interrupt, this help to treat correctly the last 2 bytes - on BTF subroutine if there is a reception delay between N-1 and N byte */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - else if(hi2c->XferCount == 2U) - { - /* Prepare next transfer or stop current transfer */ - if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Generate ReStart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - /* Disable EVT and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - else - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle SB flag for Master - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - if(hi2c->EventCount == 0U) - { - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); - } - else - { - hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); - } - } - else - { - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Send slave 7 Bits address */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); - } - else - { - hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); - } - } - else - { - if(hi2c->EventCount == 0U) - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); - } - else if(hi2c->EventCount == 1U) - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); - } - } - } - - return HAL_OK; -} - -/** - * @brief Handle ADD10 flag for Master - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) -{ - /* Send slave address */ - hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); - - return HAL_OK; -} - -/** - * @brief Handle ADDR flag for Master - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentMode = hi2c->Mode; - uint32_t CurrentXferOptions = hi2c->XferOptions; - uint32_t Prev_State = hi2c->PreviousState; - - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Restart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - hi2c->EventCount++; - } - else - { - if(hi2c->XferCount == 0U) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - else if(hi2c->XferCount == 1U) - { - if(CurrentXferOptions == I2C_NO_OPTION_FRAME) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - } - /* Prepare next transfer or stop current transfer */ - else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ - && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) - { - if(hi2c->XferOptions != I2C_NEXT_FRAME) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - } - } - else if(hi2c->XferCount == 2U) - { - if(hi2c->XferOptions != I2C_NEXT_FRAME) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Enable Pos */ - hi2c->Instance->CR1 |= I2C_CR1_POS; - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - } - - if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) - { - /* Enable Last DMA bit */ - hi2c->Instance->CR2 |= I2C_CR2_LAST; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) - { - /* Enable Last DMA bit */ - hi2c->Instance->CR2 |= I2C_CR2_LAST; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - /* Reset Event counter */ - hi2c->EventCount = 0U; - } - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - return HAL_OK; -} - -/** - * @brief Handle TXE flag for Slave - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - - if(hi2c->XferCount != 0U) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - - if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Last Byte is received, disable Interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - - /* Set state at HAL_I2C_STATE_LISTEN */ - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - hi2c->State = HAL_I2C_STATE_LISTEN; - - /* Call the Tx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Slave transmitter - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0U) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle RXNE flag for Slave - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - - if(hi2c->XferCount != 0U) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Last Byte is received, disable Interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - - /* Set state at HAL_I2C_STATE_LISTEN */ - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - hi2c->State = HAL_I2C_STATE_LISTEN; - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Slave receiver - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0U) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle ADD flag for Slave - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) -{ - uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; - uint16_t SlaveAddrCode = 0U; - - /* Transfer Direction requested by Master */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) - { - TransferDirection = I2C_DIRECTION_TRANSMIT; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) - { - SlaveAddrCode = hi2c->Init.OwnAddress1; - } - else - { - SlaveAddrCode = hi2c->Init.OwnAddress2; - } - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); - - return HAL_OK; -} - -/** - * @brief Handle STOPF flag for Slave - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* If a DMA is ongoing, Update handle size context */ - if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) - { - if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); - } - else - { - hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); - } - } - - /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) - { - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c); - } - else - { - if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ - (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - else - { - if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - } - } - return HAL_OK; -} - -/** - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - uint32_t CurrentXferOptions = hi2c->XferOptions; - - if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ - (CurrentState == HAL_I2C_STATE_LISTEN)) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - else if(CurrentState == HAL_I2C_STATE_BUSY_TX) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - else - { - /* Clear AF flag only */ - /* State Listen, but XferOptions == FIRST or NEXT */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - - return HAL_OK; -} - -/** - * @brief I2C interrupts error process - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - - if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* keep HAL_I2C_STATE_LISTEN */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_LISTEN; - } - else - { - /* If state is an abort treatment on going, don't change state */ - /* This change will be do later */ - if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) - { - hi2c->State = HAL_I2C_STATE_READY; - } - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - } - - /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ - hi2c->Instance->CR1 &= ~I2C_CR1_POS; - - /* Abort DMA transfer */ - if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) - { - hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; - - if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) - { - /* Set the DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Disable I2C peripheral to prevent dummy data in buffer */ - __HAL_I2C_DISABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - else - { - /* Set the DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - } - - /* Disable I2C peripheral to prevent dummy data in buffer */ - __HAL_I2C_DISABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - else if(hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - } - - /* Disable I2C peripheral to prevent dummy data in buffer */ - __HAL_I2C_DISABLE(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - } - - /* Call user error callback */ - HAL_I2C_ErrorCallback(hi2c); - } - /* STOP Flag is not set after a NACK reception */ - /* So may inform upper layer that listen phase is stopped */ - /* during NACK error treatment */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } -} - -/** - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -{ - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentXferOptions = hi2c->XferOptions; - - /* Generate Start condition if first transfer */ - if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) - { - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - /* Generate ReStart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - } - else - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); - - /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); - } - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress Target device address The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -{ - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentXferOptions = hi2c->XferOptions; - - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start condition if first transfer */ - if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) - { - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - /* Generate ReStart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - } - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); - } - else - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); - - /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Restart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); - } - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress Target device address - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - /* Enable Acknowledge */ - hi2c->Instance->CR1 |= I2C_CR1_ACK; - - /* Generate Start */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Generate Restart */ - hi2c->Instance->CR1 |= I2C_CR1_START; - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief DMA I2C process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ - uint32_t CurrentState = hi2c->State; - uint32_t CurrentMode = hi2c->Mode; - - if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) - { - /* Disable DMA Request */ - hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; - - hi2c->XferCount = 0U; - - /* Enable EVT and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - } - else - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Disable Last DMA */ - hi2c->Instance->CR2 &= ~I2C_CR2_LAST; - - /* Disable DMA Request */ - hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; - - hi2c->XferCount = 0U; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - if(hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - } -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Ignore DMA FIFO error */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - hi2c->XferCount = 0U; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - - hi2c->XferCount = 0U; - - /* Reset XferAbortCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Disable I2C peripheral to prevent dummy data in buffer */ - __HAL_I2C_DISABLE(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Disable I2C peripheral to prevent dummy data in buffer */ - __HAL_I2C_DISABLE(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param Flag specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - /* Wait until flag is set */ - while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for Master addressing phase. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param Flag specifies the I2C flag to check. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Generate Stop */ - hi2c->Instance->CR1 |= I2C_CR1_STOP; - - /* Clear AF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) - { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) -{ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c deleted file mode 100644 index de8f1602..00000000 --- a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extension HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C extension peripheral: - * + Extension features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral extension features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ - 429xx/439xx devices contains the following additional features : - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter - (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() - (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Functions I2C Exported Functions - * @{ - */ - - -/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions - * @brief Extension features functions - * -@verbatim - =============================================================================== - ##### Extension features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - -@endverbatim - * @{ - */ - -/** - * @brief Configures I2C Analog noise filter. - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter new state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); - - /* Disable the analog filter */ - hi2c->Instance->FLTR |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures I2C Digital noise filter. - * @param hi2c pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->FLTR; - - /* Reset I2Cx DNF bit [3:0] */ - tmpreg &= ~(I2C_FLTR_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter; - - /* Store the new register value */ - hi2c->Instance->FLTR = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ - STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ - STM32F423xx */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Inc/FreeRTOSConfig.h b/Firmware/Board/v3/Inc/FreeRTOSConfig.h index 53280d99..90e233b3 100644 --- a/Firmware/Board/v3/Inc/FreeRTOSConfig.h +++ b/Firmware/Board/v3/Inc/FreeRTOSConfig.h @@ -89,7 +89,6 @@ /* Ensure stdint is only used by the compiler, and not the assembler. */ #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) #include - #include "main.h" extern uint32_t SystemCoreClock; #endif @@ -153,7 +152,7 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ /* Normal assert() semantics without relying on the provision of an assert.h header file. */ -/* USER CODE BEGIN 1 */ +/* USER CODE BEGIN 1 */ #define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} /* USER CODE END 1 */ diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h index b3ef59aa..e518489f 100644 --- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h +++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2C_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ @@ -91,6 +91,7 @@ /* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED @@ -244,6 +245,10 @@ #include "stm32f4xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32f4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ diff --git a/Firmware/Board/v3/Inc/tim.h b/Firmware/Board/v3/Inc/tim.h index 7006b95a..ba58367a 100644 --- a/Firmware/Board/v3/Inc/tim.h +++ b/Firmware/Board/v3/Inc/tim.h @@ -80,10 +80,9 @@ void MX_TIM3_Init(void); void MX_TIM4_Init(void); void MX_TIM5_Init(void); void MX_TIM8_Init(void); - + void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); - - + /* USER CODE BEGIN Prototypes */ void OC4_PWM_Override(TIM_HandleTypeDef* htim); diff --git a/Firmware/Board/v3/Inc/usbd_cdc_if.h b/Firmware/Board/v3/Inc/usbd_cdc_if.h index ed1d6705..c15e8b91 100644 --- a/Firmware/Board/v3/Inc/usbd_cdc_if.h +++ b/Firmware/Board/v3/Inc/usbd_cdc_if.h @@ -132,7 +132,7 @@ extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; * @{ */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); /* USER CODE BEGIN EXPORTED_FUNCTIONS */ /* USER CODE END EXPORTED_FUNCTIONS */ diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index fe7867dd..bf276186 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -89,7 +89,6 @@ * @brief Defines for configuration of the Usb device. * @{ */ -#define MS_VendorCode 'P' /*---------- -----------*/ #define USBD_MAX_NUM_INTERFACES 1 @@ -98,7 +97,7 @@ /*---------- -----------*/ #define USBD_MAX_STR_DESC_SIZ 512 /*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 1 +#define USBD_SUPPORT_USER_STRING 0 /*---------- -----------*/ #define USBD_DEBUG_LEVEL 0 /*---------- -----------*/ diff --git a/Firmware/Board/v3/Inc/usbd_desc.h b/Firmware/Board/v3/Inc/usbd_desc.h index 2a74de31..18d1f34e 100644 --- a/Firmware/Board/v3/Inc/usbd_desc.h +++ b/Firmware/Board/v3/Inc/usbd_desc.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.h * @version : v1.0_Cube - * @brief : Header for usbd_desc.c file. + * @brief : Header for usbd_conf.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -46,7 +46,6 @@ * ****************************************************************************** */ - /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__H__ #define __USBD_DESC__H__ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index c029e22a..d937b2e8 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -52,15 +52,13 @@ #define CDC_IN_EP 0x81 /* EP1 for data IN */ #define CDC_OUT_EP 0x01 /* EP1 for data OUT */ #define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ -#define ODRIVE_IN_EP 0x83 /* EP3 IN: ODrive device TX endpoint */ -#define ODRIVE_OUT_EP 0x03 /* EP3 OUT: ODrive device RX endpoint */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ -#define USB_CDC_CONFIG_DESC_SIZ (67 + 39) +#define USB_CDC_CONFIG_DESC_SIZ 67 #define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE #define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE @@ -105,29 +103,23 @@ typedef struct _USBD_CDC_Itf int8_t (* Init) (void); int8_t (* DeInit) (void); int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *, uint8_t); + int8_t (* Receive) (uint8_t *, uint32_t *); }USBD_CDC_ItfTypeDef; -typedef struct -{ - uint8_t* Buffer; - uint32_t Length; - volatile uint8_t State; -} -USBD_CDC_EP_HandleTypeDef; typedef struct { uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ uint8_t CmdOpCode; - uint8_t CmdLength; - - USBD_CDC_EP_HandleTypeDef CDC_Tx; - USBD_CDC_EP_HandleTypeDef CDC_Rx; - - USBD_CDC_EP_HandleTypeDef ODRIVE_Tx; - USBD_CDC_EP_HandleTypeDef ODRIVE_Rx; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; } USBD_CDC_HandleTypeDef; @@ -159,15 +151,14 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length, - uint8_t endpoint_pair); + uint16_t length); uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, uint8_t endpoint_pair); + uint8_t *pbuff); -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 73313522..b2ca5f16 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -62,8 +62,7 @@ #include "usbd_cdc.h" #include "usbd_desc.h" #include "usbd_ctlreq.h" -#include -#include + /** @addtogroup STM32_USB_DEVICE_LIBRARY * @{ @@ -132,9 +131,6 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); -static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -//static uint8_t * USBD_GetUsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); - /* USB Standard Device Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { @@ -176,37 +172,24 @@ USBD_ClassTypeDef USBD_CDC = USBD_CDC_GetFSCfgDesc, USBD_CDC_GetOtherSpeedCfgDesc, USBD_CDC_GetDeviceQualifierDescriptor, - USBD_UsrStrDescriptor }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { /*Configuration Descriptor*/ 0x09, /* bLength: Configuration Descriptor size */ USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 custom) */ + 0x02, /* bNumInterfaces: 2 interface */ 0x01, /* bConfigurationValue: Configuration value */ 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ 0xC0, /* bmAttributes: self powered */ 0x32, /* MaxPower 0 mA */ - - /////////////////////////////////////////////////////////////////////////////// - - /* Interface Association Descriptor: CDC device (virtual com port) */ - 0x08, /* bLength: IAD size */ - 0x0B, /* bDescriptorType: Interface Association Descriptor */ - 0x00, /* bFirstInterface */ - 0x02, /* bInterfaceCount */ - 0x02, /* bFunctionClass: Communication Interface Class */ - 0x02, /* bFunctionSubClass: Abstract Control Model */ - 0x01, /* bFunctionProtocol: Common AT commands */ - 0x00, /* iFunction */ /*---------------------------------------------------------------------------*/ - + /*Interface Descriptor */ 0x09, /* bLength: Interface Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ @@ -218,7 +201,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bInterfaceSubClass: Abstract Control Model */ 0x01, /* bInterfaceProtocol: Common AT commands */ 0x00, /* iInterface: */ - + /*Header Functional Descriptor*/ 0x05, /* bLength: Endpoint Descriptor size */ 0x24, /* bDescriptorType: CS_INTERFACE */ @@ -245,7 +228,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x06, /* bDescriptorSubtype: Union func desc */ 0x00, /* bMasterInterface: Communication class interface */ 0x01, /* bSlaveInterface0: Data Class Interface */ - + /*Endpoint 2 Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ @@ -283,52 +266,196 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; - /////////////////////////////////////////////////////////////////////////////// + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ - /* Interface Association Descriptor: custom device */ - 0x08, /* bLength: IAD size */ - 0x0B, /* bDescriptorType: Interface Association Descriptor */ - 0x02, /* bFirstInterface */ - 0x01, /* bInterfaceCount */ - 0x00, /* bFunctionClass: */ - 0x00, /* bFunctionSubClass: */ - 0x00, /* bFunctionProtocol: */ - 0x06, /* iFunction */ - + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval: */ /*---------------------------------------------------------------------------*/ /*Data class interface descriptor*/ 0x09, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x02, /* bInterfaceNumber: Number of Interface */ + 0x01, /* bInterfaceNumber: Number of Interface */ 0x00, /* bAlternateSetting: Alternate setting */ 0x02, /* bNumEndpoints: Two endpoints used */ - 0x00, /* bInterfaceClass: vendor specific */ - 0x01, /* bInterfaceSubClass: ODrive Communication */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ 0x00, /* bInterfaceProtocol: */ 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - ODRIVE_OUT_EP, /* bEndpointAddress */ + CDC_OUT_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - ODRIVE_IN_EP, /* bEndpointAddress */ + CDC_IN_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ } ; +__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; /** * @} @@ -380,19 +507,6 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, USBD_EP_TYPE_BULK, CDC_DATA_FS_OUT_PACKET_SIZE); } - - /* Open ODrive IN endpoint */ - USBD_LL_OpenEP(pdev, - ODRIVE_IN_EP, - USBD_EP_TYPE_BULK, - pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_IN_PACKET_SIZE : CDC_DATA_FS_IN_PACKET_SIZE); - - /* Open ODrive OUT endpoint */ - USBD_LL_OpenEP(pdev, - ODRIVE_OUT_EP, - USBD_EP_TYPE_BULK, - pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); - /* Open Command IN EP */ USBD_LL_OpenEP(pdev, CDC_CMD_EP, @@ -414,17 +528,15 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); /* Init Xfer states */ - hcdc->CDC_Tx.State =0; - hcdc->CDC_Rx.State =0; - hcdc->ODRIVE_Tx.State =0; - hcdc->ODRIVE_Rx.State =0; + hcdc->TxState =0; + hcdc->RxState =0; if(pdev->dev_speed == USBD_SPEED_HIGH ) { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->CDC_Rx.Buffer, + hcdc->RxBuffer, CDC_DATA_HS_OUT_PACKET_SIZE); } else @@ -432,15 +544,11 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->CDC_Rx.Buffer, + hcdc->RxBuffer, CDC_DATA_FS_OUT_PACKET_SIZE); } - /* Prepare ODrive Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - ODRIVE_OUT_EP, - hcdc->ODRIVE_Rx.Buffer, - CDC_DATA_FS_OUT_PACKET_SIZE); + } return ret; } @@ -457,25 +565,17 @@ static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, { uint8_t ret = 0; - /* Close EP IN */ + /* Open EP IN */ USBD_LL_CloseEP(pdev, CDC_IN_EP); - /* Close EP OUT */ + /* Open EP OUT */ USBD_LL_CloseEP(pdev, CDC_OUT_EP); - /* Close Command IN EP */ + /* Open Command IN EP */ USBD_LL_CloseEP(pdev, CDC_CMD_EP); - - /* Close EP IN */ - USBD_LL_CloseEP(pdev, - ODRIVE_IN_EP); - - /* Close EP OUT */ - USBD_LL_CloseEP(pdev, - ODRIVE_OUT_EP); /* DeInit physical Interface components */ @@ -547,9 +647,6 @@ static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, case USB_REQ_SET_INTERFACE : break; } - - case USB_REQ_TYPE_VENDOR: - return USBD_WinUSBComm_SetupVendor(pdev, req); default: break; @@ -570,13 +667,9 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) if(pdev->pClassData != NULL) { - // NOTE: We would logically expect xx_IN_EP here, but we actually get the xx_OUT_EP - if (epnum == CDC_OUT_EP) - hcdc->CDC_Tx.State = 0; - if (epnum == ODRIVE_OUT_EP) - hcdc->ODRIVE_Tx.State = 0; - //Note: We could use independent semaphores for simoultainous USB transmission. - osSemaphoreRelease(sem_usb_tx); + + hcdc->TxState = 0; + return USBD_OK; } else @@ -595,24 +688,15 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - USBD_CDC_EP_HandleTypeDef* hEP_Rx; - if (epnum == CDC_OUT_EP) { - hEP_Rx = &hcdc->CDC_Rx; - } else if (epnum == ODRIVE_OUT_EP) { - hEP_Rx = &hcdc->ODRIVE_Rx; - } else { - return USBD_FAIL; - } /* Get the received data length */ - hEP_Rx->Length = USBD_LL_GetRxDataSize (pdev, epnum); + hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ if(pdev->pClassData != NULL) { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hEP_Rx->Buffer, &hEP_Rx->Length, epnum); + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); return USBD_OK; } @@ -655,8 +739,8 @@ static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) */ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgDesc); - return USBD_CDC_CfgDesc; + *length = sizeof (USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; } /** @@ -668,8 +752,8 @@ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgDesc); - return USBD_CDC_CfgDesc; + *length = sizeof (USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; } /** @@ -681,8 +765,8 @@ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgDesc); - return USBD_CDC_CfgDesc; + *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; } /** @@ -725,22 +809,12 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, */ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length, - uint8_t endpoint_pair) + uint16_t length) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - USBD_CDC_EP_HandleTypeDef* hEP_Tx; - if (endpoint_pair == CDC_OUT_EP) { - hEP_Tx = &hcdc->CDC_Tx; - } else if (endpoint_pair == ODRIVE_OUT_EP) { - hEP_Tx = &hcdc->ODRIVE_Tx; - } else { - return USBD_FAIL; - } - - hEP_Tx->Buffer = pbuff; - hEP_Tx->Length = length; + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; return USBD_OK; } @@ -753,20 +827,11 @@ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, * @retval status */ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, uint8_t endpoint_pair) + uint8_t *pbuff) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - USBD_CDC_EP_HandleTypeDef* hEP_Rx; - if (endpoint_pair == CDC_OUT_EP) { - hEP_Rx = &hcdc->CDC_Rx; - } else if (endpoint_pair == ODRIVE_OUT_EP) { - hEP_Rx = &hcdc->ODRIVE_Rx; - } else { - return USBD_FAIL; - } - hEP_Rx->Buffer = pbuff; + hcdc->RxBuffer = pbuff; return USBD_OK; } @@ -778,36 +843,23 @@ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, * @param epnum: endpoint number * @retval status */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; if(pdev->pClassData != NULL) { - // Select Endpoint - USBD_CDC_EP_HandleTypeDef* hEP_Tx; - uint8_t in_ep; - if (endpoint_pair == CDC_OUT_EP) { - hEP_Tx = &hcdc->CDC_Tx; - in_ep = CDC_IN_EP; - } else if (endpoint_pair == ODRIVE_OUT_EP) { - hEP_Tx = &hcdc->ODRIVE_Tx; - in_ep = ODRIVE_IN_EP; - } else { - return USBD_FAIL; - } - - if(hEP_Tx->State == 0) + if(hcdc->TxState == 0) { /* Tx Transfer in progress */ - hEP_Tx->State = 1; + hcdc->TxState = 1; /* Transmit next packet */ USBD_LL_Transmit(pdev, - in_ep, - hEP_Tx->Buffer, - hEP_Tx->Length); - + CDC_IN_EP, + hcdc->TxBuffer, + hcdc->TxLength); + return USBD_OK; } else @@ -828,32 +880,29 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; /* Suspend or Resume USB Out process */ if(pdev->pClassData != NULL) { - // Select Endpoint - USBD_CDC_EP_HandleTypeDef* hEP_Rx; - uint8_t out_ep; - if (endpoint_pair == CDC_OUT_EP) { - hEP_Rx = &hcdc->CDC_Rx; - out_ep = CDC_OUT_EP; - } else if (endpoint_pair == ODRIVE_OUT_EP) { - hEP_Rx = &hcdc->ODRIVE_Rx; - out_ep = ODRIVE_OUT_EP; - } else { - return USBD_FAIL; + if(pdev->dev_speed == USBD_SPEED_HIGH ) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } - - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - out_ep, - hEP_Rx->Buffer, - pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); - return USBD_OK; } else @@ -861,184 +910,6 @@ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) return USBD_FAIL; } } - - -/* WinUSB support ------------------------------------------------------------*/ -/* -* This section tells Windows that it should automatically load the WinUSB driver -* for the device (more specifically, interface 2 because it's a composite device). -* This allows for driverless communication with the device. -*/ - -#define NUM_INTERFACES 1 - -#if NUM_INTERFACES == 2 -#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24 + 24) -#else -#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24) -#endif - - -// This associates winusb driver with the device -__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Compat_ID_OS_Desc[USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ] __ALIGN_END = -{ - // +-- Offset in descriptor - // | +-- Size - // v v - USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ, 0, 0, 0, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended compat ID descriptor - 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format - 0x04, 0x00, // 6 wIndex 2 WORD An index that identifies the particular OS feature descriptor - NUM_INTERFACES, // 8 bCount 1 BYTE The number of custom property sections - 0, 0, 0, 0, 0, 0, 0, // 9 RESERVED 7 BYTEs Reserved - // ===================== - // 16 - - // +-- Offset from function section start - // | +-- Size - // v v - 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number - 0, // 1 RESERVED 1 BYTE Reserved - 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") - 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID - 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved - // ================================= - // 24 -#if NUM_INTERFACES == 2 - // +-- Offset from function section start - // | +-- Size - // v v - 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number - 0, // 1 RESERVED 1 BYTE Reserved - 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") - 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID - 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved - // ================================= - // 24 -#endif -}; - - -// Properties are added to: -// HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Enum\USB\VID_xxxx&PID_xxxx\sssssssss\Device Parameters -// Use USBDeview or similar to uninstall - -__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Properties_OS_Desc[0xB6] __ALIGN_END = -{ - 0xB6, 0x00, 0x00, 0x00, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended properties descriptor - 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format - 0x05, 0x00, // 6 wIndex 2 WORD The index for extended properties OS descriptors - 0x02, 0x00, // 8 wCount 2 WORD The number of custom property sections that follow the header section - // ==================== - // 10 -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - 0x84, 0x00, 0x00, 0x00, // 0 dwSize 4 DWORD The size of this custom properties section - 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 4 DWORD Property data format - 0x28, 0x00, // 8 wPropertyNameLength 2 DWORD Property name length - // ======================================== - // 10 - // 10 bPropertyName PNL WCHAR[] The property name - 'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0, - 't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0, - 'U',0, 'I',0, 'D',0, 0,0, - // ======================================== - // 40 (0x28) - - 0x4E, 0x00, 0x00, 0x00, // 10 + PNL dwPropertyDataLength 4 DWORD Length of the buffer holding the property data - // ======================================== - // 4 - // 14 + PNL bPropertyData PDL Format-dependent Property data - '{',0, 'E',0, 'A',0, '0',0, 'B',0, 'D',0, '5',0, 'C',0, - '3',0, '-',0, '5',0, '0',0, 'F',0, '3',0, '-',0, '4',0, - '8',0, '8',0, '8',0, '-',0, '8',0, '4',0, 'B',0, '4',0, - '-',0, '7',0, '4',0, 'E',0, '5',0, '0',0, 'E',0, '1',0, - '6',0, '4',0, '9',0, 'D',0, 'B',0, '}',0, 0 ,0, - // ======================================== - // 78 (0x4E) -/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - 0x3E, 0x00, 0x00, 0x00, // 0 dwSize 0x00000030 (62 bytes) - 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 0x00000001 (Unicode string) - 0x0C, 0x00, // 8 wPropertyNameLength 0x000C (12 bytes) - // ======================================== - // 10 - 'L',0, 'a',0, 'b',0, 'e',0, 'l',0, 0,0, - // 10 bPropertyName “Label” - // ======================================== - // 12 - 0x24, 0x00, 0x00, 0x00, // 22 dwPropertyDataLength 0x00000016 (36 bytes) - // ======================================== - // 4 - 'O',0, 'D',0, 'r',0, 'i',0, 'v',0, 'e',0, 0,0 - // 26 bPropertyData “ODrive” - // ======================================== - // 14 - -}; - - - -static uint8_t USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - switch (req->wIndex) - { - case 0x04: - USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Compat_ID_OS_Desc, req->wLength); - break; - default: - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - return USBD_OK; -} -static uint8_t USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - uint8_t byInterfaceIndex = (uint8_t)req->wValue; - if ( req->wIndex != 0x05 ) - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - switch ( byInterfaceIndex ) - { - case 0: -#if NUM_INTERFACES == 2 - case 1: -#endif - USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Properties_OS_Desc, req->wLength); - break; - default: - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - return USBD_OK; -} -static uint8_t USBD_WinUSBComm_SetupVendorDevice(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - USBD_CtlError(pdev , req); - return USBD_FAIL; -} -static uint8_t USBD_WinUSBComm_SetupVendorInterface(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - USBD_CtlError(pdev , req); - // TODO: check if this is important - return USBD_FAIL; -} -static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - switch ( req->bmRequest & USB_REQ_RECIPIENT_MASK ) - { - case USB_REQ_RECIPIENT_DEVICE: - return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorDevice(pdev, req); - case USB_REQ_RECIPIENT_INTERFACE: - return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorInterface(pdev, req); - case USB_REQ_RECIPIENT_ENDPOINT: - // fall through - default: - break; - } - USBD_CtlError(pdev , req); - return USBD_FAIL; -} - /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index f259b51d..8fbe81e4 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -68,9 +68,7 @@ #define USBD_IDX_PRODUCT_STR 0x02 #define USBD_IDX_SERIAL_STR 0x03 #define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 -#define USBD_IDX_ODRIVE_INTF_STR 0x06 -#define USBD_IDX_MICROSOFT_DESC_STR 0xEE +#define USBD_IDX_INTERFACE_STR 0x05 #define USB_REQ_TYPE_STANDARD 0x00 #define USB_REQ_TYPE_CLASS 0x20 diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index 7828403b..d0e0fd76 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t * @brief Wait until a Semaphore token becomes available * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @param millisec timeout value or 0 in case of no time-out. -* @retval status code that indicates the execution status of the function. +* @retval number of available tokens, or -1 in case of incorrect parameters. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ -osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 754be245..15e25b96 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -270,11 +270,11 @@ typedef enum { /// Entry point of a thread. /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void *argument); +typedef void (*os_pthread) (void const *argument); /// Entry point of a timer call back function. /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void *argument); +typedef void (*os_ptimer) (void const *argument); // >>> the following data type definitions may shall adapted towards a specific RTOS @@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; /// Thread Definition structure contains startup information of a thread. /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. typedef struct os_thread_def { - const char *name; ///< Thread name + char *name; ///< Thread name os_pthread pthread; ///< start address of thread function osPriority tpriority; ///< initial thread priority uint32_t instances; ///< maximum number of instances of that thread function @@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return status code that indicates the execution status of the function. +/// \return number of available tokens, or -1 in case of incorrect parameters. /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index 707c3f2a..0652d4df 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -76,9 +76,11 @@ ADC3.SamplingTime-7\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC3.SamplingTime-8\#ChannelInjectedConversion=ADC_SAMPLETIME_3CYCLES ADC3.ScanConvMode=DISABLE CAN1.AutoWakeUp=ENABLE +CAN1.BS1=CAN_BS1_6TQ +CAN1.BS2=CAN_BS2_5TQ CAN1.CalculateTimeBit=500 CAN1.CalculateTimeQuantum=166.66666666666669 -CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,Prescaler,TimeSeg1,TimeSeg2,AutoWakeUp +CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,Prescaler,TimeSeg1,TimeSeg2,AutoWakeUp,BS1,BS2 CAN1.Prescaler=7 CAN1.TimeSeg1=CAN_BS1_6TQ CAN1.TimeSeg2=CAN_BS2_5TQ @@ -209,8 +211,8 @@ Mcu.PinsNb=56 Mcu.ThirdPartyNb=0 Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx -MxCube.Version=4.24.0 -MxDb.Version=DB.4.0.240 +MxCube.Version=4.27.0 +MxDb.Version=DB.4.0.270 NVIC.ADC_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.CAN1_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true @@ -443,7 +445,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F405RGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.19.0 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.21.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x3C00 diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index fc7bf388..2171691a 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -70,7 +70,7 @@ void MX_CAN1_Init(void) hcan1.Init.TimeSeg2 = CAN_BS2_5TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = ENABLE; + hcan1.Init.AutoWakeUp = DISABLE; hcan1.Init.AutoRetransmission = DISABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c index 3de873ad..55d5e034 100644 --- a/Firmware/Board/v3/Src/dma.c +++ b/Firmware/Board/v3/Src/dma.c @@ -78,10 +78,8 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); /* DMA2_Stream0_IRQn interrupt configuration */ - // Dear STM, no we _don't_ want to fire an interrupt for this DMA - // (it's not possible to deselect this in CubeMX) - //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); - //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); } diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c index 524cd6cb..0865d714 100644 --- a/Firmware/Board/v3/Src/freertos.c +++ b/Firmware/Board/v3/Src/freertos.c @@ -1,3 +1,4 @@ +/* USER CODE BEGIN Header */ /** ****************************************************************************** * File Name : freertos.c @@ -45,12 +46,15 @@ * ****************************************************************************** */ +/* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "FreeRTOS.h" #include "task.h" +#include "main.h" #include "cmsis_os.h" +/* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "freertos_vars.h" #include "usb_device.h" @@ -58,9 +62,22 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; int odrive_main(void); /* USER CODE END Includes */ -/* Variables -----------------------------------------------------------------*/ -osThreadId defaultTaskHandle; +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN Variables */ // List of semaphores osSemaphoreId sem_usb_irq; @@ -74,17 +91,18 @@ osThreadId usb_irq_thread; __attribute__((section(".ccmram"))) uint8_t ucHeap[configTOTAL_HEAP_SIZE]; /* USER CODE END Variables */ +osThreadId defaultTaskHandle; -/* Function prototypes -------------------------------------------------------*/ -void StartDefaultTask(void * argument); - -extern void MX_USB_DEVICE_Init(void); -void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ - +/* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN FunctionPrototypes */ /* USER CODE END FunctionPrototypes */ +void StartDefaultTask(void const * argument); + +extern void MX_USB_DEVICE_Init(void); +void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ + /* Hook prototypes */ void vApplicationIdleHook(void); void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); @@ -135,8 +153,11 @@ void init_deferred_interrupts(void) { /* USER CODE END 4 */ -/* Init FreeRTOS */ - +/** + * @brief FreeRTOS initialization + * @param None + * @retval None + */ void MX_FREERTOS_Init(void) { /* USER CODE BEGIN Init */ @@ -186,8 +207,14 @@ void MX_FREERTOS_Init(void) { /* USER CODE END RTOS_QUEUES */ } -/* StartDefaultTask function */ -void StartDefaultTask(void * argument) +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void const * argument) { /* init code for USB_DEVICE */ MX_USB_DEVICE_Init(); @@ -202,6 +229,7 @@ void StartDefaultTask(void * argument) /* USER CODE END StartDefaultTask */ } +/* Private application code --------------------------------------------------*/ /* USER CODE BEGIN Application */ /* USER CODE END Application */ diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c index b71d6416..1a930e60 100644 --- a/Firmware/Board/v3/Src/main.c +++ b/Firmware/Board/v3/Src/main.c @@ -1,3 +1,4 @@ + /** ****************************************************************************** * @file : main.c diff --git a/Firmware/Board/v3/Src/stm32f4xx_hal_msp.c b/Firmware/Board/v3/Src/stm32f4xx_hal_msp.c index fac7e341..e49480c0 100644 --- a/Firmware/Board/v3/Src/stm32f4xx_hal_msp.c +++ b/Firmware/Board/v3/Src/stm32f4xx_hal_msp.c @@ -48,7 +48,6 @@ */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" - extern void _Error_Handler(char *, int); /* USER CODE BEGIN 0 */ @@ -62,6 +61,9 @@ void HAL_MspInit(void) /* USER CODE END MspInit 0 */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* System interrupt init*/ diff --git a/Firmware/Board/v3/Src/usbd_cdc_if.c b/Firmware/Board/v3/Src/usbd_cdc_if.c index b8cb6e6c..fcc712a3 100644 --- a/Firmware/Board/v3/Src/usbd_cdc_if.c +++ b/Firmware/Board/v3/Src/usbd_cdc_if.c @@ -117,12 +117,10 @@ /* Create buffer for reception and transmission */ /* It's up to user to redefine and/or remove those define */ /** Received data over USB are stored in this buffer */ -uint8_t CDCRxBufferFS[APP_RX_DATA_SIZE]; -uint8_t ODRIVERxBufferFS[APP_RX_DATA_SIZE]; +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; /** Data to send over USB CDC are stored in this buffer */ -uint8_t CDCTxBufferFS[APP_TX_DATA_SIZE]; -uint8_t ODRIVETxBufferFS[APP_TX_DATA_SIZE]; +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; /* USER CODE BEGIN PRIVATE_VARIABLES */ /* USER CODE END PRIVATE_VARIABLES */ @@ -153,7 +151,7 @@ extern USBD_HandleTypeDef hUsbDeviceFS; static int8_t CDC_Init_FS(void); static int8_t CDC_DeInit_FS(void); static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len, uint8_t endpoint_pair); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ @@ -291,7 +289,7 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair) +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { /* USER CODE BEGIN 6 */ usb_rx_process_packet(Buf, *Len, endpoint_pair); @@ -311,7 +309,7 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair) * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair) +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { uint8_t result = USBD_OK; /* USER CODE BEGIN 7 */ diff --git a/Firmware/Board/v3/Src/usbd_conf.c b/Firmware/Board/v3/Src/usbd_conf.c index 2d66d4a1..7046dc96 100644 --- a/Firmware/Board/v3/Src/usbd_conf.c +++ b/Firmware/Board/v3/Src/usbd_conf.c @@ -66,7 +66,7 @@ /* USER CODE END PV */ -PCD_HandleTypeDef hpcd_USB_OTG_FS; + PCD_HandleTypeDef hpcd_USB_OTG_FS; void _Error_Handler(char * file, int line); /* External functions --------------------------------------------------------*/ @@ -154,23 +154,6 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) */ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { - USBD_StatusTypeDef ret = USBD_OK; - USBD_HandleTypeDef *pdev = hpcd->pData; - USBD_SetupReqTypedef *req = &pdev->request; - USBD_ParseSetupRequest(req, (uint8_t *)hpcd->Setup); - if ( ( USB_REQ_TYPE_VENDOR == (req->bmRequest & USB_REQ_TYPE_MASK) ) && ( MS_VendorCode == req->bRequest ) ) - { - pdev->ep0_state = USBD_EP0_SETUP; - pdev->ep0_data_len = pdev->request.wLength; - - ret = pdev->pClass->Setup(pdev, req); - - if( (req->wLength == 0) && (ret == USBD_OK) ) - { - USBD_CtlSendStatus(pdev); - } - return; - } USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); } @@ -329,7 +312,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) pdev->pData = &hpcd_USB_OTG_FS; hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 6; + hpcd_USB_OTG_FS.Init.dev_endpoints = 4; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; @@ -346,8 +329,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // CDC IN endpoint - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // ODrive IN endpoint + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); } return USBD_OK; } diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index d213f64a..2e139e50 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -95,10 +95,7 @@ #define USBD_LANGID_STRING 1033 #define USBD_MANUFACTURER_STRING "ODrive Robotics" #define USBD_PID_FS 0x0D32 -#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) -#define USBD_PRODUCT_STR(s) #s -#define USBD_PRODUCT_STRING_FS ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR CDC Interface -#define NATIVE_STRING ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR Native Interface +#define USBD_PRODUCT_STRING_FS "ODrive v3.3" #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -234,17 +231,16 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = 0x00, /*bcdUSB */ #endif /* (USBD_LPM_ENABLED == 1) */ 0x02, - // Notify OS that this is a composite device - 0xEF, /*bDeviceClass*/ + 0x02, /*bDeviceClass*/ 0x02, /*bDeviceSubClass*/ - 0x01, /*bDeviceProtocol*/ + 0x00, /*bDeviceProtocol*/ USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ LOBYTE(USBD_VID), /*idVendor*/ HIBYTE(USBD_VID), /*idVendor*/ LOBYTE(USBD_PID_FS), /*idProduct*/ HIBYTE(USBD_PID_FS), /*idProduct*/ 0x00, /*bcdDevice rel. 2.00*/ - 0x03, /* bNumInterfaces */ + 0x02, USBD_IDX_MFC_STR, /*Index of manufacturer string*/ USBD_IDX_PRODUCT_STR, /*Index of product string*/ USBD_IDX_SERIAL_STR, /*Index of serial number string*/ @@ -346,11 +342,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length { if(speed == 0) { - USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); } else { - USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); } return USBD_StrDesc; } @@ -375,7 +371,14 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + } return USBD_StrDesc; } From 3850ce260fcc8effd87ca65b575f43fcc7769bc9 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:00:53 -0700 Subject: [PATCH 043/106] STM32CubeMX run to add TIM13 synced to RCRd TIM1 --- Firmware/Board/v3/Inc/tim.h | 2 ++ Firmware/Board/v3/Odrive.ioc | 20 +++++++----- Firmware/Board/v3/Src/main.c | 1 + Firmware/Board/v3/Src/tim.c | 61 +++++++++++++++++++++++++++++++++++- 4 files changed, 76 insertions(+), 8 deletions(-) diff --git a/Firmware/Board/v3/Inc/tim.h b/Firmware/Board/v3/Inc/tim.h index ba58367a..a4585c53 100644 --- a/Firmware/Board/v3/Inc/tim.h +++ b/Firmware/Board/v3/Inc/tim.h @@ -67,6 +67,7 @@ extern TIM_HandleTypeDef htim3; extern TIM_HandleTypeDef htim4; extern TIM_HandleTypeDef htim5; extern TIM_HandleTypeDef htim8; +extern TIM_HandleTypeDef htim13; /* USER CODE BEGIN Private defines */ @@ -80,6 +81,7 @@ void MX_TIM3_Init(void); void MX_TIM4_Init(void); void MX_TIM5_Init(void); void MX_TIM8_Init(void); +void MX_TIM13_Init(void); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index 0652d4df..c9bbdc7f 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -137,9 +137,10 @@ Mcu.IP12=TIM3 Mcu.IP13=TIM4 Mcu.IP14=TIM5 Mcu.IP15=TIM8 -Mcu.IP16=UART4 -Mcu.IP17=USB_DEVICE -Mcu.IP18=USB_OTG_FS +Mcu.IP16=TIM13 +Mcu.IP17=UART4 +Mcu.IP18=USB_DEVICE +Mcu.IP19=USB_OTG_FS Mcu.IP2=ADC3 Mcu.IP3=CAN1 Mcu.IP4=DMA @@ -148,7 +149,7 @@ Mcu.IP6=NVIC Mcu.IP7=RCC Mcu.IP8=SPI3 Mcu.IP9=SYS -Mcu.IPNb=19 +Mcu.IPNb=20 Mcu.Name=STM32F405RGTx Mcu.Package=LQFP64 Mcu.Pin0=PC13-ANTI_TAMP @@ -202,12 +203,13 @@ Mcu.Pin51=VP_FREERTOS_VS_ENABLE Mcu.Pin52=VP_SYS_VS_tim14 Mcu.Pin53=VP_TIM1_VS_ClockSourceINT Mcu.Pin54=VP_TIM1_VS_no_output4 -Mcu.Pin55=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS +Mcu.Pin55=VP_TIM13_VS_ClockSourceINT +Mcu.Pin56=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS Mcu.Pin6=PC1 Mcu.Pin7=PC2 Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP -Mcu.PinsNb=56 +Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx @@ -462,7 +464,7 @@ ProjectManager.StackSize=0x800 ProjectManager.TargetToolchain=Makefile ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_ADC2_Init-ADC2-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_TIM1_Init-TIM1-false-HAL-true,7-MX_TIM8_Init-TIM8-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_TIM4_Init-TIM4-false-HAL-true,10-MX_SPI3_Init-SPI3-false-HAL-true,11-MX_ADC3_Init-ADC3-false-HAL-true,12-SystemClock_Config-RCC-false-HAL-true,13-MX_TIM2_Init-TIM2-false-HAL-true,14-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true,15-MX_UART4_Init-UART4-false-HAL-true,16-MX_TIM5_Init-TIM5-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_ADC2_Init-ADC2-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_TIM1_Init-TIM1-false-HAL-true,7-MX_TIM8_Init-TIM8-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_TIM4_Init-TIM4-false-HAL-true,10-MX_SPI3_Init-SPI3-false-HAL-true,11-MX_ADC3_Init-ADC3-false-HAL-true,12-SystemClock_Config-RCC-false-HAL-true,13-MX_TIM2_Init-TIM2-false-HAL-true,14-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true,15-MX_UART4_Init-UART4-false-HAL-true,16-MX_TIM5_Init-TIM5-false-HAL-true,17-MX_TIM13_Init-TIM13-false-HAL-true RCC.48MHZClocksFreq_Value=48000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -592,6 +594,8 @@ TIM1.OffStateRunMode=TIM_OSSR_ENABLE TIM1.Period=TIM_1_8_PERIOD_CLOCKS TIM1.RepetitionCounter=TIM_1_8_RCR TIM1.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE +TIM13.IPParameters=Period +TIM13.Period=(2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1) * TIM_APB1_CLOCK_HZ) / TIM_1_8_CLOCK_HZ TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 TIM2.CounterMode=TIM_COUNTERMODE_CENTERALIGNED3 @@ -658,6 +662,8 @@ VP_FREERTOS_VS_ENABLE.Mode=Enabled VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE VP_SYS_VS_tim14.Mode=TIM14 VP_SYS_VS_tim14.Signal=SYS_VS_tim14 +VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM1_VS_no_output4.Mode=Output Compare4 No Output diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c index 1a930e60..e390af58 100644 --- a/Firmware/Board/v3/Src/main.c +++ b/Firmware/Board/v3/Src/main.c @@ -190,6 +190,7 @@ int main(void) MX_TIM2_Init(); MX_UART4_Init(); MX_TIM5_Init(); + MX_TIM13_Init(); /* USER CODE BEGIN 2 */ //Required to use OC4 for ADC triggering. diff --git a/Firmware/Board/v3/Src/tim.c b/Firmware/Board/v3/Src/tim.c index a909cf2a..b68a5894 100644 --- a/Firmware/Board/v3/Src/tim.c +++ b/Firmware/Board/v3/Src/tim.c @@ -80,6 +80,7 @@ TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim4; TIM_HandleTypeDef htim5; TIM_HandleTypeDef htim8; +TIM_HandleTypeDef htim13; /* TIM1 init function */ void MX_TIM1_Init(void) @@ -373,6 +374,21 @@ void MX_TIM8_Init(void) HAL_TIM_MspPostInit(&htim8); +} +/* TIM13 init function */ +void MX_TIM13_Init(void) +{ + + htim13.Instance = TIM13; + htim13.Init.Prescaler = 0; + htim13.Init.CounterMode = TIM_COUNTERMODE_UP; + htim13.Init.Period = (2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1) * TIM_APB1_CLOCK_HZ) / TIM_1_8_CLOCK_HZ; + htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim13) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + } void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) @@ -393,6 +409,21 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM1_MspInit 1 */ } + else if(tim_baseHandle->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspInit 0 */ + + /* USER CODE END TIM13_MspInit 0 */ + /* TIM13 clock enable */ + __HAL_RCC_TIM13_CLK_ENABLE(); + + /* TIM13 interrupt Init */ + HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); + /* USER CODE BEGIN TIM13_MspInit 1 */ + + /* USER CODE END TIM13_MspInit 1 */ + } } void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) @@ -626,6 +657,27 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM1_MspDeInit 1 */ } + else if(tim_baseHandle->Instance==TIM13) + { + /* USER CODE BEGIN TIM13_MspDeInit 0 */ + + /* USER CODE END TIM13_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM13_CLK_DISABLE(); + + /* TIM13 interrupt Deinit */ + /* USER CODE BEGIN TIM13:TIM8_UP_TIM13_IRQn disable */ + /** + * Uncomment the line below to disable the "TIM8_UP_TIM13_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs + */ + /* HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn); */ + /* USER CODE END TIM13:TIM8_UP_TIM13_IRQn disable */ + + /* USER CODE BEGIN TIM13_MspDeInit 1 */ + + /* USER CODE END TIM13_MspDeInit 1 */ + } } void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) @@ -651,7 +703,14 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) __HAL_RCC_TIM8_CLK_DISABLE(); /* TIM8 interrupt Deinit */ - HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn); + /* USER CODE BEGIN TIM8:TIM8_UP_TIM13_IRQn disable */ + /** + * Uncomment the line below to disable the "TIM8_UP_TIM13_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs + */ + /* HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn); */ + /* USER CODE END TIM8:TIM8_UP_TIM13_IRQn disable */ + HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn); /* USER CODE BEGIN TIM8_MspDeInit 1 */ From a7b7814fcecb9fe44d18b44837cfc4cf9739ea5f Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:23:46 -0700 Subject: [PATCH 044/106] bake patch: display correct ODrive version in USB descriptor --- ...ect-ODrive-version-in-USB-descriptor.patch | 41 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 8 ++-- 2 files changed, 5 insertions(+), 44 deletions(-) delete mode 100644 Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch diff --git a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch b/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch deleted file mode 100644 index 0b031242..00000000 --- a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b7ea3f500fbfc187a0a7112282ae6b1eee4555d0 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Tue, 13 Mar 2018 20:05:07 -0700 -Subject: [PATCH] display correct ODrive version in USB descriptor - ---- - Firmware/Board/v3/Src/usbd_desc.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index 94dc49b..37b4302 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -96,7 +96,9 @@ - #define USBD_LANGID_STRING 1033 - #define USBD_MANUFACTURER_STRING "ODrive Robotics" - #define USBD_PID_FS 0x0D32 --#define USBD_PRODUCT_STRING_FS "ODrive v3.3" -+#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) -+#define USBD_PRODUCT_STR(s) #s -+#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR - #define USBD_SERIALNUMBER_STRING_FS "000000000001" - #define USBD_CONFIGURATION_STRING_FS "CDC Config" - #define USBD_INTERFACE_STRING_FS "CDC Interface" -@@ -299,11 +301,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length - { - if(speed == 0) - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - else - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - return USBD_StrDesc; - } --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 2e139e50..973b0ae2 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -95,7 +95,9 @@ #define USBD_LANGID_STRING 1033 #define USBD_MANUFACTURER_STRING "ODrive Robotics" #define USBD_PID_FS 0x0D32 -#define USBD_PRODUCT_STRING_FS "ODrive v3.3" +#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) +#define USBD_PRODUCT_STR(s) #s +#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -342,11 +344,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length { if(speed == 0) { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } else { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } return USBD_StrDesc; } From 60dc428f2e00020822c0e0cb6c9ea013b0ce945a Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:27:56 -0700 Subject: [PATCH 045/106] bake patch: expose correct serial number on USB --- ...-expose-correct-serial-number-on-USB.patch | 32 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 9 +----- 2 files changed, 1 insertion(+), 40 deletions(-) delete mode 100644 Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch diff --git a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch b/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch deleted file mode 100644 index b9fef648..00000000 --- a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0867a92f742b312a0ebaafe94cade6f57be22170 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 12 Mar 2018 23:49:32 -0700 -Subject: [PATCH] expose correct serial number on USB - ---- - Firmware/Board/v3/Src/usbd_desc.c | 9 +++++++++------- - 1 file changed, 1 insertions(+), 8 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index b9c7bd0..94dc49b 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -327,14 +327,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l - */ - uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) - { -- if(speed == USBD_SPEED_HIGH) -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -- else -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -+ USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); - return USBD_StrDesc; - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 973b0ae2..b0906144 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -373,14 +373,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } + USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); return USBD_StrDesc; } From a385c0b4d37d0576853e3ffb649221330228893d Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:29:43 -0700 Subject: [PATCH 046/106] bake patch: fix return type of osSemaphoreWait --- ...1-fix-return-type-of-osSemaphoreWait.patch | 46 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 4 +- 3 files changed, 4 insertions(+), 50 deletions(-) delete mode 100644 Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch diff --git a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch b/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch deleted file mode 100644 index 53760fa1..00000000 --- a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 49353ccb7023c02c2bc6e3b6f14fac02a13fe599 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:55:17 -0800 -Subject: [PATCH] fix return type of osSemaphoreWait - ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 6 +++--- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - 2 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -index d0e0fd7..e764cbc 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -@@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - * @brief Wait until a Semaphore token becomes available - * @param semaphore_id semaphore object referenced with \ref osSemaphore. - * @param millisec timeout value or 0 in case of no time-out. --* @retval number of available tokens, or -1 in case of incorrect parameters. -+* @retval status code that indicates the execution status of the function. - * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. - */ --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) - { - TickType_t ticks; - portBASE_TYPE taskWoken = pdFALSE; -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 15e25b9..5223f8e 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - /// Wait until a Semaphore token becomes available. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. - /// \param[in] millisec timeout value or 0 in case of no time-out. --/// \return number of available tokens, or -1 in case of incorrect parameters. -+/// \return status code that indicates the execution status of the function. - /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - - /// Release a Semaphore token. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index d0e0fd76..7828403b 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t * @brief Wait until a Semaphore token becomes available * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @param millisec timeout value or 0 in case of no time-out. -* @retval number of available tokens, or -1 in case of incorrect parameters. +* @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 15e25b96..09cdf273 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \return status code that indicates the execution status of the function. /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. From 94701cec99b730fddbb3583e19d5e8867d4c4c65 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:31:41 -0700 Subject: [PATCH 047/106] bake patch: release sem_usb_tx in usb_cdc.c --- ...001-release-sem_usb_tx-in-usbd_cdc.c.patch | 35 ------------------- .../Class/CDC/Src/usbd_cdc.c | 5 +-- 2 files changed, 3 insertions(+), 37 deletions(-) delete mode 100644 Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch diff --git a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch b/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch deleted file mode 100644 index b69370f5..00000000 --- a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 965f7f2c80e30d7a66dcac7abaa9bdc371d9ea51 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:53:52 -0800 -Subject: [PATCH] release sem_usb_tx in usbd_cdc.c - ---- - .../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -index b2ca5f1..6ae33e8 100644 ---- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -+++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -@@ -62,7 +62,8 @@ - #include "usbd_cdc.h" - #include "usbd_desc.h" - #include "usbd_ctlreq.h" -- -+#include -+#include - - /** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ -@@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) - { - - hcdc->TxState = 0; -- -+ osSemaphoreRelease(sem_usb_tx); - return USBD_OK; - } - else --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index b2ca5f16..24465641 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -62,7 +62,8 @@ #include "usbd_cdc.h" #include "usbd_desc.h" #include "usbd_ctlreq.h" - +#include +#include /** @addtogroup STM32_USB_DEVICE_LIBRARY * @{ @@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) { hcdc->TxState = 0; - + osSemaphoreRelease(sem_usb_tx); return USBD_OK; } else From 96006286c0ef55d2b65f6aed16c11ab14345cf9f Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:43:04 -0700 Subject: [PATCH 048/106] bake patch: FreeRTOS constness fixes --- .../v3/0002-FreeRTOS-constness-fixes.patch | 64 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 8 +-- Firmware/Board/v3/Src/freertos.c | 4 +- 3 files changed, 6 insertions(+), 70 deletions(-) delete mode 100644 Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch diff --git a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch b/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch deleted file mode 100644 index afe0326e..00000000 --- a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 510ead2b159e1d8116e5241066c54a7bf8b7bfbe Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 15:29:44 -0700 -Subject: [PATCH] FreeRTOS constness fixes - - - make thread names const char * - - make thread argument non-const void* ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - Firmware/Board/v3/Src/freertos.c | 4 ++-- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 09cdf27..754be24 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -270,11 +270,11 @@ typedef enum { - - /// Entry point of a thread. - /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. --typedef void (*os_pthread) (void const *argument); -+typedef void (*os_pthread) (void *argument); - - /// Entry point of a timer call back function. - /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. --typedef void (*os_ptimer) (void const *argument); -+typedef void (*os_ptimer) (void *argument); - - // >>> the following data type definitions may shall adapted towards a specific RTOS - -@@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; - /// Thread Definition structure contains startup information of a thread. - /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. - typedef struct os_thread_def { -- char *name; ///< Thread name -+ const char *name; ///< Thread name - os_pthread pthread; ///< start address of thread function - osPriority tpriority; ///< initial thread priority - uint32_t instances; ///< maximum number of instances of that thread function -diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c -index 6eaea82..b247994 100644 ---- a/Firmware/Board/v3/Src/freertos.c -+++ b/Firmware/Board/v3/Src/freertos.c -@@ -75,7 +75,7 @@ uint8_t ucHeap[configTOTAL_HEAP_SIZE]; - /* USER CODE END Variables */ - - /* Function prototypes -------------------------------------------------------*/ --void StartDefaultTask(void const * argument); -+void StartDefaultTask(void * argument); - - extern void MX_USB_DEVICE_Init(void); - void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ -@@ -147,7 +147,7 @@ void MX_FREERTOS_Init(void) { - } - - /* StartDefaultTask function */ --void StartDefaultTask(void const * argument) -+void StartDefaultTask(void * argument) - { - /* init code for USB_DEVICE */ - MX_USB_DEVICE_Init(); --- -2.16.2 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 09cdf273..89a105dc 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -26,7 +26,7 @@ * *---------------------------------------------------------------------------- * - * Portions Copyright 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved. * Portions Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without @@ -270,11 +270,11 @@ typedef enum { /// Entry point of a thread. /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); +typedef void (*os_pthread) (void *argument); /// Entry point of a timer call back function. /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); +typedef void (*os_ptimer) (void *argument); // >>> the following data type definitions may shall adapted towards a specific RTOS @@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; /// Thread Definition structure contains startup information of a thread. /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. typedef struct os_thread_def { - char *name; ///< Thread name + const char *name; ///< Thread name os_pthread pthread; ///< start address of thread function osPriority tpriority; ///< initial thread priority uint32_t instances; ///< maximum number of instances of that thread function diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c index 0865d714..11154587 100644 --- a/Firmware/Board/v3/Src/freertos.c +++ b/Firmware/Board/v3/Src/freertos.c @@ -98,7 +98,7 @@ osThreadId defaultTaskHandle; /* USER CODE END FunctionPrototypes */ -void StartDefaultTask(void const * argument); +void StartDefaultTask(void * argument); extern void MX_USB_DEVICE_Init(void); void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ @@ -214,7 +214,7 @@ void MX_FREERTOS_Init(void) { * @retval None */ /* USER CODE END Header_StartDefaultTask */ -void StartDefaultTask(void const * argument) +void StartDefaultTask(void * argument) { /* init code for USB_DEVICE */ MX_USB_DEVICE_Init(); From 68e1715962842f7f9542c18fefe63f983e8ee8be Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:45:30 -0700 Subject: [PATCH 049/106] bake patch: disable IRQ for DMA2_Stream0 --- .../0003-disable-IRQ-for-DMA2_Stream0.patch | 33 ------------------- Firmware/Board/v3/Src/dma.c | 6 ++-- 2 files changed, 4 insertions(+), 35 deletions(-) delete mode 100644 Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch diff --git a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch b/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch deleted file mode 100644 index 282317d1..00000000 --- a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ab5ca860b3729d76a9c43c485776147ab69d2342 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 19:02:45 -0700 -Subject: [PATCH] disable IRQ for DMA2_Stream0 - -This DMA stream is used to read values from ADC1 -while ADC1 cycles through it's sequence of input -channels. No interrupts are required to make -this work. ---- - Firmware/Board/v3/Src/dma.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c -index 55d5e03..3de873a 100644 ---- a/Firmware/Board/v3/Src/dma.c -+++ b/Firmware/Board/v3/Src/dma.c -@@ -78,8 +78,10 @@ void MX_DMA_Init(void) - HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); - /* DMA2_Stream0_IRQn interrupt configuration */ -- HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -- HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); -+ // Dear STM, no we _don't_ want to fire an interrupt for this DMA -+ // (it's not possible to deselect this in CubeMX) -+ //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -+ //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); - - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c index 55d5e034..3de873ad 100644 --- a/Firmware/Board/v3/Src/dma.c +++ b/Firmware/Board/v3/Src/dma.c @@ -78,8 +78,10 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); /* DMA2_Stream0_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + // Dear STM, no we _don't_ want to fire an interrupt for this DMA + // (it's not possible to deselect this in CubeMX) + //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); + //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); } From fa44bc8f340e2e46556079335b043c18f6140930 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:57:44 -0700 Subject: [PATCH 050/106] bake patch: Add I2C files and settings --- .../v3/0002-Add-I2C-files-and-settings.patch | 6860 ----------------- .../Inc/stm32f4xx_hal_i2c.h | 649 ++ .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++ .../Src/stm32f4xx_hal_i2c_ex.c | 204 + Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- Firmware/Board/v3/Src/main.c | 2 +- 7 files changed, 6486 insertions(+), 6862 deletions(-) delete mode 100644 Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch b/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch deleted file mode 100644 index aae18bf4..00000000 --- a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch +++ /dev/null @@ -1,6860 +0,0 @@ -From b45bdbbbfe3d084d069da99b98116991923f5eb6 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Thu, 26 Apr 2018 13:20:38 -0700 -Subject: [PATCH] Add I2C files and settings - ---- - .../Inc/stm32f4xx_hal_i2c.h | 649 ++ - .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + - .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++++++ - .../Src/stm32f4xx_hal_i2c_ex.c | 204 + - Firmware/Board/v3/Inc/i2c.h | 91 + - Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- - Firmware/Board/v3/Odrive.ioc | 5 + - Firmware/Board/v3/Src/i2c.c | 198 + - Firmware/Board/v3/Src/main.c | 1 - - 11 files changed, 6811 insertions(+), 2 deletions(-) - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c - create mode 100644 Firmware/Board/v3/Inc/i2c.h - create mode 100644 Firmware/Board/v3/Src/i2c.c - -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -new file mode 100644 -index 0000000..5452a50 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -@@ -0,0 +1,649 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_H -+#define __STM32F4xx_HAL_I2C_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2C -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Types I2C Exported Types -+ * @{ -+ */ -+ -+/** -+ * @brief I2C Configuration Structure definition -+ */ -+typedef struct -+{ -+ uint32_t ClockSpeed; /*!< Specifies the clock frequency. -+ This parameter must be set to a value lower than 400kHz */ -+ -+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. -+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ -+ -+ uint32_t OwnAddress1; /*!< Specifies the first device own address. -+ This parameter can be a 7-bit or 10-bit address. */ -+ -+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. -+ This parameter can be a value of @ref I2C_addressing_mode */ -+ -+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. -+ This parameter can be a value of @ref I2C_dual_addressing_mode */ -+ -+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected -+ This parameter can be a 7-bit address. */ -+ -+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. -+ This parameter can be a value of @ref I2C_general_call_addressing_mode */ -+ -+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. -+ This parameter can be a value of @ref I2C_nostretch_mode */ -+ -+}I2C_InitTypeDef; -+ -+/** -+ * @brief HAL State structure definition -+ * @note HAL I2C State value coding follow below described bitmap : -+ * b7-b6 Error information -+ * 00 : No Error -+ * 01 : Abort (Abort user request on going) -+ * 10 : Timeout -+ * 11 : Error -+ * b5 IP initilisation status -+ * 0 : Reset (IP not initialized) -+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) -+ * b4 (not used) -+ * x : Should be set to 0 -+ * b3 -+ * 0 : Ready or Busy (No Listen mode ongoing) -+ * 1 : Listen (IP in Address Listen Mode) -+ * b2 Intrinsic process state -+ * 0 : Ready -+ * 1 : Busy (IP busy with some configuration or internal operations) -+ * b1 Rx state -+ * 0 : Ready (no Rx operation ongoing) -+ * 1 : Busy (Rx operation ongoing) -+ * b0 Tx state -+ * 0 : Ready (no Tx operation ongoing) -+ * 1 : Busy (Tx operation ongoing) -+ */ -+typedef enum -+{ -+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ -+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ -+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ -+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ -+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ -+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission -+ process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception -+ process is ongoing */ -+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ -+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ -+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -+ -+}HAL_I2C_StateTypeDef; -+ -+/** -+ * @brief HAL Mode structure definition -+ * @note HAL I2C Mode value coding follow below described bitmap : -+ * b7 (not used) -+ * x : Should be set to 0 -+ * b6 -+ * 0 : None -+ * 1 : Memory (HAL I2C communication is in Memory Mode) -+ * b5 -+ * 0 : None -+ * 1 : Slave (HAL I2C communication is in Slave Mode) -+ * b4 -+ * 0 : None -+ * 1 : Master (HAL I2C communication is in Master Mode) -+ * b3-b2-b1-b0 (not used) -+ * xxxx : Should be set to 0000 -+ */ -+typedef enum -+{ -+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ -+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ -+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ -+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -+ -+}HAL_I2C_ModeTypeDef; -+ -+/** -+ * @brief I2C handle Structure definition -+ */ -+typedef struct -+{ -+ I2C_TypeDef *Instance; /*!< I2C registers base address */ -+ -+ I2C_InitTypeDef Init; /*!< I2C communication parameters */ -+ -+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ -+ -+ uint16_t XferSize; /*!< I2C transfer size */ -+ -+ __IO uint16_t XferCount; /*!< I2C transfer counter */ -+ -+ __IO uint32_t XferOptions; /*!< I2C transfer options */ -+ -+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode -+ context for internal usage */ -+ -+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ -+ -+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ -+ -+ HAL_LockTypeDef Lock; /*!< I2C locking object */ -+ -+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ -+ -+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ -+ -+ __IO uint32_t ErrorCode; /*!< I2C Error code */ -+ -+ __IO uint32_t Devaddress; /*!< I2C Target device address */ -+ -+ __IO uint32_t Memaddress; /*!< I2C Target memory address */ -+ -+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ -+ -+ __IO uint32_t EventCount; /*!< I2C Event counter */ -+ -+}I2C_HandleTypeDef; -+ -+/** -+ * @} -+ */ -+ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2C_Error_Code I2C Error Code -+ * @brief I2C Error Code -+ * @{ -+ */ -+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ -+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ -+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ -+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ -+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ -+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode -+ * @{ -+ */ -+#define I2C_DUTYCYCLE_2 0x00000000U -+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_addressing_mode I2C addressing mode -+ * @{ -+ */ -+#define I2C_ADDRESSINGMODE_7BIT 0x00004000U -+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode -+ * @{ -+ */ -+#define I2C_DUALADDRESS_DISABLE 0x00000000U -+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode -+ * @{ -+ */ -+#define I2C_GENERALCALL_DISABLE 0x00000000U -+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_nostretch_mode I2C nostretch mode -+ * @{ -+ */ -+#define I2C_NOSTRETCH_DISABLE 0x00000000U -+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size -+ * @{ -+ */ -+#define I2C_MEMADD_SIZE_8BIT 0x00000001U -+#define I2C_MEMADD_SIZE_16BIT 0x00000010U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition -+ * @{ -+ */ -+#define I2C_DIRECTION_RECEIVE 0x00000000U -+#define I2C_DIRECTION_TRANSMIT 0x00000001U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition -+ * @{ -+ */ -+#define I2C_FIRST_FRAME 0x00000001U -+#define I2C_NEXT_FRAME 0x00000002U -+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U -+#define I2C_LAST_FRAME 0x00000008U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition -+ * @{ -+ */ -+#define I2C_IT_BUF I2C_CR2_ITBUFEN -+#define I2C_IT_EVT I2C_CR2_ITEVTEN -+#define I2C_IT_ERR I2C_CR2_ITERREN -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Flag_definition I2C Flag definition -+ * @{ -+ */ -+#define I2C_FLAG_SMBALERT 0x00018000U -+#define I2C_FLAG_TIMEOUT 0x00014000U -+#define I2C_FLAG_PECERR 0x00011000U -+#define I2C_FLAG_OVR 0x00010800U -+#define I2C_FLAG_AF 0x00010400U -+#define I2C_FLAG_ARLO 0x00010200U -+#define I2C_FLAG_BERR 0x00010100U -+#define I2C_FLAG_TXE 0x00010080U -+#define I2C_FLAG_RXNE 0x00010040U -+#define I2C_FLAG_STOPF 0x00010010U -+#define I2C_FLAG_ADD10 0x00010008U -+#define I2C_FLAG_BTF 0x00010004U -+#define I2C_FLAG_ADDR 0x00010002U -+#define I2C_FLAG_SB 0x00010001U -+#define I2C_FLAG_DUALF 0x00100080U -+#define I2C_FLAG_SMBHOST 0x00100040U -+#define I2C_FLAG_SMBDEFAULT 0x00100020U -+#define I2C_FLAG_GENCALL 0x00100010U -+#define I2C_FLAG_TRA 0x00100004U -+#define I2C_FLAG_BUSY 0x00100002U -+#define I2C_FLAG_MSL 0x00100001U -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Macros I2C Exported Macros -+ * @{ -+ */ -+ -+/** @brief Reset I2C handle state -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -+ -+/** @brief Enable or disable the specified I2C interrupts. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -+ -+/** @brief Checks if the specified I2C interrupt source is enabled or disabled. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the I2C interrupt source to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -+ -+/** @brief Checks whether the specified I2C flag is set or not. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @arg I2C_FLAG_TXE: Data register empty flag -+ * @arg I2C_FLAG_RXNE: Data register not empty flag -+ * @arg I2C_FLAG_STOPF: Stop detection flag -+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag -+ * @arg I2C_FLAG_BTF: Byte transfer finished flag -+ * @arg I2C_FLAG_ADDR: Address sent flag -+ * Address matched flag -+ * @arg I2C_FLAG_SB: Start bit flag -+ * @arg I2C_FLAG_DUALF: Dual flag -+ * @arg I2C_FLAG_SMBHOST: SMBus host header -+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header -+ * @arg I2C_FLAG_GENCALL: General call header flag -+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag -+ * @arg I2C_FLAG_BUSY: Bus busy flag -+ * @arg I2C_FLAG_MSL: Master/Slave flag -+ * @retval The new state of __FLAG__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ -+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -+ -+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to clear. -+ * This parameter can be any combination of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) -+ -+/** @brief Clears the I2C ADDR pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ tmpreg = (__HANDLE__)->Instance->SR2; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Clears the I2C STOPF pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Enable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -+ -+/** @brief Disable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) -+ -+/** -+ * @} -+ */ -+ -+/* Include I2C HAL Extension module */ -+#include "stm32f4xx_hal_i2c_ex.h" -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2C_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Initialization/de-initialization functions **********************************/ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group2 -+ * @{ -+ */ -+/* I/O operation functions *****************************************************/ -+/******* Blocking mode: Polling */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); -+ -+/******* Non-Blocking mode: Interrupt */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -+ -+/******* Non-Blocking mode: DMA */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group3 -+ * @{ -+ */ -+/* Peripheral State, Mode and Errors functions *********************************/ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Constants I2C Private Constants -+ * @{ -+ */ -+#define I2C_FLAG_MASK 0x0000FFFFU -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2C_Private_Macros I2C Private Macros -+ * @{ -+ */ -+ -+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) -+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) -+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) -+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) -+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) -+ -+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) -+ -+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) -+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) -+ -+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) -+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+ -+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters -+ * @{ -+ */ -+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ -+ ((CYCLE) == I2C_DUTYCYCLE_16_9)) -+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ -+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) -+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ -+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) -+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ -+ ((CALL) == I2C_GENERALCALL_ENABLE)) -+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ -+ ((STRETCH) == I2C_NOSTRETCH_ENABLE)) -+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ -+ ((SIZE) == I2C_MEMADD_SIZE_16BIT)) -+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) -+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) -+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) -+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ -+ ((REQUEST) == I2C_NEXT_FRAME) || \ -+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ -+ ((REQUEST) == I2C_LAST_FRAME)) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private functions ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Functions I2C Private Functions -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+ -+#endif /* __STM32F4xx_HAL_I2C_H */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -new file mode 100644 -index 0000000..ff47d5c ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -@@ -0,0 +1,137 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL Extension module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_EX_H -+#define __STM32F4xx_HAL_I2C_EX_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter -+ * @{ -+ */ -+#define I2C_ANALOGFILTER_ENABLE 0x00000000U -+#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2CEx_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Peripheral Control functions ************************************************/ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Constants I2C Private Constants -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Macros I2C Private Macros -+ * @{ -+ */ -+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ -+ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ -+ STM32F413xx || STM32F423xx */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __STM32F4xx_HAL_I2C_EX_H */ -+ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -new file mode 100644 -index 0000000..da18520 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -@@ -0,0 +1,5494 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.c -+ * @author MCD Application Team -+ * @brief I2C HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of the Inter Integrated Circuit (I2C) peripheral: -+ * + Initialization and de-initialization functions -+ * + IO operation functions -+ * + Peripheral State, Mode and Error functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] -+ The I2C HAL driver can be used as follows: -+ -+ (#) Declare a I2C_HandleTypeDef handle structure, for example: -+ I2C_HandleTypeDef hi2c; -+ -+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: -+ (##) Enable the I2Cx interface clock -+ (##) I2C pins configuration -+ (+++) Enable the clock for the I2C GPIOs -+ (+++) Configure I2C pins as alternate function open-drain -+ (##) NVIC configuration if you need to use interrupt process -+ (+++) Configure the I2Cx interrupt priority -+ (+++) Enable the NVIC I2C IRQ Channel -+ (##) DMA Configuration if you need to use DMA process -+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream -+ (+++) Enable the DMAx interface clock using -+ (+++) Configure the DMA handle parameters -+ (+++) Configure the DMA Tx or Rx Stream -+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle -+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on -+ the DMA Tx or Rx Stream -+ -+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, -+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. -+ -+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware -+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. -+ -+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() -+ -+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : -+ -+ *** Polling mode IO operation *** -+ ================================= -+ [..] -+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() -+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() -+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() -+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() -+ -+ *** Polling mode IO MEM operation *** -+ ===================================== -+ [..] -+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() -+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() -+ -+ -+ *** Interrupt mode IO operation *** -+ =================================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO sequential operation *** -+ ============================================== -+ [..] -+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition -+ when a direction change during transfer -+ [..] -+ (+) A specific option field manage the different steps of a sequential transfer -+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: -+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode -+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address -+ and data to transfer without a final stop condition -+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and without a final stop condition in both cases -+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and with a final stop condition in both cases -+ -+ (+) Differents sequential I2C interfaces are listed below: -+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() -+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() -+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can -+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). -+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() -+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() -+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() -+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO MEM operation *** -+ ======================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using -+ HAL_I2C_Mem_Write_IT() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using -+ HAL_I2C_Mem_Read_IT() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ *** DMA mode IO operation *** -+ ============================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** DMA mode IO MEM operation *** -+ ================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using -+ HAL_I2C_Mem_Write_DMA() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using -+ HAL_I2C_Mem_Read_DMA() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ -+ *** I2C HAL driver macros list *** -+ ================================== -+ [..] -+ Below the list of most used macros in I2C HAL driver. -+ -+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral -+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral -+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not -+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag -+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt -+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt -+ -+ [..] -+ (@) You can refer to the I2C HAL driver header file for more useful macros -+ -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2C I2C -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/** @addtogroup I2C_Private_Define -+ * @{ -+ */ -+#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ -+#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ -+#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ -+ -+/* Private define for @ref PreviousState usage */ -+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ -+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/** @addtogroup I2C_Private_Functions -+ * @{ -+ */ -+/* Private functions to handle DMA transfer */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); -+static void I2C_DMAError(DMA_HandleTypeDef *hdma); -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); -+ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); -+ -+/* Private functions for I2C transfer IRQ handler */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions -+ * @brief Initialization and Configuration functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Initialization and de-initialization functions ##### -+ =============================================================================== -+ [..] This subsection provides a set of functions allowing to initialize and -+ de-initialize the I2Cx peripheral: -+ -+ (+) User must Implement HAL_I2C_MspInit() function in which he configures -+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). -+ -+ (+) Call the function HAL_I2C_Init() to configure the selected device with -+ the selected configuration: -+ (++) Communication Speed -+ (++) Duty cycle -+ (++) Addressing mode -+ (++) Own Address 1 -+ (++) Dual Addressing mode -+ (++) Own Address 2 -+ (++) General call mode -+ (++) Nostretch mode -+ -+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration -+ of the selected I2Cx peripheral. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Initializes the I2C according to the specified parameters -+ * in the I2C_InitTypeDef and create the associated handle. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t freqrange = 0U; -+ uint32_t pclk1 = 0U; -+ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); -+ assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); -+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); -+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); -+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); -+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); -+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); -+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); -+ -+ if(hi2c->State == HAL_I2C_STATE_RESET) -+ { -+ /* Allocate lock resource and initialize it */ -+ hi2c->Lock = HAL_UNLOCKED; -+ /* Init the low level hardware : GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspInit(hi2c); -+ } -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get PCLK1 frequency */ -+ pclk1 = HAL_RCC_GetPCLK1Freq(); -+ -+ /* Calculate frequency range */ -+ freqrange = I2C_FREQRANGE(pclk1); -+ -+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/ -+ /* Configure I2Cx: Frequency range */ -+ hi2c->Instance->CR2 = freqrange; -+ -+ /*---------------------------- I2Cx TRISE Configuration --------------------*/ -+ /* Configure I2Cx: Rise Time */ -+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); -+ -+ /*---------------------------- I2Cx CCR Configuration ----------------------*/ -+ /* Configure I2Cx: Speed */ -+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); -+ -+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/ -+ /* Configure I2Cx: Generalcall and NoStretch mode */ -+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); -+ -+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ -+ /* Configure I2Cx: Own Address1 and addressing mode */ -+ hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); -+ -+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ -+ /* Configure I2Cx: Dual mode and Own Address2 */ -+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); -+ -+ /* Enable the selected I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DeInitializes the I2C peripheral. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the I2C Peripheral Clock */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspDeInit(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_RESET; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Release Lock */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C MSP Init. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C MSP DeInit -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspDeInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions -+ * @brief Data transfers functions -+ * -+@verbatim -+ =============================================================================== -+ ##### IO operation functions ##### -+ =============================================================================== -+ [..] -+ This subsection provides a set of functions allowing to manage the I2C data -+ transfers. -+ -+ (#) There are two modes of transfer: -+ (++) Blocking mode : The communication is performed in the polling mode. -+ The status of all data processing is returned by the same function -+ after finishing transfer. -+ (++) No-Blocking mode : The communication is performed using Interrupts -+ or DMA. These functions return the status of the transfer startup. -+ The end of the data processing will be indicated through the -+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when -+ using DMA mode. -+ -+ (#) Blocking mode functions are : -+ (++) HAL_I2C_Master_Transmit() -+ (++) HAL_I2C_Master_Receive() -+ (++) HAL_I2C_Slave_Transmit() -+ (++) HAL_I2C_Slave_Receive() -+ (++) HAL_I2C_Mem_Write() -+ (++) HAL_I2C_Mem_Read() -+ (++) HAL_I2C_IsDeviceReady() -+ -+ (#) No-Blocking mode functions with Interrupt are : -+ (++) HAL_I2C_Master_Transmit_IT() -+ (++) HAL_I2C_Master_Receive_IT() -+ (++) HAL_I2C_Slave_Transmit_IT() -+ (++) HAL_I2C_Slave_Receive_IT() -+ (++) HAL_I2C_Master_Sequential_Transmit_IT() -+ (++) HAL_I2C_Master_Sequential_Receive_IT() -+ (++) HAL_I2C_Slave_Sequential_Transmit_IT() -+ (++) HAL_I2C_Slave_Sequential_Receive_IT() -+ (++) HAL_I2C_Mem_Write_IT() -+ (++) HAL_I2C_Mem_Read_IT() -+ -+ (#) No-Blocking mode functions with DMA are : -+ (++) HAL_I2C_Master_Transmit_DMA() -+ (++) HAL_I2C_Master_Receive_DMA() -+ (++) HAL_I2C_Slave_Transmit_DMA() -+ (++) HAL_I2C_Slave_Receive_DMA() -+ (++) HAL_I2C_Mem_Write_DMA() -+ (++) HAL_I2C_Mem_Read_DMA() -+ -+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: -+ (++) HAL_I2C_MemTxCpltCallback() -+ (++) HAL_I2C_MemRxCpltCallback() -+ (++) HAL_I2C_MasterTxCpltCallback() -+ (++) HAL_I2C_MasterRxCpltCallback() -+ (++) HAL_I2C_SlaveTxCpltCallback() -+ (++) HAL_I2C_SlaveRxCpltCallback() -+ (++) HAL_I2C_ErrorCallback() -+ (++) HAL_I2C_AbortCpltCallback() -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Transmits in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receives in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize == 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmits in slave mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* If 10bit addressing mode is selected */ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) -+ { -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ } -+ -+ /* Wait until AF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in blocking mode -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until STOP flag is set */ -+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear STOP flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t Prev_State = 0x00U; -+ __IO uint32_t count = 0x00U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ Prev_State = hi2c->PreviousState; -+ -+ /* Generate Start */ -+ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Enable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Disable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of tmp to prevent undefined behavior of volatile usage */ -+ uint32_t tmp; -+ -+ /* Disable Address listen mode only if a transfer is not ongoing */ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; -+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Abort a master I2C process communication with Interrupt. -+ * @note This abort can be called only if state is ready -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(DevAddress); -+ -+ /* Abort Master transfer during Receive or Transmit process */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_ABORT; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Wrong usage of abort function */ -+ /* This function should be used only in case of abort monitored by master device */ -+ return HAL_ERROR; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+/** -+ * @brief Write an amount of data in blocking mode to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in blocking mode from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize== 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be read -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ uint32_t tickstart = 0x00U; -+ __IO uint32_t count = 0U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(Size == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Checks if target device is ready for communication. -+ * @note This function is used with Memory devices -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param Trials Number of trials -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; -+ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ do -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR or AF flag are set */ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) -+ { -+ hi2c->State = HAL_I2C_STATE_TIMEOUT; -+ } -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Check if the ADDR flag has been set */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear ADDR Flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ }while(I2C_Trials++ < Trials); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief This function handles I2C event interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ /* Master or Memory mode selected */ -+ if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* SB Set ----------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_SB(hi2c); -+ } -+ /* ADD10 Set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADD10(hi2c); -+ } -+ /* ADDR Set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADDR(hi2c); -+ } -+ -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterReceive_BTF(hi2c); -+ } -+ } -+ } -+ /* Slave mode selected */ -+ else -+ { -+ /* ADDR set --------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_ADDR(hi2c); -+ } -+ /* STOPF set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_STOPF(hi2c); -+ } -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ else if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset ----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveReceive_BTF(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief This function handles I2C error interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ /* I2C Bus error interrupt occurred ----------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; -+ -+ /* Clear BERR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); -+ } -+ -+ /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; -+ -+ /* Clear ARLO flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); -+ } -+ -+ /* I2C Acknowledge failure error interrupt occurred ------------------------*/ -+ if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ tmp1 = hi2c->Mode; -+ tmp2 = hi2c->XferCount; -+ tmp3 = hi2c->State; -+ tmp4 = hi2c->PreviousState; -+ if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ -+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ -+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) -+ { -+ I2C_Slave_AF(hi2c); -+ } -+ else -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ -+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Generate Stop */ -+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ } -+ -+ /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; -+ /* Clear OVR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); -+ } -+ -+ /* Call the Error Callback in case of Error detected -----------------------*/ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ I2C_ITError(hi2c); -+ } -+} -+ -+/** -+ * @brief Master Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Master Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** @brief Slave Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Address Match callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition -+ * @param AddrMatchCode Address Match Code -+ * @retval None -+ */ -+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ UNUSED(TransferDirection); -+ UNUSED(AddrMatchCode); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AddrCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Listen Complete callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ListenCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C error callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ErrorCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C abort callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AbortCpltCallback could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions -+ * @brief Peripheral State and Errors functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Peripheral State, Mode and Error functions ##### -+ =============================================================================== -+ [..] -+ This subsection permits to get in run-time the status of the peripheral -+ and the data flow. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Return the I2C handle state. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL state -+ */ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -+{ -+ /* Return I2C handle state */ -+ return hi2c->State; -+} -+ -+/** -+ * @brief Return the I2C Master, Slave, Memory or no mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL mode -+ */ -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->Mode; -+} -+ -+/** -+ * @brief Return the I2C error code -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval I2C Error Code -+ */ -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->ErrorCode; -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @brief Handle TXE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ -+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ else -+ { -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0) -+ { -+ /* If Memory address size is 8Bit */ -+ if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount += 2; -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ } -+ else if(hi2c->EventCount == 1) -+ { -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ else if(hi2c->EventCount == 2) -+ { -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ else -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ else -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ uint32_t tmp = 0U; -+ -+ tmp = hi2c->XferCount; -+ if(tmp > 3U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if(hi2c->XferCount == 3) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 4 bytes -+ on BTF subroutine */ -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ } -+ else if((tmp == 1U) || (tmp == 0U)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->XferCount == 4U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 3U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ /* Prepare next transfer or stop current transfer */ -+ if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ else -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle SB flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave 7 Bits address */ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); -+ } -+ else if(hi2c->EventCount == 1U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD10 flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) -+{ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADDR flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ uint32_t Prev_State = hi2c->PreviousState; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ hi2c->EventCount++; -+ } -+ else -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferCount == 1U) -+ { -+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ /* Prepare next transfer or stop current transfer */ -+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ -+ && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ /* Reset Event counter */ -+ hi2c->EventCount = 0U; -+ } -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle TXE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Tx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Rx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; -+ uint16_t SlaveAddrCode = 0U; -+ -+ /* Transfer Direction requested by Master */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) -+ { -+ TransferDirection = I2C_DIRECTION_TRANSMIT; -+ } -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress1; -+ } -+ else -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress2; -+ } -+ -+ /* Call Slave Addr callback */ -+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle STOPF flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear STOPF flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* If a DMA is ongoing, Update handle size context */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); -+ } -+ else -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); -+ } -+ } -+ -+ /* All data are not transferred, so set error code accordingly */ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Set ErrorCode corresponding to a Non-Acknowledge */ -+ //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ } -+ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ } -+ else -+ { -+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ -+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else -+ { -+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ -+ (CurrentState == HAL_I2C_STATE_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else if(CurrentState == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Clear AF flag only */ -+ /* State Listen, but XferOptions == FIRST or NEXT */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C interrupts error process -+ * @param hi2c I2C handle. -+ * @retval None -+ */ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* keep HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ } -+ else -+ { -+ /* If state is an abort treatment on going, don't change state */ -+ /* This change will be do later */ -+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ } -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ } -+ -+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ /* Abort DMA transfer */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) -+ { -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly XferAbortCallback function in case of error */ -+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); -+ } -+ } -+ else -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ -+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); -+ } -+ } -+ } -+ else if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Call user error callback */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ /* STOP Flag is not set after a NACK reception */ -+ /* So may inform upper layer that listen phase is stopped */ -+ /* during NACK error treatment */ -+ if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for write request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DMA I2C process complete callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) -+ { -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Disable Last DMA */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_LAST; -+ -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Check if Errors has been detected during transfer */ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief DMA I2C communication error callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAError(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Ignore DMA FIFO error */ -+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; -+ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief DMA I2C communication abort callback -+ * (To be called at end of DMA Abort procedure). -+ * @param hdma DMA handle. -+ * @retval None -+ */ -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Reset XferAbortCallback */ -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Check if come from abort from user */ -+ if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Status The new Flag status (SET or RESET). -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Wait until flag is set */ -+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) -+ { -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for Master addressing phase. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) -+ { -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) -+ { -+ /* Check if a STOPF is detected */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) -+ { -+ /* Clear STOP Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles Acknowledge failed detection during an I2C Communication. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) -+{ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Clear NACKF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ return HAL_OK; -+} -+/** -+ * @} -+ */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -new file mode 100644 -index 0000000..de8f160 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -@@ -0,0 +1,204 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.c -+ * @author MCD Application Team -+ * @brief I2C Extension HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of I2C extension peripheral: -+ * + Extension features functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### I2C peripheral extension features ##### -+ ============================================================================== -+ -+ [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ -+ 429xx/439xx devices contains the following additional features : -+ -+ (+) Possibility to disable or enable Analog Noise Filter -+ (+) Use of a configured Digital Noise Filter -+ -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] This driver provides functions to configure Noise Filter -+ (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() -+ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2CEx I2CEx -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+ -+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions -+ * @brief Extension features functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Extension features functions ##### -+ =============================================================================== -+ [..] This section provides functions allowing to: -+ (+) Configure Noise Filters -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Configures I2C Analog noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param AnalogFilter new state of the Analog filter. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Reset I2Cx ANOFF bit */ -+ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); -+ -+ /* Disable the analog filter */ -+ hi2c->Instance->FLTR |= AnalogFilter; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Configures I2C Digital noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -+{ -+ uint16_t tmpreg = 0; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get the old register value */ -+ tmpreg = hi2c->Instance->FLTR; -+ -+ /* Reset I2Cx DNF bit [3:0] */ -+ tmpreg &= ~(I2C_FLTR_DNF); -+ -+ /* Set I2Cx DNF coefficient */ -+ tmpreg |= DigitalFilter; -+ -+ /* Store the new register value */ -+ hi2c->Instance->FLTR = tmpreg; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ -+ STM32F423xx */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/i2c.h b/Firmware/Board/v3/Inc/i2c.h -new file mode 100644 -index 0000000..f449b88 ---- /dev/null -+++ b/Firmware/Board/v3/Inc/i2c.h -@@ -0,0 +1,91 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.h -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __i2c_H -+#define __i2c_H -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+#include "main.h" -+ -+/* USER CODE BEGIN Includes */ -+ -+/* USER CODE END Includes */ -+ -+extern I2C_HandleTypeDef hi2c1; -+ -+/* USER CODE BEGIN Private defines */ -+ -+/* USER CODE END Private defines */ -+ -+extern void _Error_Handler(char *, int); -+ -+void MX_I2C1_Init(uint8_t addr); -+ -+/* USER CODE BEGIN Prototypes */ -+ -+/* USER CODE END Prototypes */ -+ -+#ifdef __cplusplus -+} -+#endif -+#endif /*__ i2c_H */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -index d0f48f5..b3ef59a 100644 ---- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -+++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -@@ -65,7 +65,7 @@ - /* #define HAL_SRAM_MODULE_ENABLED */ - /* #define HAL_SDRAM_MODULE_ENABLED */ - /* #define HAL_HASH_MODULE_ENABLED */ --/* #define HAL_I2C_MODULE_ENABLED */ -+#define HAL_I2C_MODULE_ENABLED - /* #define HAL_I2S_MODULE_ENABLED */ - /* #define HAL_IWDG_MODULE_ENABLED */ - /* #define HAL_LTDC_MODULE_ENABLED */ -diff --git a/Firmware/Board/v3/Src/i2c.c b/Firmware/Board/v3/Src/i2c.c -new file mode 100644 -index 0000000..bae77f1 ---- /dev/null -+++ b/Firmware/Board/v3/Src/i2c.c -@@ -0,0 +1,198 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.c -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "i2c.h" -+ -+#include "gpio.h" -+#include "dma.h" -+ -+/* USER CODE BEGIN 0 */ -+ -+/* USER CODE END 0 */ -+ -+I2C_HandleTypeDef hi2c1; -+DMA_HandleTypeDef hdma_i2c1_rx; -+DMA_HandleTypeDef hdma_i2c1_tx; -+ -+/* I2C1 init function */ -+void MX_I2C1_Init(uint8_t addr) -+{ -+ -+ hi2c1.Instance = I2C1; -+ hi2c1.Init.ClockSpeed = 100000; -+ hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; -+ hi2c1.Init.OwnAddress1 = addr << 1; -+ hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; -+ hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; -+ hi2c1.Init.OwnAddress2 = 0; -+ hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; -+ hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; -+ if (HAL_I2C_Init(&hi2c1) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+} -+ -+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ GPIO_InitTypeDef GPIO_InitStruct; -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspInit 0 */ -+ -+ /* USER CODE END I2C1_MspInit 0 */ -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; -+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; -+ GPIO_InitStruct.Pull = GPIO_PULLUP; -+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; -+ GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; -+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); -+ -+ /* I2C1 clock enable */ -+ __HAL_RCC_I2C1_CLK_ENABLE(); -+ -+ /* I2C1 DMA Init */ -+ /* I2C1_RX Init */ -+ hdma_i2c1_rx.Instance = DMA1_Stream0; -+ hdma_i2c1_rx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; -+ hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.Mode = DMA_CIRCULAR; -+ hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c1_rx); -+ -+ /* I2C1_TX Init */ -+ hdma_i2c1_tx.Instance = DMA1_Stream6; -+ hdma_i2c1_tx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; -+ hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.Mode = DMA_NORMAL; -+ hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c1_tx); -+ -+ /* I2C1 interrupt Init */ -+ HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspInit 1 */ -+ -+ /* USER CODE END I2C1_MspInit 1 */ -+ } -+} -+ -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspDeInit 0 */ -+ -+ /* USER CODE END I2C1_MspDeInit 0 */ -+ /* Peripheral clock disable */ -+ __HAL_RCC_I2C1_CLK_DISABLE(); -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); -+ -+ /* I2C1 DMA DeInit */ -+ HAL_DMA_DeInit(i2cHandle->hdmarx); -+ HAL_DMA_DeInit(i2cHandle->hdmatx); -+ -+ /* I2C1 interrupt Deinit */ -+ HAL_NVIC_DisableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_DisableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspDeInit 1 */ -+ -+ /* USER CODE END I2C1_MspDeInit 1 */ -+ } -+} -+ -+/* USER CODE BEGIN 1 */ -+ -+/* USER CODE END 1 */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c -index 987e0bd..efaeef1 100644 ---- a/Firmware/Board/v3/Src/main.c -+++ b/Firmware/Board/v3/Src/main.c -@@ -187,7 +187,6 @@ int main(void) - MX_ADC3_Init(); - MX_TIM2_Init(); - MX_UART4_Init(); -- MX_CAN1_Init(); - /* USER CODE BEGIN 2 */ - - //Required to use OC4 for ADC triggering. --- -2.17.0 - diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 00000000..5452a507 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +}I2C_InitTypeDef; + +/** + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +}HAL_I2C_StateTypeDef; + +/** + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +}HAL_I2C_ModeTypeDef; + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + +}I2C_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_Error_Code I2C Error Code + * @brief I2C Error Code + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_SMBALERT 0x00018000U +#define I2C_FLAG_TIMEOUT 0x00014000U +#define I2C_FLAG_PECERR 0x00011000U +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_SMBHOST 0x00100040U +#define I2C_FLAG_SMBDEFAULT 0x00100020U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_SMBHOST: SMBus host header + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ + ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) + +/** @brief Disable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions *****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State, Mode and Errors functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 00000000..ff47d5cc --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,137 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ + STM32F413xx || STM32F423xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 00000000..da185200 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,5494 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx Stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup I2C_Private_Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and create the associated handle. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange = 0U; + uint32_t pclk1 = 0U; + + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->CR2 = freqrange; + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2C peripheral. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief I2C MSP Init. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2C MSP DeInit + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Master_Sequential_Transmit_IT() + (++) HAL_I2C_Master_Sequential_Receive_IT() + (++) HAL_I2C_Slave_Sequential_Transmit_IT() + (++) HAL_I2C_Slave_Sequential_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* Generate Start */ + if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize== 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if(hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0x00U; + __IO uint32_t count = 0U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(Size == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; + + /* Get tick */ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + }while(I2C_Trials++ < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + uint32_t CurrentMode = hi2c->Mode; + + /* Master or Memory mode selected */ + if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* SB Set ----------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + + /* I2C in mode Transmitter -----------------------------------------------*/ + if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + } + } + /* Slave mode selected */ + else + { + /* ADDR set --------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_ADDR(hi2c); + } + /* STOPF set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ + if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + tmp1 = hi2c->Mode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback can be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback can be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Return the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if(hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0) + { + /* If Memory address size is 8Bit */ + if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if(hi2c->EventCount == 1) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if(hi2c->EventCount == 2) + { + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp = 0U; + + tmp = hi2c->XferCount; + if(tmp > 3U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if(hi2c->XferCount == 3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if((tmp == 1U) || (tmp == 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + else + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if(hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + return HAL_OK; +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; + } + else + { + if(hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferCount == 1U) + { + if(CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + /* Prepare next transfer or stop current transfer */ + else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + else if(hi2c->XferCount == 2U) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + return HAL_OK; +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Tx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode = 0U; + + /* Transfer Direction requested by Master */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = hi2c->Init.OwnAddress2; + } + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); + + return HAL_OK; +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* If a DMA is ongoing, Update handle size context */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + else + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ + (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else + { + if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else if(CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + + return HAL_OK; +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) + { + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + /* Abort DMA transfer */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Call user error callback */ + HAL_I2C_ErrorCallback(hi2c); + } + /* STOP Flag is not set after a NACK reception */ + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Disable Last DMA */ + hi2c->Instance->CR2 &= ~I2C_CR2_LAST; + + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Ignore DMA FIFO error */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 00000000..de8f1602 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,204 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ + STM32F423xx */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h index e518489f..ed26bf39 100644 --- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h +++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c index e390af58..154c98af 100644 --- a/Firmware/Board/v3/Src/main.c +++ b/Firmware/Board/v3/Src/main.c @@ -180,7 +180,7 @@ int main(void) MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); - MX_CAN1_Init(); + // MX_CAN1_Init(); // CAN or I2C called in main.cpp instead MX_TIM1_Init(); MX_TIM8_Init(); MX_TIM3_Init(); From 2e78432fed97837563a436c216ba07cc0788dd6b Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:08:08 -0700 Subject: [PATCH 051/106] Cube: Notify OS that we are a composite device --- Firmware/Board/v3/Src/usbd_desc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index b0906144..d213f64a 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -97,7 +97,8 @@ #define USBD_PID_FS 0x0D32 #define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) #define USBD_PRODUCT_STR(s) #s -#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR +#define USBD_PRODUCT_STRING_FS ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR CDC Interface +#define NATIVE_STRING ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR Native Interface #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -233,16 +234,17 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = 0x00, /*bcdUSB */ #endif /* (USBD_LPM_ENABLED == 1) */ 0x02, - 0x02, /*bDeviceClass*/ + // Notify OS that this is a composite device + 0xEF, /*bDeviceClass*/ 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ + 0x01, /*bDeviceProtocol*/ USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ LOBYTE(USBD_VID), /*idVendor*/ HIBYTE(USBD_VID), /*idVendor*/ LOBYTE(USBD_PID_FS), /*idProduct*/ HIBYTE(USBD_PID_FS), /*idProduct*/ 0x00, /*bcdDevice rel. 2.00*/ - 0x02, + 0x03, /* bNumInterfaces */ USBD_IDX_MFC_STR, /*Index of manufacturer string*/ USBD_IDX_PRODUCT_STR, /*Index of product string*/ USBD_IDX_SERIAL_STR, /*Index of serial number string*/ From 484654fc7db3bce24c74601a4484dd8fb20aadde Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:51:04 -0700 Subject: [PATCH 052/106] cube: apply canges to USB --- Firmware/Board/v3/Inc/usbd_cdc_if.h | 2 +- Firmware/Board/v3/Inc/usbd_conf.h | 1 + Firmware/Board/v3/Inc/usbd_desc.h | 3 +- .../Class/CDC/Inc/usbd_cdc.h | 39 +- .../Class/CDC/Src/usbd_cdc.c | 562 +++++++++++------- .../Core/Inc/usbd_def.h | 4 +- Firmware/Board/v3/Src/usbd_cdc_if.c | 12 +- Firmware/Board/v3/Src/usbd_conf.c | 24 +- 8 files changed, 404 insertions(+), 243 deletions(-) diff --git a/Firmware/Board/v3/Inc/usbd_cdc_if.h b/Firmware/Board/v3/Inc/usbd_cdc_if.h index c15e8b91..ed1d6705 100644 --- a/Firmware/Board/v3/Inc/usbd_cdc_if.h +++ b/Firmware/Board/v3/Inc/usbd_cdc_if.h @@ -132,7 +132,7 @@ extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; * @{ */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair); /* USER CODE BEGIN EXPORTED_FUNCTIONS */ /* USER CODE END EXPORTED_FUNCTIONS */ diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index bf276186..a897ba43 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -89,6 +89,7 @@ * @brief Defines for configuration of the Usb device. * @{ */ + #define MS_VendorCode 'P' /*---------- -----------*/ #define USBD_MAX_NUM_INTERFACES 1 diff --git a/Firmware/Board/v3/Inc/usbd_desc.h b/Firmware/Board/v3/Inc/usbd_desc.h index 18d1f34e..2a74de31 100644 --- a/Firmware/Board/v3/Inc/usbd_desc.h +++ b/Firmware/Board/v3/Inc/usbd_desc.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.h * @version : v1.0_Cube - * @brief : Header for usbd_conf.c file. + * @brief : Header for usbd_desc.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -46,6 +46,7 @@ * ****************************************************************************** */ + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__H__ #define __USBD_DESC__H__ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index d937b2e8..c029e22a 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -52,13 +52,15 @@ #define CDC_IN_EP 0x81 /* EP1 for data IN */ #define CDC_OUT_EP 0x01 /* EP1 for data OUT */ #define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ +#define ODRIVE_IN_EP 0x83 /* EP3 IN: ODrive device TX endpoint */ +#define ODRIVE_OUT_EP 0x03 /* EP3 OUT: ODrive device RX endpoint */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ -#define USB_CDC_CONFIG_DESC_SIZ 67 +#define USB_CDC_CONFIG_DESC_SIZ (67 + 39) #define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE #define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE @@ -103,23 +105,29 @@ typedef struct _USBD_CDC_Itf int8_t (* Init) (void); int8_t (* DeInit) (void); int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); + int8_t (* Receive) (uint8_t *, uint32_t *, uint8_t); }USBD_CDC_ItfTypeDef; +typedef struct +{ + uint8_t* Buffer; + uint32_t Length; + volatile uint8_t State; +} +USBD_CDC_EP_HandleTypeDef; typedef struct { uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; + uint8_t CmdLength; + + USBD_CDC_EP_HandleTypeDef CDC_Tx; + USBD_CDC_EP_HandleTypeDef CDC_Rx; + + USBD_CDC_EP_HandleTypeDef ODRIVE_Tx; + USBD_CDC_EP_HandleTypeDef ODRIVE_Rx; } USBD_CDC_HandleTypeDef; @@ -151,14 +159,15 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length); + uint16_t length, + uint8_t endpoint_pair); uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); + uint8_t *pbuff, uint8_t endpoint_pair); -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 24465641..73313522 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -132,6 +132,9 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +//static uint8_t * USBD_GetUsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); + /* USB Standard Device Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { @@ -173,24 +176,37 @@ USBD_ClassTypeDef USBD_CDC = USBD_CDC_GetFSCfgDesc, USBD_CDC_GetOtherSpeedCfgDesc, USBD_CDC_GetDeviceQualifierDescriptor, + USBD_UsrStrDescriptor }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { /*Configuration Descriptor*/ 0x09, /* bLength: Configuration Descriptor size */ USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ + 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 custom) */ 0x01, /* bConfigurationValue: Configuration value */ 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ 0xC0, /* bmAttributes: self powered */ 0x32, /* MaxPower 0 mA */ + + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: CDC device (virtual com port) */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass: Communication Interface Class */ + 0x02, /* bFunctionSubClass: Abstract Control Model */ + 0x01, /* bFunctionProtocol: Common AT commands */ + 0x00, /* iFunction */ /*---------------------------------------------------------------------------*/ - + /*Interface Descriptor */ 0x09, /* bLength: Interface Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ @@ -202,7 +218,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bInterfaceSubClass: Abstract Control Model */ 0x01, /* bInterfaceProtocol: Common AT commands */ 0x00, /* iInterface: */ - + /*Header Functional Descriptor*/ 0x05, /* bLength: Endpoint Descriptor size */ 0x24, /* bDescriptorType: CS_INTERFACE */ @@ -229,7 +245,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x06, /* bDescriptorSubtype: Union func desc */ 0x00, /* bMasterInterface: Communication class interface */ 0x01, /* bSlaveInterface0: Data Class Interface */ - + /*Endpoint 2 Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ @@ -267,196 +283,52 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00, /* bInterval: ignore for Bulk transfer */ + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: custom device */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x02, /* bFirstInterface */ + 0x01, /* bInterfaceCount */ + 0x00, /* bFunctionClass: */ + 0x00, /* bFunctionSubClass: */ + 0x00, /* bFunctionProtocol: */ + 0x06, /* iFunction */ -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ /*---------------------------------------------------------------------------*/ /*Data class interface descriptor*/ 0x09, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ + 0x02, /* bInterfaceNumber: Number of Interface */ 0x00, /* bAlternateSetting: Alternate setting */ 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceClass: vendor specific */ + 0x01, /* bInterfaceSubClass: ODrive Communication */ 0x00, /* bInterfaceProtocol: */ 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ + ODRIVE_OUT_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ + ODRIVE_IN_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ } ; -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; /** * @} @@ -508,6 +380,19 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, USBD_EP_TYPE_BULK, CDC_DATA_FS_OUT_PACKET_SIZE); } + + /* Open ODrive IN endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_IN_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_IN_PACKET_SIZE : CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open ODrive OUT endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_OUT_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + /* Open Command IN EP */ USBD_LL_OpenEP(pdev, CDC_CMD_EP, @@ -529,15 +414,17 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; + hcdc->CDC_Tx.State =0; + hcdc->CDC_Rx.State =0; + hcdc->ODRIVE_Tx.State =0; + hcdc->ODRIVE_Rx.State =0; if(pdev->dev_speed == USBD_SPEED_HIGH ) { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_HS_OUT_PACKET_SIZE); } else @@ -545,11 +432,15 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_FS_OUT_PACKET_SIZE); } - + /* Prepare ODrive Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + ODRIVE_OUT_EP, + hcdc->ODRIVE_Rx.Buffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } return ret; } @@ -566,17 +457,25 @@ static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, { uint8_t ret = 0; - /* Open EP IN */ + /* Close EP IN */ USBD_LL_CloseEP(pdev, CDC_IN_EP); - /* Open EP OUT */ + /* Close EP OUT */ USBD_LL_CloseEP(pdev, CDC_OUT_EP); - /* Open Command IN EP */ + /* Close Command IN EP */ USBD_LL_CloseEP(pdev, CDC_CMD_EP); + + /* Close EP IN */ + USBD_LL_CloseEP(pdev, + ODRIVE_IN_EP); + + /* Close EP OUT */ + USBD_LL_CloseEP(pdev, + ODRIVE_OUT_EP); /* DeInit physical Interface components */ @@ -648,6 +547,9 @@ static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, case USB_REQ_SET_INTERFACE : break; } + + case USB_REQ_TYPE_VENDOR: + return USBD_WinUSBComm_SetupVendor(pdev, req); default: break; @@ -668,8 +570,12 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) if(pdev->pClassData != NULL) { - - hcdc->TxState = 0; + // NOTE: We would logically expect xx_IN_EP here, but we actually get the xx_OUT_EP + if (epnum == CDC_OUT_EP) + hcdc->CDC_Tx.State = 0; + if (epnum == ODRIVE_OUT_EP) + hcdc->ODRIVE_Tx.State = 0; + //Note: We could use independent semaphores for simoultainous USB transmission. osSemaphoreRelease(sem_usb_tx); return USBD_OK; } @@ -689,15 +595,24 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (epnum == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (epnum == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + hEP_Rx->Length = USBD_LL_GetRxDataSize (pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ if(pdev->pClassData != NULL) { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hEP_Rx->Buffer, &hEP_Rx->Length, epnum); return USBD_OK; } @@ -740,8 +655,8 @@ static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) */ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -753,8 +668,8 @@ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -766,8 +681,8 @@ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -810,12 +725,22 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, */ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length) + uint16_t length, + uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + } else { + return USBD_FAIL; + } + + hEP_Tx->Buffer = pbuff; + hEP_Tx->Length = length; return USBD_OK; } @@ -828,11 +753,20 @@ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, * @retval status */ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) + uint8_t *pbuff, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } - hcdc->RxBuffer = pbuff; + hEP_Rx->Buffer = pbuff; return USBD_OK; } @@ -844,23 +778,36 @@ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, * @param epnum: endpoint number * @retval status */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; if(pdev->pClassData != NULL) { - if(hcdc->TxState == 0) + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + uint8_t in_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + in_ep = CDC_IN_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + in_ep = ODRIVE_IN_EP; + } else { + return USBD_FAIL; + } + + if(hEP_Tx->State == 0) { /* Tx Transfer in progress */ - hcdc->TxState = 1; + hEP_Tx->State = 1; /* Transmit next packet */ USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - + in_ep, + hEP_Tx->Buffer, + hEP_Tx->Length); + return USBD_OK; } else @@ -881,29 +828,32 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; /* Suspend or Resume USB Out process */ if(pdev->pClassData != NULL) { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + uint8_t out_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + out_ep = CDC_OUT_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + out_ep = ODRIVE_OUT_EP; + } else { + return USBD_FAIL; } + + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + out_ep, + hEP_Rx->Buffer, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + return USBD_OK; } else @@ -911,6 +861,184 @@ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) return USBD_FAIL; } } + + +/* WinUSB support ------------------------------------------------------------*/ +/* +* This section tells Windows that it should automatically load the WinUSB driver +* for the device (more specifically, interface 2 because it's a composite device). +* This allows for driverless communication with the device. +*/ + +#define NUM_INTERFACES 1 + +#if NUM_INTERFACES == 2 +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24 + 24) +#else +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24) +#endif + + +// This associates winusb driver with the device +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Compat_ID_OS_Desc[USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ] __ALIGN_END = +{ + // +-- Offset in descriptor + // | +-- Size + // v v + USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ, 0, 0, 0, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended compat ID descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x04, 0x00, // 6 wIndex 2 WORD An index that identifies the particular OS feature descriptor + NUM_INTERFACES, // 8 bCount 1 BYTE The number of custom property sections + 0, 0, 0, 0, 0, 0, 0, // 9 RESERVED 7 BYTEs Reserved + // ===================== + // 16 + + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#if NUM_INTERFACES == 2 + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#endif +}; + + +// Properties are added to: +// HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Enum\USB\VID_xxxx&PID_xxxx\sssssssss\Device Parameters +// Use USBDeview or similar to uninstall + +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Properties_OS_Desc[0xB6] __ALIGN_END = +{ + 0xB6, 0x00, 0x00, 0x00, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended properties descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x05, 0x00, // 6 wIndex 2 WORD The index for extended properties OS descriptors + 0x02, 0x00, // 8 wCount 2 WORD The number of custom property sections that follow the header section + // ==================== + // 10 +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, // 0 dwSize 4 DWORD The size of this custom properties section + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 4 DWORD Property data format + 0x28, 0x00, // 8 wPropertyNameLength 2 DWORD Property name length + // ======================================== + // 10 + // 10 bPropertyName PNL WCHAR[] The property name + 'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0, + 't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0, + 'U',0, 'I',0, 'D',0, 0,0, + // ======================================== + // 40 (0x28) + + 0x4E, 0x00, 0x00, 0x00, // 10 + PNL dwPropertyDataLength 4 DWORD Length of the buffer holding the property data + // ======================================== + // 4 + // 14 + PNL bPropertyData PDL Format-dependent Property data + '{',0, 'E',0, 'A',0, '0',0, 'B',0, 'D',0, '5',0, 'C',0, + '3',0, '-',0, '5',0, '0',0, 'F',0, '3',0, '-',0, '4',0, + '8',0, '8',0, '8',0, '-',0, '8',0, '4',0, 'B',0, '4',0, + '-',0, '7',0, '4',0, 'E',0, '5',0, '0',0, 'E',0, '1',0, + '6',0, '4',0, '9',0, 'D',0, 'B',0, '}',0, 0 ,0, + // ======================================== + // 78 (0x4E) +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x3E, 0x00, 0x00, 0x00, // 0 dwSize 0x00000030 (62 bytes) + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 0x00000001 (Unicode string) + 0x0C, 0x00, // 8 wPropertyNameLength 0x000C (12 bytes) + // ======================================== + // 10 + 'L',0, 'a',0, 'b',0, 'e',0, 'l',0, 0,0, + // 10 bPropertyName “Label” + // ======================================== + // 12 + 0x24, 0x00, 0x00, 0x00, // 22 dwPropertyDataLength 0x00000016 (36 bytes) + // ======================================== + // 4 + 'O',0, 'D',0, 'r',0, 'i',0, 'v',0, 'e',0, 0,0 + // 26 bPropertyData “ODrive” + // ======================================== + // 14 + +}; + + + +static uint8_t USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (req->wIndex) + { + case 0x04: + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Compat_ID_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + uint8_t byInterfaceIndex = (uint8_t)req->wValue; + if ( req->wIndex != 0x05 ) + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + switch ( byInterfaceIndex ) + { + case 0: +#if NUM_INTERFACES == 2 + case 1: +#endif + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Properties_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_SetupVendorDevice(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendorInterface(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + // TODO: check if this is important + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch ( req->bmRequest & USB_REQ_RECIPIENT_MASK ) + { + case USB_REQ_RECIPIENT_DEVICE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorDevice(pdev, req); + case USB_REQ_RECIPIENT_INTERFACE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorInterface(pdev, req); + case USB_REQ_RECIPIENT_ENDPOINT: + // fall through + default: + break; + } + USBD_CtlError(pdev , req); + return USBD_FAIL; +} + /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index 8fbe81e4..f259b51d 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -68,7 +68,9 @@ #define USBD_IDX_PRODUCT_STR 0x02 #define USBD_IDX_SERIAL_STR 0x03 #define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_ODRIVE_INTF_STR 0x06 +#define USBD_IDX_MICROSOFT_DESC_STR 0xEE #define USB_REQ_TYPE_STANDARD 0x00 #define USB_REQ_TYPE_CLASS 0x20 diff --git a/Firmware/Board/v3/Src/usbd_cdc_if.c b/Firmware/Board/v3/Src/usbd_cdc_if.c index fcc712a3..b8cb6e6c 100644 --- a/Firmware/Board/v3/Src/usbd_cdc_if.c +++ b/Firmware/Board/v3/Src/usbd_cdc_if.c @@ -117,10 +117,12 @@ /* Create buffer for reception and transmission */ /* It's up to user to redefine and/or remove those define */ /** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t CDCRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t ODRIVERxBufferFS[APP_RX_DATA_SIZE]; /** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t CDCTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t ODRIVETxBufferFS[APP_TX_DATA_SIZE]; /* USER CODE BEGIN PRIVATE_VARIABLES */ /* USER CODE END PRIVATE_VARIABLES */ @@ -151,7 +153,7 @@ extern USBD_HandleTypeDef hUsbDeviceFS; static int8_t CDC_Init_FS(void); static int8_t CDC_DeInit_FS(void); static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len, uint8_t endpoint_pair); /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ @@ -289,7 +291,7 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair) { /* USER CODE BEGIN 6 */ usb_rx_process_packet(Buf, *Len, endpoint_pair); @@ -309,7 +311,7 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair) { uint8_t result = USBD_OK; /* USER CODE BEGIN 7 */ diff --git a/Firmware/Board/v3/Src/usbd_conf.c b/Firmware/Board/v3/Src/usbd_conf.c index 7046dc96..2d66d4a1 100644 --- a/Firmware/Board/v3/Src/usbd_conf.c +++ b/Firmware/Board/v3/Src/usbd_conf.c @@ -66,7 +66,7 @@ /* USER CODE END PV */ - PCD_HandleTypeDef hpcd_USB_OTG_FS; +PCD_HandleTypeDef hpcd_USB_OTG_FS; void _Error_Handler(char * file, int line); /* External functions --------------------------------------------------------*/ @@ -154,6 +154,23 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) */ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { + USBD_StatusTypeDef ret = USBD_OK; + USBD_HandleTypeDef *pdev = hpcd->pData; + USBD_SetupReqTypedef *req = &pdev->request; + USBD_ParseSetupRequest(req, (uint8_t *)hpcd->Setup); + if ( ( USB_REQ_TYPE_VENDOR == (req->bmRequest & USB_REQ_TYPE_MASK) ) && ( MS_VendorCode == req->bRequest ) ) + { + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + ret = pdev->pClass->Setup(pdev, req); + + if( (req->wLength == 0) && (ret == USBD_OK) ) + { + USBD_CtlSendStatus(pdev); + } + return; + } USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); } @@ -312,7 +329,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) pdev->pData = &hpcd_USB_OTG_FS; hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; @@ -329,7 +346,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // CDC IN endpoint + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // ODrive IN endpoint } return USBD_OK; } From 631b563bb432ab71d57c2aad12e9db2929352208 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:52:53 -0700 Subject: [PATCH 053/106] cube: can auto wake up --- Firmware/Board/v3/Src/can.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index 2171691a..fc7bf388 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -70,7 +70,7 @@ void MX_CAN1_Init(void) hcan1.Init.TimeSeg2 = CAN_BS2_5TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoWakeUp = ENABLE; hcan1.Init.AutoRetransmission = DISABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; From 26e98d5f336a9068b1f480d813a0bdba47ebe28a Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:25:50 -0700 Subject: [PATCH 054/106] move configAPPLICATION_ALLOCATED_HEAP to FreeRTOSconfig.h --- Firmware/Board/v3/Inc/FreeRTOSConfig.h | 1 + Firmware/Board/v3/Inc/main.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h | 1 - Firmware/Board/v3/Odrive.ioc | 2 +- 5 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Inc/FreeRTOSConfig.h b/Firmware/Board/v3/Inc/FreeRTOSConfig.h index 90e233b3..715b0e67 100644 --- a/Firmware/Board/v3/Inc/FreeRTOSConfig.h +++ b/Firmware/Board/v3/Inc/FreeRTOSConfig.h @@ -167,6 +167,7 @@ standard names. */ /* USER CODE BEGIN Defines */ /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +#define configAPPLICATION_ALLOCATED_HEAP 1 // ucHeap allocated in freertos.c /* USER CODE END Defines */ #endif /* FREERTOS_CONFIG_H */ diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 1e76830d..d41b19ee 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -72,7 +72,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h index 567fe028..65f45efd 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h index 5695d700..64daaa4f 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index c9bbdc7f..4d1ce2f2 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -211,7 +211,7 @@ Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 -Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 +Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx MxCube.Version=4.27.0 MxDb.Version=DB.4.0.270 From 69bac45db2fe8596d2ba2f0d289fb2daf5159668 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:32:54 -0700 Subject: [PATCH 055/106] cube: support user string --- Firmware/Board/v3/Inc/usbd_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index a897ba43..dbf800b3 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -98,7 +98,7 @@ /*---------- -----------*/ #define USBD_MAX_STR_DESC_SIZ 512 /*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 +#define USBD_SUPPORT_USER_STRING 1 /*---------- -----------*/ #define USBD_DEBUG_LEVEL 0 /*---------- -----------*/ From fcdb6b3bf10a0a3e24cca5d4a62d52d420d6c71a Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:49:16 -0700 Subject: [PATCH 056/106] update STM32CubeMX instructions to new rebasing style --- docs/developer-guide.md | 59 ++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/docs/developer-guide.md b/docs/developer-guide.md index 30a20543..d6243b5b 100644 --- a/docs/developer-guide.md +++ b/docs/developer-guide.md @@ -144,33 +144,54 @@ For working with the ODrive code you don't need an IDE, but the open-source IDE

## STM32CubeMX - This project uses the STM32CubeMX tool to generate startup code and to ease the configuration of the peripherals. You can download it from [here](http://www2.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-configurators-and-code-generators/stm32cubemx.html?icmp=stm32cubemx_pron_pr-stm32cubef2_apr2014&sc=stm32cube-pr2). All CubeMX related files are in `Firmware/Board/v3`. You will likely want the pinout for this process. It is available [here](https://docs.google.com/spreadsheets/d/1QXDCs1IRtUyG__M_9WruWOheywb-GhOwFtfPcHuN2Fg/edit#gid=404444347). -### Generate code +### Maintaining modified generated code +When generating the code, STM32CubeMX will nuke everything except some special sections that they provide. These sections are marked like `USER CODE BEGIN`...`USER CODE END`. +We used to try to make sure all edits we made to the generated code would only go in these sections, so some code structrure may reflect that. +However over time we realized this will not be tenable, so instead we use git to rebase all changes of the generated code whenever we need to regenerate it. +We use two special branches that will help us to do this, they are `STM32CubeMX-start` and `STM32CubeMX-end`. +How to use these is shown in the following example. + +**Note**: Due to how this rebasing is done, all development that changes the generated code should be done directly on `STM32CubeMX-end`, and not based on `devel`, then follow step 4 below to carry them over to your feature branch. If you did some changes to the generated code based from `devel`, you need to cherry pick just those changes over to `STM32CubeMX-end`. + +### 1. Ensuring a clean slate +* We do all changes to the STM32CubeMX config and regenerate the code on top of `STM32CubeMX-start`. + * `git checkout STM32CubeMX-start` * Run stm32cubeMX and load the `Firmware/Board/v3/Odrive.ioc` project file. -* Press `Project -> Generate code` + * If the tool asks if you wish to migrate to a new version, choose to migrate. +* Without changing any settings, press `Project -> Generate code`. * You may need to let it download some drivers and such. -* After generating/updating the code, some minor patches need to be applied. To do this, run: - `git apply Firmware/Board/v3/*.patch` -* Run `git config --local core.autocrlf input`. This will tell git that all files should be checked in with LF endings (CubeMX generates CRLF endings). -* `git status` will still claim that many files are modified but the actual diff (using `git diff`) is empty (apart from all the line ending warnings). +* STM32CubeMX may now have a newer version of some of the libraries, so there may be changes to the generated code even though we didn't change any settings. We need to check that everything is still working, and hence check in the changes: +* `git config --local core.autocrlf input` - This will tell git that all files should be checked in with LF endings (CubeMX generates CRLF endings). +* `git diff` - Ignore the pile of line ending warnings. +* If you feel qualified: you can now ispect if CubeMX introduced something stupid. If there were any changes, and they look acceptable, we should commit them: + * `git commit -am "Run STM32CubeMX v1.21"` - Replace with actual version of CubeMX -### Generating patchfiles -If you made changes to CubeMX generated files outside of the `USER CODE BEGIN`...`USER CODE END` sections and contribute them back, please add a patch file so that the next person who runs CubeMX doesn't run into problems. +### 2. Making changes to the STM32CubeMX config +* After completing the above steps, make sure the working directory is clean: + * `git status` should include "nothing to commit, working tree clean" +* Make your changes in STM32CubeMX, save the project and generate the code. (`Project -> Generate code`) +* `git diff` - Check that the introduced changes are as expected +* If everything looks ok, you can commit your changes. -CubeMX will reset everything outside these sections to the original state; we will capturing into a patch file the changes required to undo this resetting. -* Make sure your current desired state is committed. -* Make a new temporary branch: `git checkout -b cubemx_temp` -* Run the CubeMX code generation as described in the previous section, including applying previous patches. -* The diff will now _not_ be empty since CubeMX reset your changes. -* Stage this state and commit it with a message like "CubeMX reset my changes". -* Run `git revert HEAD` to undo the resetting action CubeMX's regeneration had. This is the commit which you will export, so write a meaningful commit message. -* Run `git format-patch HEAD~1` to export the commit as patch file. -* Check out your previous branch and then force-delete the temporary branch: `git branch -D cubemx_temp` -* Move the patch file to `Firmware/Board/v3/` and add it in a new commit. +### 3. Rebasing the modifications to the generated code +* `git checkout STM32CubeMX-end` +* `git rebase STM32CubeMX-start` +* Make sure the rebase finishes, fixing any conflicts that may arise + +### 4. Merge new STM32CubeMX code to your feature branch +**TODO: Nobody has done this yet, these instructions are new. Please verify that this works as intended.** +Simply merge the new state at `STM32CubeMX-end` into your feature branch. +* `git checkout your-feature` +* `git merge STM32CubeMX-end` + +### 5. Pushing back upstream +* Generate a PR like normal for your feature. +* Make sure youhave pushed to the `STM32CubeMX-start` and `STM32CubeMX-end` branches on your fork. +* Make a note in your PR to the maintainer that they need to update the STM32CubeMX branches when they merge the PR.

## Troubleshooting From e9a5c4af1fbadc2b65a5a4b5d9a030da872d35c1 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:49:16 -0700 Subject: [PATCH 057/106] update STM32CubeMX instructions to new rebasing style --- docs/developer-guide.md | 59 ++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/docs/developer-guide.md b/docs/developer-guide.md index 30a20543..d6243b5b 100644 --- a/docs/developer-guide.md +++ b/docs/developer-guide.md @@ -144,33 +144,54 @@ For working with the ODrive code you don't need an IDE, but the open-source IDE

## STM32CubeMX - This project uses the STM32CubeMX tool to generate startup code and to ease the configuration of the peripherals. You can download it from [here](http://www2.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-configurators-and-code-generators/stm32cubemx.html?icmp=stm32cubemx_pron_pr-stm32cubef2_apr2014&sc=stm32cube-pr2). All CubeMX related files are in `Firmware/Board/v3`. You will likely want the pinout for this process. It is available [here](https://docs.google.com/spreadsheets/d/1QXDCs1IRtUyG__M_9WruWOheywb-GhOwFtfPcHuN2Fg/edit#gid=404444347). -### Generate code +### Maintaining modified generated code +When generating the code, STM32CubeMX will nuke everything except some special sections that they provide. These sections are marked like `USER CODE BEGIN`...`USER CODE END`. +We used to try to make sure all edits we made to the generated code would only go in these sections, so some code structrure may reflect that. +However over time we realized this will not be tenable, so instead we use git to rebase all changes of the generated code whenever we need to regenerate it. +We use two special branches that will help us to do this, they are `STM32CubeMX-start` and `STM32CubeMX-end`. +How to use these is shown in the following example. + +**Note**: Due to how this rebasing is done, all development that changes the generated code should be done directly on `STM32CubeMX-end`, and not based on `devel`, then follow step 4 below to carry them over to your feature branch. If you did some changes to the generated code based from `devel`, you need to cherry pick just those changes over to `STM32CubeMX-end`. + +### 1. Ensuring a clean slate +* We do all changes to the STM32CubeMX config and regenerate the code on top of `STM32CubeMX-start`. + * `git checkout STM32CubeMX-start` * Run stm32cubeMX and load the `Firmware/Board/v3/Odrive.ioc` project file. -* Press `Project -> Generate code` + * If the tool asks if you wish to migrate to a new version, choose to migrate. +* Without changing any settings, press `Project -> Generate code`. * You may need to let it download some drivers and such. -* After generating/updating the code, some minor patches need to be applied. To do this, run: - `git apply Firmware/Board/v3/*.patch` -* Run `git config --local core.autocrlf input`. This will tell git that all files should be checked in with LF endings (CubeMX generates CRLF endings). -* `git status` will still claim that many files are modified but the actual diff (using `git diff`) is empty (apart from all the line ending warnings). +* STM32CubeMX may now have a newer version of some of the libraries, so there may be changes to the generated code even though we didn't change any settings. We need to check that everything is still working, and hence check in the changes: +* `git config --local core.autocrlf input` - This will tell git that all files should be checked in with LF endings (CubeMX generates CRLF endings). +* `git diff` - Ignore the pile of line ending warnings. +* If you feel qualified: you can now ispect if CubeMX introduced something stupid. If there were any changes, and they look acceptable, we should commit them: + * `git commit -am "Run STM32CubeMX v1.21"` - Replace with actual version of CubeMX -### Generating patchfiles -If you made changes to CubeMX generated files outside of the `USER CODE BEGIN`...`USER CODE END` sections and contribute them back, please add a patch file so that the next person who runs CubeMX doesn't run into problems. +### 2. Making changes to the STM32CubeMX config +* After completing the above steps, make sure the working directory is clean: + * `git status` should include "nothing to commit, working tree clean" +* Make your changes in STM32CubeMX, save the project and generate the code. (`Project -> Generate code`) +* `git diff` - Check that the introduced changes are as expected +* If everything looks ok, you can commit your changes. -CubeMX will reset everything outside these sections to the original state; we will capturing into a patch file the changes required to undo this resetting. -* Make sure your current desired state is committed. -* Make a new temporary branch: `git checkout -b cubemx_temp` -* Run the CubeMX code generation as described in the previous section, including applying previous patches. -* The diff will now _not_ be empty since CubeMX reset your changes. -* Stage this state and commit it with a message like "CubeMX reset my changes". -* Run `git revert HEAD` to undo the resetting action CubeMX's regeneration had. This is the commit which you will export, so write a meaningful commit message. -* Run `git format-patch HEAD~1` to export the commit as patch file. -* Check out your previous branch and then force-delete the temporary branch: `git branch -D cubemx_temp` -* Move the patch file to `Firmware/Board/v3/` and add it in a new commit. +### 3. Rebasing the modifications to the generated code +* `git checkout STM32CubeMX-end` +* `git rebase STM32CubeMX-start` +* Make sure the rebase finishes, fixing any conflicts that may arise + +### 4. Merge new STM32CubeMX code to your feature branch +**TODO: Nobody has done this yet, these instructions are new. Please verify that this works as intended.** +Simply merge the new state at `STM32CubeMX-end` into your feature branch. +* `git checkout your-feature` +* `git merge STM32CubeMX-end` + +### 5. Pushing back upstream +* Generate a PR like normal for your feature. +* Make sure youhave pushed to the `STM32CubeMX-start` and `STM32CubeMX-end` branches on your fork. +* Make a note in your PR to the maintainer that they need to update the STM32CubeMX branches when they merge the PR.

## Troubleshooting From 9e02d194f9fd333e56c00ec3ab4102b183859227 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:56:18 -0700 Subject: [PATCH 058/106] fix integer overflow in TIM expression --- Firmware/Board/v3/Odrive.ioc | 2 +- Firmware/Board/v3/Src/tim.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index c9bbdc7f..d18c5f86 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -595,7 +595,7 @@ TIM1.Period=TIM_1_8_PERIOD_CLOCKS TIM1.RepetitionCounter=TIM_1_8_RCR TIM1.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM13.IPParameters=Period -TIM13.Period=(2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1) * TIM_APB1_CLOCK_HZ) / TIM_1_8_CLOCK_HZ +TIM13.Period=(2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1)) * (TIM_APB1_CLOCK_HZ / TIM_1_8_CLOCK_HZ) TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 TIM2.CounterMode=TIM_COUNTERMODE_CENTERALIGNED3 diff --git a/Firmware/Board/v3/Src/tim.c b/Firmware/Board/v3/Src/tim.c index b68a5894..bd27e5f5 100644 --- a/Firmware/Board/v3/Src/tim.c +++ b/Firmware/Board/v3/Src/tim.c @@ -382,7 +382,7 @@ void MX_TIM13_Init(void) htim13.Instance = TIM13; htim13.Init.Prescaler = 0; htim13.Init.CounterMode = TIM_COUNTERMODE_UP; - htim13.Init.Period = (2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1) * TIM_APB1_CLOCK_HZ) / TIM_1_8_CLOCK_HZ; + htim13.Init.Period = (2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1)) * (TIM_APB1_CLOCK_HZ / TIM_1_8_CLOCK_HZ); htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; if (HAL_TIM_Base_Init(&htim13) != HAL_OK) { From 9dc33ad54553492319e3eba8025e3cf0086d14db Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:23:46 -0700 Subject: [PATCH 059/106] bake patch: display correct ODrive version in USB descriptor --- ...ect-ODrive-version-in-USB-descriptor.patch | 41 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 8 ++-- 2 files changed, 5 insertions(+), 44 deletions(-) delete mode 100644 Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch diff --git a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch b/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch deleted file mode 100644 index 0b031242..00000000 --- a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b7ea3f500fbfc187a0a7112282ae6b1eee4555d0 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Tue, 13 Mar 2018 20:05:07 -0700 -Subject: [PATCH] display correct ODrive version in USB descriptor - ---- - Firmware/Board/v3/Src/usbd_desc.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index 94dc49b..37b4302 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -96,7 +96,9 @@ - #define USBD_LANGID_STRING 1033 - #define USBD_MANUFACTURER_STRING "ODrive Robotics" - #define USBD_PID_FS 0x0D32 --#define USBD_PRODUCT_STRING_FS "ODrive v3.3" -+#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) -+#define USBD_PRODUCT_STR(s) #s -+#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR - #define USBD_SERIALNUMBER_STRING_FS "000000000001" - #define USBD_CONFIGURATION_STRING_FS "CDC Config" - #define USBD_INTERFACE_STRING_FS "CDC Interface" -@@ -299,11 +301,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length - { - if(speed == 0) - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - else - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - return USBD_StrDesc; - } --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 2e139e50..973b0ae2 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -95,7 +95,9 @@ #define USBD_LANGID_STRING 1033 #define USBD_MANUFACTURER_STRING "ODrive Robotics" #define USBD_PID_FS 0x0D32 -#define USBD_PRODUCT_STRING_FS "ODrive v3.3" +#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) +#define USBD_PRODUCT_STR(s) #s +#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -342,11 +344,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length { if(speed == 0) { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } else { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } return USBD_StrDesc; } From ba77fc79dccfa06db545fd1da88a083bb9864d6b Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:27:56 -0700 Subject: [PATCH 060/106] bake patch: expose correct serial number on USB --- ...-expose-correct-serial-number-on-USB.patch | 32 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 9 +----- 2 files changed, 1 insertion(+), 40 deletions(-) delete mode 100644 Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch diff --git a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch b/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch deleted file mode 100644 index b9fef648..00000000 --- a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0867a92f742b312a0ebaafe94cade6f57be22170 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 12 Mar 2018 23:49:32 -0700 -Subject: [PATCH] expose correct serial number on USB - ---- - Firmware/Board/v3/Src/usbd_desc.c | 9 +++++++++------- - 1 file changed, 1 insertions(+), 8 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index b9c7bd0..94dc49b 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -327,14 +327,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l - */ - uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) - { -- if(speed == USBD_SPEED_HIGH) -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -- else -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -+ USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); - return USBD_StrDesc; - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 973b0ae2..b0906144 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -373,14 +373,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } + USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); return USBD_StrDesc; } From ce872275be9dea74eb8fe3f7d18f0c0de03b9d77 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:29:43 -0700 Subject: [PATCH 061/106] bake patch: fix return type of osSemaphoreWait --- ...1-fix-return-type-of-osSemaphoreWait.patch | 46 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 4 +- 3 files changed, 4 insertions(+), 50 deletions(-) delete mode 100644 Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch diff --git a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch b/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch deleted file mode 100644 index 53760fa1..00000000 --- a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 49353ccb7023c02c2bc6e3b6f14fac02a13fe599 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:55:17 -0800 -Subject: [PATCH] fix return type of osSemaphoreWait - ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 6 +++--- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - 2 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -index d0e0fd7..e764cbc 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -@@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - * @brief Wait until a Semaphore token becomes available - * @param semaphore_id semaphore object referenced with \ref osSemaphore. - * @param millisec timeout value or 0 in case of no time-out. --* @retval number of available tokens, or -1 in case of incorrect parameters. -+* @retval status code that indicates the execution status of the function. - * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. - */ --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) - { - TickType_t ticks; - portBASE_TYPE taskWoken = pdFALSE; -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 15e25b9..5223f8e 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - /// Wait until a Semaphore token becomes available. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. - /// \param[in] millisec timeout value or 0 in case of no time-out. --/// \return number of available tokens, or -1 in case of incorrect parameters. -+/// \return status code that indicates the execution status of the function. - /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - - /// Release a Semaphore token. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index d0e0fd76..7828403b 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t * @brief Wait until a Semaphore token becomes available * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @param millisec timeout value or 0 in case of no time-out. -* @retval number of available tokens, or -1 in case of incorrect parameters. +* @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 15e25b96..09cdf273 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \return status code that indicates the execution status of the function. /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. From 019a71eb14238d5387117abb64d39ea5d4b90eaa Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:31:41 -0700 Subject: [PATCH 062/106] bake patch: release sem_usb_tx in usb_cdc.c --- ...001-release-sem_usb_tx-in-usbd_cdc.c.patch | 35 ------------------- .../Class/CDC/Src/usbd_cdc.c | 5 +-- 2 files changed, 3 insertions(+), 37 deletions(-) delete mode 100644 Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch diff --git a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch b/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch deleted file mode 100644 index b69370f5..00000000 --- a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 965f7f2c80e30d7a66dcac7abaa9bdc371d9ea51 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:53:52 -0800 -Subject: [PATCH] release sem_usb_tx in usbd_cdc.c - ---- - .../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -index b2ca5f1..6ae33e8 100644 ---- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -+++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -@@ -62,7 +62,8 @@ - #include "usbd_cdc.h" - #include "usbd_desc.h" - #include "usbd_ctlreq.h" -- -+#include -+#include - - /** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ -@@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) - { - - hcdc->TxState = 0; -- -+ osSemaphoreRelease(sem_usb_tx); - return USBD_OK; - } - else --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index b2ca5f16..24465641 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -62,7 +62,8 @@ #include "usbd_cdc.h" #include "usbd_desc.h" #include "usbd_ctlreq.h" - +#include +#include /** @addtogroup STM32_USB_DEVICE_LIBRARY * @{ @@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) { hcdc->TxState = 0; - + osSemaphoreRelease(sem_usb_tx); return USBD_OK; } else From 1ccf17b36af91674b612aeeb9a76bb4c659b4b45 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:43:04 -0700 Subject: [PATCH 063/106] bake patch: FreeRTOS constness fixes --- .../v3/0002-FreeRTOS-constness-fixes.patch | 64 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 8 +-- Firmware/Board/v3/Src/freertos.c | 4 +- 3 files changed, 6 insertions(+), 70 deletions(-) delete mode 100644 Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch diff --git a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch b/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch deleted file mode 100644 index afe0326e..00000000 --- a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 510ead2b159e1d8116e5241066c54a7bf8b7bfbe Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 15:29:44 -0700 -Subject: [PATCH] FreeRTOS constness fixes - - - make thread names const char * - - make thread argument non-const void* ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - Firmware/Board/v3/Src/freertos.c | 4 ++-- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 09cdf27..754be24 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -270,11 +270,11 @@ typedef enum { - - /// Entry point of a thread. - /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. --typedef void (*os_pthread) (void const *argument); -+typedef void (*os_pthread) (void *argument); - - /// Entry point of a timer call back function. - /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. --typedef void (*os_ptimer) (void const *argument); -+typedef void (*os_ptimer) (void *argument); - - // >>> the following data type definitions may shall adapted towards a specific RTOS - -@@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; - /// Thread Definition structure contains startup information of a thread. - /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. - typedef struct os_thread_def { -- char *name; ///< Thread name -+ const char *name; ///< Thread name - os_pthread pthread; ///< start address of thread function - osPriority tpriority; ///< initial thread priority - uint32_t instances; ///< maximum number of instances of that thread function -diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c -index 6eaea82..b247994 100644 ---- a/Firmware/Board/v3/Src/freertos.c -+++ b/Firmware/Board/v3/Src/freertos.c -@@ -75,7 +75,7 @@ uint8_t ucHeap[configTOTAL_HEAP_SIZE]; - /* USER CODE END Variables */ - - /* Function prototypes -------------------------------------------------------*/ --void StartDefaultTask(void const * argument); -+void StartDefaultTask(void * argument); - - extern void MX_USB_DEVICE_Init(void); - void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ -@@ -147,7 +147,7 @@ void MX_FREERTOS_Init(void) { - } - - /* StartDefaultTask function */ --void StartDefaultTask(void const * argument) -+void StartDefaultTask(void * argument) - { - /* init code for USB_DEVICE */ - MX_USB_DEVICE_Init(); --- -2.16.2 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 09cdf273..89a105dc 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -26,7 +26,7 @@ * *---------------------------------------------------------------------------- * - * Portions Copyright 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved. * Portions Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without @@ -270,11 +270,11 @@ typedef enum { /// Entry point of a thread. /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); +typedef void (*os_pthread) (void *argument); /// Entry point of a timer call back function. /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); +typedef void (*os_ptimer) (void *argument); // >>> the following data type definitions may shall adapted towards a specific RTOS @@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; /// Thread Definition structure contains startup information of a thread. /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. typedef struct os_thread_def { - char *name; ///< Thread name + const char *name; ///< Thread name os_pthread pthread; ///< start address of thread function osPriority tpriority; ///< initial thread priority uint32_t instances; ///< maximum number of instances of that thread function diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c index 0865d714..11154587 100644 --- a/Firmware/Board/v3/Src/freertos.c +++ b/Firmware/Board/v3/Src/freertos.c @@ -98,7 +98,7 @@ osThreadId defaultTaskHandle; /* USER CODE END FunctionPrototypes */ -void StartDefaultTask(void const * argument); +void StartDefaultTask(void * argument); extern void MX_USB_DEVICE_Init(void); void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ @@ -214,7 +214,7 @@ void MX_FREERTOS_Init(void) { * @retval None */ /* USER CODE END Header_StartDefaultTask */ -void StartDefaultTask(void const * argument) +void StartDefaultTask(void * argument) { /* init code for USB_DEVICE */ MX_USB_DEVICE_Init(); From fe068005875d388a2a779770974e74904174e1fc Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:45:30 -0700 Subject: [PATCH 064/106] bake patch: disable IRQ for DMA2_Stream0 --- .../0003-disable-IRQ-for-DMA2_Stream0.patch | 33 ------------------- Firmware/Board/v3/Src/dma.c | 6 ++-- 2 files changed, 4 insertions(+), 35 deletions(-) delete mode 100644 Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch diff --git a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch b/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch deleted file mode 100644 index 282317d1..00000000 --- a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ab5ca860b3729d76a9c43c485776147ab69d2342 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 19:02:45 -0700 -Subject: [PATCH] disable IRQ for DMA2_Stream0 - -This DMA stream is used to read values from ADC1 -while ADC1 cycles through it's sequence of input -channels. No interrupts are required to make -this work. ---- - Firmware/Board/v3/Src/dma.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c -index 55d5e03..3de873a 100644 ---- a/Firmware/Board/v3/Src/dma.c -+++ b/Firmware/Board/v3/Src/dma.c -@@ -78,8 +78,10 @@ void MX_DMA_Init(void) - HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); - /* DMA2_Stream0_IRQn interrupt configuration */ -- HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -- HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); -+ // Dear STM, no we _don't_ want to fire an interrupt for this DMA -+ // (it's not possible to deselect this in CubeMX) -+ //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -+ //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); - - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c index 55d5e034..3de873ad 100644 --- a/Firmware/Board/v3/Src/dma.c +++ b/Firmware/Board/v3/Src/dma.c @@ -78,8 +78,10 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); /* DMA2_Stream0_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + // Dear STM, no we _don't_ want to fire an interrupt for this DMA + // (it's not possible to deselect this in CubeMX) + //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); + //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); } From 8db7eff380d4b8b3091952d802de79bc3ffa6296 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:57:44 -0700 Subject: [PATCH 065/106] bake patch: Add I2C files and settings --- .../v3/0002-Add-I2C-files-and-settings.patch | 6860 ----------------- .../Inc/stm32f4xx_hal_i2c.h | 649 ++ .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++ .../Src/stm32f4xx_hal_i2c_ex.c | 204 + Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- Firmware/Board/v3/Src/main.c | 2 +- 7 files changed, 6486 insertions(+), 6862 deletions(-) delete mode 100644 Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch b/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch deleted file mode 100644 index aae18bf4..00000000 --- a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch +++ /dev/null @@ -1,6860 +0,0 @@ -From b45bdbbbfe3d084d069da99b98116991923f5eb6 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Thu, 26 Apr 2018 13:20:38 -0700 -Subject: [PATCH] Add I2C files and settings - ---- - .../Inc/stm32f4xx_hal_i2c.h | 649 ++ - .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + - .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++++++ - .../Src/stm32f4xx_hal_i2c_ex.c | 204 + - Firmware/Board/v3/Inc/i2c.h | 91 + - Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- - Firmware/Board/v3/Odrive.ioc | 5 + - Firmware/Board/v3/Src/i2c.c | 198 + - Firmware/Board/v3/Src/main.c | 1 - - 11 files changed, 6811 insertions(+), 2 deletions(-) - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c - create mode 100644 Firmware/Board/v3/Inc/i2c.h - create mode 100644 Firmware/Board/v3/Src/i2c.c - -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -new file mode 100644 -index 0000000..5452a50 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -@@ -0,0 +1,649 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_H -+#define __STM32F4xx_HAL_I2C_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2C -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Types I2C Exported Types -+ * @{ -+ */ -+ -+/** -+ * @brief I2C Configuration Structure definition -+ */ -+typedef struct -+{ -+ uint32_t ClockSpeed; /*!< Specifies the clock frequency. -+ This parameter must be set to a value lower than 400kHz */ -+ -+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. -+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ -+ -+ uint32_t OwnAddress1; /*!< Specifies the first device own address. -+ This parameter can be a 7-bit or 10-bit address. */ -+ -+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. -+ This parameter can be a value of @ref I2C_addressing_mode */ -+ -+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. -+ This parameter can be a value of @ref I2C_dual_addressing_mode */ -+ -+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected -+ This parameter can be a 7-bit address. */ -+ -+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. -+ This parameter can be a value of @ref I2C_general_call_addressing_mode */ -+ -+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. -+ This parameter can be a value of @ref I2C_nostretch_mode */ -+ -+}I2C_InitTypeDef; -+ -+/** -+ * @brief HAL State structure definition -+ * @note HAL I2C State value coding follow below described bitmap : -+ * b7-b6 Error information -+ * 00 : No Error -+ * 01 : Abort (Abort user request on going) -+ * 10 : Timeout -+ * 11 : Error -+ * b5 IP initilisation status -+ * 0 : Reset (IP not initialized) -+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) -+ * b4 (not used) -+ * x : Should be set to 0 -+ * b3 -+ * 0 : Ready or Busy (No Listen mode ongoing) -+ * 1 : Listen (IP in Address Listen Mode) -+ * b2 Intrinsic process state -+ * 0 : Ready -+ * 1 : Busy (IP busy with some configuration or internal operations) -+ * b1 Rx state -+ * 0 : Ready (no Rx operation ongoing) -+ * 1 : Busy (Rx operation ongoing) -+ * b0 Tx state -+ * 0 : Ready (no Tx operation ongoing) -+ * 1 : Busy (Tx operation ongoing) -+ */ -+typedef enum -+{ -+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ -+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ -+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ -+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ -+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ -+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission -+ process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception -+ process is ongoing */ -+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ -+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ -+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -+ -+}HAL_I2C_StateTypeDef; -+ -+/** -+ * @brief HAL Mode structure definition -+ * @note HAL I2C Mode value coding follow below described bitmap : -+ * b7 (not used) -+ * x : Should be set to 0 -+ * b6 -+ * 0 : None -+ * 1 : Memory (HAL I2C communication is in Memory Mode) -+ * b5 -+ * 0 : None -+ * 1 : Slave (HAL I2C communication is in Slave Mode) -+ * b4 -+ * 0 : None -+ * 1 : Master (HAL I2C communication is in Master Mode) -+ * b3-b2-b1-b0 (not used) -+ * xxxx : Should be set to 0000 -+ */ -+typedef enum -+{ -+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ -+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ -+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ -+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -+ -+}HAL_I2C_ModeTypeDef; -+ -+/** -+ * @brief I2C handle Structure definition -+ */ -+typedef struct -+{ -+ I2C_TypeDef *Instance; /*!< I2C registers base address */ -+ -+ I2C_InitTypeDef Init; /*!< I2C communication parameters */ -+ -+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ -+ -+ uint16_t XferSize; /*!< I2C transfer size */ -+ -+ __IO uint16_t XferCount; /*!< I2C transfer counter */ -+ -+ __IO uint32_t XferOptions; /*!< I2C transfer options */ -+ -+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode -+ context for internal usage */ -+ -+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ -+ -+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ -+ -+ HAL_LockTypeDef Lock; /*!< I2C locking object */ -+ -+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ -+ -+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ -+ -+ __IO uint32_t ErrorCode; /*!< I2C Error code */ -+ -+ __IO uint32_t Devaddress; /*!< I2C Target device address */ -+ -+ __IO uint32_t Memaddress; /*!< I2C Target memory address */ -+ -+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ -+ -+ __IO uint32_t EventCount; /*!< I2C Event counter */ -+ -+}I2C_HandleTypeDef; -+ -+/** -+ * @} -+ */ -+ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2C_Error_Code I2C Error Code -+ * @brief I2C Error Code -+ * @{ -+ */ -+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ -+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ -+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ -+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ -+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ -+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode -+ * @{ -+ */ -+#define I2C_DUTYCYCLE_2 0x00000000U -+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_addressing_mode I2C addressing mode -+ * @{ -+ */ -+#define I2C_ADDRESSINGMODE_7BIT 0x00004000U -+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode -+ * @{ -+ */ -+#define I2C_DUALADDRESS_DISABLE 0x00000000U -+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode -+ * @{ -+ */ -+#define I2C_GENERALCALL_DISABLE 0x00000000U -+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_nostretch_mode I2C nostretch mode -+ * @{ -+ */ -+#define I2C_NOSTRETCH_DISABLE 0x00000000U -+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size -+ * @{ -+ */ -+#define I2C_MEMADD_SIZE_8BIT 0x00000001U -+#define I2C_MEMADD_SIZE_16BIT 0x00000010U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition -+ * @{ -+ */ -+#define I2C_DIRECTION_RECEIVE 0x00000000U -+#define I2C_DIRECTION_TRANSMIT 0x00000001U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition -+ * @{ -+ */ -+#define I2C_FIRST_FRAME 0x00000001U -+#define I2C_NEXT_FRAME 0x00000002U -+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U -+#define I2C_LAST_FRAME 0x00000008U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition -+ * @{ -+ */ -+#define I2C_IT_BUF I2C_CR2_ITBUFEN -+#define I2C_IT_EVT I2C_CR2_ITEVTEN -+#define I2C_IT_ERR I2C_CR2_ITERREN -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Flag_definition I2C Flag definition -+ * @{ -+ */ -+#define I2C_FLAG_SMBALERT 0x00018000U -+#define I2C_FLAG_TIMEOUT 0x00014000U -+#define I2C_FLAG_PECERR 0x00011000U -+#define I2C_FLAG_OVR 0x00010800U -+#define I2C_FLAG_AF 0x00010400U -+#define I2C_FLAG_ARLO 0x00010200U -+#define I2C_FLAG_BERR 0x00010100U -+#define I2C_FLAG_TXE 0x00010080U -+#define I2C_FLAG_RXNE 0x00010040U -+#define I2C_FLAG_STOPF 0x00010010U -+#define I2C_FLAG_ADD10 0x00010008U -+#define I2C_FLAG_BTF 0x00010004U -+#define I2C_FLAG_ADDR 0x00010002U -+#define I2C_FLAG_SB 0x00010001U -+#define I2C_FLAG_DUALF 0x00100080U -+#define I2C_FLAG_SMBHOST 0x00100040U -+#define I2C_FLAG_SMBDEFAULT 0x00100020U -+#define I2C_FLAG_GENCALL 0x00100010U -+#define I2C_FLAG_TRA 0x00100004U -+#define I2C_FLAG_BUSY 0x00100002U -+#define I2C_FLAG_MSL 0x00100001U -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Macros I2C Exported Macros -+ * @{ -+ */ -+ -+/** @brief Reset I2C handle state -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -+ -+/** @brief Enable or disable the specified I2C interrupts. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -+ -+/** @brief Checks if the specified I2C interrupt source is enabled or disabled. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the I2C interrupt source to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -+ -+/** @brief Checks whether the specified I2C flag is set or not. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @arg I2C_FLAG_TXE: Data register empty flag -+ * @arg I2C_FLAG_RXNE: Data register not empty flag -+ * @arg I2C_FLAG_STOPF: Stop detection flag -+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag -+ * @arg I2C_FLAG_BTF: Byte transfer finished flag -+ * @arg I2C_FLAG_ADDR: Address sent flag -+ * Address matched flag -+ * @arg I2C_FLAG_SB: Start bit flag -+ * @arg I2C_FLAG_DUALF: Dual flag -+ * @arg I2C_FLAG_SMBHOST: SMBus host header -+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header -+ * @arg I2C_FLAG_GENCALL: General call header flag -+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag -+ * @arg I2C_FLAG_BUSY: Bus busy flag -+ * @arg I2C_FLAG_MSL: Master/Slave flag -+ * @retval The new state of __FLAG__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ -+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -+ -+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to clear. -+ * This parameter can be any combination of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) -+ -+/** @brief Clears the I2C ADDR pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ tmpreg = (__HANDLE__)->Instance->SR2; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Clears the I2C STOPF pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Enable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -+ -+/** @brief Disable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) -+ -+/** -+ * @} -+ */ -+ -+/* Include I2C HAL Extension module */ -+#include "stm32f4xx_hal_i2c_ex.h" -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2C_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Initialization/de-initialization functions **********************************/ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group2 -+ * @{ -+ */ -+/* I/O operation functions *****************************************************/ -+/******* Blocking mode: Polling */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); -+ -+/******* Non-Blocking mode: Interrupt */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -+ -+/******* Non-Blocking mode: DMA */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group3 -+ * @{ -+ */ -+/* Peripheral State, Mode and Errors functions *********************************/ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Constants I2C Private Constants -+ * @{ -+ */ -+#define I2C_FLAG_MASK 0x0000FFFFU -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2C_Private_Macros I2C Private Macros -+ * @{ -+ */ -+ -+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) -+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) -+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) -+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) -+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) -+ -+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) -+ -+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) -+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) -+ -+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) -+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+ -+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters -+ * @{ -+ */ -+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ -+ ((CYCLE) == I2C_DUTYCYCLE_16_9)) -+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ -+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) -+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ -+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) -+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ -+ ((CALL) == I2C_GENERALCALL_ENABLE)) -+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ -+ ((STRETCH) == I2C_NOSTRETCH_ENABLE)) -+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ -+ ((SIZE) == I2C_MEMADD_SIZE_16BIT)) -+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) -+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) -+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) -+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ -+ ((REQUEST) == I2C_NEXT_FRAME) || \ -+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ -+ ((REQUEST) == I2C_LAST_FRAME)) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private functions ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Functions I2C Private Functions -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+ -+#endif /* __STM32F4xx_HAL_I2C_H */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -new file mode 100644 -index 0000000..ff47d5c ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -@@ -0,0 +1,137 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL Extension module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_EX_H -+#define __STM32F4xx_HAL_I2C_EX_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter -+ * @{ -+ */ -+#define I2C_ANALOGFILTER_ENABLE 0x00000000U -+#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2CEx_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Peripheral Control functions ************************************************/ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Constants I2C Private Constants -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Macros I2C Private Macros -+ * @{ -+ */ -+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ -+ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ -+ STM32F413xx || STM32F423xx */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __STM32F4xx_HAL_I2C_EX_H */ -+ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -new file mode 100644 -index 0000000..da18520 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -@@ -0,0 +1,5494 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.c -+ * @author MCD Application Team -+ * @brief I2C HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of the Inter Integrated Circuit (I2C) peripheral: -+ * + Initialization and de-initialization functions -+ * + IO operation functions -+ * + Peripheral State, Mode and Error functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] -+ The I2C HAL driver can be used as follows: -+ -+ (#) Declare a I2C_HandleTypeDef handle structure, for example: -+ I2C_HandleTypeDef hi2c; -+ -+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: -+ (##) Enable the I2Cx interface clock -+ (##) I2C pins configuration -+ (+++) Enable the clock for the I2C GPIOs -+ (+++) Configure I2C pins as alternate function open-drain -+ (##) NVIC configuration if you need to use interrupt process -+ (+++) Configure the I2Cx interrupt priority -+ (+++) Enable the NVIC I2C IRQ Channel -+ (##) DMA Configuration if you need to use DMA process -+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream -+ (+++) Enable the DMAx interface clock using -+ (+++) Configure the DMA handle parameters -+ (+++) Configure the DMA Tx or Rx Stream -+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle -+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on -+ the DMA Tx or Rx Stream -+ -+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, -+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. -+ -+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware -+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. -+ -+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() -+ -+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : -+ -+ *** Polling mode IO operation *** -+ ================================= -+ [..] -+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() -+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() -+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() -+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() -+ -+ *** Polling mode IO MEM operation *** -+ ===================================== -+ [..] -+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() -+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() -+ -+ -+ *** Interrupt mode IO operation *** -+ =================================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO sequential operation *** -+ ============================================== -+ [..] -+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition -+ when a direction change during transfer -+ [..] -+ (+) A specific option field manage the different steps of a sequential transfer -+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: -+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode -+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address -+ and data to transfer without a final stop condition -+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and without a final stop condition in both cases -+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and with a final stop condition in both cases -+ -+ (+) Differents sequential I2C interfaces are listed below: -+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() -+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() -+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can -+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). -+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() -+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() -+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() -+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO MEM operation *** -+ ======================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using -+ HAL_I2C_Mem_Write_IT() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using -+ HAL_I2C_Mem_Read_IT() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ *** DMA mode IO operation *** -+ ============================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** DMA mode IO MEM operation *** -+ ================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using -+ HAL_I2C_Mem_Write_DMA() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using -+ HAL_I2C_Mem_Read_DMA() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ -+ *** I2C HAL driver macros list *** -+ ================================== -+ [..] -+ Below the list of most used macros in I2C HAL driver. -+ -+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral -+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral -+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not -+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag -+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt -+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt -+ -+ [..] -+ (@) You can refer to the I2C HAL driver header file for more useful macros -+ -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2C I2C -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/** @addtogroup I2C_Private_Define -+ * @{ -+ */ -+#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ -+#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ -+#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ -+ -+/* Private define for @ref PreviousState usage */ -+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ -+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/** @addtogroup I2C_Private_Functions -+ * @{ -+ */ -+/* Private functions to handle DMA transfer */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); -+static void I2C_DMAError(DMA_HandleTypeDef *hdma); -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); -+ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); -+ -+/* Private functions for I2C transfer IRQ handler */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions -+ * @brief Initialization and Configuration functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Initialization and de-initialization functions ##### -+ =============================================================================== -+ [..] This subsection provides a set of functions allowing to initialize and -+ de-initialize the I2Cx peripheral: -+ -+ (+) User must Implement HAL_I2C_MspInit() function in which he configures -+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). -+ -+ (+) Call the function HAL_I2C_Init() to configure the selected device with -+ the selected configuration: -+ (++) Communication Speed -+ (++) Duty cycle -+ (++) Addressing mode -+ (++) Own Address 1 -+ (++) Dual Addressing mode -+ (++) Own Address 2 -+ (++) General call mode -+ (++) Nostretch mode -+ -+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration -+ of the selected I2Cx peripheral. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Initializes the I2C according to the specified parameters -+ * in the I2C_InitTypeDef and create the associated handle. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t freqrange = 0U; -+ uint32_t pclk1 = 0U; -+ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); -+ assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); -+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); -+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); -+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); -+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); -+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); -+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); -+ -+ if(hi2c->State == HAL_I2C_STATE_RESET) -+ { -+ /* Allocate lock resource and initialize it */ -+ hi2c->Lock = HAL_UNLOCKED; -+ /* Init the low level hardware : GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspInit(hi2c); -+ } -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get PCLK1 frequency */ -+ pclk1 = HAL_RCC_GetPCLK1Freq(); -+ -+ /* Calculate frequency range */ -+ freqrange = I2C_FREQRANGE(pclk1); -+ -+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/ -+ /* Configure I2Cx: Frequency range */ -+ hi2c->Instance->CR2 = freqrange; -+ -+ /*---------------------------- I2Cx TRISE Configuration --------------------*/ -+ /* Configure I2Cx: Rise Time */ -+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); -+ -+ /*---------------------------- I2Cx CCR Configuration ----------------------*/ -+ /* Configure I2Cx: Speed */ -+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); -+ -+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/ -+ /* Configure I2Cx: Generalcall and NoStretch mode */ -+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); -+ -+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ -+ /* Configure I2Cx: Own Address1 and addressing mode */ -+ hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); -+ -+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ -+ /* Configure I2Cx: Dual mode and Own Address2 */ -+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); -+ -+ /* Enable the selected I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DeInitializes the I2C peripheral. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the I2C Peripheral Clock */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspDeInit(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_RESET; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Release Lock */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C MSP Init. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C MSP DeInit -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspDeInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions -+ * @brief Data transfers functions -+ * -+@verbatim -+ =============================================================================== -+ ##### IO operation functions ##### -+ =============================================================================== -+ [..] -+ This subsection provides a set of functions allowing to manage the I2C data -+ transfers. -+ -+ (#) There are two modes of transfer: -+ (++) Blocking mode : The communication is performed in the polling mode. -+ The status of all data processing is returned by the same function -+ after finishing transfer. -+ (++) No-Blocking mode : The communication is performed using Interrupts -+ or DMA. These functions return the status of the transfer startup. -+ The end of the data processing will be indicated through the -+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when -+ using DMA mode. -+ -+ (#) Blocking mode functions are : -+ (++) HAL_I2C_Master_Transmit() -+ (++) HAL_I2C_Master_Receive() -+ (++) HAL_I2C_Slave_Transmit() -+ (++) HAL_I2C_Slave_Receive() -+ (++) HAL_I2C_Mem_Write() -+ (++) HAL_I2C_Mem_Read() -+ (++) HAL_I2C_IsDeviceReady() -+ -+ (#) No-Blocking mode functions with Interrupt are : -+ (++) HAL_I2C_Master_Transmit_IT() -+ (++) HAL_I2C_Master_Receive_IT() -+ (++) HAL_I2C_Slave_Transmit_IT() -+ (++) HAL_I2C_Slave_Receive_IT() -+ (++) HAL_I2C_Master_Sequential_Transmit_IT() -+ (++) HAL_I2C_Master_Sequential_Receive_IT() -+ (++) HAL_I2C_Slave_Sequential_Transmit_IT() -+ (++) HAL_I2C_Slave_Sequential_Receive_IT() -+ (++) HAL_I2C_Mem_Write_IT() -+ (++) HAL_I2C_Mem_Read_IT() -+ -+ (#) No-Blocking mode functions with DMA are : -+ (++) HAL_I2C_Master_Transmit_DMA() -+ (++) HAL_I2C_Master_Receive_DMA() -+ (++) HAL_I2C_Slave_Transmit_DMA() -+ (++) HAL_I2C_Slave_Receive_DMA() -+ (++) HAL_I2C_Mem_Write_DMA() -+ (++) HAL_I2C_Mem_Read_DMA() -+ -+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: -+ (++) HAL_I2C_MemTxCpltCallback() -+ (++) HAL_I2C_MemRxCpltCallback() -+ (++) HAL_I2C_MasterTxCpltCallback() -+ (++) HAL_I2C_MasterRxCpltCallback() -+ (++) HAL_I2C_SlaveTxCpltCallback() -+ (++) HAL_I2C_SlaveRxCpltCallback() -+ (++) HAL_I2C_ErrorCallback() -+ (++) HAL_I2C_AbortCpltCallback() -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Transmits in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receives in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize == 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmits in slave mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* If 10bit addressing mode is selected */ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) -+ { -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ } -+ -+ /* Wait until AF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in blocking mode -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until STOP flag is set */ -+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear STOP flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t Prev_State = 0x00U; -+ __IO uint32_t count = 0x00U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ Prev_State = hi2c->PreviousState; -+ -+ /* Generate Start */ -+ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Enable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Disable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of tmp to prevent undefined behavior of volatile usage */ -+ uint32_t tmp; -+ -+ /* Disable Address listen mode only if a transfer is not ongoing */ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; -+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Abort a master I2C process communication with Interrupt. -+ * @note This abort can be called only if state is ready -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(DevAddress); -+ -+ /* Abort Master transfer during Receive or Transmit process */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_ABORT; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Wrong usage of abort function */ -+ /* This function should be used only in case of abort monitored by master device */ -+ return HAL_ERROR; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+/** -+ * @brief Write an amount of data in blocking mode to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in blocking mode from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize== 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be read -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ uint32_t tickstart = 0x00U; -+ __IO uint32_t count = 0U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(Size == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Checks if target device is ready for communication. -+ * @note This function is used with Memory devices -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param Trials Number of trials -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; -+ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ do -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR or AF flag are set */ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) -+ { -+ hi2c->State = HAL_I2C_STATE_TIMEOUT; -+ } -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Check if the ADDR flag has been set */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear ADDR Flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ }while(I2C_Trials++ < Trials); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief This function handles I2C event interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ /* Master or Memory mode selected */ -+ if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* SB Set ----------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_SB(hi2c); -+ } -+ /* ADD10 Set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADD10(hi2c); -+ } -+ /* ADDR Set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADDR(hi2c); -+ } -+ -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterReceive_BTF(hi2c); -+ } -+ } -+ } -+ /* Slave mode selected */ -+ else -+ { -+ /* ADDR set --------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_ADDR(hi2c); -+ } -+ /* STOPF set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_STOPF(hi2c); -+ } -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ else if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset ----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveReceive_BTF(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief This function handles I2C error interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ /* I2C Bus error interrupt occurred ----------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; -+ -+ /* Clear BERR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); -+ } -+ -+ /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; -+ -+ /* Clear ARLO flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); -+ } -+ -+ /* I2C Acknowledge failure error interrupt occurred ------------------------*/ -+ if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ tmp1 = hi2c->Mode; -+ tmp2 = hi2c->XferCount; -+ tmp3 = hi2c->State; -+ tmp4 = hi2c->PreviousState; -+ if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ -+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ -+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) -+ { -+ I2C_Slave_AF(hi2c); -+ } -+ else -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ -+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Generate Stop */ -+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ } -+ -+ /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; -+ /* Clear OVR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); -+ } -+ -+ /* Call the Error Callback in case of Error detected -----------------------*/ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ I2C_ITError(hi2c); -+ } -+} -+ -+/** -+ * @brief Master Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Master Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** @brief Slave Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Address Match callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition -+ * @param AddrMatchCode Address Match Code -+ * @retval None -+ */ -+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ UNUSED(TransferDirection); -+ UNUSED(AddrMatchCode); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AddrCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Listen Complete callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ListenCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C error callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ErrorCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C abort callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AbortCpltCallback could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions -+ * @brief Peripheral State and Errors functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Peripheral State, Mode and Error functions ##### -+ =============================================================================== -+ [..] -+ This subsection permits to get in run-time the status of the peripheral -+ and the data flow. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Return the I2C handle state. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL state -+ */ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -+{ -+ /* Return I2C handle state */ -+ return hi2c->State; -+} -+ -+/** -+ * @brief Return the I2C Master, Slave, Memory or no mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL mode -+ */ -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->Mode; -+} -+ -+/** -+ * @brief Return the I2C error code -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval I2C Error Code -+ */ -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->ErrorCode; -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @brief Handle TXE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ -+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ else -+ { -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0) -+ { -+ /* If Memory address size is 8Bit */ -+ if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount += 2; -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ } -+ else if(hi2c->EventCount == 1) -+ { -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ else if(hi2c->EventCount == 2) -+ { -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ else -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ else -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ uint32_t tmp = 0U; -+ -+ tmp = hi2c->XferCount; -+ if(tmp > 3U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if(hi2c->XferCount == 3) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 4 bytes -+ on BTF subroutine */ -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ } -+ else if((tmp == 1U) || (tmp == 0U)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->XferCount == 4U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 3U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ /* Prepare next transfer or stop current transfer */ -+ if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ else -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle SB flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave 7 Bits address */ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); -+ } -+ else if(hi2c->EventCount == 1U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD10 flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) -+{ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADDR flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ uint32_t Prev_State = hi2c->PreviousState; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ hi2c->EventCount++; -+ } -+ else -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferCount == 1U) -+ { -+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ /* Prepare next transfer or stop current transfer */ -+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ -+ && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ /* Reset Event counter */ -+ hi2c->EventCount = 0U; -+ } -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle TXE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Tx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Rx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; -+ uint16_t SlaveAddrCode = 0U; -+ -+ /* Transfer Direction requested by Master */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) -+ { -+ TransferDirection = I2C_DIRECTION_TRANSMIT; -+ } -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress1; -+ } -+ else -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress2; -+ } -+ -+ /* Call Slave Addr callback */ -+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle STOPF flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear STOPF flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* If a DMA is ongoing, Update handle size context */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); -+ } -+ else -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); -+ } -+ } -+ -+ /* All data are not transferred, so set error code accordingly */ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Set ErrorCode corresponding to a Non-Acknowledge */ -+ //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ } -+ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ } -+ else -+ { -+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ -+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else -+ { -+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ -+ (CurrentState == HAL_I2C_STATE_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else if(CurrentState == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Clear AF flag only */ -+ /* State Listen, but XferOptions == FIRST or NEXT */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C interrupts error process -+ * @param hi2c I2C handle. -+ * @retval None -+ */ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* keep HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ } -+ else -+ { -+ /* If state is an abort treatment on going, don't change state */ -+ /* This change will be do later */ -+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ } -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ } -+ -+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ /* Abort DMA transfer */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) -+ { -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly XferAbortCallback function in case of error */ -+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); -+ } -+ } -+ else -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ -+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); -+ } -+ } -+ } -+ else if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Call user error callback */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ /* STOP Flag is not set after a NACK reception */ -+ /* So may inform upper layer that listen phase is stopped */ -+ /* during NACK error treatment */ -+ if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for write request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DMA I2C process complete callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) -+ { -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Disable Last DMA */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_LAST; -+ -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Check if Errors has been detected during transfer */ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief DMA I2C communication error callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAError(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Ignore DMA FIFO error */ -+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; -+ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief DMA I2C communication abort callback -+ * (To be called at end of DMA Abort procedure). -+ * @param hdma DMA handle. -+ * @retval None -+ */ -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Reset XferAbortCallback */ -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Check if come from abort from user */ -+ if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Status The new Flag status (SET or RESET). -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Wait until flag is set */ -+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) -+ { -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for Master addressing phase. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) -+ { -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) -+ { -+ /* Check if a STOPF is detected */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) -+ { -+ /* Clear STOP Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles Acknowledge failed detection during an I2C Communication. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) -+{ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Clear NACKF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ return HAL_OK; -+} -+/** -+ * @} -+ */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -new file mode 100644 -index 0000000..de8f160 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -@@ -0,0 +1,204 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.c -+ * @author MCD Application Team -+ * @brief I2C Extension HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of I2C extension peripheral: -+ * + Extension features functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### I2C peripheral extension features ##### -+ ============================================================================== -+ -+ [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ -+ 429xx/439xx devices contains the following additional features : -+ -+ (+) Possibility to disable or enable Analog Noise Filter -+ (+) Use of a configured Digital Noise Filter -+ -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] This driver provides functions to configure Noise Filter -+ (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() -+ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2CEx I2CEx -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+ -+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions -+ * @brief Extension features functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Extension features functions ##### -+ =============================================================================== -+ [..] This section provides functions allowing to: -+ (+) Configure Noise Filters -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Configures I2C Analog noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param AnalogFilter new state of the Analog filter. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Reset I2Cx ANOFF bit */ -+ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); -+ -+ /* Disable the analog filter */ -+ hi2c->Instance->FLTR |= AnalogFilter; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Configures I2C Digital noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -+{ -+ uint16_t tmpreg = 0; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get the old register value */ -+ tmpreg = hi2c->Instance->FLTR; -+ -+ /* Reset I2Cx DNF bit [3:0] */ -+ tmpreg &= ~(I2C_FLTR_DNF); -+ -+ /* Set I2Cx DNF coefficient */ -+ tmpreg |= DigitalFilter; -+ -+ /* Store the new register value */ -+ hi2c->Instance->FLTR = tmpreg; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ -+ STM32F423xx */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/i2c.h b/Firmware/Board/v3/Inc/i2c.h -new file mode 100644 -index 0000000..f449b88 ---- /dev/null -+++ b/Firmware/Board/v3/Inc/i2c.h -@@ -0,0 +1,91 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.h -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __i2c_H -+#define __i2c_H -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+#include "main.h" -+ -+/* USER CODE BEGIN Includes */ -+ -+/* USER CODE END Includes */ -+ -+extern I2C_HandleTypeDef hi2c1; -+ -+/* USER CODE BEGIN Private defines */ -+ -+/* USER CODE END Private defines */ -+ -+extern void _Error_Handler(char *, int); -+ -+void MX_I2C1_Init(uint8_t addr); -+ -+/* USER CODE BEGIN Prototypes */ -+ -+/* USER CODE END Prototypes */ -+ -+#ifdef __cplusplus -+} -+#endif -+#endif /*__ i2c_H */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -index d0f48f5..b3ef59a 100644 ---- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -+++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -@@ -65,7 +65,7 @@ - /* #define HAL_SRAM_MODULE_ENABLED */ - /* #define HAL_SDRAM_MODULE_ENABLED */ - /* #define HAL_HASH_MODULE_ENABLED */ --/* #define HAL_I2C_MODULE_ENABLED */ -+#define HAL_I2C_MODULE_ENABLED - /* #define HAL_I2S_MODULE_ENABLED */ - /* #define HAL_IWDG_MODULE_ENABLED */ - /* #define HAL_LTDC_MODULE_ENABLED */ -diff --git a/Firmware/Board/v3/Src/i2c.c b/Firmware/Board/v3/Src/i2c.c -new file mode 100644 -index 0000000..bae77f1 ---- /dev/null -+++ b/Firmware/Board/v3/Src/i2c.c -@@ -0,0 +1,198 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.c -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "i2c.h" -+ -+#include "gpio.h" -+#include "dma.h" -+ -+/* USER CODE BEGIN 0 */ -+ -+/* USER CODE END 0 */ -+ -+I2C_HandleTypeDef hi2c1; -+DMA_HandleTypeDef hdma_i2c1_rx; -+DMA_HandleTypeDef hdma_i2c1_tx; -+ -+/* I2C1 init function */ -+void MX_I2C1_Init(uint8_t addr) -+{ -+ -+ hi2c1.Instance = I2C1; -+ hi2c1.Init.ClockSpeed = 100000; -+ hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; -+ hi2c1.Init.OwnAddress1 = addr << 1; -+ hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; -+ hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; -+ hi2c1.Init.OwnAddress2 = 0; -+ hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; -+ hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; -+ if (HAL_I2C_Init(&hi2c1) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+} -+ -+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ GPIO_InitTypeDef GPIO_InitStruct; -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspInit 0 */ -+ -+ /* USER CODE END I2C1_MspInit 0 */ -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; -+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; -+ GPIO_InitStruct.Pull = GPIO_PULLUP; -+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; -+ GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; -+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); -+ -+ /* I2C1 clock enable */ -+ __HAL_RCC_I2C1_CLK_ENABLE(); -+ -+ /* I2C1 DMA Init */ -+ /* I2C1_RX Init */ -+ hdma_i2c1_rx.Instance = DMA1_Stream0; -+ hdma_i2c1_rx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; -+ hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.Mode = DMA_CIRCULAR; -+ hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c1_rx); -+ -+ /* I2C1_TX Init */ -+ hdma_i2c1_tx.Instance = DMA1_Stream6; -+ hdma_i2c1_tx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; -+ hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.Mode = DMA_NORMAL; -+ hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c1_tx); -+ -+ /* I2C1 interrupt Init */ -+ HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspInit 1 */ -+ -+ /* USER CODE END I2C1_MspInit 1 */ -+ } -+} -+ -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspDeInit 0 */ -+ -+ /* USER CODE END I2C1_MspDeInit 0 */ -+ /* Peripheral clock disable */ -+ __HAL_RCC_I2C1_CLK_DISABLE(); -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); -+ -+ /* I2C1 DMA DeInit */ -+ HAL_DMA_DeInit(i2cHandle->hdmarx); -+ HAL_DMA_DeInit(i2cHandle->hdmatx); -+ -+ /* I2C1 interrupt Deinit */ -+ HAL_NVIC_DisableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_DisableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspDeInit 1 */ -+ -+ /* USER CODE END I2C1_MspDeInit 1 */ -+ } -+} -+ -+/* USER CODE BEGIN 1 */ -+ -+/* USER CODE END 1 */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c -index 987e0bd..efaeef1 100644 ---- a/Firmware/Board/v3/Src/main.c -+++ b/Firmware/Board/v3/Src/main.c -@@ -187,7 +187,6 @@ int main(void) - MX_ADC3_Init(); - MX_TIM2_Init(); - MX_UART4_Init(); -- MX_CAN1_Init(); - /* USER CODE BEGIN 2 */ - - //Required to use OC4 for ADC triggering. --- -2.17.0 - diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 00000000..5452a507 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +}I2C_InitTypeDef; + +/** + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +}HAL_I2C_StateTypeDef; + +/** + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +}HAL_I2C_ModeTypeDef; + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + +}I2C_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_Error_Code I2C Error Code + * @brief I2C Error Code + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_SMBALERT 0x00018000U +#define I2C_FLAG_TIMEOUT 0x00014000U +#define I2C_FLAG_PECERR 0x00011000U +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_SMBHOST 0x00100040U +#define I2C_FLAG_SMBDEFAULT 0x00100020U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_SMBHOST: SMBus host header + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ + ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) + +/** @brief Disable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions *****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State, Mode and Errors functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 00000000..ff47d5cc --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,137 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ + STM32F413xx || STM32F423xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 00000000..da185200 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,5494 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx Stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup I2C_Private_Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and create the associated handle. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange = 0U; + uint32_t pclk1 = 0U; + + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->CR2 = freqrange; + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2C peripheral. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief I2C MSP Init. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2C MSP DeInit + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Master_Sequential_Transmit_IT() + (++) HAL_I2C_Master_Sequential_Receive_IT() + (++) HAL_I2C_Slave_Sequential_Transmit_IT() + (++) HAL_I2C_Slave_Sequential_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* Generate Start */ + if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize== 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if(hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0x00U; + __IO uint32_t count = 0U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(Size == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; + + /* Get tick */ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + }while(I2C_Trials++ < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + uint32_t CurrentMode = hi2c->Mode; + + /* Master or Memory mode selected */ + if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* SB Set ----------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + + /* I2C in mode Transmitter -----------------------------------------------*/ + if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + } + } + /* Slave mode selected */ + else + { + /* ADDR set --------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_ADDR(hi2c); + } + /* STOPF set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ + if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + tmp1 = hi2c->Mode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback can be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback can be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Return the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if(hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0) + { + /* If Memory address size is 8Bit */ + if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if(hi2c->EventCount == 1) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if(hi2c->EventCount == 2) + { + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp = 0U; + + tmp = hi2c->XferCount; + if(tmp > 3U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if(hi2c->XferCount == 3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if((tmp == 1U) || (tmp == 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + else + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if(hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + return HAL_OK; +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; + } + else + { + if(hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferCount == 1U) + { + if(CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + /* Prepare next transfer or stop current transfer */ + else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + else if(hi2c->XferCount == 2U) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + return HAL_OK; +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Tx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode = 0U; + + /* Transfer Direction requested by Master */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = hi2c->Init.OwnAddress2; + } + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); + + return HAL_OK; +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* If a DMA is ongoing, Update handle size context */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + else + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ + (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else + { + if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else if(CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + + return HAL_OK; +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) + { + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + /* Abort DMA transfer */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Call user error callback */ + HAL_I2C_ErrorCallback(hi2c); + } + /* STOP Flag is not set after a NACK reception */ + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Disable Last DMA */ + hi2c->Instance->CR2 &= ~I2C_CR2_LAST; + + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Ignore DMA FIFO error */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 00000000..de8f1602 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,204 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ + STM32F423xx */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h index e518489f..ed26bf39 100644 --- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h +++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c index e390af58..154c98af 100644 --- a/Firmware/Board/v3/Src/main.c +++ b/Firmware/Board/v3/Src/main.c @@ -180,7 +180,7 @@ int main(void) MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); - MX_CAN1_Init(); + // MX_CAN1_Init(); // CAN or I2C called in main.cpp instead MX_TIM1_Init(); MX_TIM8_Init(); MX_TIM3_Init(); From 9d4456eee6e4e9e8ff2d7307fe71e344e61fcd2c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:08:08 -0700 Subject: [PATCH 066/106] Cube: Notify OS that we are a composite device --- Firmware/Board/v3/Src/usbd_desc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index b0906144..d213f64a 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -97,7 +97,8 @@ #define USBD_PID_FS 0x0D32 #define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) #define USBD_PRODUCT_STR(s) #s -#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR +#define USBD_PRODUCT_STRING_FS ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR CDC Interface +#define NATIVE_STRING ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR Native Interface #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -233,16 +234,17 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = 0x00, /*bcdUSB */ #endif /* (USBD_LPM_ENABLED == 1) */ 0x02, - 0x02, /*bDeviceClass*/ + // Notify OS that this is a composite device + 0xEF, /*bDeviceClass*/ 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ + 0x01, /*bDeviceProtocol*/ USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ LOBYTE(USBD_VID), /*idVendor*/ HIBYTE(USBD_VID), /*idVendor*/ LOBYTE(USBD_PID_FS), /*idProduct*/ HIBYTE(USBD_PID_FS), /*idProduct*/ 0x00, /*bcdDevice rel. 2.00*/ - 0x02, + 0x03, /* bNumInterfaces */ USBD_IDX_MFC_STR, /*Index of manufacturer string*/ USBD_IDX_PRODUCT_STR, /*Index of product string*/ USBD_IDX_SERIAL_STR, /*Index of serial number string*/ From 9bd3d0b53c2adb9c03bae29e30fd32224ff3f6ea Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:51:04 -0700 Subject: [PATCH 067/106] cube: apply canges to USB --- Firmware/Board/v3/Inc/usbd_cdc_if.h | 2 +- Firmware/Board/v3/Inc/usbd_conf.h | 1 + Firmware/Board/v3/Inc/usbd_desc.h | 3 +- .../Class/CDC/Inc/usbd_cdc.h | 39 +- .../Class/CDC/Src/usbd_cdc.c | 562 +++++++++++------- .../Core/Inc/usbd_def.h | 4 +- Firmware/Board/v3/Src/usbd_cdc_if.c | 12 +- Firmware/Board/v3/Src/usbd_conf.c | 24 +- 8 files changed, 404 insertions(+), 243 deletions(-) diff --git a/Firmware/Board/v3/Inc/usbd_cdc_if.h b/Firmware/Board/v3/Inc/usbd_cdc_if.h index c15e8b91..ed1d6705 100644 --- a/Firmware/Board/v3/Inc/usbd_cdc_if.h +++ b/Firmware/Board/v3/Inc/usbd_cdc_if.h @@ -132,7 +132,7 @@ extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; * @{ */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair); /* USER CODE BEGIN EXPORTED_FUNCTIONS */ /* USER CODE END EXPORTED_FUNCTIONS */ diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index bf276186..a897ba43 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -89,6 +89,7 @@ * @brief Defines for configuration of the Usb device. * @{ */ + #define MS_VendorCode 'P' /*---------- -----------*/ #define USBD_MAX_NUM_INTERFACES 1 diff --git a/Firmware/Board/v3/Inc/usbd_desc.h b/Firmware/Board/v3/Inc/usbd_desc.h index 18d1f34e..2a74de31 100644 --- a/Firmware/Board/v3/Inc/usbd_desc.h +++ b/Firmware/Board/v3/Inc/usbd_desc.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.h * @version : v1.0_Cube - * @brief : Header for usbd_conf.c file. + * @brief : Header for usbd_desc.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -46,6 +46,7 @@ * ****************************************************************************** */ + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__H__ #define __USBD_DESC__H__ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index d937b2e8..c029e22a 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -52,13 +52,15 @@ #define CDC_IN_EP 0x81 /* EP1 for data IN */ #define CDC_OUT_EP 0x01 /* EP1 for data OUT */ #define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ +#define ODRIVE_IN_EP 0x83 /* EP3 IN: ODrive device TX endpoint */ +#define ODRIVE_OUT_EP 0x03 /* EP3 OUT: ODrive device RX endpoint */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ -#define USB_CDC_CONFIG_DESC_SIZ 67 +#define USB_CDC_CONFIG_DESC_SIZ (67 + 39) #define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE #define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE @@ -103,23 +105,29 @@ typedef struct _USBD_CDC_Itf int8_t (* Init) (void); int8_t (* DeInit) (void); int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); + int8_t (* Receive) (uint8_t *, uint32_t *, uint8_t); }USBD_CDC_ItfTypeDef; +typedef struct +{ + uint8_t* Buffer; + uint32_t Length; + volatile uint8_t State; +} +USBD_CDC_EP_HandleTypeDef; typedef struct { uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; + uint8_t CmdLength; + + USBD_CDC_EP_HandleTypeDef CDC_Tx; + USBD_CDC_EP_HandleTypeDef CDC_Rx; + + USBD_CDC_EP_HandleTypeDef ODRIVE_Tx; + USBD_CDC_EP_HandleTypeDef ODRIVE_Rx; } USBD_CDC_HandleTypeDef; @@ -151,14 +159,15 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length); + uint16_t length, + uint8_t endpoint_pair); uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); + uint8_t *pbuff, uint8_t endpoint_pair); -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 24465641..73313522 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -132,6 +132,9 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +//static uint8_t * USBD_GetUsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); + /* USB Standard Device Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { @@ -173,24 +176,37 @@ USBD_ClassTypeDef USBD_CDC = USBD_CDC_GetFSCfgDesc, USBD_CDC_GetOtherSpeedCfgDesc, USBD_CDC_GetDeviceQualifierDescriptor, + USBD_UsrStrDescriptor }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { /*Configuration Descriptor*/ 0x09, /* bLength: Configuration Descriptor size */ USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ + 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 custom) */ 0x01, /* bConfigurationValue: Configuration value */ 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ 0xC0, /* bmAttributes: self powered */ 0x32, /* MaxPower 0 mA */ + + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: CDC device (virtual com port) */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass: Communication Interface Class */ + 0x02, /* bFunctionSubClass: Abstract Control Model */ + 0x01, /* bFunctionProtocol: Common AT commands */ + 0x00, /* iFunction */ /*---------------------------------------------------------------------------*/ - + /*Interface Descriptor */ 0x09, /* bLength: Interface Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ @@ -202,7 +218,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bInterfaceSubClass: Abstract Control Model */ 0x01, /* bInterfaceProtocol: Common AT commands */ 0x00, /* iInterface: */ - + /*Header Functional Descriptor*/ 0x05, /* bLength: Endpoint Descriptor size */ 0x24, /* bDescriptorType: CS_INTERFACE */ @@ -229,7 +245,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x06, /* bDescriptorSubtype: Union func desc */ 0x00, /* bMasterInterface: Communication class interface */ 0x01, /* bSlaveInterface0: Data Class Interface */ - + /*Endpoint 2 Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ @@ -267,196 +283,52 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00, /* bInterval: ignore for Bulk transfer */ + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: custom device */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x02, /* bFirstInterface */ + 0x01, /* bInterfaceCount */ + 0x00, /* bFunctionClass: */ + 0x00, /* bFunctionSubClass: */ + 0x00, /* bFunctionProtocol: */ + 0x06, /* iFunction */ -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ /*---------------------------------------------------------------------------*/ /*Data class interface descriptor*/ 0x09, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ + 0x02, /* bInterfaceNumber: Number of Interface */ 0x00, /* bAlternateSetting: Alternate setting */ 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceClass: vendor specific */ + 0x01, /* bInterfaceSubClass: ODrive Communication */ 0x00, /* bInterfaceProtocol: */ 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ + ODRIVE_OUT_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ + ODRIVE_IN_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ } ; -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; /** * @} @@ -508,6 +380,19 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, USBD_EP_TYPE_BULK, CDC_DATA_FS_OUT_PACKET_SIZE); } + + /* Open ODrive IN endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_IN_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_IN_PACKET_SIZE : CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open ODrive OUT endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_OUT_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + /* Open Command IN EP */ USBD_LL_OpenEP(pdev, CDC_CMD_EP, @@ -529,15 +414,17 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; + hcdc->CDC_Tx.State =0; + hcdc->CDC_Rx.State =0; + hcdc->ODRIVE_Tx.State =0; + hcdc->ODRIVE_Rx.State =0; if(pdev->dev_speed == USBD_SPEED_HIGH ) { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_HS_OUT_PACKET_SIZE); } else @@ -545,11 +432,15 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_FS_OUT_PACKET_SIZE); } - + /* Prepare ODrive Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + ODRIVE_OUT_EP, + hcdc->ODRIVE_Rx.Buffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } return ret; } @@ -566,17 +457,25 @@ static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, { uint8_t ret = 0; - /* Open EP IN */ + /* Close EP IN */ USBD_LL_CloseEP(pdev, CDC_IN_EP); - /* Open EP OUT */ + /* Close EP OUT */ USBD_LL_CloseEP(pdev, CDC_OUT_EP); - /* Open Command IN EP */ + /* Close Command IN EP */ USBD_LL_CloseEP(pdev, CDC_CMD_EP); + + /* Close EP IN */ + USBD_LL_CloseEP(pdev, + ODRIVE_IN_EP); + + /* Close EP OUT */ + USBD_LL_CloseEP(pdev, + ODRIVE_OUT_EP); /* DeInit physical Interface components */ @@ -648,6 +547,9 @@ static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, case USB_REQ_SET_INTERFACE : break; } + + case USB_REQ_TYPE_VENDOR: + return USBD_WinUSBComm_SetupVendor(pdev, req); default: break; @@ -668,8 +570,12 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) if(pdev->pClassData != NULL) { - - hcdc->TxState = 0; + // NOTE: We would logically expect xx_IN_EP here, but we actually get the xx_OUT_EP + if (epnum == CDC_OUT_EP) + hcdc->CDC_Tx.State = 0; + if (epnum == ODRIVE_OUT_EP) + hcdc->ODRIVE_Tx.State = 0; + //Note: We could use independent semaphores for simoultainous USB transmission. osSemaphoreRelease(sem_usb_tx); return USBD_OK; } @@ -689,15 +595,24 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (epnum == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (epnum == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + hEP_Rx->Length = USBD_LL_GetRxDataSize (pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ if(pdev->pClassData != NULL) { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hEP_Rx->Buffer, &hEP_Rx->Length, epnum); return USBD_OK; } @@ -740,8 +655,8 @@ static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) */ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -753,8 +668,8 @@ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -766,8 +681,8 @@ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -810,12 +725,22 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, */ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length) + uint16_t length, + uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + } else { + return USBD_FAIL; + } + + hEP_Tx->Buffer = pbuff; + hEP_Tx->Length = length; return USBD_OK; } @@ -828,11 +753,20 @@ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, * @retval status */ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) + uint8_t *pbuff, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } - hcdc->RxBuffer = pbuff; + hEP_Rx->Buffer = pbuff; return USBD_OK; } @@ -844,23 +778,36 @@ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, * @param epnum: endpoint number * @retval status */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; if(pdev->pClassData != NULL) { - if(hcdc->TxState == 0) + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + uint8_t in_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + in_ep = CDC_IN_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + in_ep = ODRIVE_IN_EP; + } else { + return USBD_FAIL; + } + + if(hEP_Tx->State == 0) { /* Tx Transfer in progress */ - hcdc->TxState = 1; + hEP_Tx->State = 1; /* Transmit next packet */ USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - + in_ep, + hEP_Tx->Buffer, + hEP_Tx->Length); + return USBD_OK; } else @@ -881,29 +828,32 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; /* Suspend or Resume USB Out process */ if(pdev->pClassData != NULL) { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + uint8_t out_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + out_ep = CDC_OUT_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + out_ep = ODRIVE_OUT_EP; + } else { + return USBD_FAIL; } + + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + out_ep, + hEP_Rx->Buffer, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + return USBD_OK; } else @@ -911,6 +861,184 @@ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) return USBD_FAIL; } } + + +/* WinUSB support ------------------------------------------------------------*/ +/* +* This section tells Windows that it should automatically load the WinUSB driver +* for the device (more specifically, interface 2 because it's a composite device). +* This allows for driverless communication with the device. +*/ + +#define NUM_INTERFACES 1 + +#if NUM_INTERFACES == 2 +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24 + 24) +#else +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24) +#endif + + +// This associates winusb driver with the device +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Compat_ID_OS_Desc[USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ] __ALIGN_END = +{ + // +-- Offset in descriptor + // | +-- Size + // v v + USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ, 0, 0, 0, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended compat ID descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x04, 0x00, // 6 wIndex 2 WORD An index that identifies the particular OS feature descriptor + NUM_INTERFACES, // 8 bCount 1 BYTE The number of custom property sections + 0, 0, 0, 0, 0, 0, 0, // 9 RESERVED 7 BYTEs Reserved + // ===================== + // 16 + + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#if NUM_INTERFACES == 2 + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#endif +}; + + +// Properties are added to: +// HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Enum\USB\VID_xxxx&PID_xxxx\sssssssss\Device Parameters +// Use USBDeview or similar to uninstall + +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Properties_OS_Desc[0xB6] __ALIGN_END = +{ + 0xB6, 0x00, 0x00, 0x00, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended properties descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x05, 0x00, // 6 wIndex 2 WORD The index for extended properties OS descriptors + 0x02, 0x00, // 8 wCount 2 WORD The number of custom property sections that follow the header section + // ==================== + // 10 +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, // 0 dwSize 4 DWORD The size of this custom properties section + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 4 DWORD Property data format + 0x28, 0x00, // 8 wPropertyNameLength 2 DWORD Property name length + // ======================================== + // 10 + // 10 bPropertyName PNL WCHAR[] The property name + 'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0, + 't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0, + 'U',0, 'I',0, 'D',0, 0,0, + // ======================================== + // 40 (0x28) + + 0x4E, 0x00, 0x00, 0x00, // 10 + PNL dwPropertyDataLength 4 DWORD Length of the buffer holding the property data + // ======================================== + // 4 + // 14 + PNL bPropertyData PDL Format-dependent Property data + '{',0, 'E',0, 'A',0, '0',0, 'B',0, 'D',0, '5',0, 'C',0, + '3',0, '-',0, '5',0, '0',0, 'F',0, '3',0, '-',0, '4',0, + '8',0, '8',0, '8',0, '-',0, '8',0, '4',0, 'B',0, '4',0, + '-',0, '7',0, '4',0, 'E',0, '5',0, '0',0, 'E',0, '1',0, + '6',0, '4',0, '9',0, 'D',0, 'B',0, '}',0, 0 ,0, + // ======================================== + // 78 (0x4E) +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x3E, 0x00, 0x00, 0x00, // 0 dwSize 0x00000030 (62 bytes) + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 0x00000001 (Unicode string) + 0x0C, 0x00, // 8 wPropertyNameLength 0x000C (12 bytes) + // ======================================== + // 10 + 'L',0, 'a',0, 'b',0, 'e',0, 'l',0, 0,0, + // 10 bPropertyName “Label” + // ======================================== + // 12 + 0x24, 0x00, 0x00, 0x00, // 22 dwPropertyDataLength 0x00000016 (36 bytes) + // ======================================== + // 4 + 'O',0, 'D',0, 'r',0, 'i',0, 'v',0, 'e',0, 0,0 + // 26 bPropertyData “ODrive” + // ======================================== + // 14 + +}; + + + +static uint8_t USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (req->wIndex) + { + case 0x04: + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Compat_ID_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + uint8_t byInterfaceIndex = (uint8_t)req->wValue; + if ( req->wIndex != 0x05 ) + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + switch ( byInterfaceIndex ) + { + case 0: +#if NUM_INTERFACES == 2 + case 1: +#endif + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Properties_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_SetupVendorDevice(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendorInterface(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + // TODO: check if this is important + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch ( req->bmRequest & USB_REQ_RECIPIENT_MASK ) + { + case USB_REQ_RECIPIENT_DEVICE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorDevice(pdev, req); + case USB_REQ_RECIPIENT_INTERFACE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorInterface(pdev, req); + case USB_REQ_RECIPIENT_ENDPOINT: + // fall through + default: + break; + } + USBD_CtlError(pdev , req); + return USBD_FAIL; +} + /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index 8fbe81e4..f259b51d 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -68,7 +68,9 @@ #define USBD_IDX_PRODUCT_STR 0x02 #define USBD_IDX_SERIAL_STR 0x03 #define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_ODRIVE_INTF_STR 0x06 +#define USBD_IDX_MICROSOFT_DESC_STR 0xEE #define USB_REQ_TYPE_STANDARD 0x00 #define USB_REQ_TYPE_CLASS 0x20 diff --git a/Firmware/Board/v3/Src/usbd_cdc_if.c b/Firmware/Board/v3/Src/usbd_cdc_if.c index fcc712a3..b8cb6e6c 100644 --- a/Firmware/Board/v3/Src/usbd_cdc_if.c +++ b/Firmware/Board/v3/Src/usbd_cdc_if.c @@ -117,10 +117,12 @@ /* Create buffer for reception and transmission */ /* It's up to user to redefine and/or remove those define */ /** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t CDCRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t ODRIVERxBufferFS[APP_RX_DATA_SIZE]; /** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t CDCTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t ODRIVETxBufferFS[APP_TX_DATA_SIZE]; /* USER CODE BEGIN PRIVATE_VARIABLES */ /* USER CODE END PRIVATE_VARIABLES */ @@ -151,7 +153,7 @@ extern USBD_HandleTypeDef hUsbDeviceFS; static int8_t CDC_Init_FS(void); static int8_t CDC_DeInit_FS(void); static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len, uint8_t endpoint_pair); /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ @@ -289,7 +291,7 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair) { /* USER CODE BEGIN 6 */ usb_rx_process_packet(Buf, *Len, endpoint_pair); @@ -309,7 +311,7 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair) { uint8_t result = USBD_OK; /* USER CODE BEGIN 7 */ diff --git a/Firmware/Board/v3/Src/usbd_conf.c b/Firmware/Board/v3/Src/usbd_conf.c index 7046dc96..2d66d4a1 100644 --- a/Firmware/Board/v3/Src/usbd_conf.c +++ b/Firmware/Board/v3/Src/usbd_conf.c @@ -66,7 +66,7 @@ /* USER CODE END PV */ - PCD_HandleTypeDef hpcd_USB_OTG_FS; +PCD_HandleTypeDef hpcd_USB_OTG_FS; void _Error_Handler(char * file, int line); /* External functions --------------------------------------------------------*/ @@ -154,6 +154,23 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) */ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { + USBD_StatusTypeDef ret = USBD_OK; + USBD_HandleTypeDef *pdev = hpcd->pData; + USBD_SetupReqTypedef *req = &pdev->request; + USBD_ParseSetupRequest(req, (uint8_t *)hpcd->Setup); + if ( ( USB_REQ_TYPE_VENDOR == (req->bmRequest & USB_REQ_TYPE_MASK) ) && ( MS_VendorCode == req->bRequest ) ) + { + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + ret = pdev->pClass->Setup(pdev, req); + + if( (req->wLength == 0) && (ret == USBD_OK) ) + { + USBD_CtlSendStatus(pdev); + } + return; + } USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); } @@ -312,7 +329,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) pdev->pData = &hpcd_USB_OTG_FS; hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; @@ -329,7 +346,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // CDC IN endpoint + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // ODrive IN endpoint } return USBD_OK; } From 47acbe3d30d965a5195cd9aac32408d9582fabbc Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:52:53 -0700 Subject: [PATCH 068/106] cube: can auto wake up --- Firmware/Board/v3/Src/can.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index 2171691a..fc7bf388 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -70,7 +70,7 @@ void MX_CAN1_Init(void) hcan1.Init.TimeSeg2 = CAN_BS2_5TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoWakeUp = ENABLE; hcan1.Init.AutoRetransmission = DISABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; From 536bfce2ed9ec76f1353eae8cb57dd3df6a0d878 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:25:50 -0700 Subject: [PATCH 069/106] move configAPPLICATION_ALLOCATED_HEAP to FreeRTOSconfig.h --- Firmware/Board/v3/Inc/FreeRTOSConfig.h | 1 + Firmware/Board/v3/Inc/main.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h | 1 - Firmware/Board/v3/Odrive.ioc | 2 +- 5 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Inc/FreeRTOSConfig.h b/Firmware/Board/v3/Inc/FreeRTOSConfig.h index 90e233b3..715b0e67 100644 --- a/Firmware/Board/v3/Inc/FreeRTOSConfig.h +++ b/Firmware/Board/v3/Inc/FreeRTOSConfig.h @@ -167,6 +167,7 @@ standard names. */ /* USER CODE BEGIN Defines */ /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +#define configAPPLICATION_ALLOCATED_HEAP 1 // ucHeap allocated in freertos.c /* USER CODE END Defines */ #endif /* FREERTOS_CONFIG_H */ diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 1e76830d..d41b19ee 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -72,7 +72,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h index 567fe028..65f45efd 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h index 5695d700..64daaa4f 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index d18c5f86..9f636781 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -211,7 +211,7 @@ Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 -Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 +Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx MxCube.Version=4.27.0 MxDb.Version=DB.4.0.270 From c968f21f44735c59ec5a2a5b68480ff2df96be84 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:32:54 -0700 Subject: [PATCH 070/106] cube: support user string --- Firmware/Board/v3/Inc/usbd_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index a897ba43..dbf800b3 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -98,7 +98,7 @@ /*---------- -----------*/ #define USBD_MAX_STR_DESC_SIZ 512 /*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 +#define USBD_SUPPORT_USER_STRING 1 /*---------- -----------*/ #define USBD_DEBUG_LEVEL 0 /*---------- -----------*/ From f22199bf95f38592688201e2cecbe34e89c18905 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:58:41 -0700 Subject: [PATCH 071/106] merge is ugly but is confirmed working --- docs/developer-guide.md | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/developer-guide.md b/docs/developer-guide.md index d6243b5b..ecf3e1ea 100644 --- a/docs/developer-guide.md +++ b/docs/developer-guide.md @@ -183,7 +183,6 @@ How to use these is shown in the following example. * Make sure the rebase finishes, fixing any conflicts that may arise ### 4. Merge new STM32CubeMX code to your feature branch -**TODO: Nobody has done this yet, these instructions are new. Please verify that this works as intended.** Simply merge the new state at `STM32CubeMX-end` into your feature branch. * `git checkout your-feature` * `git merge STM32CubeMX-end` From 7800d7cc9bebfb7838ece5888ba1efe3531c3497 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 19:58:41 -0700 Subject: [PATCH 072/106] merge is ugly but is confirmed working --- docs/developer-guide.md | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/developer-guide.md b/docs/developer-guide.md index d6243b5b..ecf3e1ea 100644 --- a/docs/developer-guide.md +++ b/docs/developer-guide.md @@ -183,7 +183,6 @@ How to use these is shown in the following example. * Make sure the rebase finishes, fixing any conflicts that may arise ### 4. Merge new STM32CubeMX code to your feature branch -**TODO: Nobody has done this yet, these instructions are new. Please verify that this works as intended.** Simply merge the new state at `STM32CubeMX-end` into your feature branch. * `git checkout your-feature` * `git merge STM32CubeMX-end` From 1511ae1db79d8c8621e8082b2c8aea2aefd71f0c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 21:56:02 -0700 Subject: [PATCH 073/106] use tim13 as realtime control diagnostic timebase --- Firmware/Board/v3/Src/tim.c | 2 +- Firmware/MotorControl/low_level.cpp | 25 ++++++++++++++++--------- Firmware/MotorControl/low_level.h | 3 ++- Firmware/MotorControl/motor.cpp | 9 ++------- 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/Firmware/Board/v3/Src/tim.c b/Firmware/Board/v3/Src/tim.c index bd27e5f5..97205c15 100644 --- a/Firmware/Board/v3/Src/tim.c +++ b/Firmware/Board/v3/Src/tim.c @@ -382,7 +382,7 @@ void MX_TIM13_Init(void) htim13.Instance = TIM13; htim13.Init.Prescaler = 0; htim13.Init.CounterMode = TIM_COUNTERMODE_UP; - htim13.Init.Period = (2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1)) * (TIM_APB1_CLOCK_HZ / TIM_1_8_CLOCK_HZ); + htim13.Init.Period = (2 * TIM_1_8_PERIOD_CLOCKS * (TIM_1_8_RCR+1)) * ((float)TIM_APB1_CLOCK_HZ / (float)TIM_1_8_CLOCK_HZ) - 1; htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; if (HAL_TIM_Base_Init(&htim13) != HAL_OK) { diff --git a/Firmware/MotorControl/low_level.cpp b/Firmware/MotorControl/low_level.cpp index d807dc33..5bc256ae 100644 --- a/Firmware/MotorControl/low_level.cpp +++ b/Firmware/MotorControl/low_level.cpp @@ -216,7 +216,8 @@ void start_adc_pwm() { start_pwm(&htim1); start_pwm(&htim8); // TODO: explain why this offset - sync_timers(&htim1, &htim8, TIM_CLOCKSOURCE_ITR0, TIM_1_8_PERIOD_CLOCKS / 2 - 1 * 128); + sync_timers(&htim1, &htim8, TIM_CLOCKSOURCE_ITR0, TIM_1_8_PERIOD_CLOCKS / 2 - 1 * 128, + &htim13); // Motor output starts in the disabled state __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(&htim1); @@ -259,7 +260,8 @@ void start_pwm(TIM_HandleTypeDef* htim) { } void sync_timers(TIM_HandleTypeDef* htim_a, TIM_HandleTypeDef* htim_b, - uint16_t TIM_CLOCKSOURCE_ITRx, uint16_t count_offset) { + uint16_t TIM_CLOCKSOURCE_ITRx, uint16_t count_offset, + TIM_HandleTypeDef* htim_refbase) { // Store intial timer configs uint16_t MOE_store_a = htim_a->Instance->BDTR & (TIM_BDTR_MOE); uint16_t MOE_store_b = htim_b->Instance->BDTR & (TIM_BDTR_MOE); @@ -294,6 +296,11 @@ void sync_timers(TIM_HandleTypeDef* htim_a, TIM_HandleTypeDef* htim_b, // set counter offset htim_a->Instance->CNT = count_offset; htim_b->Instance->CNT = 0; + // Set and start reference timebase timer (if used) + if (htim_refbase) { + htim_refbase->Instance->CNT = count_offset; + htim_refbase->Instance->CR1 |= (TIM_CR1_CEN); // start + } // Start Timer a htim_a->Instance->CR1 |= (TIM_CR1_CEN); // Restore timer configs @@ -475,8 +482,14 @@ void pwm_trig_adc_cb(ADC_HandleTypeDef* hadc, bool injected) { int axis_num = injected ? 0 : 1; Axis& other_axis = injected ? *axes[1] : *axes[0]; bool counting_down = axis.motor_.hw_config_.timer->Instance->CR1 & TIM_CR1_DIR; - bool current_meas_not_DC_CAL = !counting_down; + + // Check the timing of the sequencing + if (current_meas_not_DC_CAL) + axis.motor_.log_timing(Motor::TIMING_LOG_ADC_CB_I); + else + axis.motor_.log_timing(Motor::TIMING_LOG_ADC_CB_DC); + bool update_timings = false; if (hadc == &hadc2) { if (&axis == axes[1] && counting_down) @@ -503,12 +516,6 @@ void pwm_trig_adc_cb(ADC_HandleTypeDef* hadc, bool injected) { update_brake_current(); } - // Check the timing of the sequencing - if (current_meas_not_DC_CAL) - axis.motor_.log_timing(Motor::TIMING_LOG_ADC_CB_I); - else - axis.motor_.log_timing(Motor::TIMING_LOG_ADC_CB_DC); - uint32_t ADCValue; if (injected) { ADCValue = HAL_ADCEx_InjectedGetValue(hadc, ADC_INJECTED_RANK_1); diff --git a/Firmware/MotorControl/low_level.h b/Firmware/MotorControl/low_level.h index 605db9ba..3a3225de 100644 --- a/Firmware/MotorControl/low_level.h +++ b/Firmware/MotorControl/low_level.h @@ -46,7 +46,8 @@ void pwm_in_cb(int channel, uint32_t timestamp); void start_adc_pwm(); void start_pwm(TIM_HandleTypeDef* htim); void sync_timers(TIM_HandleTypeDef* htim_a, TIM_HandleTypeDef* htim_b, - uint16_t TIM_CLOCKSOURCE_ITRx, uint16_t count_offset); + uint16_t TIM_CLOCKSOURCE_ITRx, uint16_t count_offset, + TIM_HandleTypeDef* htim_refbase = nullptr); void start_general_purpose_adc(); float get_adc_voltage(GPIO_TypeDef* GPIO_port, uint16_t GPIO_pin); void pwm_in_init(); diff --git a/Firmware/MotorControl/motor.cpp b/Firmware/MotorControl/motor.cpp index 230f7f64..5585a862 100644 --- a/Firmware/MotorControl/motor.cpp +++ b/Firmware/MotorControl/motor.cpp @@ -149,13 +149,8 @@ bool Motor::do_checks() { } void Motor::log_timing(TimingLog_t log_idx) { - TIM_HandleTypeDef* htim = hw_config_.timer; - uint16_t timing = htim->Instance->CNT; - bool down = htim->Instance->CR1 & TIM_CR1_DIR; - if (down) { - uint16_t delta = TIM_1_8_PERIOD_CLOCKS - timing; - timing = TIM_1_8_PERIOD_CLOCKS + delta; - } + static const uint16_t clocks_per_cnt = (uint16_t)((float)TIM_1_8_CLOCK_HZ / (float)TIM_APB1_CLOCK_HZ); + uint16_t timing = clocks_per_cnt * htim13.Instance->CNT; // TODO: Use a hw_config if (log_idx < TIMING_LOG_NUM_SLOTS) { timing_log_[log_idx] = timing; From b4fcb290a450b5acf957e85049529a67d7554e18 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 23:57:42 -0700 Subject: [PATCH 074/106] add overspeed fault --- CHANGELOG.md | 3 +++ Firmware/MotorControl/controller.cpp | 13 +++++++++++++ Firmware/MotorControl/controller.hpp | 16 ++++++++++++++-- Firmware/MotorControl/encoder.cpp | 2 +- 4 files changed, 31 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 2d918843..34e7ada3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,9 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. +### Added +* Overspeed fault + ### Changed * Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. * Renamed `axis.enable_step_dir` to `axis.step_dir_active` diff --git a/Firmware/MotorControl/controller.cpp b/Firmware/MotorControl/controller.cpp index bf50a15a..8c202ae0 100644 --- a/Firmware/MotorControl/controller.cpp +++ b/Firmware/MotorControl/controller.cpp @@ -13,6 +13,11 @@ void Controller::reset() { current_setpoint_ = 0.0f; } +void Controller::set_error(Error_t error) { + error_ |= error; + axis_->error_ |= Axis::ERROR_CONTROLLER_FAILED; +} + //-------------------------------- // Command Handling //-------------------------------- @@ -126,6 +131,14 @@ bool Controller::update(float pos_estimate, float vel_estimate, float* current_s if (vel_des > vel_lim) vel_des = vel_lim; if (vel_des < -vel_lim) vel_des = -vel_lim; + // Check for overspeed fault (done in this module (controller) for cohesion with vel_lim) + if (config_.vel_limit_tolerance > 0.0f) { // 0.0f to disable + if (fabsf(vel_estimate) > config_.vel_limit_tolerance * vel_lim) { + set_error(ERROR_OVERSPEED); + return false; + } + } + // Velocity control float Iq = current_setpoint_; diff --git a/Firmware/MotorControl/controller.hpp b/Firmware/MotorControl/controller.hpp index 3db712e4..f99f25d4 100644 --- a/Firmware/MotorControl/controller.hpp +++ b/Firmware/MotorControl/controller.hpp @@ -7,6 +7,11 @@ class Controller { public: + enum Error_t { + ERROR_NONE = 0, + ERROR_OVERSPEED = 0x01, + }; + // Note: these should be sorted from lowest level of control to // highest level of control, to allow "<" style comparisons. enum ControlMode_t{ @@ -23,11 +28,13 @@ public: float vel_gain = 5.0f / 10000.0f; // [A/(counts/s)] // float vel_gain = 5.0f / 200.0f, // [A/(rad/s)] float vel_integrator_gain = 10.0f / 10000.0f; // [A/(counts/s * s)] - float vel_limit = 20000.0f; // [counts/s] + float vel_limit = 20000.0f; // [counts/s] + float vel_limit_tolerance = 1.2f; // ratio to vel_lim. 0.0f to disable }; Controller(Config_t& config); void reset(); + void set_error(Error_t error); void set_pos_setpoint(float pos_setpoint, float vel_feed_forward, float current_feed_forward); void set_vel_setpoint(float vel_setpoint, float current_feed_forward); @@ -68,6 +75,7 @@ public: .calib_vel_threshold = 1.0f, }; + Error_t error_ = ERROR_NONE; // variables exposed on protocol float pos_setpoint_ = 0.0f; float vel_setpoint_ = 0.0f; @@ -80,6 +88,7 @@ public: // Communication protocol definitions auto make_protocol_definitions() { return make_protocol_member_list( + make_protocol_property("error", &error_), make_protocol_property("pos_setpoint", &pos_setpoint_), make_protocol_property("vel_setpoint", &vel_setpoint_), make_protocol_property("vel_integrator_current", &vel_integrator_current_), @@ -89,7 +98,8 @@ public: make_protocol_property("pos_gain", &config_.pos_gain), make_protocol_property("vel_gain", &config_.vel_gain), make_protocol_property("vel_integrator_gain", &config_.vel_integrator_gain), - make_protocol_property("vel_limit", &config_.vel_limit) + make_protocol_property("vel_limit", &config_.vel_limit), + make_protocol_property("vel_limit_tolerance", &config_.vel_limit_tolerance) ), make_protocol_function("set_pos_setpoint", *this, &Controller::set_pos_setpoint, "pos_setpoint", "vel_feed_forward", "current_feed_forward"), @@ -103,4 +113,6 @@ public: } }; +DEFINE_ENUM_FLAG_OPERATORS(Controller::Error_t) + #endif // __CONTROLLER_HPP diff --git a/Firmware/MotorControl/encoder.cpp b/Firmware/MotorControl/encoder.cpp index f8e1e530..58926958 100644 --- a/Firmware/MotorControl/encoder.cpp +++ b/Firmware/MotorControl/encoder.cpp @@ -24,7 +24,7 @@ void Encoder::setup() { enc_index_cb_wrapper, this); } -void Encoder::set_error(Encoder::Error_t error) { +void Encoder::set_error(Error_t error) { error_ |= error; axis_->error_ |= Axis::ERROR_ENCODER_FAILED; } From 86f97555d8036970701759c5c38b0b217f93f0be Mon Sep 17 00:00:00 2001 From: metanoic <5554798+metanoic@users.noreply.github.com> Date: Thu, 25 Oct 2018 14:45:50 -0500 Subject: [PATCH 075/106] Hoverboard docs J2->J4 Pretty sure this should be J4 rather than J2, no? --- docs/hoverboard.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/hoverboard.md b/docs/hoverboard.md index be35e74d..2e9f6cf4 100644 --- a/docs/hoverboard.md +++ b/docs/hoverboard.md @@ -8,9 +8,9 @@ Each step is acompanied by some explanation so hopefully you can carry over some ### Hoverboard motor wiring Hoverboard motors come with three motor phases (usually colored yellow, blue, green) which are thicker, and a set of 5 thinner wires for the hall sensor feedback (usually colored red, yellow, blue, green, black). -You may wire the motor phases in any order into a motor connector on the ODrive, as we will calibrate the phase alignment later anyway. Wire the hall feedback into the ODrive J2 conenctor (make sure that the motor channel number matches) as follows: +You may wire the motor phases in any order into a motor connector on the ODrive, as we will calibrate the phase alignment later anyway. Wire the hall feedback into the ODrive J4 conenctor (make sure that the motor channel number matches) as follows: -| Hall wire | J2 signal | +| Hall wire | J4 signal | |-----------|-----------| | Red | 5V | | Yellow | A | From 138fd19d737e3f76155fc07ef957a26fdd176fe2 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 28 Oct 2018 14:59:18 -0700 Subject: [PATCH 076/106] update Cangelog --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 34e7ada3..3167be4c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Please add a note of your changes below this heading if you make a Pull Request. ### Changed * Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. * Renamed `axis.enable_step_dir` to `axis.step_dir_active` +* New process for working with STM32CubeMX. ## Fixed * Would get ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. From b3890ef9ff05df7e60bf0d85b4f05d3e733a42d7 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 30 Oct 2018 01:13:39 -0700 Subject: [PATCH 077/106] add option to keep encoder count from startup value --- CHANGELOG.md | 2 ++ Firmware/MotorControl/axis.cpp | 2 ++ Firmware/MotorControl/encoder.cpp | 3 ++- Firmware/MotorControl/encoder.hpp | 2 ++ 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 87ec6c0c..e5684a89 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -3,7 +3,9 @@ Please add a note of your changes below this heading if you make a Pull Request. ### Added * Overspeed fault +* Supress startup transients by sampling encoder estimate into position setpoint when entering closed loop control. * Make step dir gpio pins configurable. +* Configuration variable `encoder.config.zero_count_on_find_idx`, true by default. Set to false to leave the initial encoder count to be where the axis was at boot. ### Changed * Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index cae62223..de631b2c 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -198,6 +198,8 @@ bool Axis::run_sensorless_control_loop() { } bool Axis::run_closed_loop_control_loop() { + // To avoid any transient on startup, we intialize the setpoint to be the current position + controller_.pos_setpoint_ = encoder_.pos_estimate_; set_step_dir_active(config_.enable_step_dir); run_control_loop([this](){ // Note that all estimators are updated in the loop prefix in run_control_loop diff --git a/Firmware/MotorControl/encoder.cpp b/Firmware/MotorControl/encoder.cpp index 58926958..8c0691f8 100644 --- a/Firmware/MotorControl/encoder.cpp +++ b/Firmware/MotorControl/encoder.cpp @@ -44,7 +44,8 @@ bool Encoder::do_checks(){ void Encoder::enc_index_cb() { if (config_.use_index && !index_found_) { set_circular_count(0, false); - set_linear_count(0); // Avoid position control transient after search + if (config_.zero_count_on_find_idx) + set_linear_count(0); // Avoid position control transient after search if (config_.pre_calibrated) { is_ready_ = true; } else { diff --git a/Firmware/MotorControl/encoder.hpp b/Firmware/MotorControl/encoder.hpp index 27ba284b..78f8f4f6 100644 --- a/Firmware/MotorControl/encoder.hpp +++ b/Firmware/MotorControl/encoder.hpp @@ -31,6 +31,7 @@ public: // In this case the encoder will enter ready // state as soon as the index is found. float idx_search_speed = 10.0f; // [rad/s electrical] + bool zero_count_on_find_idx = true; int32_t cpr = (2048 * 4); // Default resolution of CUI-AMT102 encoder, int32_t offset = 0; // Offset between encoder count and rotor electrical phase float offset_float = 0.0f; // Sub-count phase alignment offset @@ -99,6 +100,7 @@ public: make_protocol_property("use_index", &config_.use_index), make_protocol_property("pre_calibrated", &config_.pre_calibrated), make_protocol_property("idx_search_speed", &config_.idx_search_speed), + make_protocol_property("zero_count_on_find_idx", &config_.zero_count_on_find_idx), make_protocol_property("cpr", &config_.cpr), make_protocol_property("offset", &config_.offset), make_protocol_property("offset_float", &config_.offset_float), From 921987a09f0e70aad37d85fd0588b112cb5f8157 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 30 Oct 2018 18:20:08 -0700 Subject: [PATCH 078/106] increase comms stack size (we really need to refactor this) --- Firmware/communication/communication.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/communication/communication.cpp b/Firmware/communication/communication.cpp index 622bdefb..625a3cf7 100644 --- a/Firmware/communication/communication.cpp +++ b/Firmware/communication/communication.cpp @@ -84,7 +84,7 @@ void init_communication(void) { printf("hi!\r\n"); // Start command handling thread - osThreadDef(task_cmd_parse, communication_task, osPriorityNormal, 0, 5000 /* in 32-bit words */); // TODO: fix stack issues + osThreadDef(task_cmd_parse, communication_task, osPriorityNormal, 0, 6000 /* in 32-bit words */); // TODO: fix stack issues comm_thread = osThreadCreate(osThread(task_cmd_parse), NULL); while (!endpoint_list_valid) From 025fd7c59a13f294251475003d839ccab368c506 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Fri, 9 Nov 2018 14:56:51 -0800 Subject: [PATCH 079/106] update ODrive thermistor beta value to 3434K --- Firmware/MotorControl/board_config_v3.h | 2 +- analysis/thermistors.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/MotorControl/board_config_v3.h b/Firmware/MotorControl/board_config_v3.h index 7aee4881..e865102d 100644 --- a/Firmware/MotorControl/board_config_v3.h +++ b/Firmware/MotorControl/board_config_v3.h @@ -66,7 +66,7 @@ extern const size_t thermistor_num_coeffs; //TODO stick this in a C file #ifdef __MAIN_CPP__ const float thermistor_poly_coeffs[] = - {363.0172658f, -459.19773008f, 308.29273921f, -28.12731452f}; + {363.93910201f, -462.15369634f, 307.55129571f, -27.72569531f}; const size_t thermistor_num_coeffs = sizeof(thermistor_poly_coeffs)/sizeof(thermistor_poly_coeffs[1]); const BoardHardwareConfig_t hw_configs[2] = { { diff --git a/analysis/thermistors.py b/analysis/thermistors.py index 5a5c904c..2a3792a9 100644 --- a/analysis/thermistors.py +++ b/analysis/thermistors.py @@ -5,7 +5,7 @@ import numpy as np Rload = 3300 R_25 = 10000 T_25 = 25 + 273.15 #Kelvin -Beta = 3380 +Beta = 3434 Tmin = 0 Tmax = 140 From bbef49611aa41a2190dd220dfc11a298488cd33e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 14 Nov 2018 00:13:19 -0800 Subject: [PATCH 080/106] implement vel ramp --- Firmware/MotorControl/controller.cpp | 13 +++++++++++++ Firmware/MotorControl/controller.hpp | 8 +++++++- Firmware/MotorControl/low_level.cpp | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Firmware/MotorControl/controller.cpp b/Firmware/MotorControl/controller.cpp index 8c202ae0..7f517ae0 100644 --- a/Firmware/MotorControl/controller.cpp +++ b/Firmware/MotorControl/controller.cpp @@ -118,6 +118,19 @@ bool Controller::update(float pos_estimate, float vel_estimate, float* current_s anticogging_pos = pos_setpoint_; // FF the position setpoint instead of the pos_estimate } + // Ramp rate limited velocity setpoint + if (config_.control_mode == CTRL_MODE_VELOCITY_CONTROL && vel_ramp_enable_) { + float max_step_size = current_meas_period * config_.vel_ramp_limit; + float full_step = vel_ramp_target_ - vel_setpoint_; + float step; + if (fabsf(full_step) > max_step_size) { + step = std::copysignf(max_step_size, full_step); + } else { + step = full_step; + } + vel_setpoint_ += step; + } + // Position control // TODO Decide if we want to use encoder or pll position here float vel_des = vel_setpoint_; diff --git a/Firmware/MotorControl/controller.hpp b/Firmware/MotorControl/controller.hpp index f99f25d4..45fa55df 100644 --- a/Firmware/MotorControl/controller.hpp +++ b/Firmware/MotorControl/controller.hpp @@ -30,6 +30,7 @@ public: float vel_integrator_gain = 10.0f / 10000.0f; // [A/(counts/s * s)] float vel_limit = 20000.0f; // [counts/s] float vel_limit_tolerance = 1.2f; // ratio to vel_lim. 0.0f to disable + float vel_ramp_limit = 10000.0f; // [(counts/s) / s] }; Controller(Config_t& config); @@ -82,6 +83,8 @@ public: // float vel_setpoint = 800.0f; float vel_integrator_current_ = 0.0f; // [A] float current_setpoint_ = 0.0f; // [A] + float vel_ramp_target_ = 0.0f; + bool vel_ramp_enable_ = false; uint32_t traj_start_loop_count_ = 0; @@ -93,13 +96,16 @@ public: make_protocol_property("vel_setpoint", &vel_setpoint_), make_protocol_property("vel_integrator_current", &vel_integrator_current_), make_protocol_property("current_setpoint", ¤t_setpoint_), + make_protocol_property("vel_ramp_target", &vel_ramp_target_), + make_protocol_property("vel_ramp_enable", &vel_ramp_enable_), make_protocol_object("config", make_protocol_property("control_mode", &config_.control_mode), make_protocol_property("pos_gain", &config_.pos_gain), make_protocol_property("vel_gain", &config_.vel_gain), make_protocol_property("vel_integrator_gain", &config_.vel_integrator_gain), make_protocol_property("vel_limit", &config_.vel_limit), - make_protocol_property("vel_limit_tolerance", &config_.vel_limit_tolerance) + make_protocol_property("vel_limit_tolerance", &config_.vel_limit_tolerance), + make_protocol_property("vel_ramp_limit", &config_.vel_ramp_limit) ), make_protocol_function("set_pos_setpoint", *this, &Controller::set_pos_setpoint, "pos_setpoint", "vel_feed_forward", "current_feed_forward"), diff --git a/Firmware/MotorControl/low_level.cpp b/Firmware/MotorControl/low_level.cpp index 5bc256ae..b40b3274 100644 --- a/Firmware/MotorControl/low_level.cpp +++ b/Firmware/MotorControl/low_level.cpp @@ -667,6 +667,7 @@ void pwm_in_init() { } } +//TODO: These expressions have integer division by 1MHz, so it will be incorrect for clock speeds of not-integer MHz #define TIM_2_5_CLOCK_HZ TIM_APB1_CLOCK_HZ #define PWM_MIN_HIGH_TIME ((TIM_2_5_CLOCK_HZ / 1000000UL) * 1000UL) // 1ms high is considered full reverse #define PWM_MAX_HIGH_TIME ((TIM_2_5_CLOCK_HZ / 1000000UL) * 2000UL) // 2ms high is considered full forward From d9612ab53494408b21d3b951103bff1b855132ed Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 24 Nov 2018 14:09:38 -0800 Subject: [PATCH 081/106] circular position setpoint mode --- CHANGELOG.md | 1 + Firmware/MotorControl/axis.hpp | 2 +- Firmware/MotorControl/controller.cpp | 14 +++++++++++++- Firmware/MotorControl/controller.hpp | 4 +++- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e5684a89..5085658b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,7 @@ Please add a note of your changes below this heading if you make a Pull Request. * Supress startup transients by sampling encoder estimate into position setpoint when entering closed loop control. * Make step dir gpio pins configurable. * Configuration variable `encoder.config.zero_count_on_find_idx`, true by default. Set to false to leave the initial encoder count to be where the axis was at boot. +* Circular position setpoint mode: position setpoints wrapped [0, cpr). Useful for infinite incremental position control. ### Changed * Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index d9f95ad8..fe057569 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -174,7 +174,7 @@ public: // variables exposed on protocol Error_t error_ = ERROR_NONE; bool step_dir_active_ = false; // auto enabled after calibration, based on config.enable_step_dir - + // updated from config in constructor, and on protocol hook GPIO_TypeDef* step_port_; uint16_t step_pin_; diff --git a/Firmware/MotorControl/controller.cpp b/Firmware/MotorControl/controller.cpp index 7f517ae0..c0494397 100644 --- a/Firmware/MotorControl/controller.cpp +++ b/Firmware/MotorControl/controller.cpp @@ -135,7 +135,19 @@ bool Controller::update(float pos_estimate, float vel_estimate, float* current_s // TODO Decide if we want to use encoder or pll position here float vel_des = vel_setpoint_; if (config_.control_mode >= CTRL_MODE_POSITION_CONTROL) { - float pos_err = pos_setpoint_ - pos_estimate; + float pos_err; + if (config_.setpoints_in_cpr) { + // TODO this breaks the semantics that estimates come in on the arguments. + // It's probably better to call a get_estimate that will arbitrate (enc vs sensorless) instead. + float cpr = (float)(axis_->encoder_.config_.cpr); + // Keep pos setpoint from drifting + pos_setpoint_ = fmodf_pos(pos_setpoint_, cpr); + // Circular delta + pos_err = pos_setpoint_ - axis_->encoder_.pos_cpr_; + pos_err = wrap_pm(pos_err, 0.5f * cpr); + } else { + pos_err = pos_setpoint_ - pos_estimate; + } vel_des += config_.pos_gain * pos_err; } diff --git a/Firmware/MotorControl/controller.hpp b/Firmware/MotorControl/controller.hpp index 45fa55df..9e1193a1 100644 --- a/Firmware/MotorControl/controller.hpp +++ b/Firmware/MotorControl/controller.hpp @@ -31,6 +31,7 @@ public: float vel_limit = 20000.0f; // [counts/s] float vel_limit_tolerance = 1.2f; // ratio to vel_lim. 0.0f to disable float vel_ramp_limit = 10000.0f; // [(counts/s) / s] + bool setpoints_in_cpr = false; }; Controller(Config_t& config); @@ -105,7 +106,8 @@ public: make_protocol_property("vel_integrator_gain", &config_.vel_integrator_gain), make_protocol_property("vel_limit", &config_.vel_limit), make_protocol_property("vel_limit_tolerance", &config_.vel_limit_tolerance), - make_protocol_property("vel_ramp_limit", &config_.vel_ramp_limit) + make_protocol_property("vel_ramp_limit", &config_.vel_ramp_limit), + make_protocol_property("setpoints_in_cpr", &config_.setpoints_in_cpr) ), make_protocol_function("set_pos_setpoint", *this, &Controller::set_pos_setpoint, "pos_setpoint", "vel_feed_forward", "current_feed_forward"), From e1f17c559011ef349e0580af44ce498cda8319df Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sat, 24 Nov 2018 22:16:04 -0800 Subject: [PATCH 082/106] odrivetool locals --- CHANGELOG.md | 1 + Firmware/fibre/python/fibre/shell.py | 1 + 2 files changed, 2 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5085658b..7af1a076 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -15,6 +15,7 @@ Please add a note of your changes below this heading if you make a Pull Request. ## Fixed * Would get ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. +* ODrive tool can now run interactive nested scripts with "%run -i script.py" # Releases ## [0.4.6] - 2018-10-07 diff --git a/Firmware/fibre/python/fibre/shell.py b/Firmware/fibre/python/fibre/shell.py index 9dd31d7a..d5e24d85 100644 --- a/Firmware/fibre/python/fibre/shell.py +++ b/Firmware/fibre/python/fibre/shell.py @@ -81,6 +81,7 @@ def launch_shell(args, # If IPython is installed, embed IPython shell, otherwise embed regular shell if use_ipython: help = lambda: print_help(args, len(discovered_devices) > 0) # Override help function # pylint: disable=W0612 + locals()['__name__'] = globals()['__name__'] # to fix broken "%run -i script.py" console = IPython.terminal.embed.InteractiveShellEmbed(banner1='') console.runcode = console.run_code # hack to make IPython look like the regular console interact = console From 4348698ee18e35935ef5cfc7fc96cd7e52815697 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Sun, 25 Nov 2018 19:07:35 -0800 Subject: [PATCH 083/106] cube: add SPI irqs and DMA --- Firmware/Board/v3/Inc/stm32f4xx_it.h | 3 ++ Firmware/Board/v3/Odrive.ioc | 27 ++++++++++++++- Firmware/Board/v3/Src/dma.c | 6 ++++ Firmware/Board/v3/Src/spi.c | 49 ++++++++++++++++++++++++++++ Firmware/Board/v3/Src/stm32f4xx_it.c | 45 +++++++++++++++++++++++++ 5 files changed, 129 insertions(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Inc/stm32f4xx_it.h b/Firmware/Board/v3/Inc/stm32f4xx_it.h index bed8a253..784a3333 100644 --- a/Firmware/Board/v3/Inc/stm32f4xx_it.h +++ b/Firmware/Board/v3/Inc/stm32f4xx_it.h @@ -54,8 +54,10 @@ void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); void SysTick_Handler(void); +void DMA1_Stream0_IRQHandler(void); void DMA1_Stream2_IRQHandler(void); void DMA1_Stream4_IRQHandler(void); +void DMA1_Stream5_IRQHandler(void); void ADC_IRQHandler(void); void CAN1_TX_IRQHandler(void); void CAN1_RX0_IRQHandler(void); @@ -63,6 +65,7 @@ void CAN1_RX1_IRQHandler(void); void CAN1_SCE_IRQHandler(void); void TIM8_TRG_COM_TIM14_IRQHandler(void); void TIM5_IRQHandler(void); +void SPI3_IRQHandler(void); void UART4_IRQHandler(void); void OTG_FS_IRQHandler(void); diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index d18c5f86..ab299065 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -97,7 +97,29 @@ Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlign Dma.Request0=UART4_RX Dma.Request1=UART4_TX Dma.Request2=ADC1 -Dma.RequestsNb=3 +Dma.Request3=SPI3_TX +Dma.Request4=SPI3_RX +Dma.RequestsNb=5 +Dma.SPI3_RX.4.Direction=DMA_PERIPH_TO_MEMORY +Dma.SPI3_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.SPI3_RX.4.Instance=DMA1_Stream0 +Dma.SPI3_RX.4.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.SPI3_RX.4.MemInc=DMA_MINC_ENABLE +Dma.SPI3_RX.4.Mode=DMA_NORMAL +Dma.SPI3_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.SPI3_RX.4.PeriphInc=DMA_PINC_DISABLE +Dma.SPI3_RX.4.Priority=DMA_PRIORITY_MEDIUM +Dma.SPI3_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.SPI3_TX.3.Direction=DMA_MEMORY_TO_PERIPH +Dma.SPI3_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.SPI3_TX.3.Instance=DMA1_Stream5 +Dma.SPI3_TX.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.SPI3_TX.3.MemInc=DMA_MINC_ENABLE +Dma.SPI3_TX.3.Mode=DMA_NORMAL +Dma.SPI3_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.SPI3_TX.3.PeriphInc=DMA_PINC_DISABLE +Dma.SPI3_TX.3.Priority=DMA_PRIORITY_MEDIUM +Dma.SPI3_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode Dma.UART4_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.UART4_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE Dma.UART4_RX.0.Instance=DMA1_Stream2 @@ -221,8 +243,10 @@ NVIC.CAN1_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true NVIC.CAN1_RX1_IRQn=true\:6\:0\:true\:false\:true\:true\:true NVIC.CAN1_SCE_IRQn=true\:6\:0\:true\:false\:true\:true\:true NVIC.CAN1_TX_IRQn=true\:6\:0\:true\:false\:true\:true\:true +NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false +NVIC.DMA1_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:false\:true\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true @@ -231,6 +255,7 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SPI3_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:true NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:false\:false\:true diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c index 55d5e034..753fa090 100644 --- a/Firmware/Board/v3/Src/dma.c +++ b/Firmware/Board/v3/Src/dma.c @@ -71,12 +71,18 @@ void MX_DMA_Init(void) __HAL_RCC_DMA2_CLK_ENABLE(); /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); /* DMA2_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); diff --git a/Firmware/Board/v3/Src/spi.c b/Firmware/Board/v3/Src/spi.c index 87b2a018..d66515f9 100644 --- a/Firmware/Board/v3/Src/spi.c +++ b/Firmware/Board/v3/Src/spi.c @@ -51,12 +51,15 @@ #include "spi.h" #include "gpio.h" +#include "dma.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ SPI_HandleTypeDef hspi3; +DMA_HandleTypeDef hdma_spi3_tx; +DMA_HandleTypeDef hdma_spi3_rx; /* SPI3 init function */ void MX_SPI3_Init(void) @@ -105,6 +108,46 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + /* SPI3 DMA Init */ + /* SPI3_TX Init */ + hdma_spi3_tx.Instance = DMA1_Stream5; + hdma_spi3_tx.Init.Channel = DMA_CHANNEL_0; + hdma_spi3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_spi3_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi3_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_spi3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_spi3_tx.Init.Mode = DMA_NORMAL; + hdma_spi3_tx.Init.Priority = DMA_PRIORITY_MEDIUM; + hdma_spi3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi3_tx) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi3_tx); + + /* SPI3_RX Init */ + hdma_spi3_rx.Instance = DMA1_Stream0; + hdma_spi3_rx.Init.Channel = DMA_CHANNEL_0; + hdma_spi3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_spi3_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi3_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_spi3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_spi3_rx.Init.Mode = DMA_NORMAL; + hdma_spi3_rx.Init.Priority = DMA_PRIORITY_MEDIUM; + hdma_spi3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi3_rx) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi3_rx); + + /* SPI3 interrupt Init */ + HAL_NVIC_SetPriority(SPI3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SPI3_IRQn); /* USER CODE BEGIN SPI3_MspInit 1 */ /* USER CODE END SPI3_MspInit 1 */ @@ -129,6 +172,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12); + /* SPI3 DMA DeInit */ + HAL_DMA_DeInit(spiHandle->hdmatx); + HAL_DMA_DeInit(spiHandle->hdmarx); + + /* SPI3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(SPI3_IRQn); /* USER CODE BEGIN SPI3_MspDeInit 1 */ /* USER CODE END SPI3_MspDeInit 1 */ diff --git a/Firmware/Board/v3/Src/stm32f4xx_it.c b/Firmware/Board/v3/Src/stm32f4xx_it.c index 8acc96ee..f0fe1d3e 100644 --- a/Firmware/Board/v3/Src/stm32f4xx_it.c +++ b/Firmware/Board/v3/Src/stm32f4xx_it.c @@ -63,6 +63,9 @@ extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; extern ADC_HandleTypeDef hadc3; extern CAN_HandleTypeDef hcan1; +extern DMA_HandleTypeDef hdma_spi3_tx; +extern DMA_HandleTypeDef hdma_spi3_rx; +extern SPI_HandleTypeDef hspi3; extern TIM_HandleTypeDef htim5; extern TIM_HandleTypeDef htim8; extern DMA_HandleTypeDef hdma_uart4_rx; @@ -194,6 +197,20 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32f4xx.s). */ /******************************************************************************/ +/** +* @brief This function handles DMA1 stream0 global interrupt. +*/ +void DMA1_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi3_rx); + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + /** * @brief This function handles DMA1 stream2 global interrupt. */ @@ -222,6 +239,20 @@ void DMA1_Stream4_IRQHandler(void) /* USER CODE END DMA1_Stream4_IRQn 1 */ } +/** +* @brief This function handles DMA1 stream5 global interrupt. +*/ +void DMA1_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi3_tx); + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + /** * @brief This function handles ADC1, ADC2 and ADC3 global interrupts. */ @@ -336,6 +367,20 @@ void TIM5_IRQHandler(void) /* USER CODE END TIM5_IRQn 1 */ } +/** +* @brief This function handles SPI3 global interrupt. +*/ +void SPI3_IRQHandler(void) +{ + /* USER CODE BEGIN SPI3_IRQn 0 */ + + /* USER CODE END SPI3_IRQn 0 */ + HAL_SPI_IRQHandler(&hspi3); + /* USER CODE BEGIN SPI3_IRQn 1 */ + + /* USER CODE END SPI3_IRQn 1 */ +} + /** * @brief This function handles UART4 global interrupt. */ From c4aac84c72254496c3777865b13a9dbc5c9d4f8c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:23:46 -0700 Subject: [PATCH 084/106] bake patch: display correct ODrive version in USB descriptor --- ...ect-ODrive-version-in-USB-descriptor.patch | 41 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 8 ++-- 2 files changed, 5 insertions(+), 44 deletions(-) delete mode 100644 Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch diff --git a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch b/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch deleted file mode 100644 index 0b031242..00000000 --- a/Firmware/Board/v3/0001-display-correct-ODrive-version-in-USB-descriptor.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b7ea3f500fbfc187a0a7112282ae6b1eee4555d0 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Tue, 13 Mar 2018 20:05:07 -0700 -Subject: [PATCH] display correct ODrive version in USB descriptor - ---- - Firmware/Board/v3/Src/usbd_desc.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index 94dc49b..37b4302 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -96,7 +96,9 @@ - #define USBD_LANGID_STRING 1033 - #define USBD_MANUFACTURER_STRING "ODrive Robotics" - #define USBD_PID_FS 0x0D32 --#define USBD_PRODUCT_STRING_FS "ODrive v3.3" -+#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) -+#define USBD_PRODUCT_STR(s) #s -+#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR - #define USBD_SERIALNUMBER_STRING_FS "000000000001" - #define USBD_CONFIGURATION_STRING_FS "CDC Config" - #define USBD_INTERFACE_STRING_FS "CDC Interface" -@@ -299,11 +301,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length - { - if(speed == 0) - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - else - { -- USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); -+ USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); - } - return USBD_StrDesc; - } --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 2e139e50..973b0ae2 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -95,7 +95,9 @@ #define USBD_LANGID_STRING 1033 #define USBD_MANUFACTURER_STRING "ODrive Robotics" #define USBD_PID_FS 0x0D32 -#define USBD_PRODUCT_STRING_FS "ODrive v3.3" +#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) +#define USBD_PRODUCT_STR(s) #s +#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -342,11 +344,11 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length { if(speed == 0) { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } else { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); } return USBD_StrDesc; } From 1b95b2af9488728425a00a1f844efa5f9e1d6ca2 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:27:56 -0700 Subject: [PATCH 085/106] bake patch: expose correct serial number on USB --- ...-expose-correct-serial-number-on-USB.patch | 32 ------------------- Firmware/Board/v3/Src/usbd_desc.c | 9 +----- 2 files changed, 1 insertion(+), 40 deletions(-) delete mode 100644 Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch diff --git a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch b/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch deleted file mode 100644 index b9fef648..00000000 --- a/Firmware/Board/v3/0001-expose-correct-serial-number-on-USB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0867a92f742b312a0ebaafe94cade6f57be22170 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 12 Mar 2018 23:49:32 -0700 -Subject: [PATCH] expose correct serial number on USB - ---- - Firmware/Board/v3/Src/usbd_desc.c | 9 +++++++++------- - 1 file changed, 1 insertions(+), 8 deletions(-) - -diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c -index b9c7bd0..94dc49b 100644 ---- a/Firmware/Board/v3/Src/usbd_desc.c -+++ b/Firmware/Board/v3/Src/usbd_desc.c -@@ -327,14 +327,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l - */ - uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) - { -- if(speed == USBD_SPEED_HIGH) -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -- else -- { -- USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); -- } -+ USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); - return USBD_StrDesc; - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index 973b0ae2..b0906144 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -373,14 +373,7 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } + USBD_GetString ((uint8_t *)serial_number_str, USBD_StrDesc, length); return USBD_StrDesc; } From 6b441b134e91ed41113d1996827900d032f8ec5c Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:29:43 -0700 Subject: [PATCH 086/106] bake patch: fix return type of osSemaphoreWait --- ...1-fix-return-type-of-osSemaphoreWait.patch | 46 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 4 +- 3 files changed, 4 insertions(+), 50 deletions(-) delete mode 100644 Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch diff --git a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch b/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch deleted file mode 100644 index 53760fa1..00000000 --- a/Firmware/Board/v3/0001-fix-return-type-of-osSemaphoreWait.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 49353ccb7023c02c2bc6e3b6f14fac02a13fe599 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:55:17 -0800 -Subject: [PATCH] fix return type of osSemaphoreWait - ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 6 +++--- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - 2 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -index d0e0fd7..e764cbc 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c -@@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - * @brief Wait until a Semaphore token becomes available - * @param semaphore_id semaphore object referenced with \ref osSemaphore. - * @param millisec timeout value or 0 in case of no time-out. --* @retval number of available tokens, or -1 in case of incorrect parameters. -+* @retval status code that indicates the execution status of the function. - * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. - */ --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) - { - TickType_t ticks; - portBASE_TYPE taskWoken = pdFALSE; -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 15e25b9..5223f8e 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t - /// Wait until a Semaphore token becomes available. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. - /// \param[in] millisec timeout value or 0 in case of no time-out. --/// \return number of available tokens, or -1 in case of incorrect parameters. -+/// \return status code that indicates the execution status of the function. - /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. --int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); -+osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - - /// Release a Semaphore token. - /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index d0e0fd76..7828403b 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -816,10 +816,10 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t * @brief Wait until a Semaphore token becomes available * @param semaphore_id semaphore object referenced with \ref osSemaphore. * @param millisec timeout value or 0 in case of no time-out. -* @retval number of available tokens, or -1 in case of incorrect parameters. +* @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 15e25b96..09cdf273 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \return status code that indicates the execution status of the function. /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); +osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. From 1a687e05376fd7a99c812d004d6a09332162f63e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:31:41 -0700 Subject: [PATCH 087/106] bake patch: release sem_usb_tx in usb_cdc.c --- ...001-release-sem_usb_tx-in-usbd_cdc.c.patch | 35 ------------------- .../Class/CDC/Src/usbd_cdc.c | 5 +-- 2 files changed, 3 insertions(+), 37 deletions(-) delete mode 100644 Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch diff --git a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch b/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch deleted file mode 100644 index b69370f5..00000000 --- a/Firmware/Board/v3/0001-release-sem_usb_tx-in-usbd_cdc.c.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 965f7f2c80e30d7a66dcac7abaa9bdc371d9ea51 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Feb 2018 14:53:52 -0800 -Subject: [PATCH] release sem_usb_tx in usbd_cdc.c - ---- - .../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -index b2ca5f1..6ae33e8 100644 ---- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -+++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -@@ -62,7 +62,8 @@ - #include "usbd_cdc.h" - #include "usbd_desc.h" - #include "usbd_ctlreq.h" -- -+#include -+#include - - /** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ -@@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) - { - - hcdc->TxState = 0; -- -+ osSemaphoreRelease(sem_usb_tx); - return USBD_OK; - } - else --- -2.16.1 - diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index b2ca5f16..24465641 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -62,7 +62,8 @@ #include "usbd_cdc.h" #include "usbd_desc.h" #include "usbd_ctlreq.h" - +#include +#include /** @addtogroup STM32_USB_DEVICE_LIBRARY * @{ @@ -669,7 +670,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) { hcdc->TxState = 0; - + osSemaphoreRelease(sem_usb_tx); return USBD_OK; } else From f606958bf2507f3715f672258a69dba2065273e9 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:43:04 -0700 Subject: [PATCH 088/106] bake patch: FreeRTOS constness fixes --- .../v3/0002-FreeRTOS-constness-fixes.patch | 64 ------------------- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 8 +-- Firmware/Board/v3/Src/freertos.c | 4 +- 3 files changed, 6 insertions(+), 70 deletions(-) delete mode 100644 Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch diff --git a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch b/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch deleted file mode 100644 index afe0326e..00000000 --- a/Firmware/Board/v3/0002-FreeRTOS-constness-fixes.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 510ead2b159e1d8116e5241066c54a7bf8b7bfbe Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 15:29:44 -0700 -Subject: [PATCH] FreeRTOS constness fixes - - - make thread names const char * - - make thread argument non-const void* ---- - .../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 6 +++--- - Firmware/Board/v3/Src/freertos.c | 4 ++-- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -index 09cdf27..754be24 100644 ---- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -+++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h -@@ -270,11 +270,11 @@ typedef enum { - - /// Entry point of a thread. - /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. --typedef void (*os_pthread) (void const *argument); -+typedef void (*os_pthread) (void *argument); - - /// Entry point of a timer call back function. - /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. --typedef void (*os_ptimer) (void const *argument); -+typedef void (*os_ptimer) (void *argument); - - // >>> the following data type definitions may shall adapted towards a specific RTOS - -@@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; - /// Thread Definition structure contains startup information of a thread. - /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. - typedef struct os_thread_def { -- char *name; ///< Thread name -+ const char *name; ///< Thread name - os_pthread pthread; ///< start address of thread function - osPriority tpriority; ///< initial thread priority - uint32_t instances; ///< maximum number of instances of that thread function -diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c -index 6eaea82..b247994 100644 ---- a/Firmware/Board/v3/Src/freertos.c -+++ b/Firmware/Board/v3/Src/freertos.c -@@ -75,7 +75,7 @@ uint8_t ucHeap[configTOTAL_HEAP_SIZE]; - /* USER CODE END Variables */ - - /* Function prototypes -------------------------------------------------------*/ --void StartDefaultTask(void const * argument); -+void StartDefaultTask(void * argument); - - extern void MX_USB_DEVICE_Init(void); - void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ -@@ -147,7 +147,7 @@ void MX_FREERTOS_Init(void) { - } - - /* StartDefaultTask function */ --void StartDefaultTask(void const * argument) -+void StartDefaultTask(void * argument) - { - /* init code for USB_DEVICE */ - MX_USB_DEVICE_Init(); --- -2.16.2 - diff --git a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 09cdf273..89a105dc 100644 --- a/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -26,7 +26,7 @@ * *---------------------------------------------------------------------------- * - * Portions Copyright 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved. * Portions Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without @@ -270,11 +270,11 @@ typedef enum { /// Entry point of a thread. /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); +typedef void (*os_pthread) (void *argument); /// Entry point of a timer call back function. /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); +typedef void (*os_ptimer) (void *argument); // >>> the following data type definitions may shall adapted towards a specific RTOS @@ -323,7 +323,7 @@ typedef StaticQueue_t osStaticMessageQDef_t; /// Thread Definition structure contains startup information of a thread. /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. typedef struct os_thread_def { - char *name; ///< Thread name + const char *name; ///< Thread name os_pthread pthread; ///< start address of thread function osPriority tpriority; ///< initial thread priority uint32_t instances; ///< maximum number of instances of that thread function diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c index 0865d714..11154587 100644 --- a/Firmware/Board/v3/Src/freertos.c +++ b/Firmware/Board/v3/Src/freertos.c @@ -98,7 +98,7 @@ osThreadId defaultTaskHandle; /* USER CODE END FunctionPrototypes */ -void StartDefaultTask(void const * argument); +void StartDefaultTask(void * argument); extern void MX_USB_DEVICE_Init(void); void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ @@ -214,7 +214,7 @@ void MX_FREERTOS_Init(void) { * @retval None */ /* USER CODE END Header_StartDefaultTask */ -void StartDefaultTask(void const * argument) +void StartDefaultTask(void * argument) { /* init code for USB_DEVICE */ MX_USB_DEVICE_Init(); From 8816a42aacfae92348e675e49422070ebe3b3c31 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:45:30 -0700 Subject: [PATCH 089/106] bake patch: disable IRQ for DMA2_Stream0 --- .../0003-disable-IRQ-for-DMA2_Stream0.patch | 33 ------------------- Firmware/Board/v3/Src/dma.c | 6 ++-- 2 files changed, 4 insertions(+), 35 deletions(-) delete mode 100644 Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch diff --git a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch b/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch deleted file mode 100644 index 282317d1..00000000 --- a/Firmware/Board/v3/0003-disable-IRQ-for-DMA2_Stream0.patch +++ /dev/null @@ -1,33 +0,0 @@ -From ab5ca860b3729d76a9c43c485776147ab69d2342 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Mon, 26 Mar 2018 19:02:45 -0700 -Subject: [PATCH] disable IRQ for DMA2_Stream0 - -This DMA stream is used to read values from ADC1 -while ADC1 cycles through it's sequence of input -channels. No interrupts are required to make -this work. ---- - Firmware/Board/v3/Src/dma.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c -index 55d5e03..3de873a 100644 ---- a/Firmware/Board/v3/Src/dma.c -+++ b/Firmware/Board/v3/Src/dma.c -@@ -78,8 +78,10 @@ void MX_DMA_Init(void) - HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); - /* DMA2_Stream0_IRQn interrupt configuration */ -- HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -- HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); -+ // Dear STM, no we _don't_ want to fire an interrupt for this DMA -+ // (it's not possible to deselect this in CubeMX) -+ //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); -+ //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); - - } - --- -2.16.2 - diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c index 753fa090..813c735a 100644 --- a/Firmware/Board/v3/Src/dma.c +++ b/Firmware/Board/v3/Src/dma.c @@ -84,8 +84,10 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); /* DMA2_Stream0_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + // Dear STM, no we _don't_ want to fire an interrupt for this DMA + // (it's not possible to deselect this in CubeMX) + //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); + //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); } From 2ca83c1d41949974dac58b87f8ebe22a8348a734 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 23 Oct 2018 23:57:44 -0700 Subject: [PATCH 090/106] bake patch: Add I2C files and settings --- .../v3/0002-Add-I2C-files-and-settings.patch | 6860 ----------------- .../Inc/stm32f4xx_hal_i2c.h | 649 ++ .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++ .../Src/stm32f4xx_hal_i2c_ex.c | 204 + Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- Firmware/Board/v3/Src/main.c | 2 +- 7 files changed, 6486 insertions(+), 6862 deletions(-) delete mode 100644 Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch b/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch deleted file mode 100644 index aae18bf4..00000000 --- a/Firmware/Board/v3/0002-Add-I2C-files-and-settings.patch +++ /dev/null @@ -1,6860 +0,0 @@ -From b45bdbbbfe3d084d069da99b98116991923f5eb6 Mon Sep 17 00:00:00 2001 -From: Samuel Sadok -Date: Thu, 26 Apr 2018 13:20:38 -0700 -Subject: [PATCH] Add I2C files and settings - ---- - .../Inc/stm32f4xx_hal_i2c.h | 649 ++ - .../Inc/stm32f4xx_hal_i2c_ex.h | 137 + - .../Src/stm32f4xx_hal_i2c.c | 5494 +++++++++++++++++ - .../Src/stm32f4xx_hal_i2c_ex.c | 204 + - Firmware/Board/v3/Inc/i2c.h | 91 + - Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h | 2 +- - Firmware/Board/v3/Odrive.ioc | 5 + - Firmware/Board/v3/Src/i2c.c | 198 + - Firmware/Board/v3/Src/main.c | 1 - - 11 files changed, 6811 insertions(+), 2 deletions(-) - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c - create mode 100644 Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c - create mode 100644 Firmware/Board/v3/Inc/i2c.h - create mode 100644 Firmware/Board/v3/Src/i2c.c - -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -new file mode 100644 -index 0000000..5452a50 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h -@@ -0,0 +1,649 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_H -+#define __STM32F4xx_HAL_I2C_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2C -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Types I2C Exported Types -+ * @{ -+ */ -+ -+/** -+ * @brief I2C Configuration Structure definition -+ */ -+typedef struct -+{ -+ uint32_t ClockSpeed; /*!< Specifies the clock frequency. -+ This parameter must be set to a value lower than 400kHz */ -+ -+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. -+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ -+ -+ uint32_t OwnAddress1; /*!< Specifies the first device own address. -+ This parameter can be a 7-bit or 10-bit address. */ -+ -+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. -+ This parameter can be a value of @ref I2C_addressing_mode */ -+ -+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. -+ This parameter can be a value of @ref I2C_dual_addressing_mode */ -+ -+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected -+ This parameter can be a 7-bit address. */ -+ -+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. -+ This parameter can be a value of @ref I2C_general_call_addressing_mode */ -+ -+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. -+ This parameter can be a value of @ref I2C_nostretch_mode */ -+ -+}I2C_InitTypeDef; -+ -+/** -+ * @brief HAL State structure definition -+ * @note HAL I2C State value coding follow below described bitmap : -+ * b7-b6 Error information -+ * 00 : No Error -+ * 01 : Abort (Abort user request on going) -+ * 10 : Timeout -+ * 11 : Error -+ * b5 IP initilisation status -+ * 0 : Reset (IP not initialized) -+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) -+ * b4 (not used) -+ * x : Should be set to 0 -+ * b3 -+ * 0 : Ready or Busy (No Listen mode ongoing) -+ * 1 : Listen (IP in Address Listen Mode) -+ * b2 Intrinsic process state -+ * 0 : Ready -+ * 1 : Busy (IP busy with some configuration or internal operations) -+ * b1 Rx state -+ * 0 : Ready (no Rx operation ongoing) -+ * 1 : Busy (Rx operation ongoing) -+ * b0 Tx state -+ * 0 : Ready (no Tx operation ongoing) -+ * 1 : Busy (Tx operation ongoing) -+ */ -+typedef enum -+{ -+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ -+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ -+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ -+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ -+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ -+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission -+ process is ongoing */ -+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception -+ process is ongoing */ -+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ -+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ -+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -+ -+}HAL_I2C_StateTypeDef; -+ -+/** -+ * @brief HAL Mode structure definition -+ * @note HAL I2C Mode value coding follow below described bitmap : -+ * b7 (not used) -+ * x : Should be set to 0 -+ * b6 -+ * 0 : None -+ * 1 : Memory (HAL I2C communication is in Memory Mode) -+ * b5 -+ * 0 : None -+ * 1 : Slave (HAL I2C communication is in Slave Mode) -+ * b4 -+ * 0 : None -+ * 1 : Master (HAL I2C communication is in Master Mode) -+ * b3-b2-b1-b0 (not used) -+ * xxxx : Should be set to 0000 -+ */ -+typedef enum -+{ -+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ -+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ -+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ -+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -+ -+}HAL_I2C_ModeTypeDef; -+ -+/** -+ * @brief I2C handle Structure definition -+ */ -+typedef struct -+{ -+ I2C_TypeDef *Instance; /*!< I2C registers base address */ -+ -+ I2C_InitTypeDef Init; /*!< I2C communication parameters */ -+ -+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ -+ -+ uint16_t XferSize; /*!< I2C transfer size */ -+ -+ __IO uint16_t XferCount; /*!< I2C transfer counter */ -+ -+ __IO uint32_t XferOptions; /*!< I2C transfer options */ -+ -+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode -+ context for internal usage */ -+ -+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ -+ -+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ -+ -+ HAL_LockTypeDef Lock; /*!< I2C locking object */ -+ -+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ -+ -+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ -+ -+ __IO uint32_t ErrorCode; /*!< I2C Error code */ -+ -+ __IO uint32_t Devaddress; /*!< I2C Target device address */ -+ -+ __IO uint32_t Memaddress; /*!< I2C Target memory address */ -+ -+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ -+ -+ __IO uint32_t EventCount; /*!< I2C Event counter */ -+ -+}I2C_HandleTypeDef; -+ -+/** -+ * @} -+ */ -+ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2C_Error_Code I2C Error Code -+ * @brief I2C Error Code -+ * @{ -+ */ -+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ -+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ -+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ -+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ -+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ -+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode -+ * @{ -+ */ -+#define I2C_DUTYCYCLE_2 0x00000000U -+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_addressing_mode I2C addressing mode -+ * @{ -+ */ -+#define I2C_ADDRESSINGMODE_7BIT 0x00004000U -+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode -+ * @{ -+ */ -+#define I2C_DUALADDRESS_DISABLE 0x00000000U -+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode -+ * @{ -+ */ -+#define I2C_GENERALCALL_DISABLE 0x00000000U -+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_nostretch_mode I2C nostretch mode -+ * @{ -+ */ -+#define I2C_NOSTRETCH_DISABLE 0x00000000U -+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size -+ * @{ -+ */ -+#define I2C_MEMADD_SIZE_8BIT 0x00000001U -+#define I2C_MEMADD_SIZE_16BIT 0x00000010U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition -+ * @{ -+ */ -+#define I2C_DIRECTION_RECEIVE 0x00000000U -+#define I2C_DIRECTION_TRANSMIT 0x00000001U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition -+ * @{ -+ */ -+#define I2C_FIRST_FRAME 0x00000001U -+#define I2C_NEXT_FRAME 0x00000002U -+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U -+#define I2C_LAST_FRAME 0x00000008U -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition -+ * @{ -+ */ -+#define I2C_IT_BUF I2C_CR2_ITBUFEN -+#define I2C_IT_EVT I2C_CR2_ITEVTEN -+#define I2C_IT_ERR I2C_CR2_ITERREN -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Flag_definition I2C Flag definition -+ * @{ -+ */ -+#define I2C_FLAG_SMBALERT 0x00018000U -+#define I2C_FLAG_TIMEOUT 0x00014000U -+#define I2C_FLAG_PECERR 0x00011000U -+#define I2C_FLAG_OVR 0x00010800U -+#define I2C_FLAG_AF 0x00010400U -+#define I2C_FLAG_ARLO 0x00010200U -+#define I2C_FLAG_BERR 0x00010100U -+#define I2C_FLAG_TXE 0x00010080U -+#define I2C_FLAG_RXNE 0x00010040U -+#define I2C_FLAG_STOPF 0x00010010U -+#define I2C_FLAG_ADD10 0x00010008U -+#define I2C_FLAG_BTF 0x00010004U -+#define I2C_FLAG_ADDR 0x00010002U -+#define I2C_FLAG_SB 0x00010001U -+#define I2C_FLAG_DUALF 0x00100080U -+#define I2C_FLAG_SMBHOST 0x00100040U -+#define I2C_FLAG_SMBDEFAULT 0x00100020U -+#define I2C_FLAG_GENCALL 0x00100010U -+#define I2C_FLAG_TRA 0x00100004U -+#define I2C_FLAG_BUSY 0x00100002U -+#define I2C_FLAG_MSL 0x00100001U -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Macros I2C Exported Macros -+ * @{ -+ */ -+ -+/** @brief Reset I2C handle state -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -+ -+/** @brief Enable or disable the specified I2C interrupts. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -+ -+/** @brief Checks if the specified I2C interrupt source is enabled or disabled. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __INTERRUPT__ specifies the I2C interrupt source to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_IT_BUF: Buffer interrupt enable -+ * @arg I2C_IT_EVT: Event interrupt enable -+ * @arg I2C_IT_ERR: Error interrupt enable -+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -+ -+/** @brief Checks whether the specified I2C flag is set or not. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to check. -+ * This parameter can be one of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @arg I2C_FLAG_TXE: Data register empty flag -+ * @arg I2C_FLAG_RXNE: Data register not empty flag -+ * @arg I2C_FLAG_STOPF: Stop detection flag -+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag -+ * @arg I2C_FLAG_BTF: Byte transfer finished flag -+ * @arg I2C_FLAG_ADDR: Address sent flag -+ * Address matched flag -+ * @arg I2C_FLAG_SB: Start bit flag -+ * @arg I2C_FLAG_DUALF: Dual flag -+ * @arg I2C_FLAG_SMBHOST: SMBus host header -+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header -+ * @arg I2C_FLAG_GENCALL: General call header flag -+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag -+ * @arg I2C_FLAG_BUSY: Bus busy flag -+ * @arg I2C_FLAG_MSL: Master/Slave flag -+ * @retval The new state of __FLAG__ (TRUE or FALSE). -+ */ -+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ -+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -+ -+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @param __FLAG__ specifies the flag to clear. -+ * This parameter can be any combination of the following values: -+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag -+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag -+ * @arg I2C_FLAG_PECERR: PEC error in reception flag -+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) -+ * @arg I2C_FLAG_AF: Acknowledge failure flag -+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) -+ * @arg I2C_FLAG_BERR: Bus error flag -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) -+ -+/** @brief Clears the I2C ADDR pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ tmpreg = (__HANDLE__)->Instance->SR2; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Clears the I2C STOPF pending flag. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ -+ do{ \ -+ __IO uint32_t tmpreg = 0x00U; \ -+ tmpreg = (__HANDLE__)->Instance->SR1; \ -+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ -+ UNUSED(tmpreg); \ -+ } while(0) -+ -+/** @brief Enable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -+ -+/** @brief Disable the I2C peripheral. -+ * @param __HANDLE__ specifies the I2C Handle. -+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. -+ * @retval None -+ */ -+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) -+ -+/** -+ * @} -+ */ -+ -+/* Include I2C HAL Extension module */ -+#include "stm32f4xx_hal_i2c_ex.h" -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2C_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Initialization/de-initialization functions **********************************/ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group2 -+ * @{ -+ */ -+/* I/O operation functions *****************************************************/ -+/******* Blocking mode: Polling */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); -+ -+/******* Non-Blocking mode: Interrupt */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -+ -+/******* Non-Blocking mode: DMA */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -+ -+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/** @addtogroup I2C_Exported_Functions_Group3 -+ * @{ -+ */ -+/* Peripheral State, Mode and Errors functions *********************************/ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Constants I2C Private Constants -+ * @{ -+ */ -+#define I2C_FLAG_MASK 0x0000FFFFU -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2C_Private_Macros I2C Private Macros -+ * @{ -+ */ -+ -+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) -+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) -+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) -+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) -+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ -+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) -+ -+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) -+ -+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) -+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) -+ -+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) -+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) -+ -+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters -+ * @{ -+ */ -+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ -+ ((CYCLE) == I2C_DUTYCYCLE_16_9)) -+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ -+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) -+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ -+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) -+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ -+ ((CALL) == I2C_GENERALCALL_ENABLE)) -+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ -+ ((STRETCH) == I2C_NOSTRETCH_ENABLE)) -+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ -+ ((SIZE) == I2C_MEMADD_SIZE_16BIT)) -+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) -+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) -+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) -+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ -+ ((REQUEST) == I2C_NEXT_FRAME) || \ -+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ -+ ((REQUEST) == I2C_LAST_FRAME)) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private functions ---------------------------------------------------------*/ -+/** @defgroup I2C_Private_Functions I2C Private Functions -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+ -+#endif /* __STM32F4xx_HAL_I2C_H */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -new file mode 100644 -index 0000000..ff47d5c ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h -@@ -0,0 +1,137 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.h -+ * @author MCD Application Team -+ * @brief Header file of I2C HAL Extension module. -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __STM32F4xx_HAL_I2C_EX_H -+#define __STM32F4xx_HAL_I2C_EX_H -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal_def.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx -+ * @{ -+ */ -+ -+/* Exported types ------------------------------------------------------------*/ -+/* Exported constants --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants -+ * @{ -+ */ -+ -+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter -+ * @{ -+ */ -+#define I2C_ANALOGFILTER_ENABLE 0x00000000U -+#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Exported macro ------------------------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @addtogroup I2CEx_Exported_Functions -+ * @{ -+ */ -+ -+/** @addtogroup I2CEx_Exported_Functions_Group1 -+ * @{ -+ */ -+/* Peripheral Control functions ************************************************/ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+/* Private types -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private constants ---------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Constants I2C Private Constants -+ * @{ -+ */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macros ------------------------------------------------------------*/ -+/** @defgroup I2CEx_Private_Macros I2C Private Macros -+ * @{ -+ */ -+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ -+ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ -+ STM32F413xx || STM32F423xx */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __STM32F4xx_HAL_I2C_EX_H */ -+ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -new file mode 100644 -index 0000000..da18520 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c -@@ -0,0 +1,5494 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c.c -+ * @author MCD Application Team -+ * @brief I2C HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of the Inter Integrated Circuit (I2C) peripheral: -+ * + Initialization and de-initialization functions -+ * + IO operation functions -+ * + Peripheral State, Mode and Error functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] -+ The I2C HAL driver can be used as follows: -+ -+ (#) Declare a I2C_HandleTypeDef handle structure, for example: -+ I2C_HandleTypeDef hi2c; -+ -+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: -+ (##) Enable the I2Cx interface clock -+ (##) I2C pins configuration -+ (+++) Enable the clock for the I2C GPIOs -+ (+++) Configure I2C pins as alternate function open-drain -+ (##) NVIC configuration if you need to use interrupt process -+ (+++) Configure the I2Cx interrupt priority -+ (+++) Enable the NVIC I2C IRQ Channel -+ (##) DMA Configuration if you need to use DMA process -+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream -+ (+++) Enable the DMAx interface clock using -+ (+++) Configure the DMA handle parameters -+ (+++) Configure the DMA Tx or Rx Stream -+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle -+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on -+ the DMA Tx or Rx Stream -+ -+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, -+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. -+ -+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware -+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. -+ -+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() -+ -+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : -+ -+ *** Polling mode IO operation *** -+ ================================= -+ [..] -+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() -+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() -+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() -+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() -+ -+ *** Polling mode IO MEM operation *** -+ ===================================== -+ [..] -+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() -+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() -+ -+ -+ *** Interrupt mode IO operation *** -+ =================================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO sequential operation *** -+ ============================================== -+ [..] -+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition -+ when a direction change during transfer -+ [..] -+ (+) A specific option field manage the different steps of a sequential transfer -+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: -+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode -+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address -+ and data to transfer without a final stop condition -+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and without a final stop condition in both cases -+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address -+ and with new data to transfer if the direction change or manage only the new data to transfer -+ if no direction change and with a final stop condition in both cases -+ -+ (+) Differents sequential I2C interfaces are listed below: -+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() -+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() -+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can -+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). -+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() -+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() -+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() -+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() -+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() -+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback() -+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** Interrupt mode IO MEM operation *** -+ ======================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using -+ HAL_I2C_Mem_Write_IT() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using -+ HAL_I2C_Mem_Read_IT() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ *** DMA mode IO operation *** -+ ============================== -+ [..] -+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback -+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Master_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback -+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Transmit_DMA() -+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback -+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using -+ HAL_I2C_Slave_Receive_DMA() -+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() -+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can -+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() -+ -+ *** DMA mode IO MEM operation *** -+ ================================= -+ [..] -+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using -+ HAL_I2C_Mem_Write_DMA() -+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback -+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using -+ HAL_I2C_Mem_Read_DMA() -+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can -+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback -+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can -+ add his own code by customization of function pointer HAL_I2C_ErrorCallback -+ -+ -+ *** I2C HAL driver macros list *** -+ ================================== -+ [..] -+ Below the list of most used macros in I2C HAL driver. -+ -+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral -+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral -+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not -+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag -+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt -+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt -+ -+ [..] -+ (@) You can refer to the I2C HAL driver header file for more useful macros -+ -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2C I2C -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/** @addtogroup I2C_Private_Define -+ * @{ -+ */ -+#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ -+#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ -+#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ -+ -+/* Private define for @ref PreviousState usage */ -+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ -+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -+ -+/** -+ * @} -+ */ -+ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/** @addtogroup I2C_Private_Functions -+ * @{ -+ */ -+/* Private functions to handle DMA transfer */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); -+static void I2C_DMAError(DMA_HandleTypeDef *hdma); -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); -+ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); -+ -+/* Private functions for I2C transfer IRQ handler */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); -+ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); -+/** -+ * @} -+ */ -+ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2C_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions -+ * @brief Initialization and Configuration functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Initialization and de-initialization functions ##### -+ =============================================================================== -+ [..] This subsection provides a set of functions allowing to initialize and -+ de-initialize the I2Cx peripheral: -+ -+ (+) User must Implement HAL_I2C_MspInit() function in which he configures -+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). -+ -+ (+) Call the function HAL_I2C_Init() to configure the selected device with -+ the selected configuration: -+ (++) Communication Speed -+ (++) Duty cycle -+ (++) Addressing mode -+ (++) Own Address 1 -+ (++) Dual Addressing mode -+ (++) Own Address 2 -+ (++) General call mode -+ (++) Nostretch mode -+ -+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration -+ of the selected I2Cx peripheral. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Initializes the I2C according to the specified parameters -+ * in the I2C_InitTypeDef and create the associated handle. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t freqrange = 0U; -+ uint32_t pclk1 = 0U; -+ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); -+ assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); -+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); -+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); -+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); -+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); -+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); -+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); -+ -+ if(hi2c->State == HAL_I2C_STATE_RESET) -+ { -+ /* Allocate lock resource and initialize it */ -+ hi2c->Lock = HAL_UNLOCKED; -+ /* Init the low level hardware : GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspInit(hi2c); -+ } -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get PCLK1 frequency */ -+ pclk1 = HAL_RCC_GetPCLK1Freq(); -+ -+ /* Calculate frequency range */ -+ freqrange = I2C_FREQRANGE(pclk1); -+ -+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/ -+ /* Configure I2Cx: Frequency range */ -+ hi2c->Instance->CR2 = freqrange; -+ -+ /*---------------------------- I2Cx TRISE Configuration --------------------*/ -+ /* Configure I2Cx: Rise Time */ -+ hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); -+ -+ /*---------------------------- I2Cx CCR Configuration ----------------------*/ -+ /* Configure I2Cx: Speed */ -+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); -+ -+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/ -+ /* Configure I2Cx: Generalcall and NoStretch mode */ -+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); -+ -+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ -+ /* Configure I2Cx: Own Address1 and addressing mode */ -+ hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); -+ -+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ -+ /* Configure I2Cx: Dual mode and Own Address2 */ -+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); -+ -+ /* Enable the selected I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DeInitializes the I2C peripheral. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Check the I2C handle allocation */ -+ if(hi2c == NULL) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the I2C Peripheral Clock */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ -+ HAL_I2C_MspDeInit(hi2c); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->State = HAL_I2C_STATE_RESET; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Release Lock */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C MSP Init. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C MSP DeInit -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval None -+ */ -+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ /* NOTE : This function Should not be modified, when the callback is needed, -+ the HAL_I2C_MspDeInit could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions -+ * @brief Data transfers functions -+ * -+@verbatim -+ =============================================================================== -+ ##### IO operation functions ##### -+ =============================================================================== -+ [..] -+ This subsection provides a set of functions allowing to manage the I2C data -+ transfers. -+ -+ (#) There are two modes of transfer: -+ (++) Blocking mode : The communication is performed in the polling mode. -+ The status of all data processing is returned by the same function -+ after finishing transfer. -+ (++) No-Blocking mode : The communication is performed using Interrupts -+ or DMA. These functions return the status of the transfer startup. -+ The end of the data processing will be indicated through the -+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when -+ using DMA mode. -+ -+ (#) Blocking mode functions are : -+ (++) HAL_I2C_Master_Transmit() -+ (++) HAL_I2C_Master_Receive() -+ (++) HAL_I2C_Slave_Transmit() -+ (++) HAL_I2C_Slave_Receive() -+ (++) HAL_I2C_Mem_Write() -+ (++) HAL_I2C_Mem_Read() -+ (++) HAL_I2C_IsDeviceReady() -+ -+ (#) No-Blocking mode functions with Interrupt are : -+ (++) HAL_I2C_Master_Transmit_IT() -+ (++) HAL_I2C_Master_Receive_IT() -+ (++) HAL_I2C_Slave_Transmit_IT() -+ (++) HAL_I2C_Slave_Receive_IT() -+ (++) HAL_I2C_Master_Sequential_Transmit_IT() -+ (++) HAL_I2C_Master_Sequential_Receive_IT() -+ (++) HAL_I2C_Slave_Sequential_Transmit_IT() -+ (++) HAL_I2C_Slave_Sequential_Receive_IT() -+ (++) HAL_I2C_Mem_Write_IT() -+ (++) HAL_I2C_Mem_Read_IT() -+ -+ (#) No-Blocking mode functions with DMA are : -+ (++) HAL_I2C_Master_Transmit_DMA() -+ (++) HAL_I2C_Master_Receive_DMA() -+ (++) HAL_I2C_Slave_Transmit_DMA() -+ (++) HAL_I2C_Slave_Receive_DMA() -+ (++) HAL_I2C_Mem_Write_DMA() -+ (++) HAL_I2C_Mem_Read_DMA() -+ -+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: -+ (++) HAL_I2C_MemTxCpltCallback() -+ (++) HAL_I2C_MemRxCpltCallback() -+ (++) HAL_I2C_MasterTxCpltCallback() -+ (++) HAL_I2C_MasterRxCpltCallback() -+ (++) HAL_I2C_SlaveTxCpltCallback() -+ (++) HAL_I2C_SlaveRxCpltCallback() -+ (++) HAL_I2C_ErrorCallback() -+ (++) HAL_I2C_AbortCpltCallback() -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Transmits in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receives in master mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address */ -+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize == 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmits in slave mode an amount of data in blocking mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* If 10bit addressing mode is selected */ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) -+ { -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ hi2c->XferSize--; -+ } -+ } -+ -+ /* Wait until AF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in blocking mode -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until STOP flag is set */ -+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear STOP flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t Prev_State = 0x00U; -+ __IO uint32_t count = 0x00U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ Prev_State = hi2c->PreviousState; -+ -+ /* Generate Start */ -+ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Check Busy Flag only if FIRST call of Master interface */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) -+ { -+ /* Generate Start condition if first transfer */ -+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ } -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt -+ * @note This interface allow to manage repeated start condition when a direction change during transfer -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); -+ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = XferOptions; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Enable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Disable the Address listen mode with Interrupt. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of tmp to prevent undefined behavior of volatile usage */ -+ uint32_t tmp; -+ -+ /* Disable Address listen mode only if a transfer is not ongoing */ -+ if(hi2c->State == HAL_I2C_STATE_LISTEN) -+ { -+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; -+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable Address Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MASTER; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ hi2c->Devaddress = DevAddress; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Abort a master I2C process communication with Interrupt. -+ * @note This abort can be called only if state is ready -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(DevAddress); -+ -+ /* Abort Master transfer during Receive or Transmit process */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_ABORT; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Wrong usage of abort function */ -+ /* This function should be used only in case of abort monitored by master device */ -+ return HAL_ERROR; -+ } -+} -+ -+/** -+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ if((pData == NULL) || (Size == 0U)) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_SLAVE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Enable Address Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+/** -+ * @brief Write an amount of data in blocking mode to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in blocking mode from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(hi2c->XferSize == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ while(hi2c->XferSize > 0U) -+ { -+ if(hi2c->XferSize <= 3U) -+ { -+ /* One byte */ -+ if(hi2c->XferSize== 1U) -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* Two bytes */ -+ else if(hi2c->XferSize == 2U) -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ /* 3 Last bytes */ -+ else -+ { -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Wait until BTF flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ else -+ { -+ /* Wait until RXNE flag is set */ -+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) -+ { -+ return HAL_TIMEOUT; -+ } -+ else -+ { -+ return HAL_ERROR; -+ } -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferSize--; -+ hi2c->XferCount--; -+ } -+ } -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->Devaddress = DevAddress; -+ hi2c->Memaddress = MemAddress; -+ hi2c->MemaddSize = MemAddSize; -+ hi2c->EventCount = 0U; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ -+ /* Enable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be sent -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ __IO uint32_t count = 0U; -+ -+ uint32_t tickstart = 0x00U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferSize = Size; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmatx->XferHalfCpltCallback = NULL; -+ hi2c->hdmatx->XferM1CpltCallback = NULL; -+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param pData Pointer to data buffer -+ * @param Size Amount of data to be read -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -+{ -+ uint32_t tickstart = 0x00U; -+ __IO uint32_t count = 0U; -+ -+ /* Init tickstart for timeout management*/ -+ tickstart = HAL_GetTick(); -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); -+ do -+ { -+ if(count-- == 0U) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY_RX; -+ hi2c->Mode = HAL_I2C_MODE_MEM; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Prepare transfer parameters */ -+ hi2c->pBuffPtr = pData; -+ hi2c->XferCount = Size; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->XferSize = hi2c->XferCount; -+ -+ if(hi2c->XferSize > 0U) -+ { -+ /* Set the I2C DMA transfer complete callback */ -+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; -+ -+ /* Set the DMA error callback */ -+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; -+ -+ /* Set the unused DMA callbacks to NULL */ -+ hi2c->hdmarx->XferHalfCpltCallback = NULL; -+ hi2c->hdmarx->XferM1CpltCallback = NULL; -+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Enable the DMA Stream */ -+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); -+ -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ if(Size == 1U) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ /* Note : The I2C interrupts must be enabled after unlocking current process -+ to avoid the risk of I2C interrupt handle execution before current -+ process unlock */ -+ /* Enable ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); -+ -+ /* Enable DMA Request */ -+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN; -+ } -+ else -+ { -+ /* Send Slave Address and Memory Address */ -+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_ERROR; -+ } -+ else -+ { -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ } -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Checks if target device is ready for communication. -+ * @note This function is used with Memory devices -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param DevAddress Target device address -+ * @param Trials Number of trials -+ * @param Timeout Timeout duration -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -+{ -+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; -+ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_BUSY; -+ } -+ -+ /* Process Locked */ -+ __HAL_LOCK(hi2c); -+ -+ /* Check if the I2C is already enabled */ -+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) -+ { -+ /* Enable I2C peripheral */ -+ __HAL_I2C_ENABLE(hi2c); -+ } -+ -+ /* Disable Pos */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ do -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR or AF flag are set */ -+ /* Get tick */ -+ tickstart = HAL_GetTick(); -+ -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) -+ { -+ hi2c->State = HAL_I2C_STATE_TIMEOUT; -+ } -+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); -+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); -+ tmp3 = hi2c->State; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Check if the ADDR flag has been set */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear ADDR Flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_OK; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Wait until BUSY flag is reset */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ }while(I2C_Trials++ < Trials); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief This function handles I2C event interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ /* Master or Memory mode selected */ -+ if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* SB Set ----------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_SB(hi2c); -+ } -+ /* ADD10 Set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADD10(hi2c); -+ } -+ /* ADDR Set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Master_ADDR(hi2c); -+ } -+ -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_MasterReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_MasterReceive_BTF(hi2c); -+ } -+ } -+ } -+ /* Slave mode selected */ -+ else -+ { -+ /* ADDR set --------------------------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_ADDR(hi2c); -+ } -+ /* STOPF set --------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_Slave_STOPF(hi2c); -+ } -+ /* I2C in mode Transmitter -----------------------------------------------*/ -+ else if((sr2itflags & I2C_FLAG_TRA) != RESET) -+ { -+ /* TXE set and BTF reset -----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveTransmit_TXE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveTransmit_BTF(hi2c); -+ } -+ } -+ /* I2C in mode Receiver --------------------------------------------------*/ -+ else -+ { -+ /* RXNE set and BTF reset ----------------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) -+ { -+ I2C_SlaveReceive_RXNE(hi2c); -+ } -+ /* BTF set -------------------------------------------------------------*/ -+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) -+ { -+ I2C_SlaveReceive_BTF(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief This function handles I2C error interrupt request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -+{ -+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; -+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); -+ uint32_t itsources = READ_REG(hi2c->Instance->CR2); -+ -+ /* I2C Bus error interrupt occurred ----------------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; -+ -+ /* Clear BERR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); -+ } -+ -+ /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ -+ if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; -+ -+ /* Clear ARLO flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); -+ } -+ -+ /* I2C Acknowledge failure error interrupt occurred ------------------------*/ -+ if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ tmp1 = hi2c->Mode; -+ tmp2 = hi2c->XferCount; -+ tmp3 = hi2c->State; -+ tmp4 = hi2c->PreviousState; -+ if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ -+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ -+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) -+ { -+ I2C_Slave_AF(hi2c); -+ } -+ else -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ -+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ -+ if(hi2c->Mode == HAL_I2C_MODE_MASTER) -+ { -+ /* Generate Stop */ -+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); -+ } -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ } -+ -+ /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ -+ if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; -+ /* Clear OVR flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); -+ } -+ -+ /* Call the Error Callback in case of Error detected -----------------------*/ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ I2C_ITError(hi2c); -+ } -+} -+ -+/** -+ * @brief Master Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Master Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MasterRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** @brief Slave Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Slave Address Match callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition -+ * @param AddrMatchCode Address Match Code -+ * @retval None -+ */ -+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ UNUSED(TransferDirection); -+ UNUSED(AddrMatchCode); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AddrCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Listen Complete callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ListenCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Tx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemTxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief Memory Rx Transfer completed callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_MemRxCpltCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C error callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_ErrorCallback can be implemented in the user file -+ */ -+} -+ -+/** -+ * @brief I2C abort callback. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval None -+ */ -+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -+{ -+ /* Prevent unused argument(s) compilation warning */ -+ UNUSED(hi2c); -+ -+ /* NOTE : This function should not be modified, when the callback is needed, -+ the HAL_I2C_AbortCpltCallback could be implemented in the user file -+ */ -+} -+ -+/** -+ * @} -+ */ -+ -+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions -+ * @brief Peripheral State and Errors functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Peripheral State, Mode and Error functions ##### -+ =============================================================================== -+ [..] -+ This subsection permits to get in run-time the status of the peripheral -+ and the data flow. -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Return the I2C handle state. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL state -+ */ -+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -+{ -+ /* Return I2C handle state */ -+ return hi2c->State; -+} -+ -+/** -+ * @brief Return the I2C Master, Slave, Memory or no mode. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL mode -+ */ -+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->Mode; -+} -+ -+/** -+ * @brief Return the I2C error code -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval I2C Error Code -+ */ -+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -+{ -+ return hi2c->ErrorCode; -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @brief Handle TXE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ -+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ else -+ { -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0) -+ { -+ /* If Memory address size is 8Bit */ -+ if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount += 2; -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ } -+ else if(hi2c->EventCount == 1) -+ { -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); -+ -+ hi2c->EventCount++; -+ } -+ else if(hi2c->EventCount == 2) -+ { -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ else -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ else -+ { -+ /* Call TxCpltCallback() directly if no stop mode is set */ -+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) -+ { -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ else /* Generate Stop condition then Call TxCpltCallback() */ -+ { -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemTxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterTxCpltCallback(hi2c); -+ } -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ uint32_t tmp = 0U; -+ -+ tmp = hi2c->XferCount; -+ if(tmp > 3U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if(hi2c->XferCount == 3) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 4 bytes -+ on BTF subroutine */ -+ /* Disable BUF interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ } -+ } -+ else if((tmp == 1U) || (tmp == 0U)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Master receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(hi2c->XferCount == 4U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 3U) -+ { -+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes -+ on BTF subroutine if there is a reception delay between N-1 and N byte */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ /* Prepare next transfer or stop current transfer */ -+ if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ /* Disable EVT and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ else -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle SB flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave 7 Bits address */ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); -+ } -+ else -+ { -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); -+ } -+ } -+ else -+ { -+ if(hi2c->EventCount == 0U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); -+ } -+ else if(hi2c->EventCount == 1U) -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD10 flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) -+{ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADDR flag for Master -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentMode = hi2c->Mode; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ uint32_t Prev_State = hi2c->PreviousState; -+ -+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX) -+ { -+ if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ hi2c->EventCount++; -+ } -+ else -+ { -+ if(hi2c->XferCount == 0U) -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ else if(hi2c->XferCount == 1U) -+ { -+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ /* Prepare next transfer or stop current transfer */ -+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ -+ && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ } -+ } -+ else if(hi2c->XferCount == 2U) -+ { -+ if(hi2c->XferOptions != I2C_NEXT_FRAME) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Enable Pos */ -+ hi2c->Instance->CR1 |= I2C_CR1_POS; -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ } -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ else -+ { -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ /* Enable Last DMA bit */ -+ hi2c->Instance->CR2 |= I2C_CR2_LAST; -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ /* Reset Event counter */ -+ hi2c->EventCount = 0U; -+ } -+ } -+ else -+ { -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle TXE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Tx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave transmitter -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Write data to DR */ -+ hi2c->Instance->DR = (*hi2c->pBuffPtr++); -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle RXNE flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ -+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* Last Byte is received, disable Interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); -+ -+ /* Set state at HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ -+ /* Call the Rx complete callback to inform upper layer of the end of receive process */ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle BTF flag for Slave receiver -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) -+{ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle ADD flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) -+{ -+ uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; -+ uint16_t SlaveAddrCode = 0U; -+ -+ /* Transfer Direction requested by Master */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) -+ { -+ TransferDirection = I2C_DIRECTION_TRANSMIT; -+ } -+ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress1; -+ } -+ else -+ { -+ SlaveAddrCode = hi2c->Init.OwnAddress2; -+ } -+ -+ /* Call Slave Addr callback */ -+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Handle STOPF flag for Slave -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear STOPF flag */ -+ __HAL_I2C_CLEAR_STOPFLAG(hi2c); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* If a DMA is ongoing, Update handle size context */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); -+ } -+ else -+ { -+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); -+ } -+ } -+ -+ /* All data are not transferred, so set error code accordingly */ -+ if(hi2c->XferCount != 0U) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ hi2c->XferCount--; -+ } -+ -+ /* Set ErrorCode corresponding to a Non-Acknowledge */ -+ //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; -+ } -+ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ I2C_ITError(hi2c); -+ } -+ else -+ { -+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ -+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else -+ { -+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_SlaveRxCpltCallback(hi2c); -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ -+ (CurrentState == HAL_I2C_STATE_LISTEN)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+ else if(CurrentState == HAL_I2C_STATE_BUSY_TX) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable EVT, BUF and ERR interrupt */ -+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); -+ -+ /* Clear AF flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ HAL_I2C_SlaveTxCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Clear AF flag only */ -+ /* State Listen, but XferOptions == FIRST or NEXT */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief I2C interrupts error process -+ * @param hi2c I2C handle. -+ * @retval None -+ */ -+static void I2C_ITError(I2C_HandleTypeDef *hi2c) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) -+ { -+ /* keep HAL_I2C_STATE_LISTEN */ -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_LISTEN; -+ } -+ else -+ { -+ /* If state is an abort treatment on going, don't change state */ -+ /* This change will be do later */ -+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ } -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ } -+ -+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_POS; -+ -+ /* Abort DMA transfer */ -+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) -+ { -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) -+ { -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly XferAbortCallback function in case of error */ -+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); -+ } -+ } -+ else -+ { -+ /* Set the DMA Abort callback : -+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ -+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; -+ -+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ -+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); -+ } -+ } -+ } -+ else if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ /* Store Last receive data if any */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) -+ { -+ /* Read data from DR */ -+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; -+ } -+ -+ /* Call user error callback */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ /* STOP Flag is not set after a NACK reception */ -+ /* So may inform upper layer that listen phase is stopped */ -+ /* during NACK error treatment */ -+ if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) -+ { -+ hi2c->XferOptions = I2C_NO_OPTION_FRAME; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -+ HAL_I2C_ListenCpltCallback(hi2c); -+ } -+} -+ -+/** -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address The device 7 bits address value -+ * in datasheet must be shifted to the left before calling the interface -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentXferOptions = hi2c->XferOptions; -+ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start condition if first transfer */ -+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) -+ { -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) -+ { -+ /* Generate ReStart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ } -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) -+ { -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ } -+ else -+ { -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); -+ -+ /* Wait until ADD10 flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send header of slave address */ -+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); -+ } -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for write request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief Master sends target device address followed by internal memory address for read request. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param DevAddress Target device address -+ * @param MemAddress Internal memory address -+ * @param MemAddSize Size of internal memory address -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Enable Acknowledge */ -+ hi2c->Instance->CR1 |= I2C_CR1_ACK; -+ -+ /* Generate Start */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Clear ADDR flag */ -+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* If Memory address size is 8Bit */ -+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) -+ { -+ /* Send Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ /* If Memory address size is 16Bit */ -+ else -+ { -+ /* Send MSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Send LSB of Memory Address */ -+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); -+ } -+ -+ /* Wait until TXE flag is set */ -+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ /* Generate Restart */ -+ hi2c->Instance->CR1 |= I2C_CR1_START; -+ -+ /* Wait until SB flag is set */ -+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) -+ { -+ return HAL_TIMEOUT; -+ } -+ -+ /* Send slave address */ -+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); -+ -+ /* Wait until ADDR flag is set */ -+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) -+ { -+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) -+ { -+ return HAL_ERROR; -+ } -+ else -+ { -+ return HAL_TIMEOUT; -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief DMA I2C process complete callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ -+ uint32_t CurrentState = hi2c->State; -+ uint32_t CurrentMode = hi2c->Mode; -+ -+ if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) -+ { -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Enable EVT and ERR interrupt */ -+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); -+ } -+ else -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Disable Last DMA */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_LAST; -+ -+ /* Disable DMA Request */ -+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Check if Errors has been detected during transfer */ -+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) -+ { -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ if(hi2c->Mode == HAL_I2C_MODE_MEM) -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MemRxCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ HAL_I2C_MasterRxCpltCallback(hi2c); -+ } -+ } -+ } -+} -+ -+/** -+ * @brief DMA I2C communication error callback. -+ * @param hdma DMA handle -+ * @retval None -+ */ -+static void I2C_DMAError(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; -+ -+ /* Ignore DMA FIFO error */ -+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) -+ { -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; -+ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief DMA I2C communication abort callback -+ * (To be called at end of DMA Abort procedure). -+ * @param hdma DMA handle. -+ * @retval None -+ */ -+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -+{ -+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; -+ -+ /* Disable Acknowledge */ -+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; -+ -+ hi2c->XferCount = 0U; -+ -+ /* Reset XferAbortCallback */ -+ hi2c->hdmatx->XferAbortCallback = NULL; -+ hi2c->hdmarx->XferAbortCallback = NULL; -+ -+ /* Check if come from abort from user */ -+ if(hi2c->State == HAL_I2C_STATE_ABORT) -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_AbortCpltCallback(hi2c); -+ } -+ else -+ { -+ hi2c->State = HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Disable I2C peripheral to prevent dummy data in buffer */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Call the corresponding callback to inform upper layer of End of Transfer */ -+ HAL_I2C_ErrorCallback(hi2c); -+ } -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Status The new Flag status (SET or RESET). -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -+{ -+ /* Wait until flag is set */ -+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) -+ { -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ hi2c->Mode = HAL_I2C_MODE_NONE; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for Master addressing phase. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for I2C module -+ * @param Flag specifies the I2C flag to check. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) -+ { -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Generate Stop */ -+ hi2c->Instance->CR1 |= I2C_CR1_STOP; -+ -+ /* Clear AF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) -+ { -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if(Timeout != HAL_MAX_DELAY) -+ { -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) -+ { -+ /* Check if a NACK is detected */ -+ if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) -+ { -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @param Timeout Timeout duration -+ * @param Tickstart Tick start value -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -+{ -+ -+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) -+ { -+ /* Check if a STOPF is detected */ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) -+ { -+ /* Clear STOP Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ -+ /* Check for the Timeout */ -+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) -+ { -+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_TIMEOUT; -+ } -+ } -+ return HAL_OK; -+} -+ -+/** -+ * @brief This function handles Acknowledge failed detection during an I2C Communication. -+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2C. -+ * @retval HAL status -+ */ -+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) -+{ -+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) -+ { -+ /* Clear NACKF Flag */ -+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); -+ -+ hi2c->ErrorCode = HAL_I2C_ERROR_AF; -+ hi2c->PreviousState = I2C_STATE_NONE; -+ hi2c->State= HAL_I2C_STATE_READY; -+ -+ /* Process Unlocked */ -+ __HAL_UNLOCK(hi2c); -+ -+ return HAL_ERROR; -+ } -+ return HAL_OK; -+} -+/** -+ * @} -+ */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -new file mode 100644 -index 0000000..de8f160 ---- /dev/null -+++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c -@@ -0,0 +1,204 @@ -+/** -+ ****************************************************************************** -+ * @file stm32f4xx_hal_i2c_ex.c -+ * @author MCD Application Team -+ * @brief I2C Extension HAL module driver. -+ * This file provides firmware functions to manage the following -+ * functionalities of I2C extension peripheral: -+ * + Extension features functions -+ * -+ @verbatim -+ ============================================================================== -+ ##### I2C peripheral extension features ##### -+ ============================================================================== -+ -+ [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ -+ 429xx/439xx devices contains the following additional features : -+ -+ (+) Possibility to disable or enable Analog Noise Filter -+ (+) Use of a configured Digital Noise Filter -+ -+ ##### How to use this driver ##### -+ ============================================================================== -+ [..] This driver provides functions to configure Noise Filter -+ (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() -+ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() -+ -+ @endverbatim -+ ****************************************************************************** -+ * @attention -+ * -+ *

© COPYRIGHT(c) 2017 STMicroelectronics

-+ * -+ * Redistribution and use in source and binary forms, with or without modification, -+ * are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+ -+/** @addtogroup STM32F4xx_HAL_Driver -+ * @{ -+ */ -+ -+/** @defgroup I2CEx I2CEx -+ * @brief I2C HAL module driver -+ * @{ -+ */ -+ -+#ifdef HAL_I2C_MODULE_ENABLED -+ -+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ -+ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ -+ defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) -+/* Private typedef -----------------------------------------------------------*/ -+/* Private define ------------------------------------------------------------*/ -+/* Private macro -------------------------------------------------------------*/ -+/* Private variables ---------------------------------------------------------*/ -+/* Private function prototypes -----------------------------------------------*/ -+/* Exported functions --------------------------------------------------------*/ -+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions -+ * @{ -+ */ -+ -+ -+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions -+ * @brief Extension features functions -+ * -+@verbatim -+ =============================================================================== -+ ##### Extension features functions ##### -+ =============================================================================== -+ [..] This section provides functions allowing to: -+ (+) Configure Noise Filters -+ -+@endverbatim -+ * @{ -+ */ -+ -+/** -+ * @brief Configures I2C Analog noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param AnalogFilter new state of the Analog filter. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -+{ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Reset I2Cx ANOFF bit */ -+ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); -+ -+ /* Disable the analog filter */ -+ hi2c->Instance->FLTR |= AnalogFilter; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @brief Configures I2C Digital noise filter. -+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains -+ * the configuration information for the specified I2Cx peripheral. -+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. -+ * @retval HAL status -+ */ -+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -+{ -+ uint16_t tmpreg = 0; -+ -+ /* Check the parameters */ -+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); -+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); -+ -+ if(hi2c->State == HAL_I2C_STATE_READY) -+ { -+ hi2c->State = HAL_I2C_STATE_BUSY; -+ -+ /* Disable the selected I2C peripheral */ -+ __HAL_I2C_DISABLE(hi2c); -+ -+ /* Get the old register value */ -+ tmpreg = hi2c->Instance->FLTR; -+ -+ /* Reset I2Cx DNF bit [3:0] */ -+ tmpreg &= ~(I2C_FLTR_DNF); -+ -+ /* Set I2Cx DNF coefficient */ -+ tmpreg |= DigitalFilter; -+ -+ /* Store the new register value */ -+ hi2c->Instance->FLTR = tmpreg; -+ -+ __HAL_I2C_ENABLE(hi2c); -+ -+ hi2c->State = HAL_I2C_STATE_READY; -+ -+ return HAL_OK; -+ } -+ else -+ { -+ return HAL_BUSY; -+ } -+} -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ -+ STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ -+ STM32F423xx */ -+ -+#endif /* HAL_I2C_MODULE_ENABLED */ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/i2c.h b/Firmware/Board/v3/Inc/i2c.h -new file mode 100644 -index 0000000..f449b88 ---- /dev/null -+++ b/Firmware/Board/v3/Inc/i2c.h -@@ -0,0 +1,91 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.h -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+/* Define to prevent recursive inclusion -------------------------------------*/ -+#ifndef __i2c_H -+#define __i2c_H -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "stm32f4xx_hal.h" -+#include "main.h" -+ -+/* USER CODE BEGIN Includes */ -+ -+/* USER CODE END Includes */ -+ -+extern I2C_HandleTypeDef hi2c1; -+ -+/* USER CODE BEGIN Private defines */ -+ -+/* USER CODE END Private defines */ -+ -+extern void _Error_Handler(char *, int); -+ -+void MX_I2C1_Init(uint8_t addr); -+ -+/* USER CODE BEGIN Prototypes */ -+ -+/* USER CODE END Prototypes */ -+ -+#ifdef __cplusplus -+} -+#endif -+#endif /*__ i2c_H */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -index d0f48f5..b3ef59a 100644 ---- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -+++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h -@@ -65,7 +65,7 @@ - /* #define HAL_SRAM_MODULE_ENABLED */ - /* #define HAL_SDRAM_MODULE_ENABLED */ - /* #define HAL_HASH_MODULE_ENABLED */ --/* #define HAL_I2C_MODULE_ENABLED */ -+#define HAL_I2C_MODULE_ENABLED - /* #define HAL_I2S_MODULE_ENABLED */ - /* #define HAL_IWDG_MODULE_ENABLED */ - /* #define HAL_LTDC_MODULE_ENABLED */ -diff --git a/Firmware/Board/v3/Src/i2c.c b/Firmware/Board/v3/Src/i2c.c -new file mode 100644 -index 0000000..bae77f1 ---- /dev/null -+++ b/Firmware/Board/v3/Src/i2c.c -@@ -0,0 +1,198 @@ -+/** -+ ****************************************************************************** -+ * File Name : I2C.c -+ * Description : This file provides code for the configuration -+ * of the I2C instances. -+ ****************************************************************************** -+ * This notice applies to any and all portions of this file -+ * that are not between comment pairs USER CODE BEGIN and -+ * USER CODE END. Other portions of this file, whether -+ * inserted by the user or by software development tools -+ * are owned by their respective copyright owners. -+ * -+ * Copyright (c) 2018 STMicroelectronics International N.V. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted, provided that the following conditions are met: -+ * -+ * 1. Redistribution of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. Neither the name of STMicroelectronics nor the names of other -+ * contributors to this software may be used to endorse or promote products -+ * derived from this software without specific written permission. -+ * 4. This software, including modifications and/or derivative works of this -+ * software, must execute solely and exclusively on microcontroller or -+ * microprocessor devices manufactured by or for STMicroelectronics. -+ * 5. Redistribution and use of this software other than as permitted under -+ * this license is void and will automatically terminate your rights under -+ * this license. -+ * -+ * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -+ * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY -+ * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT -+ * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ ****************************************************************************** -+ */ -+ -+/* Includes ------------------------------------------------------------------*/ -+#include "i2c.h" -+ -+#include "gpio.h" -+#include "dma.h" -+ -+/* USER CODE BEGIN 0 */ -+ -+/* USER CODE END 0 */ -+ -+I2C_HandleTypeDef hi2c1; -+DMA_HandleTypeDef hdma_i2c1_rx; -+DMA_HandleTypeDef hdma_i2c1_tx; -+ -+/* I2C1 init function */ -+void MX_I2C1_Init(uint8_t addr) -+{ -+ -+ hi2c1.Instance = I2C1; -+ hi2c1.Init.ClockSpeed = 100000; -+ hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; -+ hi2c1.Init.OwnAddress1 = addr << 1; -+ hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; -+ hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; -+ hi2c1.Init.OwnAddress2 = 0; -+ hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; -+ hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; -+ if (HAL_I2C_Init(&hi2c1) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+} -+ -+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ GPIO_InitTypeDef GPIO_InitStruct; -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspInit 0 */ -+ -+ /* USER CODE END I2C1_MspInit 0 */ -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; -+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; -+ GPIO_InitStruct.Pull = GPIO_PULLUP; -+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; -+ GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; -+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); -+ -+ /* I2C1 clock enable */ -+ __HAL_RCC_I2C1_CLK_ENABLE(); -+ -+ /* I2C1 DMA Init */ -+ /* I2C1_RX Init */ -+ hdma_i2c1_rx.Instance = DMA1_Stream0; -+ hdma_i2c1_rx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; -+ hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_rx.Init.Mode = DMA_CIRCULAR; -+ hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c1_rx); -+ -+ /* I2C1_TX Init */ -+ hdma_i2c1_tx.Instance = DMA1_Stream6; -+ hdma_i2c1_tx.Init.Channel = DMA_CHANNEL_1; -+ hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; -+ hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; -+ hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; -+ hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; -+ hdma_i2c1_tx.Init.Mode = DMA_NORMAL; -+ hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_LOW; -+ hdma_i2c1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; -+ if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK) -+ { -+ _Error_Handler(__FILE__, __LINE__); -+ } -+ -+ __HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c1_tx); -+ -+ /* I2C1 interrupt Init */ -+ HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0); -+ HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspInit 1 */ -+ -+ /* USER CODE END I2C1_MspInit 1 */ -+ } -+} -+ -+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) -+{ -+ -+ if(i2cHandle->Instance==I2C1) -+ { -+ /* USER CODE BEGIN I2C1_MspDeInit 0 */ -+ -+ /* USER CODE END I2C1_MspDeInit 0 */ -+ /* Peripheral clock disable */ -+ __HAL_RCC_I2C1_CLK_DISABLE(); -+ -+ /**I2C1 GPIO Configuration -+ PB8 ------> I2C1_SCL -+ PB9 ------> I2C1_SDA -+ */ -+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); -+ -+ /* I2C1 DMA DeInit */ -+ HAL_DMA_DeInit(i2cHandle->hdmarx); -+ HAL_DMA_DeInit(i2cHandle->hdmatx); -+ -+ /* I2C1 interrupt Deinit */ -+ HAL_NVIC_DisableIRQ(I2C1_EV_IRQn); -+ HAL_NVIC_DisableIRQ(I2C1_ER_IRQn); -+ /* USER CODE BEGIN I2C1_MspDeInit 1 */ -+ -+ /* USER CODE END I2C1_MspDeInit 1 */ -+ } -+} -+ -+/* USER CODE BEGIN 1 */ -+ -+/* USER CODE END 1 */ -+ -+/** -+ * @} -+ */ -+ -+/** -+ * @} -+ */ -+ -+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c -index 987e0bd..efaeef1 100644 ---- a/Firmware/Board/v3/Src/main.c -+++ b/Firmware/Board/v3/Src/main.c -@@ -187,7 +187,6 @@ int main(void) - MX_ADC3_Init(); - MX_TIM2_Init(); - MX_UART4_Init(); -- MX_CAN1_Init(); - /* USER CODE BEGIN 2 */ - - //Required to use OC4 for ADC triggering. --- -2.17.0 - diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 00000000..5452a507 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +}I2C_InitTypeDef; + +/** + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +}HAL_I2C_StateTypeDef; + +/** + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +}HAL_I2C_ModeTypeDef; + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + +}I2C_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_Error_Code I2C Error Code + * @brief I2C Error Code + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_SMBALERT 0x00018000U +#define I2C_FLAG_TIMEOUT 0x00014000U +#define I2C_FLAG_PECERR 0x00011000U +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_SMBHOST 0x00100040U +#define I2C_FLAG_SMBDEFAULT 0x00100020U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_SMBHOST: SMBus host header + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ + ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) + +/** @brief Disable the I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions *****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State, Mode and Errors functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 00000000..ff47d5cc --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,137 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\ + STM32F413xx || STM32F423xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 00000000..da185200 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,5494 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx Stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup I2C_Private_Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and create the associated handle. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange = 0U; + uint32_t pclk1 = 0U; + + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->CR2 = freqrange; + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2C peripheral. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief I2C MSP Init. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2C MSP DeInit + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Master_Sequential_Transmit_IT() + (++) HAL_I2C_Master_Sequential_Receive_IT() + (++) HAL_I2C_Slave_Sequential_Transmit_IT() + (++) HAL_I2C_Slave_Sequential_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* Generate Start */ + if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + while(hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(hi2c->XferSize > 0U) + { + if(hi2c->XferSize <= 3U) + { + /* One byte */ + if(hi2c->XferSize== 1U) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if(hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if(hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart = 0x00U; + __IO uint32_t count = 0U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(Size == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; + + /* Get tick */ + tickstart = HAL_GetTick(); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + tmp3 = hi2c->State; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + }while(I2C_Trials++ < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + uint32_t CurrentMode = hi2c->Mode; + + /* Master or Memory mode selected */ + if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* SB Set ----------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + + /* I2C in mode Transmitter -----------------------------------------------*/ + if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + } + } + /* Slave mode selected */ + else + { + /* ADDR set --------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_ADDR(hi2c); + } + /* STOPF set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if((sr2itflags & I2C_FLAG_TRA) != RESET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ + if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + tmp1 = hi2c->Mode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback can be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback can be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Return the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if(hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0) + { + /* If Memory address size is 8Bit */ + if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if(hi2c->EventCount == 1) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if(hi2c->EventCount == 2) + { + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp = 0U; + + tmp = hi2c->XferCount; + if(tmp > 3U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if(hi2c->XferCount == 3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if((tmp == 1U) || (tmp == 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + else + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if(hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + return HAL_OK; +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; + } + else + { + if(hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferCount == 1U) + { + if(CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + /* Prepare next transfer or stop current transfer */ + else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + else if(hi2c->XferCount == 2U) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + return HAL_OK; +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Tx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0U) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode = 0U; + + /* Transfer Direction requested by Master */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = hi2c->Init.OwnAddress2; + } + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); + + return HAL_OK; +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* If a DMA is ongoing, Update handle size context */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + else + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + //hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ + (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else + { + if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + } + return HAL_OK; +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else if(CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + + return HAL_OK; +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) + { + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + /* Abort DMA transfer */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Call user error callback */ + HAL_I2C_ErrorCallback(hi2c); + } + /* STOP Flag is not set after a NACK reception */ + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Disable Last DMA */ + hi2c->Instance->CR2 &= ~I2C_CR2_LAST; + + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Ignore DMA FIFO error */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 00000000..de8f1602 --- /dev/null +++ b/Firmware/Board/v3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,204 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\ + STM32F423xx */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h index e518489f..ed26bf39 100644 --- a/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h +++ b/Firmware/Board/v3/Inc/stm32f4xx_hal_conf.h @@ -65,7 +65,7 @@ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ diff --git a/Firmware/Board/v3/Src/main.c b/Firmware/Board/v3/Src/main.c index e390af58..154c98af 100644 --- a/Firmware/Board/v3/Src/main.c +++ b/Firmware/Board/v3/Src/main.c @@ -180,7 +180,7 @@ int main(void) MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); - MX_CAN1_Init(); + // MX_CAN1_Init(); // CAN or I2C called in main.cpp instead MX_TIM1_Init(); MX_TIM8_Init(); MX_TIM3_Init(); From eea82a2e6ac41082065e270cd6ee107a98734000 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:08:08 -0700 Subject: [PATCH 091/106] Cube: Notify OS that we are a composite device --- Firmware/Board/v3/Src/usbd_desc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Src/usbd_desc.c b/Firmware/Board/v3/Src/usbd_desc.c index b0906144..d213f64a 100644 --- a/Firmware/Board/v3/Src/usbd_desc.c +++ b/Firmware/Board/v3/Src/usbd_desc.c @@ -97,7 +97,8 @@ #define USBD_PID_FS 0x0D32 #define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) #define USBD_PRODUCT_STR(s) #s -#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR +#define USBD_PRODUCT_STRING_FS ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR CDC Interface +#define NATIVE_STRING ODrive HW_VERSION_MAJOR.HW_VERSION_MINOR Native Interface #define USBD_SERIALNUMBER_STRING_FS "000000000001" #define USBD_CONFIGURATION_STRING_FS "CDC Config" #define USBD_INTERFACE_STRING_FS "CDC Interface" @@ -233,16 +234,17 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = 0x00, /*bcdUSB */ #endif /* (USBD_LPM_ENABLED == 1) */ 0x02, - 0x02, /*bDeviceClass*/ + // Notify OS that this is a composite device + 0xEF, /*bDeviceClass*/ 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ + 0x01, /*bDeviceProtocol*/ USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ LOBYTE(USBD_VID), /*idVendor*/ HIBYTE(USBD_VID), /*idVendor*/ LOBYTE(USBD_PID_FS), /*idProduct*/ HIBYTE(USBD_PID_FS), /*idProduct*/ 0x00, /*bcdDevice rel. 2.00*/ - 0x02, + 0x03, /* bNumInterfaces */ USBD_IDX_MFC_STR, /*Index of manufacturer string*/ USBD_IDX_PRODUCT_STR, /*Index of product string*/ USBD_IDX_SERIAL_STR, /*Index of serial number string*/ From 492816961ae714786fd4b54146d5463e66f0f9d9 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:51:04 -0700 Subject: [PATCH 092/106] cube: apply canges to USB --- Firmware/Board/v3/Inc/usbd_cdc_if.h | 2 +- Firmware/Board/v3/Inc/usbd_conf.h | 1 + Firmware/Board/v3/Inc/usbd_desc.h | 3 +- .../Class/CDC/Inc/usbd_cdc.h | 39 +- .../Class/CDC/Src/usbd_cdc.c | 562 +++++++++++------- .../Core/Inc/usbd_def.h | 4 +- Firmware/Board/v3/Src/usbd_cdc_if.c | 12 +- Firmware/Board/v3/Src/usbd_conf.c | 24 +- 8 files changed, 404 insertions(+), 243 deletions(-) diff --git a/Firmware/Board/v3/Inc/usbd_cdc_if.h b/Firmware/Board/v3/Inc/usbd_cdc_if.h index c15e8b91..ed1d6705 100644 --- a/Firmware/Board/v3/Inc/usbd_cdc_if.h +++ b/Firmware/Board/v3/Inc/usbd_cdc_if.h @@ -132,7 +132,7 @@ extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; * @{ */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair); /* USER CODE BEGIN EXPORTED_FUNCTIONS */ /* USER CODE END EXPORTED_FUNCTIONS */ diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index bf276186..a897ba43 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -89,6 +89,7 @@ * @brief Defines for configuration of the Usb device. * @{ */ + #define MS_VendorCode 'P' /*---------- -----------*/ #define USBD_MAX_NUM_INTERFACES 1 diff --git a/Firmware/Board/v3/Inc/usbd_desc.h b/Firmware/Board/v3/Inc/usbd_desc.h index 18d1f34e..2a74de31 100644 --- a/Firmware/Board/v3/Inc/usbd_desc.h +++ b/Firmware/Board/v3/Inc/usbd_desc.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.h * @version : v1.0_Cube - * @brief : Header for usbd_conf.c file. + * @brief : Header for usbd_desc.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -46,6 +46,7 @@ * ****************************************************************************** */ + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__H__ #define __USBD_DESC__H__ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index d937b2e8..c029e22a 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -52,13 +52,15 @@ #define CDC_IN_EP 0x81 /* EP1 for data IN */ #define CDC_OUT_EP 0x01 /* EP1 for data OUT */ #define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ +#define ODRIVE_IN_EP 0x83 /* EP3 IN: ODrive device TX endpoint */ +#define ODRIVE_OUT_EP 0x03 /* EP3 OUT: ODrive device RX endpoint */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ -#define USB_CDC_CONFIG_DESC_SIZ 67 +#define USB_CDC_CONFIG_DESC_SIZ (67 + 39) #define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE #define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE @@ -103,23 +105,29 @@ typedef struct _USBD_CDC_Itf int8_t (* Init) (void); int8_t (* DeInit) (void); int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); + int8_t (* Receive) (uint8_t *, uint32_t *, uint8_t); }USBD_CDC_ItfTypeDef; +typedef struct +{ + uint8_t* Buffer; + uint32_t Length; + volatile uint8_t State; +} +USBD_CDC_EP_HandleTypeDef; typedef struct { uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; + uint8_t CmdLength; + + USBD_CDC_EP_HandleTypeDef CDC_Tx; + USBD_CDC_EP_HandleTypeDef CDC_Rx; + + USBD_CDC_EP_HandleTypeDef ODRIVE_Tx; + USBD_CDC_EP_HandleTypeDef ODRIVE_Rx; } USBD_CDC_HandleTypeDef; @@ -151,14 +159,15 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length); + uint16_t length, + uint8_t endpoint_pair); uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); + uint8_t *pbuff, uint8_t endpoint_pair); -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair); /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 24465641..73313522 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -132,6 +132,9 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +//static uint8_t * USBD_GetUsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); + /* USB Standard Device Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { @@ -173,24 +176,37 @@ USBD_ClassTypeDef USBD_CDC = USBD_CDC_GetFSCfgDesc, USBD_CDC_GetOtherSpeedCfgDesc, USBD_CDC_GetDeviceQualifierDescriptor, + USBD_UsrStrDescriptor }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { /*Configuration Descriptor*/ 0x09, /* bLength: Configuration Descriptor size */ USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ + 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 custom) */ 0x01, /* bConfigurationValue: Configuration value */ 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ 0xC0, /* bmAttributes: self powered */ 0x32, /* MaxPower 0 mA */ + + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: CDC device (virtual com port) */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass: Communication Interface Class */ + 0x02, /* bFunctionSubClass: Abstract Control Model */ + 0x01, /* bFunctionProtocol: Common AT commands */ + 0x00, /* iFunction */ /*---------------------------------------------------------------------------*/ - + /*Interface Descriptor */ 0x09, /* bLength: Interface Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ @@ -202,7 +218,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bInterfaceSubClass: Abstract Control Model */ 0x01, /* bInterfaceProtocol: Common AT commands */ 0x00, /* iInterface: */ - + /*Header Functional Descriptor*/ 0x05, /* bLength: Endpoint Descriptor size */ 0x24, /* bDescriptorType: CS_INTERFACE */ @@ -229,7 +245,7 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x06, /* bDescriptorSubtype: Union func desc */ 0x00, /* bMasterInterface: Communication class interface */ 0x01, /* bSlaveInterface0: Data Class Interface */ - + /*Endpoint 2 Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ @@ -267,196 +283,52 @@ __ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00, /* bInterval: ignore for Bulk transfer */ + /////////////////////////////////////////////////////////////////////////////// + + /* Interface Association Descriptor: custom device */ + 0x08, /* bLength: IAD size */ + 0x0B, /* bDescriptorType: Interface Association Descriptor */ + 0x02, /* bFirstInterface */ + 0x01, /* bInterfaceCount */ + 0x00, /* bFunctionClass: */ + 0x00, /* bFunctionSubClass: */ + 0x00, /* bFunctionProtocol: */ + 0x06, /* iFunction */ -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ /*---------------------------------------------------------------------------*/ /*Data class interface descriptor*/ 0x09, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ + 0x02, /* bInterfaceNumber: Number of Interface */ 0x00, /* bAlternateSetting: Alternate setting */ 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceClass: vendor specific */ + 0x01, /* bInterfaceSubClass: ODrive Communication */ 0x00, /* bInterfaceProtocol: */ 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ + ODRIVE_OUT_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ 0x07, /* bLength: Endpoint Descriptor size */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ + ODRIVE_IN_EP, /* bEndpointAddress */ 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ } ; -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; /** * @} @@ -508,6 +380,19 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, USBD_EP_TYPE_BULK, CDC_DATA_FS_OUT_PACKET_SIZE); } + + /* Open ODrive IN endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_IN_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_IN_PACKET_SIZE : CDC_DATA_FS_IN_PACKET_SIZE); + + /* Open ODrive OUT endpoint */ + USBD_LL_OpenEP(pdev, + ODRIVE_OUT_EP, + USBD_EP_TYPE_BULK, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + /* Open Command IN EP */ USBD_LL_OpenEP(pdev, CDC_CMD_EP, @@ -529,15 +414,17 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; + hcdc->CDC_Tx.State =0; + hcdc->CDC_Rx.State =0; + hcdc->ODRIVE_Tx.State =0; + hcdc->ODRIVE_Rx.State =0; if(pdev->dev_speed == USBD_SPEED_HIGH ) { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_HS_OUT_PACKET_SIZE); } else @@ -545,11 +432,15 @@ static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, - hcdc->RxBuffer, + hcdc->CDC_Rx.Buffer, CDC_DATA_FS_OUT_PACKET_SIZE); } - + /* Prepare ODrive Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + ODRIVE_OUT_EP, + hcdc->ODRIVE_Rx.Buffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } return ret; } @@ -566,17 +457,25 @@ static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, { uint8_t ret = 0; - /* Open EP IN */ + /* Close EP IN */ USBD_LL_CloseEP(pdev, CDC_IN_EP); - /* Open EP OUT */ + /* Close EP OUT */ USBD_LL_CloseEP(pdev, CDC_OUT_EP); - /* Open Command IN EP */ + /* Close Command IN EP */ USBD_LL_CloseEP(pdev, CDC_CMD_EP); + + /* Close EP IN */ + USBD_LL_CloseEP(pdev, + ODRIVE_IN_EP); + + /* Close EP OUT */ + USBD_LL_CloseEP(pdev, + ODRIVE_OUT_EP); /* DeInit physical Interface components */ @@ -648,6 +547,9 @@ static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, case USB_REQ_SET_INTERFACE : break; } + + case USB_REQ_TYPE_VENDOR: + return USBD_WinUSBComm_SetupVendor(pdev, req); default: break; @@ -668,8 +570,12 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) if(pdev->pClassData != NULL) { - - hcdc->TxState = 0; + // NOTE: We would logically expect xx_IN_EP here, but we actually get the xx_OUT_EP + if (epnum == CDC_OUT_EP) + hcdc->CDC_Tx.State = 0; + if (epnum == ODRIVE_OUT_EP) + hcdc->ODRIVE_Tx.State = 0; + //Note: We could use independent semaphores for simoultainous USB transmission. osSemaphoreRelease(sem_usb_tx); return USBD_OK; } @@ -689,15 +595,24 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (epnum == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (epnum == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); + hEP_Rx->Length = USBD_LL_GetRxDataSize (pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ if(pdev->pClassData != NULL) { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hEP_Rx->Buffer, &hEP_Rx->Length, epnum); return USBD_OK; } @@ -740,8 +655,8 @@ static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) */ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -753,8 +668,8 @@ static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -766,8 +681,8 @@ static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) { - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; } /** @@ -810,12 +725,22 @@ uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, */ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, uint8_t *pbuff, - uint16_t length) + uint16_t length, + uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + } else { + return USBD_FAIL; + } + + hEP_Tx->Buffer = pbuff; + hEP_Tx->Length = length; return USBD_OK; } @@ -828,11 +753,20 @@ uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, * @retval status */ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) + uint8_t *pbuff, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; + + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + } else { + return USBD_FAIL; + } - hcdc->RxBuffer = pbuff; + hEP_Rx->Buffer = pbuff; return USBD_OK; } @@ -844,23 +778,36 @@ uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, * @param epnum: endpoint number * @retval status */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; if(pdev->pClassData != NULL) { - if(hcdc->TxState == 0) + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Tx; + uint8_t in_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Tx = &hcdc->CDC_Tx; + in_ep = CDC_IN_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Tx = &hcdc->ODRIVE_Tx; + in_ep = ODRIVE_IN_EP; + } else { + return USBD_FAIL; + } + + if(hEP_Tx->State == 0) { /* Tx Transfer in progress */ - hcdc->TxState = 1; + hEP_Tx->State = 1; /* Transmit next packet */ USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - + in_ep, + hEP_Tx->Buffer, + hEP_Tx->Length); + return USBD_OK; } else @@ -881,29 +828,32 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; /* Suspend or Resume USB Out process */ if(pdev->pClassData != NULL) { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); + // Select Endpoint + USBD_CDC_EP_HandleTypeDef* hEP_Rx; + uint8_t out_ep; + if (endpoint_pair == CDC_OUT_EP) { + hEP_Rx = &hcdc->CDC_Rx; + out_ep = CDC_OUT_EP; + } else if (endpoint_pair == ODRIVE_OUT_EP) { + hEP_Rx = &hcdc->ODRIVE_Rx; + out_ep = ODRIVE_OUT_EP; + } else { + return USBD_FAIL; } + + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + out_ep, + hEP_Rx->Buffer, + pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE); + return USBD_OK; } else @@ -911,6 +861,184 @@ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) return USBD_FAIL; } } + + +/* WinUSB support ------------------------------------------------------------*/ +/* +* This section tells Windows that it should automatically load the WinUSB driver +* for the device (more specifically, interface 2 because it's a composite device). +* This allows for driverless communication with the device. +*/ + +#define NUM_INTERFACES 1 + +#if NUM_INTERFACES == 2 +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24 + 24) +#else +#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ (16 + 24) +#endif + + +// This associates winusb driver with the device +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Compat_ID_OS_Desc[USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ] __ALIGN_END = +{ + // +-- Offset in descriptor + // | +-- Size + // v v + USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ, 0, 0, 0, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended compat ID descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x04, 0x00, // 6 wIndex 2 WORD An index that identifies the particular OS feature descriptor + NUM_INTERFACES, // 8 bCount 1 BYTE The number of custom property sections + 0, 0, 0, 0, 0, 0, 0, // 9 RESERVED 7 BYTEs Reserved + // ===================== + // 16 + + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#if NUM_INTERFACES == 2 + // +-- Offset from function section start + // | +-- Size + // v v + 2, // 0 bFirstInterfaceNumber 1 BYTE The interface or function number + 0, // 1 RESERVED 1 BYTE Reserved + 0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00, // 2 compatibleID 8 BYTEs The function’s compatible ID ("WINUSB") + 0, 0, 0, 0, 0, 0, 0, 0, // 10 subCompatibleID 8 BYTEs The function’s subcompatible ID + 0, 0, 0, 0, 0, 0, // 18 RESERVED 6 BYTEs Reserved + // ================================= + // 24 +#endif +}; + + +// Properties are added to: +// HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Enum\USB\VID_xxxx&PID_xxxx\sssssssss\Device Parameters +// Use USBDeview or similar to uninstall + +__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Properties_OS_Desc[0xB6] __ALIGN_END = +{ + 0xB6, 0x00, 0x00, 0x00, // 0 dwLength 4 DWORD The length, in bytes, of the complete extended properties descriptor + 0x00, 0x01, // 4 bcdVersion 2 BCD The descriptor’s version number, in binary coded decimal (BCD) format + 0x05, 0x00, // 6 wIndex 2 WORD The index for extended properties OS descriptors + 0x02, 0x00, // 8 wCount 2 WORD The number of custom property sections that follow the header section + // ==================== + // 10 +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, // 0 dwSize 4 DWORD The size of this custom properties section + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 4 DWORD Property data format + 0x28, 0x00, // 8 wPropertyNameLength 2 DWORD Property name length + // ======================================== + // 10 + // 10 bPropertyName PNL WCHAR[] The property name + 'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0, + 't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0, + 'U',0, 'I',0, 'D',0, 0,0, + // ======================================== + // 40 (0x28) + + 0x4E, 0x00, 0x00, 0x00, // 10 + PNL dwPropertyDataLength 4 DWORD Length of the buffer holding the property data + // ======================================== + // 4 + // 14 + PNL bPropertyData PDL Format-dependent Property data + '{',0, 'E',0, 'A',0, '0',0, 'B',0, 'D',0, '5',0, 'C',0, + '3',0, '-',0, '5',0, '0',0, 'F',0, '3',0, '-',0, '4',0, + '8',0, '8',0, '8',0, '-',0, '8',0, '4',0, 'B',0, '4',0, + '-',0, '7',0, '4',0, 'E',0, '5',0, '0',0, 'E',0, '1',0, + '6',0, '4',0, '9',0, 'D',0, 'B',0, '}',0, 0 ,0, + // ======================================== + // 78 (0x4E) +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + 0x3E, 0x00, 0x00, 0x00, // 0 dwSize 0x00000030 (62 bytes) + 0x01, 0x00, 0x00, 0x00, // 4 dwPropertyDataType 0x00000001 (Unicode string) + 0x0C, 0x00, // 8 wPropertyNameLength 0x000C (12 bytes) + // ======================================== + // 10 + 'L',0, 'a',0, 'b',0, 'e',0, 'l',0, 0,0, + // 10 bPropertyName “Label” + // ======================================== + // 12 + 0x24, 0x00, 0x00, 0x00, // 22 dwPropertyDataLength 0x00000016 (36 bytes) + // ======================================== + // 4 + 'O',0, 'D',0, 'r',0, 'i',0, 'v',0, 'e',0, 0,0 + // 26 bPropertyData “ODrive” + // ======================================== + // 14 + +}; + + + +static uint8_t USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (req->wIndex) + { + case 0x04: + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Compat_ID_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + uint8_t byInterfaceIndex = (uint8_t)req->wValue; + if ( req->wIndex != 0x05 ) + { + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + switch ( byInterfaceIndex ) + { + case 0: +#if NUM_INTERFACES == 2 + case 1: +#endif + USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Properties_OS_Desc, req->wLength); + break; + default: + USBD_CtlError(pdev , req); + return USBD_FAIL; + } + return USBD_OK; +} +static uint8_t USBD_WinUSBComm_SetupVendorDevice(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendorInterface(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_CtlError(pdev , req); + // TODO: check if this is important + return USBD_FAIL; +} +static uint8_t USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch ( req->bmRequest & USB_REQ_RECIPIENT_MASK ) + { + case USB_REQ_RECIPIENT_DEVICE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorDevice(pdev, req); + case USB_REQ_RECIPIENT_INTERFACE: + return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorInterface(pdev, req); + case USB_REQ_RECIPIENT_ENDPOINT: + // fall through + default: + break; + } + USBD_CtlError(pdev , req); + return USBD_FAIL; +} + /** * @} */ diff --git a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index 8fbe81e4..f259b51d 100644 --- a/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/Firmware/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -68,7 +68,9 @@ #define USBD_IDX_PRODUCT_STR 0x02 #define USBD_IDX_SERIAL_STR 0x03 #define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_INTERFACE_STR 0x05 +#define USBD_IDX_ODRIVE_INTF_STR 0x06 +#define USBD_IDX_MICROSOFT_DESC_STR 0xEE #define USB_REQ_TYPE_STANDARD 0x00 #define USB_REQ_TYPE_CLASS 0x20 diff --git a/Firmware/Board/v3/Src/usbd_cdc_if.c b/Firmware/Board/v3/Src/usbd_cdc_if.c index fcc712a3..b8cb6e6c 100644 --- a/Firmware/Board/v3/Src/usbd_cdc_if.c +++ b/Firmware/Board/v3/Src/usbd_cdc_if.c @@ -117,10 +117,12 @@ /* Create buffer for reception and transmission */ /* It's up to user to redefine and/or remove those define */ /** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t CDCRxBufferFS[APP_RX_DATA_SIZE]; +uint8_t ODRIVERxBufferFS[APP_RX_DATA_SIZE]; /** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t CDCTxBufferFS[APP_TX_DATA_SIZE]; +uint8_t ODRIVETxBufferFS[APP_TX_DATA_SIZE]; /* USER CODE BEGIN PRIVATE_VARIABLES */ /* USER CODE END PRIVATE_VARIABLES */ @@ -151,7 +153,7 @@ extern USBD_HandleTypeDef hUsbDeviceFS; static int8_t CDC_Init_FS(void); static int8_t CDC_DeInit_FS(void); static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len, uint8_t endpoint_pair); /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ @@ -289,7 +291,7 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair) { /* USER CODE BEGIN 6 */ usb_rx_process_packet(Buf, *Len, endpoint_pair); @@ -309,7 +311,7 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair) { uint8_t result = USBD_OK; /* USER CODE BEGIN 7 */ diff --git a/Firmware/Board/v3/Src/usbd_conf.c b/Firmware/Board/v3/Src/usbd_conf.c index 7046dc96..2d66d4a1 100644 --- a/Firmware/Board/v3/Src/usbd_conf.c +++ b/Firmware/Board/v3/Src/usbd_conf.c @@ -66,7 +66,7 @@ /* USER CODE END PV */ - PCD_HandleTypeDef hpcd_USB_OTG_FS; +PCD_HandleTypeDef hpcd_USB_OTG_FS; void _Error_Handler(char * file, int line); /* External functions --------------------------------------------------------*/ @@ -154,6 +154,23 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) */ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { + USBD_StatusTypeDef ret = USBD_OK; + USBD_HandleTypeDef *pdev = hpcd->pData; + USBD_SetupReqTypedef *req = &pdev->request; + USBD_ParseSetupRequest(req, (uint8_t *)hpcd->Setup); + if ( ( USB_REQ_TYPE_VENDOR == (req->bmRequest & USB_REQ_TYPE_MASK) ) && ( MS_VendorCode == req->bRequest ) ) + { + pdev->ep0_state = USBD_EP0_SETUP; + pdev->ep0_data_len = pdev->request.wLength; + + ret = pdev->pClass->Setup(pdev, req); + + if( (req->wLength == 0) && (ret == USBD_OK) ) + { + USBD_CtlSendStatus(pdev); + } + return; + } USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); } @@ -312,7 +329,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) pdev->pData = &hpcd_USB_OTG_FS; hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; @@ -329,7 +346,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // CDC IN endpoint + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // ODrive IN endpoint } return USBD_OK; } From 5a4e1a4d598609ee7c39325e7f7dc7b7c229c101 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 00:52:53 -0700 Subject: [PATCH 093/106] cube: can auto wake up --- Firmware/Board/v3/Src/can.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index 2171691a..fc7bf388 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -70,7 +70,7 @@ void MX_CAN1_Init(void) hcan1.Init.TimeSeg2 = CAN_BS2_5TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoWakeUp = ENABLE; hcan1.Init.AutoRetransmission = DISABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; From 5e5516b665c0d27e1271d5f1a29d0cfaf6054f99 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:25:50 -0700 Subject: [PATCH 094/106] move configAPPLICATION_ALLOCATED_HEAP to FreeRTOSconfig.h --- Firmware/Board/v3/Inc/FreeRTOSConfig.h | 1 + Firmware/Board/v3/Inc/main.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h | 1 - Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h | 1 - Firmware/Board/v3/Odrive.ioc | 2 +- 5 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Firmware/Board/v3/Inc/FreeRTOSConfig.h b/Firmware/Board/v3/Inc/FreeRTOSConfig.h index 90e233b3..715b0e67 100644 --- a/Firmware/Board/v3/Inc/FreeRTOSConfig.h +++ b/Firmware/Board/v3/Inc/FreeRTOSConfig.h @@ -167,6 +167,7 @@ standard names. */ /* USER CODE BEGIN Defines */ /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +#define configAPPLICATION_ALLOCATED_HEAP 1 // ucHeap allocated in freertos.c /* USER CODE END Defines */ #endif /* FREERTOS_CONFIG_H */ diff --git a/Firmware/Board/v3/Inc/main.h b/Firmware/Board/v3/Inc/main.h index 1e76830d..d41b19ee 100644 --- a/Firmware/Board/v3/Inc/main.h +++ b/Firmware/Board/v3/Inc/main.h @@ -72,7 +72,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h index 567fe028..65f45efd 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_2.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h index 5695d700..64daaa4f 100644 --- a/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h +++ b/Firmware/Board/v3/Inc/prev_board_ver/main_V3_4.h @@ -6,7 +6,6 @@ #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 #define TIM_APB1_DEADTIME_CLOCKS 40 -#define configAPPLICATION_ALLOCATED_HEAP 1 #define TIM_1_8_RCR 2 #define M0_nCS_Pin GPIO_PIN_13 diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc index ab299065..7a334af7 100644 --- a/Firmware/Board/v3/Odrive.ioc +++ b/Firmware/Board/v3/Odrive.ioc @@ -233,7 +233,7 @@ Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 -Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;configAPPLICATION_ALLOCATED_HEAP,1;TIM_1_8_RCR,2 +Mcu.UserConstants=TIM_1_8_CLOCK_HZ,168000000;TIM_1_8_PERIOD_CLOCKS,3500;TIM_1_8_DEADTIME_CLOCKS,20;TIM_APB1_CLOCK_HZ,84000000;TIM_APB1_PERIOD_CLOCKS,4096;TIM_APB1_DEADTIME_CLOCKS,40;TIM_1_8_RCR,2 Mcu.UserName=STM32F405RGTx MxCube.Version=4.27.0 MxDb.Version=DB.4.0.270 From 5559de4eca4c572380fd5c72ec094e6732c106d5 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 24 Oct 2018 01:32:54 -0700 Subject: [PATCH 095/106] cube: support user string --- Firmware/Board/v3/Inc/usbd_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Inc/usbd_conf.h b/Firmware/Board/v3/Inc/usbd_conf.h index a897ba43..dbf800b3 100644 --- a/Firmware/Board/v3/Inc/usbd_conf.h +++ b/Firmware/Board/v3/Inc/usbd_conf.h @@ -98,7 +98,7 @@ /*---------- -----------*/ #define USBD_MAX_STR_DESC_SIZ 512 /*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 +#define USBD_SUPPORT_USER_STRING 1 /*---------- -----------*/ #define USBD_DEBUG_LEVEL 0 /*---------- -----------*/ From fdfa8cf764122d189f3d9ab0e1c1373da13a2db3 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 27 Nov 2018 18:25:13 -0800 Subject: [PATCH 096/106] rename vel ramp rate, add to changelog --- CHANGELOG.md | 1 + Firmware/MotorControl/controller.hpp | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7af1a076..a257960d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Please add a note of your changes below this heading if you make a Pull Request. * Make step dir gpio pins configurable. * Configuration variable `encoder.config.zero_count_on_find_idx`, true by default. Set to false to leave the initial encoder count to be where the axis was at boot. * Circular position setpoint mode: position setpoints wrapped [0, cpr). Useful for infinite incremental position control. +* Velocity setpoint ramping. Use velocity control mode, and set `controller.vel_ramp_enable` to true. This will ramp `controller.vel_setpoint` towards `controller.vel_ramp_target` at a ramp rate of `controller.config.vel_ramp_rate`. ### Changed * Increased switching frequency from around 8kHz to 24kHz. Control loops still run at 8kHz. diff --git a/Firmware/MotorControl/controller.hpp b/Firmware/MotorControl/controller.hpp index 9e1193a1..b39c2890 100644 --- a/Firmware/MotorControl/controller.hpp +++ b/Firmware/MotorControl/controller.hpp @@ -30,7 +30,7 @@ public: float vel_integrator_gain = 10.0f / 10000.0f; // [A/(counts/s * s)] float vel_limit = 20000.0f; // [counts/s] float vel_limit_tolerance = 1.2f; // ratio to vel_lim. 0.0f to disable - float vel_ramp_limit = 10000.0f; // [(counts/s) / s] + float vel_ramp_rate = 10000.0f; // [(counts/s) / s] bool setpoints_in_cpr = false; }; @@ -106,7 +106,7 @@ public: make_protocol_property("vel_integrator_gain", &config_.vel_integrator_gain), make_protocol_property("vel_limit", &config_.vel_limit), make_protocol_property("vel_limit_tolerance", &config_.vel_limit_tolerance), - make_protocol_property("vel_ramp_limit", &config_.vel_ramp_limit), + make_protocol_property("vel_ramp_rate", &config_.vel_ramp_rate), make_protocol_property("setpoints_in_cpr", &config_.setpoints_in_cpr) ), make_protocol_function("set_pos_setpoint", *this, &Controller::set_pos_setpoint, From 5684e14f9259be8a497b20240008da7c262d5c8e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 27 Nov 2018 19:35:51 -0800 Subject: [PATCH 097/106] fix rename redidual --- Firmware/MotorControl/controller.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/MotorControl/controller.cpp b/Firmware/MotorControl/controller.cpp index c0494397..16aef47a 100644 --- a/Firmware/MotorControl/controller.cpp +++ b/Firmware/MotorControl/controller.cpp @@ -120,7 +120,7 @@ bool Controller::update(float pos_estimate, float vel_estimate, float* current_s // Ramp rate limited velocity setpoint if (config_.control_mode == CTRL_MODE_VELOCITY_CONTROL && vel_ramp_enable_) { - float max_step_size = current_meas_period * config_.vel_ramp_limit; + float max_step_size = current_meas_period * config_.vel_ramp_rate; float full_step = vel_ramp_target_ - vel_setpoint_; float step; if (fabsf(full_step) > max_step_size) { From f36fe0058e5af39bcbe2d53c4736968c8dfa9923 Mon Sep 17 00:00:00 2001 From: Unknown Date: Tue, 27 Nov 2018 22:51:13 -0500 Subject: [PATCH 098/106] Add controller_with_ff.png to docs --- docs/controller_with_ff.png | Bin 0 -> 100261 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 docs/controller_with_ff.png diff --git a/docs/controller_with_ff.png b/docs/controller_with_ff.png new file mode 100644 index 0000000000000000000000000000000000000000..212b1f266d7309882c1fa0c05ea69732250456f2 GIT binary patch literal 100261 zcmeFZXIPWl5;lw|pme1QBG~9nsnU_A^j@VX(!2C7pnxKvQk331p#?&3A|NHSPy?YT z9ResMNFeY&(XH)?mu2J1lFvzX6}3Do_X?IQ(cLSn1L7%50C8LU3qOh zJfib>c=*@P5(4iG2aT!Y;j!S|lb6-?Ikky67jRz>aq`97&`L?h>yhs*0_6lXO6y~m zsHo($W^t0j)a z>@0mp=5ukky|>a-N3N$ma(*-D+x*^ff7X4=|Bl8MHf>j&tn*=|E%g~n8N5^f>z~Z) z71S5bvOK}V|6l*e7(QWnXc)HgzdnQe3l?Y2AKdtd74bqM@nk=oCF1)h)1I(gZ9V-@ zD^i|kiKJhcC-|S{1Ex{RFM9v)lK_5t75~inYnPh-X#=N1Bag`c@yO(XBYPS~_fH#; zp?p2}KW_+UbtGW_OV=IzfBN9rt6#Nx7-k?Q8od_nOy{t$G13{t87e zZ2j*>aE*s9eB&I)9J3g=t-W)JeQ9`+2MiwX@ z{_*iYoqk9iF#ziuB65vCVK(HIjE>+7L#xCGwa^r*r<6RBR)WtcQ%b>x)!Bz@qy*B9 zJQJ_0!sWqMwBh_de`6gB|0cj;5ozy;fBi{@vw~`sUmtxSfD|@E4jx`M~tQqXW`LfTUW^_e@&+h4_5m6ahX41=50BY7h+y=&}wX zd3fT2F<)gngEoglk3wwaq`ucmY0eFr+v=QS51Fu+3dAQK@D%A*q+80#^=k7l(Sqvt zlOyXB2_0+);#1=7wr(qO>IN5o6}3hr*Bcts-5NU&$_wC6zw#?;e_O|`{)FYzr>Ea8 z{p7;P=Q5&sc0mJ8nk>Ajy@GZ+Y$D;tGfqrJPlal&dN*#Y!vbb+LC>kwkUE0ex9&%& zaKRIMlw#rrZA#U;i!M~?$nXu%SSJPe2tSzpnk1|uSgm`nhr!+}L!$t$D}6&ix|{Q1 zk-p*TMzP20?vsGOF^NS}0pNNX>e)L#FZUq_rMex%xlEeUOX4Z^3-k}Yy9IYI%EG4Z z*df|OtyDtl0`jM58I?A-D(u=z+j46TKT}tYr*FRQt-X=m-BV-u-XPVn)-lTl+7Vhl zd24(|qf;$Sfs1fD*+^^}hAz{0ARCY9H<>PVr4+Pr$1Zk08oiP@#}@s|fSdZrK zfT6q0$<^e38kdc)CX7%*a>tJdicIuYf_wDSBi@0HvSeoWSWoWd2zgqE3DF9;cZAg0 zM*AhCjM4T>soFG_jxiTh_88mLnsCI}CM7NHW!FCz9E97{8vDLolbs*FVGn>@{?L_+? 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z!g$UqJLCp!j5yYhBO+YwQj|?@7snJsYtv_G#um!=dw_3Rp+9%`jvktW)H0{47t!gB@R$bp?xGZut*84{EjTZB8>D$7u$U-=7{c#{S-^ zUn<3Mx6)$0+~#ZJHJMOTt$kulGEQXXPrR7j!B`(DYvmquQ}qW#M~0qDL6Q6FW&T5- z4~T zfH+>{T~Ya^i}i=X(NBXl@LQk0`EN0V|MmF5Zy(h0mg_$z{Ns&(Ty26Xfr6fV^Z)i* zen{s3*e`PW;=jy;RwQprPoU(#yf%OlmifQS_k&LUy!!uR`9yt97uT)Z(0S>cEb4!8 zQvOScf7@pW2LAUT|0ge^G0*?2M82J^kF#lJK{2-B^um1lKBmWPJjs>5d Xcu{=N774p`@bA)j<#TCr#(w_?1mc}^ literal 0 HcmV?d00001 From eea174f82b08d4db10e1d845a27e626ddadbe9b8 Mon Sep 17 00:00:00 2001 From: Unknown Date: Tue, 27 Nov 2018 22:54:54 -0500 Subject: [PATCH 099/106] Replace controller image in docs with new FF diagram --- docs/control.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/control.md b/docs/control.md index f0b2da1d..fd04ac6d 100644 --- a/docs/control.md +++ b/docs/control.md @@ -2,7 +2,7 @@ The motor controller is a cascaded style position, velocity and current control loop, as per the diagram below. When the control mode is set to position control, the whole loop runs. When running in velocity control mode, the position control part is removed and the velocity command is fed directly in to the second stage input. In current control mode, only the current controller is used. -![Cascaded pos vel I loops](https://static1.squarespace.com/static/58aff26de4fcb53b5efd2f02/t/5b66284a0e2e72aae8818d64/1533421649405/CascadedController.png?format=2500w) +![Cascaded pos vel I loops](https://github.com/madcowswe/ODrive/blob/master/docs/controller_with_ff.png?raw=true) ### Position loop: The position controller is a P loop with a single proportional gain. From 167f00e622d2b95f0a89b8b5ad17a3eb01b11ef4 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Tue, 27 Nov 2018 22:29:02 -0800 Subject: [PATCH 100/106] add current sense saturation fault --- CHANGELOG.md | 1 + Firmware/MotorControl/motor.cpp | 11 ++++++++++- Firmware/MotorControl/motor.hpp | 16 ++++++++++------ 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index a257960d..e6069fbc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -3,6 +3,7 @@ Please add a note of your changes below this heading if you make a Pull Request. ### Added * Overspeed fault +* Current sense saturation fault. * Supress startup transients by sampling encoder estimate into position setpoint when entering closed loop control. * Make step dir gpio pins configurable. * Configuration variable `encoder.config.zero_count_on_find_idx`, true by default. Set to false to leave the initial encoder count to be where the axis was at boot. diff --git a/Firmware/MotorControl/motor.cpp b/Firmware/MotorControl/motor.cpp index 5585a862..7cee19b0 100644 --- a/Firmware/MotorControl/motor.cpp +++ b/Firmware/MotorControl/motor.cpp @@ -73,7 +73,8 @@ void Motor::DRV8301_setup() { // Solve for exact gain, then snap down to have equal or larger range as requested // or largest possible range otherwise static const float kMargin = 0.90f; - static const float max_output_swing = 1.6f; // [V] out of amplifier + static const float kTripMargin = 1.0f; // Trip level is at edge of linear range of amplifer + static const float max_output_swing = 1.35f; // [V] out of amplifier float max_unity_gain_current = kMargin * max_output_swing * hw_config_.shunt_conductance; // [A] float requested_gain = max_unity_gain_current / config_.requested_current_range; // [V/V] @@ -99,6 +100,8 @@ void Motor::DRV8301_setup() { phase_current_rev_gain_ = 1.0f / gain_snap_down->first; // Clip all current control to actual usable range current_control_.max_allowed_current = max_unity_gain_current * phase_current_rev_gain_; + // Set trip level + current_control_.overcurrent_trip_level = (kTripMargin / kMargin) * current_control_.max_allowed_current; // We now have the gain settings we want to use, lets set up DRV chip DRV_SPI_8301_Vars_t* local_regs = &gate_driver_regs_; @@ -296,6 +299,12 @@ bool Motor::FOC_current(float Id_des, float Iq_des, float phase) { // For Reporting ictrl.Iq_setpoint = Iq_des; + // Check for current sense saturation + if (fabsf(current_meas_.phB) > ictrl.overcurrent_trip_level + || fabsf(current_meas_.phC) > ictrl.overcurrent_trip_level) { + set_error(ERROR_CURRENT_SENSE_SATURATION); + } + // Clarke transform float Ialpha = -current_meas_.phB - current_meas_.phC; float Ibeta = one_by_sqrt3 * (current_meas_.phB - current_meas_.phC); diff --git a/Firmware/MotorControl/motor.hpp b/Firmware/MotorControl/motor.hpp index ebfd3a12..2fe384e5 100644 --- a/Firmware/MotorControl/motor.hpp +++ b/Firmware/MotorControl/motor.hpp @@ -20,7 +20,8 @@ public: ERROR_BRAKE_CURRENT_OUT_OF_RANGE = 0x0040, ERROR_MODULATION_MAGNITUDE = 0x0080, ERROR_BRAKE_DEADTIME_VIOLATION = 0x0100, - ERROR_UNEXPECTED_TIMER_CALLBACK = 0x0200 + ERROR_UNEXPECTED_TIMER_CALLBACK = 0x0200, + ERROR_CURRENT_SENSE_SATURATION = 0x0400 }; enum MotorType_t { @@ -43,9 +44,10 @@ public: // Voltage applied at end of cycle: float final_v_alpha; // [V] float final_v_beta; // [V] - float Iq_setpoint; - float Iq_measured; - float max_allowed_current; + float Iq_setpoint; // [A] + float Iq_measured; // [A] + float max_allowed_current; // [A] + float overcurrent_trip_level; // [A] }; // NOTE: for gimbal motors, all units of A are instead V. @@ -64,7 +66,7 @@ public: // float current_lim = 70.0f; //[A] float current_lim = 10.0f; //[A] // Value used to compute shunt amplifier gains - float requested_current_range = 70.0f; // [A] + float requested_current_range = 60.0f; // [A] float current_control_bandwidth = 1000.0f; // [rad/s] }; @@ -153,6 +155,7 @@ public: .Iq_setpoint = 0.0f, .Iq_measured = 0.0f, .max_allowed_current = 0.0f, + .overcurrent_trip_level = 0.0f, }; DRV8301_FaultType_e drv_fault_ = DRV8301_FaultType_NoFault; DRV_SPI_8301_Vars_t gate_driver_regs_; //Local view of DRV registers (initialized by DRV8301_setup) @@ -178,7 +181,8 @@ public: make_protocol_property("final_v_beta", ¤t_control_.final_v_beta), make_protocol_property("Iq_setpoint", ¤t_control_.Iq_setpoint), make_protocol_property("Iq_measured", ¤t_control_.Iq_measured), - make_protocol_property("max_allowed_current", ¤t_control_.max_allowed_current) + make_protocol_ro_property("max_allowed_current", ¤t_control_.max_allowed_current), + make_protocol_ro_property("overcurrent_trip_level", ¤t_control_.overcurrent_trip_level) ), make_protocol_object("gate_driver", make_protocol_ro_property("drv_fault", &drv_fault_) From bb680e175a5ce545c30a8abd2d38eadb9b6fa633 Mon Sep 17 00:00:00 2001 From: Mark Omo Date: Wed, 28 Nov 2018 16:33:53 -0700 Subject: [PATCH 101/106] Fix issues with spaces in install path on windows --- tools/odrivetool.bat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/odrivetool.bat b/tools/odrivetool.bat index 02b0a0bb..06dc5e56 100644 --- a/tools/odrivetool.bat +++ b/tools/odrivetool.bat @@ -1,2 +1,2 @@ @echo off -ipython %~dp0\odrivetool -- %* +ipython "%~dp0\odrivetool" -- %* From 8c393973b7120d3f517c843932b85d75df707e0e Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 28 Nov 2018 22:44:58 -0800 Subject: [PATCH 102/106] document different control modes --- docs/TrapTrajPosVel.PNG | Bin 0 -> 14096 bytes docs/getting-started.md | 76 +++++++++++++++++++++++++++++++++++----- 2 files changed, 67 insertions(+), 9 deletions(-) create mode 100644 docs/TrapTrajPosVel.PNG diff --git a/docs/TrapTrajPosVel.PNG b/docs/TrapTrajPosVel.PNG new file mode 100644 index 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z(-Xi$$YrhTqxU^2RNN(WV5z|&E`~~BAonaj77(fh1ud~d6zS*Bn(_xOz$p=YR`Ao^ z`32t1>1uggfeW=ig$J&*V`2H{BUPKiD literal 0 HcmV?d00001 diff --git a/docs/getting-started.md b/docs/getting-started.md index 0127efad..022f0362 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -16,6 +16,7 @@ permalink: / - [Start `odrivetool`](#start-odrivetool) - [Configure M0](#configure-m0) - [Position control of M0](#position-control-of-m0) +- [Other control modes](#other-control-modes) - [What's next?](#whats-next) @@ -165,7 +166,7 @@ For instance, to set the current limit of M0 to 10A you would type: `odrv0.axis0 **Current limit**
`odrv0.axis0.motor.config.current_lim` [A]. -The default current limit, for safety reasons, is set to 10A. This is quite weak, but good for making sure the drive is stable. Once you have tuned the oDrive, you can increase this to 75A to increase performance. Note that above 75A, you must change the current amplifier gains. You do this by requesting a different current range. i.e. for 90A on M0: `odrv0.axis0.motor.config.requested_current_range = 90` [A], then save the configuration and reboot as the gains are written out to the DRV (MOSFET driver) only during startup. +The default current limit, for safety reasons, is set to 10A. This is quite weak, but good for making sure the drive is stable. Once you have tuned the oDrive, you can increase this to 60A to increase performance. Note that above 60A, you must change the current amplifier gains. You do this by requesting a different current range. i.e. for 90A on M0: `odrv0.axis0.motor.config.requested_current_range = 90` [A], then save the configuration and reboot as the gains are written out to the DRV (MOSFET driver) only during startup. *Note: The motor current and the current drawn from the power supply is not the same in general. You should not look at the power supply current to see what is going on with the motor current.*

Ok, so tell me how it actually works then...
@@ -241,16 +242,73 @@ Let's get motor 0 up and running. The procedure for motor 1 is exactly the same, 2. Type `odrv0.axis0.requested_state = AXIS_STATE_CLOSED_LOOP_CONTROL` Enter. From now on the ODrive will try to hold the motor's position. If you try to turn it by hand, it will fight you gently. That is unless you bump up `odrv0.axis0.motor.config.current_lim`, in which case it will fight you more fiercely. 3. Send the motor a new position setpoint. `odrv0.axis0.controller.pos_setpoint = 10000` Enter. The units are in encoder counts. -### Other control modes -The ODrive also supports velocity control and current (torque) control. +## Other control modes +The default control mode is unfiltered position control in the absolute encoder reference frame. You may wish to use a controlled trajectory instead. Or you may wish to control position in a circular frame to allow continous rotation forever without growing the numeric value of the setpoint too large. +You may also wish to control velocity (directly or with a ramping filter). +You can also directly control the current of the motor, which is proportional to torque. -**Velocity control**
-Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`. -You can now control the velocity with `odrv0.axis0.controller.vel_setpoint = 5000` [count/s]. +- [Trajectory control](#trajectory-control) +- [Circular position control](#circular-position-control) +- [Velocity control](#velocity-control) +- [Ramped velocity control](#ramped-velocity-control) +- [Current control](#current-control) -**Current control**
-Set `odrv0.axis0.controller.config.control_mode = CTRL_MODE_CURRENT_CONTROL`. -You can now control the current with `odrv0.axis0.controller.current_setpoint = 3` [A]. + +### Trajectory control +This mode lets you smoothly accelerate, coast, and decelerate the axis from one position to another. With raw position control, the controller simply tries to go to the setpoint as quickly as possible. Using a trajectory lets you tune the feedback gains more aggressively to reject disturbance, while keeping smooth motion. + +![Taptraj](TrapTrajPosVel.PNG)
+In the above image blue is position and orange is velocity. + +#### Parameters +``` +..trap_traj.config.vel_limit = +..trap_traj.config.accel_limit = +..trap_traj.config.decel_limit = +..trap_traj.config.A_per_css = +``` + +`vel_limit` is the maximum planned trajectory speed. This sets your coasting speed.
+`accel_limit` is the maximum acceleration in counts / sec^2
+`decel_limit` is the maximum deceleration in counts / sec^2
+`A_per_css` is a value which correlates acceleration (in counts / sec^2) and motor current. It is 0 by default. It is optional, but can improve response of your system if correctly tuned. Keep in mind this will need to change with the load / mass of your system. + +All values should be strictly positive (>= 0). + +Keep in mind that you must still set your safety limits as before. I recommend you set these a little higher ( > 10%) than the planner values, to give the controller enough control authority. +``` +..motor.config.current_lim = +..controller.config.vel_limit = +``` + +#### Usage +Use the `move_to_pos` function to move to an absolute position: +``` +..controller.move_to_pos() +``` + +### Circular position control +This mode is useful for continuos incremental position movement. For example a robot rolling indefinitely, or an extruder motor or conveyor belt moving with controlled increments indefinitely. +In the regular position mode, the `pos_setpoint` would grow to a very large value and would lose precision due to floating point rounding. + +In this mode, the controller will try to track the position within only one turn of the motor. Specifically, `pos_setpoint` is expected in the range `[0, cpr-1]`, where `cpr` is the number of encoder counts in one revolution. If the `pos_setpoint` is incremented to outside this range (say via step/dir input), it is automatically wrapped around into the correct value. +Note that in this mode `encoder.pos_cpr` is used for feedback in stead of `encoder.pos_estimate`. + +If you try to increment the axis with a large step in one go that exceeds `cpr/2` steps, the motor will go to the same angle around the wrong way. This is also the case if there is a large disturbance. If you have an application where you would like to handle larger steps, you can use a virtual CPR that is an integer times larger than your encoder's actual CPR. Set `encoder.config.cpr = N * your_enc_cpr`, where N is some integer. Choose N to give you an appropriate circular space for your application. + +### Velocity control +Set `axis.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`.
+You can now control the velocity with `axis.controller.vel_setpoint = 5000` [count/s]. + +### Ramped velocity control +Set `axis.controller.config.control_mode = CTRL_MODE_VELOCITY_CONTROL`.
+Set the velocity ramp rate (acceleration): `axis.controller.config.vel_ramp_rate = 2000` [counts/s^2]
+Activate the ramped velocity mode: `axis.controller.vel_ramp_enable = True`.
+You can now control the velocity with `axis.controller.vel_ramp_target = 5000` [count/s]. + +### Current control +Set `axis.controller.config.control_mode = CTRL_MODE_CURRENT_CONTROL`.
+You can now control the current with `axis.controller.current_setpoint = 3` [A]. *Note: There is no velocity limiting in current control mode. Make sure that you don't overrev the motor, or exceed the max speed for your encoder.* From 16b1f7e60f30372319e1b29f9175e3835e79e2de Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 28 Nov 2018 22:46:01 -0800 Subject: [PATCH 103/106] add release info to changelog --- CHANGELOG.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e6069fbc..10fc161e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,8 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. +# Releases +## [0.4.7] - 2018-11-28 ### Added * Overspeed fault * Current sense saturation fault. @@ -19,7 +21,6 @@ Please add a note of your changes below this heading if you make a Pull Request. * Would get ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. * ODrive tool can now run interactive nested scripts with "%run -i script.py" -# Releases ## [0.4.6] - 2018-10-07 ### Fixed * Broken printing of floats on ascii protocol From 763e50aa9535d66d5ced8d49258e96f4cbc72a5d Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 28 Nov 2018 22:50:06 -0800 Subject: [PATCH 104/106] format changelog --- CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 10fc161e..d77a003e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,7 +17,7 @@ Please add a note of your changes below this heading if you make a Pull Request. * Renamed `axis.enable_step_dir` to `axis.step_dir_active` * New process for working with STM32CubeMX. -## Fixed +### Fixed * Would get ERROR_CONTROL_DEADLINE_MISSED along with every ERROR_PHASE_RESISTANCE_OUT_OF_RANGE. * ODrive tool can now run interactive nested scripts with "%run -i script.py" From 0c75e280a564f960a2d9a0facdbc32e50dacb6c4 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Wed, 28 Nov 2018 23:02:15 -0800 Subject: [PATCH 105/106] fix docs remenant --- docs/getting-started.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/getting-started.md b/docs/getting-started.md index 022f0362..d9cc3dd6 100644 --- a/docs/getting-started.md +++ b/docs/getting-started.md @@ -130,10 +130,10 @@ Try step 5 again ## Firmware **ODrive v3.5 and later**
-Your board should come preflashed with firmware. If you run into problems, follow the instructions [here](odrivetool.md#device-firmware-update) on the DFU procedure before you continue.
+Your board should come preflashed with firmware. If you run into problems, follow the instructions [here](odrivetool.md#device-firmware-update) on the DFU procedure before you continue. **ODrive v3.4 and earlier**
-Your board does **not** come preflashed with any firmware. Follow the instructions [here](odrivetool.md#device-firmware-update) on the STP Link procedure before you continue.
+Your board does **not** come preflashed with any firmware. Follow the instructions [here](odrivetool.md#device-firmware-update) on the STP Link procedure before you continue. ## Start `odrivetool` To launch the main interactive ODrive tool, type `odrivetool` Enter. Connect your ODrive and wait for the tool to find it. Now you can, for instance type `odrv0.vbus_voltage` Enter to inpect the boards main supply voltage. From 414f84a2ce16b2616141809368ef778329586551 Mon Sep 17 00:00:00 2001 From: Oskar Weigl Date: Thu, 6 Dec 2018 20:21:00 -0800 Subject: [PATCH 106/106] add dump errors util function --- CHANGELOG.md | 3 +++ docs/troubleshooting.md | 16 ++----------- tools/odrive/enums.py | 52 ++++++++++++++++++++++++++++++++--------- tools/odrive/shell.py | 5 ++-- tools/odrive/utils.py | 42 ++++++++++++++++++++++++++++++--- 5 files changed, 88 insertions(+), 30 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d77a003e..6b001221 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,9 @@ # Unreleased Features Please add a note of your changes below this heading if you make a Pull Request. +### Added +* `dump_errors()` utility function in odrivetool to dump, decode and optionally clear errors. + # Releases ## [0.4.7] - 2018-11-28 ### Added diff --git a/docs/troubleshooting.md b/docs/troubleshooting.md index c05c7f92..c5556d02 100644 --- a/docs/troubleshooting.md +++ b/docs/troubleshooting.md @@ -14,21 +14,9 @@ Table of Contents: ## Error codes -If your ODrive is not working as expected, run `odrivetool` and type `hex(.error)` Enter where `` is the axis that isn't working. This will display a [hexadecimal](https://en.wikipedia.org/wiki/Hexadecimal) representation of the error code. Each bit represents one error flag. - -
Example
-Say you got this error output: -```python -In [1]: hex(odrv0.axis0.error) -Out[1]: '0x6' -``` - -Written in binary, the number `0x6` corresponds to `110`, that means bits 1 and 2 are set (counting starts at 0). -Looking at the reference below, this means that both `ERROR_DC_BUS_UNDER_VOLTAGE` and `ERROR_DC_BUS_OVER_VOLTAGE` occurred. -
- -The axis error may say that some other component has failed. Say it reports `ERROR_ENCODER_FAILED`, then you need to go check the encoder error: `hex(.encoder.error)`. +If your ODrive is not working as expected, run `odrivetool` and type `dump_errors(odrv0)` Enter. This will dump a list of all the errors that are present. To also clear all the errors, you can run `dump_errors(odrv0, True)`. +The following sections will give some guidance on the most common errors. You may also check the code for the full list of errors: * Axis error flags defined [here](../Firmware/MotorControl/axis.hpp). * Motor error flags defined [here](../Firmware/MotorControl/motor.hpp). * Encoder error flags defined [here](../Firmware/MotorControl/encoder.hpp). diff --git a/tools/odrive/enums.py b/tools/odrive/enums.py index 19572c90..26e0f816 100644 --- a/tools/odrive/enums.py +++ b/tools/odrive/enums.py @@ -11,17 +11,47 @@ AXIS_STATE_ENCODER_INDEX_SEARCH = 6 AXIS_STATE_ENCODER_OFFSET_CALIBRATION = 7 AXIS_STATE_CLOSED_LOOP_CONTROL = 8 -AXIS_ERROR_NONE = 0 -AXIS_ERROR_INVALID_STATE = 1 -#AXIS_ERROR_DC_BUS_UNDER_VOLTAGE = 2 -#AXIS_ERROR_DC_BUS_OVER_VOLTAGE = 3 -#AXIS_ERROR_CURRENT_MEASUREMENT_TIMEOUT = 4 -#AXIS_ERROR_CONTROL_LOOP_TIMEOUT = 5 -#AXIS_ERROR_MOTOR_FAILED = 6 -#AXIS_ERROR_SENSORLESS_ESTIMATOR_FAILED = 7 -#AXIS_ERROR_ENCODER_FAILED = 8 -#AXIS_ERROR_CONTROLLER_FAILED = 9 -#AXIS_ERROR_POS_CTRL_DURING_SENSORLESS = 10 +class errors: + class axis: + ERROR_NONE = 0x00 + ERROR_INVALID_STATE = 0x01 #