diff --git a/Firmware/Board/v3/Inc/stm32f4xx_it.h b/Firmware/Board/v3/Inc/stm32f4xx_it.h
index bed8a253..784a3333 100644
--- a/Firmware/Board/v3/Inc/stm32f4xx_it.h
+++ b/Firmware/Board/v3/Inc/stm32f4xx_it.h
@@ -54,8 +54,10 @@ void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void SysTick_Handler(void);
+void DMA1_Stream0_IRQHandler(void);
 void DMA1_Stream2_IRQHandler(void);
 void DMA1_Stream4_IRQHandler(void);
+void DMA1_Stream5_IRQHandler(void);
 void ADC_IRQHandler(void);
 void CAN1_TX_IRQHandler(void);
 void CAN1_RX0_IRQHandler(void);
@@ -63,6 +65,7 @@ void CAN1_RX1_IRQHandler(void);
 void CAN1_SCE_IRQHandler(void);
 void TIM8_TRG_COM_TIM14_IRQHandler(void);
 void TIM5_IRQHandler(void);
+void SPI3_IRQHandler(void);
 void UART4_IRQHandler(void);
 void OTG_FS_IRQHandler(void);
 
diff --git a/Firmware/Board/v3/Odrive.ioc b/Firmware/Board/v3/Odrive.ioc
index 9f636781..7a334af7 100644
--- a/Firmware/Board/v3/Odrive.ioc
+++ b/Firmware/Board/v3/Odrive.ioc
@@ -97,7 +97,29 @@ Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlign
 Dma.Request0=UART4_RX
 Dma.Request1=UART4_TX
 Dma.Request2=ADC1
-Dma.RequestsNb=3
+Dma.Request3=SPI3_TX
+Dma.Request4=SPI3_RX
+Dma.RequestsNb=5
+Dma.SPI3_RX.4.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI3_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI3_RX.4.Instance=DMA1_Stream0
+Dma.SPI3_RX.4.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
+Dma.SPI3_RX.4.MemInc=DMA_MINC_ENABLE
+Dma.SPI3_RX.4.Mode=DMA_NORMAL
+Dma.SPI3_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
+Dma.SPI3_RX.4.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI3_RX.4.Priority=DMA_PRIORITY_MEDIUM
+Dma.SPI3_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.SPI3_TX.3.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI3_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI3_TX.3.Instance=DMA1_Stream5
+Dma.SPI3_TX.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
+Dma.SPI3_TX.3.MemInc=DMA_MINC_ENABLE
+Dma.SPI3_TX.3.Mode=DMA_NORMAL
+Dma.SPI3_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
+Dma.SPI3_TX.3.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI3_TX.3.Priority=DMA_PRIORITY_MEDIUM
+Dma.SPI3_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
 Dma.UART4_RX.0.Direction=DMA_PERIPH_TO_MEMORY
 Dma.UART4_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
 Dma.UART4_RX.0.Instance=DMA1_Stream2
@@ -221,8 +243,10 @@ NVIC.CAN1_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true
 NVIC.CAN1_RX1_IRQn=true\:6\:0\:true\:false\:true\:true\:true
 NVIC.CAN1_SCE_IRQn=true\:6\:0\:true\:false\:true\:true\:true
 NVIC.CAN1_TX_IRQn=true\:6\:0\:true\:false\:true\:true\:true
+NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false
 NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:true
 NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false
+NVIC.DMA1_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false
 NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:false\:true\:false
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true
@@ -231,6 +255,7 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:true
 NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SPI3_IRQn=true\:5\:0\:false\:false\:true\:true\:true
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true
 NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:true
 NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:false\:false\:true
diff --git a/Firmware/Board/v3/Src/dma.c b/Firmware/Board/v3/Src/dma.c
index 3de873ad..813c735a 100644
--- a/Firmware/Board/v3/Src/dma.c
+++ b/Firmware/Board/v3/Src/dma.c
@@ -71,12 +71,18 @@ void MX_DMA_Init(void)
   __HAL_RCC_DMA2_CLK_ENABLE();
 
   /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
   /* DMA1_Stream2_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
   /* DMA1_Stream4_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
+  /* DMA1_Stream5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
   /* DMA2_Stream0_IRQn interrupt configuration */
   // Dear STM, no we _don't_ want to fire an interrupt for this DMA
   // (it's not possible to deselect this in CubeMX)
diff --git a/Firmware/Board/v3/Src/spi.c b/Firmware/Board/v3/Src/spi.c
index 87b2a018..d66515f9 100644
--- a/Firmware/Board/v3/Src/spi.c
+++ b/Firmware/Board/v3/Src/spi.c
@@ -51,12 +51,15 @@
 #include "spi.h"
 
 #include "gpio.h"
+#include "dma.h"
 
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
 
 SPI_HandleTypeDef hspi3;
+DMA_HandleTypeDef hdma_spi3_tx;
+DMA_HandleTypeDef hdma_spi3_rx;
 
 /* SPI3 init function */
 void MX_SPI3_Init(void)
@@ -105,6 +108,46 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
     GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
+    /* SPI3 DMA Init */
+    /* SPI3_TX Init */
+    hdma_spi3_tx.Instance = DMA1_Stream5;
+    hdma_spi3_tx.Init.Channel = DMA_CHANNEL_0;
+    hdma_spi3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi3_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi3_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_spi3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_spi3_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi3_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
+    hdma_spi3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi3_tx) != HAL_OK)
+    {
+      _Error_Handler(__FILE__, __LINE__);
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi3_tx);
+
+    /* SPI3_RX Init */
+    hdma_spi3_rx.Instance = DMA1_Stream0;
+    hdma_spi3_rx.Init.Channel = DMA_CHANNEL_0;
+    hdma_spi3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi3_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_spi3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_spi3_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi3_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
+    hdma_spi3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi3_rx) != HAL_OK)
+    {
+      _Error_Handler(__FILE__, __LINE__);
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi3_rx);
+
+    /* SPI3 interrupt Init */
+    HAL_NVIC_SetPriority(SPI3_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(SPI3_IRQn);
   /* USER CODE BEGIN SPI3_MspInit 1 */
 
   /* USER CODE END SPI3_MspInit 1 */
@@ -129,6 +172,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
     */
     HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12);
 
+    /* SPI3 DMA DeInit */
+    HAL_DMA_DeInit(spiHandle->hdmatx);
+    HAL_DMA_DeInit(spiHandle->hdmarx);
+
+    /* SPI3 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI3_IRQn);
   /* USER CODE BEGIN SPI3_MspDeInit 1 */
 
   /* USER CODE END SPI3_MspDeInit 1 */
diff --git a/Firmware/Board/v3/Src/stm32f4xx_it.c b/Firmware/Board/v3/Src/stm32f4xx_it.c
index 8acc96ee..f0fe1d3e 100644
--- a/Firmware/Board/v3/Src/stm32f4xx_it.c
+++ b/Firmware/Board/v3/Src/stm32f4xx_it.c
@@ -63,6 +63,9 @@ extern ADC_HandleTypeDef hadc1;
 extern ADC_HandleTypeDef hadc2;
 extern ADC_HandleTypeDef hadc3;
 extern CAN_HandleTypeDef hcan1;
+extern DMA_HandleTypeDef hdma_spi3_tx;
+extern DMA_HandleTypeDef hdma_spi3_rx;
+extern SPI_HandleTypeDef hspi3;
 extern TIM_HandleTypeDef htim5;
 extern TIM_HandleTypeDef htim8;
 extern DMA_HandleTypeDef hdma_uart4_rx;
@@ -194,6 +197,20 @@ void SysTick_Handler(void)
 /* please refer to the startup file (startup_stm32f4xx.s).                    */
 /******************************************************************************/
 
+/**
+* @brief This function handles DMA1 stream0 global interrupt.
+*/
+void DMA1_Stream0_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi3_rx);
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+
 /**
 * @brief This function handles DMA1 stream2 global interrupt.
 */
@@ -222,6 +239,20 @@ void DMA1_Stream4_IRQHandler(void)
   /* USER CODE END DMA1_Stream4_IRQn 1 */
 }
 
+/**
+* @brief This function handles DMA1 stream5 global interrupt.
+*/
+void DMA1_Stream5_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream5_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi3_tx);
+  /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream5_IRQn 1 */
+}
+
 /**
 * @brief This function handles ADC1, ADC2 and ADC3 global interrupts.
 */
@@ -336,6 +367,20 @@ void TIM5_IRQHandler(void)
   /* USER CODE END TIM5_IRQn 1 */
 }
 
+/**
+* @brief This function handles SPI3 global interrupt.
+*/
+void SPI3_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI3_IRQn 0 */
+
+  /* USER CODE END SPI3_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi3);
+  /* USER CODE BEGIN SPI3_IRQn 1 */
+
+  /* USER CODE END SPI3_IRQn 1 */
+}
+
 /**
 * @brief This function handles UART4 global interrupt.
 */